b43legacy: Convert to use of the new SPROM structure
[linux-2.6.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2  *
3  *  Broadcom B43legacy wireless driver
4  *
5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6  *  Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
7  *  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11  *
12  *  Some parts of the code in this file are derived from the ipw2200
13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  *  This program is free software; you can redistribute it and/or modify
16  *  it under the terms of the GNU General Public License as published by
17  *  the Free Software Foundation; either version 2 of the License, or
18  *  (at your option) any later version.
19  *
20  *  This program is distributed in the hope that it will be useful,
21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *  GNU General Public License for more details.
24  *
25  *  You should have received a copy of the GNU General Public License
26  *  along with this program; see the file COPYING.  If not, write to
27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  *  Boston, MA 02110-1301, USA.
29  *
30  */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/moduleparam.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/version.h>
38 #include <linux/firmware.h>
39 #include <linux/wireless.h>
40 #include <linux/workqueue.h>
41 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55
56
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
64 static int modparam_pio;
65 module_param_named(pio, modparam_pio, int, 0444);
66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67 #elif defined(CONFIG_B43LEGACY_DMA)
68 # define modparam_pio   0
69 #elif defined(CONFIG_B43LEGACY_PIO)
70 # define modparam_pio   1
71 #endif
72
73 static int modparam_bad_frames_preempt;
74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
76                  " Preemption");
77
78 static char modparam_fwpostfix[16];
79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
80 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
81
82 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
83 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
86         SSB_DEVTABLE_END
87 };
88 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
89
90
91 /* Channel and ratetables are shared for all devices.
92  * They can't be const, because ieee80211 puts some precalculated
93  * data in there. This data is the same for all devices, so we don't
94  * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
96         {                                                       \
97                 .rate   = B43legacy_RATE_TO_100KBPS(_rateid),   \
98                 .val    = (_rateid),                            \
99                 .val2   = (_rateid),                            \
100                 .flags  = (_flags),                             \
101         }
102 static struct ieee80211_rate __b43legacy_ratetable[] = {
103         RATETAB_ENT(B43legacy_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
115 };
116 #define b43legacy_a_ratetable           (__b43legacy_ratetable + 4)
117 #define b43legacy_a_ratetable_size      8
118 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
119 #define b43legacy_b_ratetable_size      4
120 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
121 #define b43legacy_g_ratetable_size      12
122
123 #define CHANTAB_ENT(_chanid, _freq) \
124         {                                                       \
125                 .chan   = (_chanid),                            \
126                 .freq   = (_freq),                              \
127                 .val    = (_chanid),                            \
128                 .flag   = IEEE80211_CHAN_W_SCAN |               \
129                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
130                           IEEE80211_CHAN_W_IBSS,                \
131                 .power_level    = 0x0A,                         \
132                 .antenna_max    = 0xFF,                         \
133         }
134 static struct ieee80211_channel b43legacy_bg_chantable[] = {
135         CHANTAB_ENT(1, 2412),
136         CHANTAB_ENT(2, 2417),
137         CHANTAB_ENT(3, 2422),
138         CHANTAB_ENT(4, 2427),
139         CHANTAB_ENT(5, 2432),
140         CHANTAB_ENT(6, 2437),
141         CHANTAB_ENT(7, 2442),
142         CHANTAB_ENT(8, 2447),
143         CHANTAB_ENT(9, 2452),
144         CHANTAB_ENT(10, 2457),
145         CHANTAB_ENT(11, 2462),
146         CHANTAB_ENT(12, 2467),
147         CHANTAB_ENT(13, 2472),
148         CHANTAB_ENT(14, 2484),
149 };
150 #define b43legacy_bg_chantable_size     ARRAY_SIZE(b43legacy_bg_chantable)
151
152 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
153 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
154 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
155 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
156
157
158 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
159 {
160         if (!wl || !wl->current_dev)
161                 return 1;
162         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
163                 return 1;
164         /* We are up and running.
165          * Ratelimit the messages to avoid DoS over the net. */
166         return net_ratelimit();
167 }
168
169 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
170 {
171         va_list args;
172
173         if (!b43legacy_ratelimit(wl))
174                 return;
175         va_start(args, fmt);
176         printk(KERN_INFO "b43legacy-%s: ",
177                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
178         vprintk(fmt, args);
179         va_end(args);
180 }
181
182 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
183 {
184         va_list args;
185
186         if (!b43legacy_ratelimit(wl))
187                 return;
188         va_start(args, fmt);
189         printk(KERN_ERR "b43legacy-%s ERROR: ",
190                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
191         vprintk(fmt, args);
192         va_end(args);
193 }
194
195 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
196 {
197         va_list args;
198
199         if (!b43legacy_ratelimit(wl))
200                 return;
201         va_start(args, fmt);
202         printk(KERN_WARNING "b43legacy-%s warning: ",
203                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
204         vprintk(fmt, args);
205         va_end(args);
206 }
207
208 #if B43legacy_DEBUG
209 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
210 {
211         va_list args;
212
213         va_start(args, fmt);
214         printk(KERN_DEBUG "b43legacy-%s debug: ",
215                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
216         vprintk(fmt, args);
217         va_end(args);
218 }
219 #endif /* DEBUG */
220
221 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
222                                 u32 val)
223 {
224         u32 status;
225
226         B43legacy_WARN_ON(offset % 4 != 0);
227
228         status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
229         if (status & B43legacy_SBF_XFER_REG_BYTESWAP)
230                 val = swab32(val);
231
232         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
233         mmiowb();
234         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
235 }
236
237 static inline
238 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
239                                 u16 routing, u16 offset)
240 {
241         u32 control;
242
243         /* "offset" is the WORD offset. */
244
245         control = routing;
246         control <<= 16;
247         control |= offset;
248         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
249 }
250
251 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
252                        u16 routing, u16 offset)
253 {
254         u32 ret;
255
256         if (routing == B43legacy_SHM_SHARED) {
257                 B43legacy_WARN_ON((offset & 0x0001) != 0);
258                 if (offset & 0x0003) {
259                         /* Unaligned access */
260                         b43legacy_shm_control_word(dev, routing, offset >> 2);
261                         ret = b43legacy_read16(dev,
262                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
263                         ret <<= 16;
264                         b43legacy_shm_control_word(dev, routing,
265                                                      (offset >> 2) + 1);
266                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
267
268                         return ret;
269                 }
270                 offset >>= 2;
271         }
272         b43legacy_shm_control_word(dev, routing, offset);
273         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
274
275         return ret;
276 }
277
278 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
279                            u16 routing, u16 offset)
280 {
281         u16 ret;
282
283         if (routing == B43legacy_SHM_SHARED) {
284                 B43legacy_WARN_ON((offset & 0x0001) != 0);
285                 if (offset & 0x0003) {
286                         /* Unaligned access */
287                         b43legacy_shm_control_word(dev, routing, offset >> 2);
288                         ret = b43legacy_read16(dev,
289                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
290
291                         return ret;
292                 }
293                 offset >>= 2;
294         }
295         b43legacy_shm_control_word(dev, routing, offset);
296         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
297
298         return ret;
299 }
300
301 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
302                            u16 routing, u16 offset,
303                            u32 value)
304 {
305         if (routing == B43legacy_SHM_SHARED) {
306                 B43legacy_WARN_ON((offset & 0x0001) != 0);
307                 if (offset & 0x0003) {
308                         /* Unaligned access */
309                         b43legacy_shm_control_word(dev, routing, offset >> 2);
310                         mmiowb();
311                         b43legacy_write16(dev,
312                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
313                                           (value >> 16) & 0xffff);
314                         mmiowb();
315                         b43legacy_shm_control_word(dev, routing,
316                                                    (offset >> 2) + 1);
317                         mmiowb();
318                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
319                                           value & 0xffff);
320                         return;
321                 }
322                 offset >>= 2;
323         }
324         b43legacy_shm_control_word(dev, routing, offset);
325         mmiowb();
326         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
327 }
328
329 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
330                            u16 value)
331 {
332         if (routing == B43legacy_SHM_SHARED) {
333                 B43legacy_WARN_ON((offset & 0x0001) != 0);
334                 if (offset & 0x0003) {
335                         /* Unaligned access */
336                         b43legacy_shm_control_word(dev, routing, offset >> 2);
337                         mmiowb();
338                         b43legacy_write16(dev,
339                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
340                                           value);
341                         return;
342                 }
343                 offset >>= 2;
344         }
345         b43legacy_shm_control_word(dev, routing, offset);
346         mmiowb();
347         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
348 }
349
350 /* Read HostFlags */
351 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
352 {
353         u32 ret;
354
355         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
356                                    B43legacy_SHM_SH_HOSTFHI);
357         ret <<= 16;
358         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
359                                     B43legacy_SHM_SH_HOSTFLO);
360
361         return ret;
362 }
363
364 /* Write HostFlags */
365 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
366 {
367         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
368                               B43legacy_SHM_SH_HOSTFLO,
369                               (value & 0x0000FFFF));
370         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
371                               B43legacy_SHM_SH_HOSTFHI,
372                               ((value & 0xFFFF0000) >> 16));
373 }
374
375 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
376 {
377         /* We need to be careful. As we read the TSF from multiple
378          * registers, we should take care of register overflows.
379          * In theory, the whole tsf read process should be atomic.
380          * We try to be atomic here, by restaring the read process,
381          * if any of the high registers changed (overflew).
382          */
383         if (dev->dev->id.revision >= 3) {
384                 u32 low;
385                 u32 high;
386                 u32 high2;
387
388                 do {
389                         high = b43legacy_read32(dev,
390                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
391                         low = b43legacy_read32(dev,
392                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
393                         high2 = b43legacy_read32(dev,
394                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
395                 } while (unlikely(high != high2));
396
397                 *tsf = high;
398                 *tsf <<= 32;
399                 *tsf |= low;
400         } else {
401                 u64 tmp;
402                 u16 v0;
403                 u16 v1;
404                 u16 v2;
405                 u16 v3;
406                 u16 test1;
407                 u16 test2;
408                 u16 test3;
409
410                 do {
411                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
412                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
413                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
414                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
415
416                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
417                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
418                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
419                 } while (v3 != test3 || v2 != test2 || v1 != test1);
420
421                 *tsf = v3;
422                 *tsf <<= 48;
423                 tmp = v2;
424                 tmp <<= 32;
425                 *tsf |= tmp;
426                 tmp = v1;
427                 tmp <<= 16;
428                 *tsf |= tmp;
429                 *tsf |= v0;
430         }
431 }
432
433 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
434 {
435         u32 status;
436
437         status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
438         status |= B43legacy_SBF_TIME_UPDATE;
439         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
440         mmiowb();
441 }
442
443 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
444 {
445         u32 status;
446
447         status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
448         status &= ~B43legacy_SBF_TIME_UPDATE;
449         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
450 }
451
452 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
453 {
454         /* Be careful with the in-progress timer.
455          * First zero out the low register, so we have a full
456          * register-overflow duration to complete the operation.
457          */
458         if (dev->dev->id.revision >= 3) {
459                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
460                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
461
462                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
463                 mmiowb();
464                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
465                                     hi);
466                 mmiowb();
467                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
468                                     lo);
469         } else {
470                 u16 v0 = (tsf & 0x000000000000FFFFULL);
471                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
472                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
473                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
474
475                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
476                 mmiowb();
477                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
478                 mmiowb();
479                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
480                 mmiowb();
481                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
482                 mmiowb();
483                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
484         }
485 }
486
487 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
488 {
489         b43legacy_time_lock(dev);
490         b43legacy_tsf_write_locked(dev, tsf);
491         b43legacy_time_unlock(dev);
492 }
493
494 static
495 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
496                              u16 offset, const u8 *mac)
497 {
498         static const u8 zero_addr[ETH_ALEN] = { 0 };
499         u16 data;
500
501         if (!mac)
502                 mac = zero_addr;
503
504         offset |= 0x0020;
505         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
506
507         data = mac[0];
508         data |= mac[1] << 8;
509         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
510         data = mac[2];
511         data |= mac[3] << 8;
512         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
513         data = mac[4];
514         data |= mac[5] << 8;
515         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
516 }
517
518 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
519 {
520         static const u8 zero_addr[ETH_ALEN] = { 0 };
521         const u8 *mac = dev->wl->mac_addr;
522         const u8 *bssid = dev->wl->bssid;
523         u8 mac_bssid[ETH_ALEN * 2];
524         int i;
525         u32 tmp;
526
527         if (!bssid)
528                 bssid = zero_addr;
529         if (!mac)
530                 mac = zero_addr;
531
532         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
533
534         memcpy(mac_bssid, mac, ETH_ALEN);
535         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
536
537         /* Write our MAC address and BSSID to template ram */
538         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
539                 tmp =  (u32)(mac_bssid[i + 0]);
540                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
541                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
542                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
543                 b43legacy_ram_write(dev, 0x20 + i, tmp);
544                 b43legacy_ram_write(dev, 0x78 + i, tmp);
545                 b43legacy_ram_write(dev, 0x478 + i, tmp);
546         }
547 }
548
549 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
550 {
551         b43legacy_write_mac_bssid_templates(dev);
552         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
553                                 dev->wl->mac_addr);
554 }
555
556 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
557                                     u16 slot_time)
558 {
559         /* slot_time is in usec. */
560         if (dev->phy.type != B43legacy_PHYTYPE_G)
561                 return;
562         b43legacy_write16(dev, 0x684, 510 + slot_time);
563         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
564                               slot_time);
565 }
566
567 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
568 {
569         b43legacy_set_slot_time(dev, 9);
570         dev->short_slot = 1;
571 }
572
573 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
574 {
575         b43legacy_set_slot_time(dev, 20);
576         dev->short_slot = 0;
577 }
578
579 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
580  * Returns the _previously_ enabled IRQ mask.
581  */
582 static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
583                                              u32 mask)
584 {
585         u32 old_mask;
586
587         old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
588         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
589                           mask);
590
591         return old_mask;
592 }
593
594 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
595  * Returns the _previously_ enabled IRQ mask.
596  */
597 static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
598                                               u32 mask)
599 {
600         u32 old_mask;
601
602         old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
603         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
604
605         return old_mask;
606 }
607
608 /* Synchronize IRQ top- and bottom-half.
609  * IRQs must be masked before calling this.
610  * This must not be called with the irq_lock held.
611  */
612 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
613 {
614         synchronize_irq(dev->dev->irq);
615         tasklet_kill(&dev->isr_tasklet);
616 }
617
618 /* DummyTransmission function, as documented on
619  * http://bcm-specs.sipsolutions.net/DummyTransmission
620  */
621 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
622 {
623         struct b43legacy_phy *phy = &dev->phy;
624         unsigned int i;
625         unsigned int max_loop;
626         u16 value;
627         u32 buffer[5] = {
628                 0x00000000,
629                 0x00D40000,
630                 0x00000000,
631                 0x01000000,
632                 0x00000000,
633         };
634
635         switch (phy->type) {
636         case B43legacy_PHYTYPE_B:
637         case B43legacy_PHYTYPE_G:
638                 max_loop = 0xFA;
639                 buffer[0] = 0x000B846E;
640                 break;
641         default:
642                 B43legacy_BUG_ON(1);
643                 return;
644         }
645
646         for (i = 0; i < 5; i++)
647                 b43legacy_ram_write(dev, i * 4, buffer[i]);
648
649         /* dummy read follows */
650         b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
651
652         b43legacy_write16(dev, 0x0568, 0x0000);
653         b43legacy_write16(dev, 0x07C0, 0x0000);
654         b43legacy_write16(dev, 0x050C, 0x0000);
655         b43legacy_write16(dev, 0x0508, 0x0000);
656         b43legacy_write16(dev, 0x050A, 0x0000);
657         b43legacy_write16(dev, 0x054C, 0x0000);
658         b43legacy_write16(dev, 0x056A, 0x0014);
659         b43legacy_write16(dev, 0x0568, 0x0826);
660         b43legacy_write16(dev, 0x0500, 0x0000);
661         b43legacy_write16(dev, 0x0502, 0x0030);
662
663         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
664                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
665         for (i = 0x00; i < max_loop; i++) {
666                 value = b43legacy_read16(dev, 0x050E);
667                 if (value & 0x0080)
668                         break;
669                 udelay(10);
670         }
671         for (i = 0x00; i < 0x0A; i++) {
672                 value = b43legacy_read16(dev, 0x050E);
673                 if (value & 0x0400)
674                         break;
675                 udelay(10);
676         }
677         for (i = 0x00; i < 0x0A; i++) {
678                 value = b43legacy_read16(dev, 0x0690);
679                 if (!(value & 0x0100))
680                         break;
681                 udelay(10);
682         }
683         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
684                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
685 }
686
687 /* Turn the Analog ON/OFF */
688 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
689 {
690         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
691 }
692
693 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
694 {
695         u32 tmslow;
696         u32 macctl;
697
698         flags |= B43legacy_TMSLOW_PHYCLKEN;
699         flags |= B43legacy_TMSLOW_PHYRESET;
700         ssb_device_enable(dev->dev, flags);
701         msleep(2); /* Wait for the PLL to turn on. */
702
703         /* Now take the PHY out of Reset again */
704         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
705         tmslow |= SSB_TMSLOW_FGC;
706         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
707         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
708         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
709         msleep(1);
710         tmslow &= ~SSB_TMSLOW_FGC;
711         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
712         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
713         msleep(1);
714
715         /* Turn Analog ON */
716         b43legacy_switch_analog(dev, 1);
717
718         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
719         macctl &= ~B43legacy_MACCTL_GMODE;
720         if (flags & B43legacy_TMSLOW_GMODE) {
721                 macctl |= B43legacy_MACCTL_GMODE;
722                 dev->phy.gmode = 1;
723         } else
724                 dev->phy.gmode = 0;
725         macctl |= B43legacy_MACCTL_IHR_ENABLED;
726         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
727 }
728
729 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
730 {
731         u32 v0;
732         u32 v1;
733         u16 tmp;
734         struct b43legacy_txstatus stat;
735
736         while (1) {
737                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
738                 if (!(v0 & 0x00000001))
739                         break;
740                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
741
742                 stat.cookie = (v0 >> 16);
743                 stat.seq = (v1 & 0x0000FFFF);
744                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
745                 tmp = (v0 & 0x0000FFFF);
746                 stat.frame_count = ((tmp & 0xF000) >> 12);
747                 stat.rts_count = ((tmp & 0x0F00) >> 8);
748                 stat.supp_reason = ((tmp & 0x001C) >> 2);
749                 stat.pm_indicated = !!(tmp & 0x0080);
750                 stat.intermediate = !!(tmp & 0x0040);
751                 stat.for_ampdu = !!(tmp & 0x0020);
752                 stat.acked = !!(tmp & 0x0002);
753
754                 b43legacy_handle_txstatus(dev, &stat);
755         }
756 }
757
758 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
759 {
760         u32 dummy;
761
762         if (dev->dev->id.revision < 5)
763                 return;
764         /* Read all entries from the microcode TXstatus FIFO
765          * and throw them away.
766          */
767         while (1) {
768                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
769                 if (!(dummy & 0x00000001))
770                         break;
771                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
772         }
773 }
774
775 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
776 {
777         u32 val = 0;
778
779         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
780         val <<= 16;
781         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
782
783         return val;
784 }
785
786 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
787 {
788         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
789                               (jssi & 0x0000FFFF));
790         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
791                               (jssi & 0xFFFF0000) >> 16);
792 }
793
794 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
795 {
796         b43legacy_jssi_write(dev, 0x7F7F7F7F);
797         b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
798                           b43legacy_read32(dev,
799                           B43legacy_MMIO_STATUS2_BITFIELD)
800                           | (1 << 4));
801         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
802                             dev->phy.channel);
803 }
804
805 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
806 {
807         /* Top half of Link Quality calculation. */
808
809         if (dev->noisecalc.calculation_running)
810                 return;
811         dev->noisecalc.channel_at_start = dev->phy.channel;
812         dev->noisecalc.calculation_running = 1;
813         dev->noisecalc.nr_samples = 0;
814
815         b43legacy_generate_noise_sample(dev);
816 }
817
818 static void handle_irq_noise(struct b43legacy_wldev *dev)
819 {
820         struct b43legacy_phy *phy = &dev->phy;
821         u16 tmp;
822         u8 noise[4];
823         u8 i;
824         u8 j;
825         s32 average;
826
827         /* Bottom half of Link Quality calculation. */
828
829         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
830         if (dev->noisecalc.channel_at_start != phy->channel)
831                 goto drop_calculation;
832         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
833         if (noise[0] == 0x7F || noise[1] == 0x7F ||
834             noise[2] == 0x7F || noise[3] == 0x7F)
835                 goto generate_new;
836
837         /* Get the noise samples. */
838         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
839         i = dev->noisecalc.nr_samples;
840         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
841         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
842         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
843         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
844         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
845         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
846         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
847         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
848         dev->noisecalc.nr_samples++;
849         if (dev->noisecalc.nr_samples == 8) {
850                 /* Calculate the Link Quality by the noise samples. */
851                 average = 0;
852                 for (i = 0; i < 8; i++) {
853                         for (j = 0; j < 4; j++)
854                                 average += dev->noisecalc.samples[i][j];
855                 }
856                 average /= (8 * 4);
857                 average *= 125;
858                 average += 64;
859                 average /= 128;
860                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
861                                              0x40C);
862                 tmp = (tmp / 128) & 0x1F;
863                 if (tmp >= 8)
864                         average += 2;
865                 else
866                         average -= 25;
867                 if (tmp == 8)
868                         average -= 72;
869                 else
870                         average -= 48;
871
872                 dev->stats.link_noise = average;
873 drop_calculation:
874                 dev->noisecalc.calculation_running = 0;
875                 return;
876         }
877 generate_new:
878         b43legacy_generate_noise_sample(dev);
879 }
880
881 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
882 {
883         if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
884                 /* TODO: PS TBTT */
885         } else {
886                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
887                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
888         }
889         dev->reg124_set_0x4 = 0;
890         if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
891                 dev->reg124_set_0x4 = 1;
892 }
893
894 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
895 {
896         if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
897                 return;
898         b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
899                           b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD)
900                           | 0x4);
901 }
902
903 static void handle_irq_pmq(struct b43legacy_wldev *dev)
904 {
905         u32 tmp;
906
907         /* TODO: AP mode. */
908
909         while (1) {
910                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
911                 if (!(tmp & 0x00000008))
912                         break;
913         }
914         /* 16bit write is odd, but correct. */
915         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
916 }
917
918 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
919                                             const u8 *data, u16 size,
920                                             u16 ram_offset,
921                                             u16 shm_size_offset, u8 rate)
922 {
923         u32 i;
924         u32 tmp;
925         struct b43legacy_plcp_hdr4 plcp;
926
927         plcp.data = 0;
928         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
929         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
930         ram_offset += sizeof(u32);
931         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
932          * So leave the first two bytes of the next write blank.
933          */
934         tmp = (u32)(data[0]) << 16;
935         tmp |= (u32)(data[1]) << 24;
936         b43legacy_ram_write(dev, ram_offset, tmp);
937         ram_offset += sizeof(u32);
938         for (i = 2; i < size; i += sizeof(u32)) {
939                 tmp = (u32)(data[i + 0]);
940                 if (i + 1 < size)
941                         tmp |= (u32)(data[i + 1]) << 8;
942                 if (i + 2 < size)
943                         tmp |= (u32)(data[i + 2]) << 16;
944                 if (i + 3 < size)
945                         tmp |= (u32)(data[i + 3]) << 24;
946                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
947         }
948         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
949                               size + sizeof(struct b43legacy_plcp_hdr6));
950 }
951
952 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
953                                             u16 ram_offset,
954                                             u16 shm_size_offset, u8 rate)
955 {
956         int len;
957         const u8 *data;
958
959         B43legacy_WARN_ON(!dev->cached_beacon);
960         len = min((size_t)dev->cached_beacon->len,
961                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
962         data = (const u8 *)(dev->cached_beacon->data);
963         b43legacy_write_template_common(dev, data,
964                                         len, ram_offset,
965                                         shm_size_offset, rate);
966 }
967
968 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
969                                             u16 shm_offset, u16 size,
970                                             u8 rate)
971 {
972         struct b43legacy_plcp_hdr4 plcp;
973         u32 tmp;
974         __le16 dur;
975
976         plcp.data = 0;
977         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
978         dur = ieee80211_generic_frame_duration(dev->wl->hw,
979                                                dev->wl->if_id,
980                                                size,
981                                                B43legacy_RATE_TO_100KBPS(rate));
982         /* Write PLCP in two parts and timing for packet transfer */
983         tmp = le32_to_cpu(plcp.data);
984         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
985                               tmp & 0xFFFF);
986         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
987                               tmp >> 16);
988         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
989                               le16_to_cpu(dur));
990 }
991
992 /* Instead of using custom probe response template, this function
993  * just patches custom beacon template by:
994  * 1) Changing packet type
995  * 2) Patching duration field
996  * 3) Stripping TIM
997  */
998 static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
999                                          u16 *dest_size, u8 rate)
1000 {
1001         const u8 *src_data;
1002         u8 *dest_data;
1003         u16 src_size;
1004         u16 elem_size;
1005         u16 src_pos;
1006         u16 dest_pos;
1007         __le16 dur;
1008         struct ieee80211_hdr *hdr;
1009
1010         B43legacy_WARN_ON(!dev->cached_beacon);
1011         src_size = dev->cached_beacon->len;
1012         src_data = (const u8 *)dev->cached_beacon->data;
1013
1014         if (unlikely(src_size < 0x24)) {
1015                 b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
1016                        "invalid beacon\n");
1017                 return NULL;
1018         }
1019
1020         dest_data = kmalloc(src_size, GFP_ATOMIC);
1021         if (unlikely(!dest_data))
1022                 return NULL;
1023
1024         /* 0x24 is offset of first variable-len Information-Element
1025          * in beacon frame.
1026          */
1027         memcpy(dest_data, src_data, 0x24);
1028         src_pos = 0x24;
1029         dest_pos = 0x24;
1030         for (; src_pos < src_size - 2; src_pos += elem_size) {
1031                 elem_size = src_data[src_pos + 1] + 2;
1032                 if (src_data[src_pos] != 0x05) { /* TIM */
1033                         memcpy(dest_data + dest_pos, src_data + src_pos,
1034                                elem_size);
1035                         dest_pos += elem_size;
1036                 }
1037         }
1038         *dest_size = dest_pos;
1039         hdr = (struct ieee80211_hdr *)dest_data;
1040
1041         /* Set the frame control. */
1042         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1043                                          IEEE80211_STYPE_PROBE_RESP);
1044         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1045                                                dev->wl->if_id,
1046                                                *dest_size,
1047                                                B43legacy_RATE_TO_100KBPS(rate));
1048         hdr->duration_id = dur;
1049
1050         return dest_data;
1051 }
1052
1053 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1054                                                 u16 ram_offset,
1055                                                 u16 shm_size_offset, u8 rate)
1056 {
1057         u8 *probe_resp_data;
1058         u16 size;
1059
1060         B43legacy_WARN_ON(!dev->cached_beacon);
1061         size = dev->cached_beacon->len;
1062         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1063         if (unlikely(!probe_resp_data))
1064                 return;
1065
1066         /* Looks like PLCP headers plus packet timings are stored for
1067          * all possible basic rates
1068          */
1069         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1070                                         B43legacy_CCK_RATE_1MB);
1071         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1072                                         B43legacy_CCK_RATE_2MB);
1073         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1074                                         B43legacy_CCK_RATE_5MB);
1075         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1076                                         B43legacy_CCK_RATE_11MB);
1077
1078         size = min((size_t)size,
1079                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1080         b43legacy_write_template_common(dev, probe_resp_data,
1081                                         size, ram_offset,
1082                                         shm_size_offset, rate);
1083         kfree(probe_resp_data);
1084 }
1085
1086 static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
1087                                            struct sk_buff *beacon)
1088 {
1089         if (dev->cached_beacon)
1090                 kfree_skb(dev->cached_beacon);
1091         dev->cached_beacon = beacon;
1092
1093         return 0;
1094 }
1095
1096 static void b43legacy_update_templates(struct b43legacy_wldev *dev)
1097 {
1098         u32 status;
1099
1100         B43legacy_WARN_ON(!dev->cached_beacon);
1101
1102         b43legacy_write_beacon_template(dev, 0x68, 0x18,
1103                                         B43legacy_CCK_RATE_1MB);
1104         b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1105                                         B43legacy_CCK_RATE_1MB);
1106         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1107                                             B43legacy_CCK_RATE_11MB);
1108
1109         status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
1110         status |= 0x03;
1111         b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD, status);
1112 }
1113
1114 static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
1115                                         struct sk_buff *beacon)
1116 {
1117         int err;
1118
1119         err = b43legacy_refresh_cached_beacon(dev, beacon);
1120         if (unlikely(err))
1121                 return;
1122         b43legacy_update_templates(dev);
1123 }
1124
1125 static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
1126                                const u8 *ssid, u8 ssid_len)
1127 {
1128         u32 tmp;
1129         u16 i;
1130         u16 len;
1131
1132         len = min((u16)ssid_len, (u16)0x100);
1133         for (i = 0; i < len; i += sizeof(u32)) {
1134                 tmp = (u32)(ssid[i + 0]);
1135                 if (i + 1 < len)
1136                         tmp |= (u32)(ssid[i + 1]) << 8;
1137                 if (i + 2 < len)
1138                         tmp |= (u32)(ssid[i + 2]) << 16;
1139                 if (i + 3 < len)
1140                         tmp |= (u32)(ssid[i + 3]) << 24;
1141                 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
1142                                       0x380 + i, tmp);
1143         }
1144         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1145                               0x48, len);
1146 }
1147
1148 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1149                                      u16 beacon_int)
1150 {
1151         b43legacy_time_lock(dev);
1152         if (dev->dev->id.revision >= 3)
1153                 b43legacy_write32(dev, 0x188, (beacon_int << 16));
1154         else {
1155                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1156                 b43legacy_write16(dev, 0x610, beacon_int);
1157         }
1158         b43legacy_time_unlock(dev);
1159 }
1160
1161 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1162 {
1163         u32 status;
1164
1165         if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1166                 return;
1167
1168         dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
1169         status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
1170
1171         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1172                 /* ACK beacon IRQ. */
1173                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1174                                   B43legacy_IRQ_BEACON);
1175                 dev->irq_savedstate |= B43legacy_IRQ_BEACON;
1176                 if (dev->cached_beacon)
1177                         kfree_skb(dev->cached_beacon);
1178                 dev->cached_beacon = NULL;
1179                 return;
1180         }
1181         if (!(status & 0x1)) {
1182                 b43legacy_write_beacon_template(dev, 0x68, 0x18,
1183                                                 B43legacy_CCK_RATE_1MB);
1184                 status |= 0x1;
1185                 b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
1186                                   status);
1187         }
1188         if (!(status & 0x2)) {
1189                 b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1190                                                 B43legacy_CCK_RATE_1MB);
1191                 status |= 0x2;
1192                 b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
1193                                   status);
1194         }
1195 }
1196
1197 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1198 {
1199 }
1200
1201 /* Interrupt handler bottom-half */
1202 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1203 {
1204         u32 reason;
1205         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1206         u32 merged_dma_reason = 0;
1207         int i;
1208         unsigned long flags;
1209
1210         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1211
1212         B43legacy_WARN_ON(b43legacy_status(dev) <
1213                           B43legacy_STAT_INITIALIZED);
1214
1215         reason = dev->irq_reason;
1216         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1217                 dma_reason[i] = dev->dma_reason[i];
1218                 merged_dma_reason |= dma_reason[i];
1219         }
1220
1221         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1222                 b43legacyerr(dev->wl, "MAC transmission error\n");
1223
1224         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR))
1225                 b43legacyerr(dev->wl, "PHY transmission error\n");
1226
1227         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1228                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1229                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1230                         b43legacyerr(dev->wl, "Fatal DMA error: "
1231                                "0x%08X, 0x%08X, 0x%08X, "
1232                                "0x%08X, 0x%08X, 0x%08X\n",
1233                                dma_reason[0], dma_reason[1],
1234                                dma_reason[2], dma_reason[3],
1235                                dma_reason[4], dma_reason[5]);
1236                         b43legacy_controller_restart(dev, "DMA error");
1237                         mmiowb();
1238                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1239                         return;
1240                 }
1241                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1242                         b43legacyerr(dev->wl, "DMA error: "
1243                                "0x%08X, 0x%08X, 0x%08X, "
1244                                "0x%08X, 0x%08X, 0x%08X\n",
1245                                dma_reason[0], dma_reason[1],
1246                                dma_reason[2], dma_reason[3],
1247                                dma_reason[4], dma_reason[5]);
1248         }
1249
1250         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1251                 handle_irq_ucode_debug(dev);
1252         if (reason & B43legacy_IRQ_TBTT_INDI)
1253                 handle_irq_tbtt_indication(dev);
1254         if (reason & B43legacy_IRQ_ATIM_END)
1255                 handle_irq_atim_end(dev);
1256         if (reason & B43legacy_IRQ_BEACON)
1257                 handle_irq_beacon(dev);
1258         if (reason & B43legacy_IRQ_PMQ)
1259                 handle_irq_pmq(dev);
1260         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1261                 ;/*TODO*/
1262         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1263                 handle_irq_noise(dev);
1264
1265         /* Check the DMA reason registers for received data. */
1266         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1267                 if (b43legacy_using_pio(dev))
1268                         b43legacy_pio_rx(dev->pio.queue0);
1269                 else
1270                         b43legacy_dma_rx(dev->dma.rx_ring0);
1271         }
1272         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1273         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1274         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1275                 if (b43legacy_using_pio(dev))
1276                         b43legacy_pio_rx(dev->pio.queue3);
1277                 else
1278                         b43legacy_dma_rx(dev->dma.rx_ring3);
1279         }
1280         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1281         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1282
1283         if (reason & B43legacy_IRQ_TX_OK)
1284                 handle_irq_transmit_status(dev);
1285
1286         b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1287         mmiowb();
1288         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1289 }
1290
1291 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1292                                u16 base, int queueidx)
1293 {
1294         u16 rxctl;
1295
1296         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1297         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1298                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1299         else
1300                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1301 }
1302
1303 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1304 {
1305         if (b43legacy_using_pio(dev) &&
1306             (dev->dev->id.revision < 3) &&
1307             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1308                 /* Apply a PIO specific workaround to the dma_reasons */
1309                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1310                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1311                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1312                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1313         }
1314
1315         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1316
1317         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1318                           dev->dma_reason[0]);
1319         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1320                           dev->dma_reason[1]);
1321         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1322                           dev->dma_reason[2]);
1323         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1324                           dev->dma_reason[3]);
1325         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1326                           dev->dma_reason[4]);
1327         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1328                           dev->dma_reason[5]);
1329 }
1330
1331 /* Interrupt handler top-half */
1332 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1333 {
1334         irqreturn_t ret = IRQ_NONE;
1335         struct b43legacy_wldev *dev = dev_id;
1336         u32 reason;
1337
1338         if (!dev)
1339                 return IRQ_NONE;
1340
1341         spin_lock(&dev->wl->irq_lock);
1342
1343         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
1344                 goto out;
1345         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1346         if (reason == 0xffffffff) /* shared IRQ */
1347                 goto out;
1348         ret = IRQ_HANDLED;
1349         reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1350         if (!reason)
1351                 goto out;
1352
1353         dev->dma_reason[0] = b43legacy_read32(dev,
1354                                               B43legacy_MMIO_DMA0_REASON)
1355                                               & 0x0001DC00;
1356         dev->dma_reason[1] = b43legacy_read32(dev,
1357                                               B43legacy_MMIO_DMA1_REASON)
1358                                               & 0x0000DC00;
1359         dev->dma_reason[2] = b43legacy_read32(dev,
1360                                               B43legacy_MMIO_DMA2_REASON)
1361                                               & 0x0000DC00;
1362         dev->dma_reason[3] = b43legacy_read32(dev,
1363                                               B43legacy_MMIO_DMA3_REASON)
1364                                               & 0x0001DC00;
1365         dev->dma_reason[4] = b43legacy_read32(dev,
1366                                               B43legacy_MMIO_DMA4_REASON)
1367                                               & 0x0000DC00;
1368         dev->dma_reason[5] = b43legacy_read32(dev,
1369                                               B43legacy_MMIO_DMA5_REASON)
1370                                               & 0x0000DC00;
1371
1372         b43legacy_interrupt_ack(dev, reason);
1373         /* disable all IRQs. They are enabled again in the bottom half. */
1374         dev->irq_savedstate = b43legacy_interrupt_disable(dev,
1375                                                           B43legacy_IRQ_ALL);
1376         /* save the reason code and call our bottom half. */
1377         dev->irq_reason = reason;
1378         tasklet_schedule(&dev->isr_tasklet);
1379 out:
1380         mmiowb();
1381         spin_unlock(&dev->wl->irq_lock);
1382
1383         return ret;
1384 }
1385
1386 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1387 {
1388         release_firmware(dev->fw.ucode);
1389         dev->fw.ucode = NULL;
1390         release_firmware(dev->fw.pcm);
1391         dev->fw.pcm = NULL;
1392         release_firmware(dev->fw.initvals);
1393         dev->fw.initvals = NULL;
1394         release_firmware(dev->fw.initvals_band);
1395         dev->fw.initvals_band = NULL;
1396 }
1397
1398 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1399 {
1400         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1401                      "Drivers/b43#devicefirmware "
1402                      "and download the correct firmware (version 3).\n");
1403 }
1404
1405 static int do_request_fw(struct b43legacy_wldev *dev,
1406                          const char *name,
1407                          const struct firmware **fw)
1408 {
1409         char path[sizeof(modparam_fwpostfix) + 32];
1410         struct b43legacy_fw_header *hdr;
1411         u32 size;
1412         int err;
1413
1414         if (!name)
1415                 return 0;
1416
1417         snprintf(path, ARRAY_SIZE(path),
1418                  "b43legacy%s/%s.fw",
1419                  modparam_fwpostfix, name);
1420         err = request_firmware(fw, path, dev->dev->dev);
1421         if (err) {
1422                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1423                        "or load failed.\n", path);
1424                 return err;
1425         }
1426         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1427                 goto err_format;
1428         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1429         switch (hdr->type) {
1430         case B43legacy_FW_TYPE_UCODE:
1431         case B43legacy_FW_TYPE_PCM:
1432                 size = be32_to_cpu(hdr->size);
1433                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1434                         goto err_format;
1435                 /* fallthrough */
1436         case B43legacy_FW_TYPE_IV:
1437                 if (hdr->ver != 1)
1438                         goto err_format;
1439                 break;
1440         default:
1441                 goto err_format;
1442         }
1443
1444         return err;
1445
1446 err_format:
1447         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1448         return -EPROTO;
1449 }
1450
1451 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1452 {
1453         struct b43legacy_firmware *fw = &dev->fw;
1454         const u8 rev = dev->dev->id.revision;
1455         const char *filename;
1456         u32 tmshigh;
1457         int err;
1458
1459         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1460         if (!fw->ucode) {
1461                 if (rev == 2)
1462                         filename = "ucode2";
1463                 else if (rev == 4)
1464                         filename = "ucode4";
1465                 else
1466                         filename = "ucode5";
1467                 err = do_request_fw(dev, filename, &fw->ucode);
1468                 if (err)
1469                         goto err_load;
1470         }
1471         if (!fw->pcm) {
1472                 if (rev < 5)
1473                         filename = "pcm4";
1474                 else
1475                         filename = "pcm5";
1476                 err = do_request_fw(dev, filename, &fw->pcm);
1477                 if (err)
1478                         goto err_load;
1479         }
1480         if (!fw->initvals) {
1481                 switch (dev->phy.type) {
1482                 case B43legacy_PHYTYPE_G:
1483                         if ((rev >= 5) && (rev <= 10))
1484                                 filename = "b0g0initvals5";
1485                         else if (rev == 2 || rev == 4)
1486                                 filename = "b0g0initvals2";
1487                         else
1488                                 goto err_no_initvals;
1489                         break;
1490                 default:
1491                         goto err_no_initvals;
1492                 }
1493                 err = do_request_fw(dev, filename, &fw->initvals);
1494                 if (err)
1495                         goto err_load;
1496         }
1497         if (!fw->initvals_band) {
1498                 switch (dev->phy.type) {
1499                 case B43legacy_PHYTYPE_G:
1500                         if ((rev >= 5) && (rev <= 10))
1501                                 filename = "b0g0bsinitvals5";
1502                         else if (rev >= 11)
1503                                 filename = NULL;
1504                         else if (rev == 2 || rev == 4)
1505                                 filename = NULL;
1506                         else
1507                                 goto err_no_initvals;
1508                         break;
1509                 default:
1510                         goto err_no_initvals;
1511                 }
1512                 err = do_request_fw(dev, filename, &fw->initvals_band);
1513                 if (err)
1514                         goto err_load;
1515         }
1516
1517         return 0;
1518
1519 err_load:
1520         b43legacy_print_fw_helptext(dev->wl);
1521         goto error;
1522
1523 err_no_initvals:
1524         err = -ENODEV;
1525         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1526                "core rev %u\n", dev->phy.type, rev);
1527         goto error;
1528
1529 error:
1530         b43legacy_release_firmware(dev);
1531         return err;
1532 }
1533
1534 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1535 {
1536         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1537         const __be32 *data;
1538         unsigned int i;
1539         unsigned int len;
1540         u16 fwrev;
1541         u16 fwpatch;
1542         u16 fwdate;
1543         u16 fwtime;
1544         u32 tmp;
1545         int err = 0;
1546
1547         /* Upload Microcode. */
1548         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1549         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1550         b43legacy_shm_control_word(dev,
1551                                    B43legacy_SHM_UCODE |
1552                                    B43legacy_SHM_AUTOINC_W,
1553                                    0x0000);
1554         for (i = 0; i < len; i++) {
1555                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1556                                     be32_to_cpu(data[i]));
1557                 udelay(10);
1558         }
1559
1560         if (dev->fw.pcm) {
1561                 /* Upload PCM data. */
1562                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1563                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1564                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1565                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1566                 /* No need for autoinc bit in SHM_HW */
1567                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1568                 for (i = 0; i < len; i++) {
1569                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1570                                           be32_to_cpu(data[i]));
1571                         udelay(10);
1572                 }
1573         }
1574
1575         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1576                           B43legacy_IRQ_ALL);
1577         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0x00020402);
1578
1579         /* Wait for the microcode to load and respond */
1580         i = 0;
1581         while (1) {
1582                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1583                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1584                         break;
1585                 i++;
1586                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1587                         b43legacyerr(dev->wl, "Microcode not responding\n");
1588                         b43legacy_print_fw_helptext(dev->wl);
1589                         err = -ENODEV;
1590                         goto out;
1591                 }
1592                 udelay(10);
1593         }
1594         /* dummy read follows */
1595         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1596
1597         /* Get and check the revisions. */
1598         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1599                                      B43legacy_SHM_SH_UCODEREV);
1600         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1601                                        B43legacy_SHM_SH_UCODEPATCH);
1602         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1603                                       B43legacy_SHM_SH_UCODEDATE);
1604         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1605                                       B43legacy_SHM_SH_UCODETIME);
1606
1607         if (fwrev > 0x128) {
1608                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1609                              " Only firmware from binary drivers version 3.x"
1610                              " is supported. You must change your firmware"
1611                              " files.\n");
1612                 b43legacy_print_fw_helptext(dev->wl);
1613                 b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0);
1614                 err = -EOPNOTSUPP;
1615                 goto out;
1616         }
1617         b43legacydbg(dev->wl, "Loading firmware version 0x%X, patch level %u "
1618                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1619                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1620                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1621
1622         dev->fw.rev = fwrev;
1623         dev->fw.patch = fwpatch;
1624
1625 out:
1626         return err;
1627 }
1628
1629 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1630                                     const struct b43legacy_iv *ivals,
1631                                     size_t count,
1632                                     size_t array_size)
1633 {
1634         const struct b43legacy_iv *iv;
1635         u16 offset;
1636         size_t i;
1637         bool bit32;
1638
1639         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1640         iv = ivals;
1641         for (i = 0; i < count; i++) {
1642                 if (array_size < sizeof(iv->offset_size))
1643                         goto err_format;
1644                 array_size -= sizeof(iv->offset_size);
1645                 offset = be16_to_cpu(iv->offset_size);
1646                 bit32 = !!(offset & B43legacy_IV_32BIT);
1647                 offset &= B43legacy_IV_OFFSET_MASK;
1648                 if (offset >= 0x1000)
1649                         goto err_format;
1650                 if (bit32) {
1651                         u32 value;
1652
1653                         if (array_size < sizeof(iv->data.d32))
1654                                 goto err_format;
1655                         array_size -= sizeof(iv->data.d32);
1656
1657                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1658                         b43legacy_write32(dev, offset, value);
1659
1660                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1661                                                         sizeof(__be16) +
1662                                                         sizeof(__be32));
1663                 } else {
1664                         u16 value;
1665
1666                         if (array_size < sizeof(iv->data.d16))
1667                                 goto err_format;
1668                         array_size -= sizeof(iv->data.d16);
1669
1670                         value = be16_to_cpu(iv->data.d16);
1671                         b43legacy_write16(dev, offset, value);
1672
1673                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1674                                                         sizeof(__be16) +
1675                                                         sizeof(__be16));
1676                 }
1677         }
1678         if (array_size)
1679                 goto err_format;
1680
1681         return 0;
1682
1683 err_format:
1684         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1685         b43legacy_print_fw_helptext(dev->wl);
1686
1687         return -EPROTO;
1688 }
1689
1690 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1691 {
1692         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1693         const struct b43legacy_fw_header *hdr;
1694         struct b43legacy_firmware *fw = &dev->fw;
1695         const struct b43legacy_iv *ivals;
1696         size_t count;
1697         int err;
1698
1699         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1700         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1701         count = be32_to_cpu(hdr->size);
1702         err = b43legacy_write_initvals(dev, ivals, count,
1703                                  fw->initvals->size - hdr_len);
1704         if (err)
1705                 goto out;
1706         if (fw->initvals_band) {
1707                 hdr = (const struct b43legacy_fw_header *)
1708                       (fw->initvals_band->data);
1709                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1710                         + hdr_len);
1711                 count = be32_to_cpu(hdr->size);
1712                 err = b43legacy_write_initvals(dev, ivals, count,
1713                                          fw->initvals_band->size - hdr_len);
1714                 if (err)
1715                         goto out;
1716         }
1717 out:
1718
1719         return err;
1720 }
1721
1722 /* Initialize the GPIOs
1723  * http://bcm-specs.sipsolutions.net/GPIO
1724  */
1725 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1726 {
1727         struct ssb_bus *bus = dev->dev->bus;
1728         struct ssb_device *gpiodev, *pcidev = NULL;
1729         u32 mask;
1730         u32 set;
1731
1732         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
1733                           b43legacy_read32(dev,
1734                           B43legacy_MMIO_STATUS_BITFIELD)
1735                           & 0xFFFF3FFF);
1736
1737         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1738                           b43legacy_read16(dev,
1739                           B43legacy_MMIO_GPIO_MASK)
1740                           | 0x000F);
1741
1742         mask = 0x0000001F;
1743         set = 0x0000000F;
1744         if (dev->dev->bus->chip_id == 0x4301) {
1745                 mask |= 0x0060;
1746                 set |= 0x0060;
1747         }
1748         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1749                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1750                                   b43legacy_read16(dev,
1751                                   B43legacy_MMIO_GPIO_MASK)
1752                                   | 0x0200);
1753                 mask |= 0x0200;
1754                 set |= 0x0200;
1755         }
1756         if (dev->dev->id.revision >= 2)
1757                 mask  |= 0x0010; /* FIXME: This is redundant. */
1758
1759 #ifdef CONFIG_SSB_DRIVER_PCICORE
1760         pcidev = bus->pcicore.dev;
1761 #endif
1762         gpiodev = bus->chipco.dev ? : pcidev;
1763         if (!gpiodev)
1764                 return 0;
1765         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1766                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1767                      & mask) | set);
1768
1769         return 0;
1770 }
1771
1772 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1773 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1774 {
1775         struct ssb_bus *bus = dev->dev->bus;
1776         struct ssb_device *gpiodev, *pcidev = NULL;
1777
1778 #ifdef CONFIG_SSB_DRIVER_PCICORE
1779         pcidev = bus->pcicore.dev;
1780 #endif
1781         gpiodev = bus->chipco.dev ? : pcidev;
1782         if (!gpiodev)
1783                 return;
1784         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1785 }
1786
1787 /* http://bcm-specs.sipsolutions.net/EnableMac */
1788 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1789 {
1790         dev->mac_suspended--;
1791         B43legacy_WARN_ON(dev->mac_suspended < 0);
1792         B43legacy_WARN_ON(irqs_disabled());
1793         if (dev->mac_suspended == 0) {
1794                 b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
1795                                   b43legacy_read32(dev,
1796                                   B43legacy_MMIO_STATUS_BITFIELD)
1797                                   | B43legacy_SBF_MAC_ENABLED);
1798                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1799                                   B43legacy_IRQ_MAC_SUSPENDED);
1800                 /* the next two are dummy reads */
1801                 b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
1802                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1803                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1804
1805                 /* Re-enable IRQs. */
1806                 spin_lock_irq(&dev->wl->irq_lock);
1807                 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1808                 spin_unlock_irq(&dev->wl->irq_lock);
1809         }
1810 }
1811
1812 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1813 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1814 {
1815         int i;
1816         u32 tmp;
1817
1818         might_sleep();
1819         B43legacy_WARN_ON(irqs_disabled());
1820         B43legacy_WARN_ON(dev->mac_suspended < 0);
1821
1822         if (dev->mac_suspended == 0) {
1823                 /* Mask IRQs before suspending MAC. Otherwise
1824                  * the MAC stays busy and won't suspend. */
1825                 spin_lock_irq(&dev->wl->irq_lock);
1826                 tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
1827                 spin_unlock_irq(&dev->wl->irq_lock);
1828                 b43legacy_synchronize_irq(dev);
1829                 dev->irq_savedstate = tmp;
1830
1831                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1832                 b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
1833                                   b43legacy_read32(dev,
1834                                   B43legacy_MMIO_STATUS_BITFIELD)
1835                                   & ~B43legacy_SBF_MAC_ENABLED);
1836                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1837                 for (i = 40; i; i--) {
1838                         tmp = b43legacy_read32(dev,
1839                                                B43legacy_MMIO_GEN_IRQ_REASON);
1840                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1841                                 goto out;
1842                         msleep(1);
1843                 }
1844                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1845         }
1846 out:
1847         dev->mac_suspended++;
1848 }
1849
1850 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1851 {
1852         struct b43legacy_wl *wl = dev->wl;
1853         u32 ctl;
1854         u16 cfp_pretbtt;
1855
1856         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1857         /* Reset status to STA infrastructure mode. */
1858         ctl &= ~B43legacy_MACCTL_AP;
1859         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1860         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1861         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1862         ctl &= ~B43legacy_MACCTL_PROMISC;
1863         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
1864         ctl |= B43legacy_MACCTL_INFRA;
1865
1866         if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
1867                 ctl |= B43legacy_MACCTL_AP;
1868         else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
1869                 ctl &= ~B43legacy_MACCTL_INFRA;
1870
1871         if (wl->filter_flags & FIF_CONTROL)
1872                 ctl |= B43legacy_MACCTL_KEEP_CTL;
1873         if (wl->filter_flags & FIF_FCSFAIL)
1874                 ctl |= B43legacy_MACCTL_KEEP_BAD;
1875         if (wl->filter_flags & FIF_PLCPFAIL)
1876                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1877         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
1878                 ctl |= B43legacy_MACCTL_PROMISC;
1879         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1880                 ctl |= B43legacy_MACCTL_BEACPROMISC;
1881
1882         /* Workaround: On old hardware the HW-MAC-address-filter
1883          * doesn't work properly, so always run promisc in filter
1884          * it in software. */
1885         if (dev->dev->id.revision <= 4)
1886                 ctl |= B43legacy_MACCTL_PROMISC;
1887
1888         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
1889
1890         cfp_pretbtt = 2;
1891         if ((ctl & B43legacy_MACCTL_INFRA) &&
1892             !(ctl & B43legacy_MACCTL_AP)) {
1893                 if (dev->dev->bus->chip_id == 0x4306 &&
1894                     dev->dev->bus->chip_rev == 3)
1895                         cfp_pretbtt = 100;
1896                 else
1897                         cfp_pretbtt = 50;
1898         }
1899         b43legacy_write16(dev, 0x612, cfp_pretbtt);
1900 }
1901
1902 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
1903                                         u16 rate,
1904                                         int is_ofdm)
1905 {
1906         u16 offset;
1907
1908         if (is_ofdm) {
1909                 offset = 0x480;
1910                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1911         } else {
1912                 offset = 0x4C0;
1913                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1914         }
1915         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
1916                               b43legacy_shm_read16(dev,
1917                               B43legacy_SHM_SHARED, offset));
1918 }
1919
1920 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
1921 {
1922         switch (dev->phy.type) {
1923         case B43legacy_PHYTYPE_G:
1924                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
1925                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
1926                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
1927                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
1928                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
1929                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
1930                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
1931                 /* fallthrough */
1932         case B43legacy_PHYTYPE_B:
1933                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
1934                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
1935                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
1936                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
1937                 break;
1938         default:
1939                 B43legacy_BUG_ON(1);
1940         }
1941 }
1942
1943 /* Set the TX-Antenna for management frames sent by firmware. */
1944 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
1945                                           int antenna)
1946 {
1947         u16 ant = 0;
1948         u16 tmp;
1949
1950         switch (antenna) {
1951         case B43legacy_ANTENNA0:
1952                 ant |= B43legacy_TX4_PHY_ANT0;
1953                 break;
1954         case B43legacy_ANTENNA1:
1955                 ant |= B43legacy_TX4_PHY_ANT1;
1956                 break;
1957         case B43legacy_ANTENNA_AUTO:
1958                 ant |= B43legacy_TX4_PHY_ANTLAST;
1959                 break;
1960         default:
1961                 B43legacy_BUG_ON(1);
1962         }
1963
1964         /* FIXME We also need to set the other flags of the PHY control
1965          * field somewhere. */
1966
1967         /* For Beacons */
1968         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1969                                    B43legacy_SHM_SH_BEACPHYCTL);
1970         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
1971         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1972                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
1973         /* For ACK/CTS */
1974         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1975                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
1976         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
1977         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1978                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
1979         /* For Probe Resposes */
1980         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1981                                    B43legacy_SHM_SH_PRPHYCTL);
1982         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
1983         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1984                               B43legacy_SHM_SH_PRPHYCTL, tmp);
1985 }
1986
1987 /* This is the opposite of b43legacy_chip_init() */
1988 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
1989 {
1990         b43legacy_radio_turn_off(dev, 1);
1991         b43legacy_leds_exit(dev);
1992         b43legacy_gpio_cleanup(dev);
1993         /* firmware is released later */
1994 }
1995
1996 /* Initialize the chip
1997  * http://bcm-specs.sipsolutions.net/ChipInit
1998  */
1999 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2000 {
2001         struct b43legacy_phy *phy = &dev->phy;
2002         int err;
2003         int tmp;
2004         u32 value32;
2005         u16 value16;
2006
2007         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
2008                           B43legacy_SBF_CORE_READY
2009                           | B43legacy_SBF_400);
2010
2011         err = b43legacy_request_firmware(dev);
2012         if (err)
2013                 goto out;
2014         err = b43legacy_upload_microcode(dev);
2015         if (err)
2016                 goto out; /* firmware is released later */
2017
2018         err = b43legacy_gpio_init(dev);
2019         if (err)
2020                 goto out; /* firmware is released later */
2021         b43legacy_leds_init(dev);
2022
2023         err = b43legacy_upload_initvals(dev);
2024         if (err)
2025                 goto err_leds_exit;
2026         b43legacy_radio_turn_on(dev);
2027
2028         b43legacy_write16(dev, 0x03E6, 0x0000);
2029         err = b43legacy_phy_init(dev);
2030         if (err)
2031                 goto err_radio_off;
2032
2033         /* Select initial Interference Mitigation. */
2034         tmp = phy->interfmode;
2035         phy->interfmode = B43legacy_INTERFMODE_NONE;
2036         b43legacy_radio_set_interference_mitigation(dev, tmp);
2037
2038         b43legacy_phy_set_antenna_diversity(dev);
2039         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2040
2041         if (phy->type == B43legacy_PHYTYPE_B) {
2042                 value16 = b43legacy_read16(dev, 0x005E);
2043                 value16 |= 0x0004;
2044                 b43legacy_write16(dev, 0x005E, value16);
2045         }
2046         b43legacy_write32(dev, 0x0100, 0x01000000);
2047         if (dev->dev->id.revision < 5)
2048                 b43legacy_write32(dev, 0x010C, 0x01000000);
2049
2050         value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
2051         value32 &= ~B43legacy_SBF_MODE_NOTADHOC;
2052         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
2053         value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
2054         value32 |= B43legacy_SBF_MODE_NOTADHOC;
2055         b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
2056
2057         if (b43legacy_using_pio(dev)) {
2058                 b43legacy_write32(dev, 0x0210, 0x00000100);
2059                 b43legacy_write32(dev, 0x0230, 0x00000100);
2060                 b43legacy_write32(dev, 0x0250, 0x00000100);
2061                 b43legacy_write32(dev, 0x0270, 0x00000100);
2062                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2063                                       0x0000);
2064         }
2065
2066         /* Probe Response Timeout value */
2067         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2068         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2069
2070         /* Initially set the wireless operation mode. */
2071         b43legacy_adjust_opmode(dev);
2072
2073         if (dev->dev->id.revision < 3) {
2074                 b43legacy_write16(dev, 0x060E, 0x0000);
2075                 b43legacy_write16(dev, 0x0610, 0x8000);
2076                 b43legacy_write16(dev, 0x0604, 0x0000);
2077                 b43legacy_write16(dev, 0x0606, 0x0200);
2078         } else {
2079                 b43legacy_write32(dev, 0x0188, 0x80000000);
2080                 b43legacy_write32(dev, 0x018C, 0x02000000);
2081         }
2082         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2083         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2084         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2085         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2086         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2087         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2088         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2089
2090         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2091         value32 |= 0x00100000;
2092         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2093
2094         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2095                           dev->dev->bus->chipco.fast_pwrup_delay);
2096
2097         B43legacy_WARN_ON(err != 0);
2098         b43legacydbg(dev->wl, "Chip initialized\n");
2099 out:
2100         return err;
2101
2102 err_radio_off:
2103         b43legacy_radio_turn_off(dev, 1);
2104 err_leds_exit:
2105         b43legacy_leds_exit(dev);
2106         b43legacy_gpio_cleanup(dev);
2107         goto out;
2108 }
2109
2110 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2111 {
2112         struct b43legacy_phy *phy = &dev->phy;
2113
2114         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2115                 return;
2116
2117         b43legacy_mac_suspend(dev);
2118         b43legacy_phy_lo_g_measure(dev);
2119         b43legacy_mac_enable(dev);
2120 }
2121
2122 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2123 {
2124         b43legacy_phy_lo_mark_all_unused(dev);
2125         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2126                 b43legacy_mac_suspend(dev);
2127                 b43legacy_calc_nrssi_slope(dev);
2128                 b43legacy_mac_enable(dev);
2129         }
2130 }
2131
2132 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2133 {
2134         /* Update device statistics. */
2135         b43legacy_calculate_link_quality(dev);
2136 }
2137
2138 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2139 {
2140         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2141 }
2142
2143 static void do_periodic_work(struct b43legacy_wldev *dev)
2144 {
2145         unsigned int state;
2146
2147         state = dev->periodic_state;
2148         if (state % 8 == 0)
2149                 b43legacy_periodic_every120sec(dev);
2150         if (state % 4 == 0)
2151                 b43legacy_periodic_every60sec(dev);
2152         if (state % 2 == 0)
2153                 b43legacy_periodic_every30sec(dev);
2154         b43legacy_periodic_every15sec(dev);
2155 }
2156
2157 /* Periodic work locking policy:
2158  *      The whole periodic work handler is protected by
2159  *      wl->mutex. If another lock is needed somewhere in the
2160  *      pwork callchain, it's aquired in-place, where it's needed.
2161  */
2162 static void b43legacy_periodic_work_handler(struct work_struct *work)
2163 {
2164         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2165                                              periodic_work.work);
2166         struct b43legacy_wl *wl = dev->wl;
2167         unsigned long delay;
2168
2169         mutex_lock(&wl->mutex);
2170
2171         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2172                 goto out;
2173         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2174                 goto out_requeue;
2175
2176         do_periodic_work(dev);
2177
2178         dev->periodic_state++;
2179 out_requeue:
2180         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2181                 delay = msecs_to_jiffies(50);
2182         else
2183                 delay = round_jiffies_relative(HZ * 15);
2184         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2185 out:
2186         mutex_unlock(&wl->mutex);
2187 }
2188
2189 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2190 {
2191         struct delayed_work *work = &dev->periodic_work;
2192
2193         dev->periodic_state = 0;
2194         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2195         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2196 }
2197
2198 /* Validate access to the chip (SHM) */
2199 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2200 {
2201         u32 value;
2202         u32 shm_backup;
2203
2204         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2205         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2206         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2207                                  0xAA5555AA)
2208                 goto error;
2209         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2210         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2211                                  0x55AAAA55)
2212                 goto error;
2213         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2214
2215         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2216         if ((value | B43legacy_MACCTL_GMODE) !=
2217             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2218                 goto error;
2219
2220         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2221         if (value)
2222                 goto error;
2223
2224         return 0;
2225 error:
2226         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2227         return -ENODEV;
2228 }
2229
2230 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2231 {
2232         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2233         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2234         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2235                                         0x0056);
2236         /* KTP is a word address, but we address SHM bytewise.
2237          * So multiply by two.
2238          */
2239         dev->ktp *= 2;
2240         if (dev->dev->id.revision >= 5)
2241                 /* Number of RCMTA address slots */
2242                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2243                                   dev->max_nr_keys - 8);
2244 }
2245
2246 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2247 {
2248         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2249         unsigned long flags;
2250
2251         /* Don't take wl->mutex here, as it could deadlock with
2252          * hwrng internal locking. It's not needed to take
2253          * wl->mutex here, anyway. */
2254
2255         spin_lock_irqsave(&wl->irq_lock, flags);
2256         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2257         spin_unlock_irqrestore(&wl->irq_lock, flags);
2258
2259         return (sizeof(u16));
2260 }
2261
2262 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2263 {
2264         if (wl->rng_initialized)
2265                 hwrng_unregister(&wl->rng);
2266 }
2267
2268 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2269 {
2270         int err;
2271
2272         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2273                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2274         wl->rng.name = wl->rng_name;
2275         wl->rng.data_read = b43legacy_rng_read;
2276         wl->rng.priv = (unsigned long)wl;
2277         wl->rng_initialized = 1;
2278         err = hwrng_register(&wl->rng);
2279         if (err) {
2280                 wl->rng_initialized = 0;
2281                 b43legacyerr(wl, "Failed to register the random "
2282                        "number generator (%d)\n", err);
2283         }
2284
2285         return err;
2286 }
2287
2288 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2289                            struct sk_buff *skb,
2290                            struct ieee80211_tx_control *ctl)
2291 {
2292         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2293         struct b43legacy_wldev *dev = wl->current_dev;
2294         int err = -ENODEV;
2295         unsigned long flags;
2296
2297         if (unlikely(!dev))
2298                 goto out;
2299         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2300                 goto out;
2301         /* DMA-TX is done without a global lock. */
2302         if (b43legacy_using_pio(dev)) {
2303                 spin_lock_irqsave(&wl->irq_lock, flags);
2304                 err = b43legacy_pio_tx(dev, skb, ctl);
2305                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2306         } else
2307                 err = b43legacy_dma_tx(dev, skb, ctl);
2308 out:
2309         if (unlikely(err))
2310                 return NETDEV_TX_BUSY;
2311         return NETDEV_TX_OK;
2312 }
2313
2314 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2315                                 int queue,
2316                                 const struct ieee80211_tx_queue_params *params)
2317 {
2318         return 0;
2319 }
2320
2321 static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2322                                      struct ieee80211_tx_queue_stats *stats)
2323 {
2324         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2325         struct b43legacy_wldev *dev = wl->current_dev;
2326         unsigned long flags;
2327         int err = -ENODEV;
2328
2329         if (!dev)
2330                 goto out;
2331         spin_lock_irqsave(&wl->irq_lock, flags);
2332         if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2333                 if (b43legacy_using_pio(dev))
2334                         b43legacy_pio_get_tx_stats(dev, stats);
2335                 else
2336                         b43legacy_dma_get_tx_stats(dev, stats);
2337                 err = 0;
2338         }
2339         spin_unlock_irqrestore(&wl->irq_lock, flags);
2340 out:
2341         return err;
2342 }
2343
2344 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2345                                   struct ieee80211_low_level_stats *stats)
2346 {
2347         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2348         unsigned long flags;
2349
2350         spin_lock_irqsave(&wl->irq_lock, flags);
2351         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2352         spin_unlock_irqrestore(&wl->irq_lock, flags);
2353
2354         return 0;
2355 }
2356
2357 static const char *phymode_to_string(unsigned int phymode)
2358 {
2359         switch (phymode) {
2360         case B43legacy_PHYMODE_B:
2361                 return "B";
2362         case B43legacy_PHYMODE_G:
2363                 return "G";
2364         default:
2365                 B43legacy_BUG_ON(1);
2366         }
2367         return "";
2368 }
2369
2370 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2371                                   unsigned int phymode,
2372                                   struct b43legacy_wldev **dev,
2373                                   bool *gmode)
2374 {
2375         struct b43legacy_wldev *d;
2376
2377         list_for_each_entry(d, &wl->devlist, list) {
2378                 if (d->phy.possible_phymodes & phymode) {
2379                         /* Ok, this device supports the PHY-mode.
2380                          * Set the gmode bit. */
2381                         *gmode = 1;
2382                         *dev = d;
2383
2384                         return 0;
2385                 }
2386         }
2387
2388         return -ESRCH;
2389 }
2390
2391 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2392 {
2393         struct ssb_device *sdev = dev->dev;
2394         u32 tmslow;
2395
2396         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2397         tmslow &= ~B43legacy_TMSLOW_GMODE;
2398         tmslow |= B43legacy_TMSLOW_PHYRESET;
2399         tmslow |= SSB_TMSLOW_FGC;
2400         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2401         msleep(1);
2402
2403         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2404         tmslow &= ~SSB_TMSLOW_FGC;
2405         tmslow |= B43legacy_TMSLOW_PHYRESET;
2406         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2407         msleep(1);
2408 }
2409
2410 /* Expects wl->mutex locked */
2411 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2412                                       unsigned int new_mode)
2413 {
2414         struct b43legacy_wldev *up_dev;
2415         struct b43legacy_wldev *down_dev;
2416         int err;
2417         bool gmode = 0;
2418         int prev_status;
2419
2420         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2421         if (err) {
2422                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2423                        phymode_to_string(new_mode));
2424                 return err;
2425         }
2426         if ((up_dev == wl->current_dev) &&
2427             (!!wl->current_dev->phy.gmode == !!gmode))
2428                 /* This device is already running. */
2429                 return 0;
2430         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2431                phymode_to_string(new_mode));
2432         down_dev = wl->current_dev;
2433
2434         prev_status = b43legacy_status(down_dev);
2435         /* Shutdown the currently running core. */
2436         if (prev_status >= B43legacy_STAT_STARTED)
2437                 b43legacy_wireless_core_stop(down_dev);
2438         if (prev_status >= B43legacy_STAT_INITIALIZED)
2439                 b43legacy_wireless_core_exit(down_dev);
2440
2441         if (down_dev != up_dev)
2442                 /* We switch to a different core, so we put PHY into
2443                  * RESET on the old core. */
2444                 b43legacy_put_phy_into_reset(down_dev);
2445
2446         /* Now start the new core. */
2447         up_dev->phy.gmode = gmode;
2448         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2449                 err = b43legacy_wireless_core_init(up_dev);
2450                 if (err) {
2451                         b43legacyerr(wl, "Fatal: Could not initialize device"
2452                                      " for newly selected %s-PHY mode\n",
2453                                      phymode_to_string(new_mode));
2454                         goto init_failure;
2455                 }
2456         }
2457         if (prev_status >= B43legacy_STAT_STARTED) {
2458                 err = b43legacy_wireless_core_start(up_dev);
2459                 if (err) {
2460                         b43legacyerr(wl, "Fatal: Coult not start device for "
2461                                "newly selected %s-PHY mode\n",
2462                                phymode_to_string(new_mode));
2463                         b43legacy_wireless_core_exit(up_dev);
2464                         goto init_failure;
2465                 }
2466         }
2467         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2468
2469         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2470
2471         wl->current_dev = up_dev;
2472
2473         return 0;
2474 init_failure:
2475         /* Whoops, failed to init the new core. No core is operating now. */
2476         wl->current_dev = NULL;
2477         return err;
2478 }
2479
2480 static int b43legacy_antenna_from_ieee80211(u8 antenna)
2481 {
2482         switch (antenna) {
2483         case 0: /* default/diversity */
2484                 return B43legacy_ANTENNA_DEFAULT;
2485         case 1: /* Antenna 0 */
2486                 return B43legacy_ANTENNA0;
2487         case 2: /* Antenna 1 */
2488                 return B43legacy_ANTENNA1;
2489         default:
2490                 return B43legacy_ANTENNA_DEFAULT;
2491         }
2492 }
2493
2494 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2495                                    struct ieee80211_conf *conf)
2496 {
2497         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2498         struct b43legacy_wldev *dev;
2499         struct b43legacy_phy *phy;
2500         unsigned long flags;
2501         unsigned int new_phymode = 0xFFFF;
2502         int antenna_tx;
2503         int antenna_rx;
2504         int err = 0;
2505         u32 savedirqs;
2506
2507         antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
2508         antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
2509
2510         mutex_lock(&wl->mutex);
2511
2512         /* Switch the PHY mode (if necessary). */
2513         switch (conf->phymode) {
2514         case MODE_IEEE80211B:
2515                 new_phymode = B43legacy_PHYMODE_B;
2516                 break;
2517         case MODE_IEEE80211G:
2518                 new_phymode = B43legacy_PHYMODE_G;
2519                 break;
2520         default:
2521                 B43legacy_WARN_ON(1);
2522         }
2523         err = b43legacy_switch_phymode(wl, new_phymode);
2524         if (err)
2525                 goto out_unlock_mutex;
2526         dev = wl->current_dev;
2527         phy = &dev->phy;
2528
2529         /* Disable IRQs while reconfiguring the device.
2530          * This makes it possible to drop the spinlock throughout
2531          * the reconfiguration process. */
2532         spin_lock_irqsave(&wl->irq_lock, flags);
2533         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2534                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2535                 goto out_unlock_mutex;
2536         }
2537         savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2538         spin_unlock_irqrestore(&wl->irq_lock, flags);
2539         b43legacy_synchronize_irq(dev);
2540
2541         /* Switch to the requested channel.
2542          * The firmware takes care of races with the TX handler. */
2543         if (conf->channel_val != phy->channel)
2544                 b43legacy_radio_selectchannel(dev, conf->channel_val, 0);
2545
2546         /* Enable/Disable ShortSlot timing. */
2547         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
2548              != dev->short_slot) {
2549                 B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
2550                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2551                         b43legacy_short_slot_timing_enable(dev);
2552                 else
2553                         b43legacy_short_slot_timing_disable(dev);
2554         }
2555
2556         /* Adjust the desired TX power level. */
2557         if (conf->power_level != 0) {
2558                 if (conf->power_level != phy->power_level) {
2559                         phy->power_level = conf->power_level;
2560                         b43legacy_phy_xmitpower(dev);
2561                 }
2562         }
2563
2564         /* Antennas for RX and management frame TX. */
2565         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2566
2567         /* Update templates for AP mode. */
2568         if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
2569                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2570
2571
2572         if (!!conf->radio_enabled != phy->radio_on) {
2573                 if (conf->radio_enabled) {
2574                         b43legacy_radio_turn_on(dev);
2575                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2576                         if (!dev->radio_hw_enable)
2577                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2578                                               " button still turns the radio"
2579                                               " physically off. Press the"
2580                                               " button to turn it on.\n");
2581                 } else {
2582                         b43legacy_radio_turn_off(dev, 0);
2583                         b43legacyinfo(dev->wl, "Radio turned off by"
2584                                       " software\n");
2585                 }
2586         }
2587
2588         spin_lock_irqsave(&wl->irq_lock, flags);
2589         b43legacy_interrupt_enable(dev, savedirqs);
2590         mmiowb();
2591         spin_unlock_irqrestore(&wl->irq_lock, flags);
2592 out_unlock_mutex:
2593         mutex_unlock(&wl->mutex);
2594
2595         return err;
2596 }
2597
2598 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2599                                           unsigned int changed,
2600                                           unsigned int *fflags,
2601                                           int mc_count,
2602                                           struct dev_addr_list *mc_list)
2603 {
2604         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2605         struct b43legacy_wldev *dev = wl->current_dev;
2606         unsigned long flags;
2607
2608         if (!dev) {
2609                 *fflags = 0;
2610                 return;
2611         }
2612
2613         spin_lock_irqsave(&wl->irq_lock, flags);
2614         *fflags &= FIF_PROMISC_IN_BSS |
2615                   FIF_ALLMULTI |
2616                   FIF_FCSFAIL |
2617                   FIF_PLCPFAIL |
2618                   FIF_CONTROL |
2619                   FIF_OTHER_BSS |
2620                   FIF_BCN_PRBRESP_PROMISC;
2621
2622         changed &= FIF_PROMISC_IN_BSS |
2623                    FIF_ALLMULTI |
2624                    FIF_FCSFAIL |
2625                    FIF_PLCPFAIL |
2626                    FIF_CONTROL |
2627                    FIF_OTHER_BSS |
2628                    FIF_BCN_PRBRESP_PROMISC;
2629
2630         wl->filter_flags = *fflags;
2631
2632         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2633                 b43legacy_adjust_opmode(dev);
2634         spin_unlock_irqrestore(&wl->irq_lock, flags);
2635 }
2636
2637 static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
2638                                          int if_id,
2639                                          struct ieee80211_if_conf *conf)
2640 {
2641         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2642         struct b43legacy_wldev *dev = wl->current_dev;
2643         unsigned long flags;
2644
2645         if (!dev)
2646                 return -ENODEV;
2647         mutex_lock(&wl->mutex);
2648         spin_lock_irqsave(&wl->irq_lock, flags);
2649         B43legacy_WARN_ON(wl->if_id != if_id);
2650         if (conf->bssid)
2651                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2652         else
2653                 memset(wl->bssid, 0, ETH_ALEN);
2654         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2655                 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2656                         B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2657                         b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
2658                         if (conf->beacon)
2659                                 b43legacy_refresh_templates(dev, conf->beacon);
2660                 }
2661                 b43legacy_write_mac_bssid_templates(dev);
2662         }
2663         spin_unlock_irqrestore(&wl->irq_lock, flags);
2664         mutex_unlock(&wl->mutex);
2665
2666         return 0;
2667 }
2668
2669 /* Locking: wl->mutex */
2670 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2671 {
2672         struct b43legacy_wl *wl = dev->wl;
2673         unsigned long flags;
2674
2675         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2676                 return;
2677
2678         /* Disable and sync interrupts. We must do this before than
2679          * setting the status to INITIALIZED, as the interrupt handler
2680          * won't care about IRQs then. */
2681         spin_lock_irqsave(&wl->irq_lock, flags);
2682         dev->irq_savedstate = b43legacy_interrupt_disable(dev,
2683                                                           B43legacy_IRQ_ALL);
2684         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2685         spin_unlock_irqrestore(&wl->irq_lock, flags);
2686         b43legacy_synchronize_irq(dev);
2687
2688         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2689
2690         mutex_unlock(&wl->mutex);
2691         /* Must unlock as it would otherwise deadlock. No races here.
2692          * Cancel the possibly running self-rearming periodic work. */
2693         cancel_delayed_work_sync(&dev->periodic_work);
2694         mutex_lock(&wl->mutex);
2695
2696         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2697
2698         b43legacy_mac_suspend(dev);
2699         free_irq(dev->dev->irq, dev);
2700         b43legacydbg(wl, "Wireless interface stopped\n");
2701 }
2702
2703 /* Locking: wl->mutex */
2704 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2705 {
2706         int err;
2707
2708         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2709
2710         drain_txstatus_queue(dev);
2711         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2712                           IRQF_SHARED, KBUILD_MODNAME, dev);
2713         if (err) {
2714                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2715                        dev->dev->irq);
2716                 goto out;
2717         }
2718         /* We are ready to run. */
2719         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2720
2721         /* Start data flow (TX/RX) */
2722         b43legacy_mac_enable(dev);
2723         b43legacy_interrupt_enable(dev, dev->irq_savedstate);
2724         ieee80211_start_queues(dev->wl->hw);
2725
2726         /* Start maintenance work */
2727         b43legacy_periodic_tasks_setup(dev);
2728
2729         b43legacydbg(dev->wl, "Wireless interface started\n");
2730 out:
2731         return err;
2732 }
2733
2734 /* Get PHY and RADIO versioning numbers */
2735 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2736 {
2737         struct b43legacy_phy *phy = &dev->phy;
2738         u32 tmp;
2739         u8 analog_type;
2740         u8 phy_type;
2741         u8 phy_rev;
2742         u16 radio_manuf;
2743         u16 radio_ver;
2744         u16 radio_rev;
2745         int unsupported = 0;
2746
2747         /* Get PHY versioning */
2748         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2749         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2750                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2751         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2752         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2753         switch (phy_type) {
2754         case B43legacy_PHYTYPE_B:
2755                 if (phy_rev != 2 && phy_rev != 4
2756                     && phy_rev != 6 && phy_rev != 7)
2757                         unsupported = 1;
2758                 break;
2759         case B43legacy_PHYTYPE_G:
2760                 if (phy_rev > 8)
2761                         unsupported = 1;
2762                 break;
2763         default:
2764                 unsupported = 1;
2765         };
2766         if (unsupported) {
2767                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2768                        "(Analog %u, Type %u, Revision %u)\n",
2769                        analog_type, phy_type, phy_rev);
2770                 return -EOPNOTSUPP;
2771         }
2772         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2773                analog_type, phy_type, phy_rev);
2774
2775
2776         /* Get RADIO versioning */
2777         if (dev->dev->bus->chip_id == 0x4317) {
2778                 if (dev->dev->bus->chip_rev == 0)
2779                         tmp = 0x3205017F;
2780                 else if (dev->dev->bus->chip_rev == 1)
2781                         tmp = 0x4205017F;
2782                 else
2783                         tmp = 0x5205017F;
2784         } else {
2785                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2786                                   B43legacy_RADIOCTL_ID);
2787                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2788                 tmp <<= 16;
2789                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2790                                   B43legacy_RADIOCTL_ID);
2791                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2792         }
2793         radio_manuf = (tmp & 0x00000FFF);
2794         radio_ver = (tmp & 0x0FFFF000) >> 12;
2795         radio_rev = (tmp & 0xF0000000) >> 28;
2796         switch (phy_type) {
2797         case B43legacy_PHYTYPE_B:
2798                 if ((radio_ver & 0xFFF0) != 0x2050)
2799                         unsupported = 1;
2800                 break;
2801         case B43legacy_PHYTYPE_G:
2802                 if (radio_ver != 0x2050)
2803                         unsupported = 1;
2804                 break;
2805         default:
2806                 B43legacy_BUG_ON(1);
2807         }
2808         if (unsupported) {
2809                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
2810                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
2811                        radio_manuf, radio_ver, radio_rev);
2812                 return -EOPNOTSUPP;
2813         }
2814         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
2815                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
2816
2817
2818         phy->radio_manuf = radio_manuf;
2819         phy->radio_ver = radio_ver;
2820         phy->radio_rev = radio_rev;
2821
2822         phy->analog = analog_type;
2823         phy->type = phy_type;
2824         phy->rev = phy_rev;
2825
2826         return 0;
2827 }
2828
2829 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
2830                                       struct b43legacy_phy *phy)
2831 {
2832         struct b43legacy_lopair *lo;
2833         int i;
2834
2835         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
2836         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
2837
2838         /* Flags */
2839         phy->locked = 0;
2840         /* Assume the radio is enabled. If it's not enabled, the state will
2841          * immediately get fixed on the first periodic work run. */
2842         dev->radio_hw_enable = 1;
2843
2844         phy->savedpctlreg = 0xFFFF;
2845         phy->aci_enable = 0;
2846         phy->aci_wlan_automatic = 0;
2847         phy->aci_hw_rssi = 0;
2848
2849         lo = phy->_lo_pairs;
2850         if (lo)
2851                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
2852                                      B43legacy_LO_COUNT);
2853         phy->max_lb_gain = 0;
2854         phy->trsw_rx_gain = 0;
2855
2856         /* Set default attenuation values. */
2857         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
2858         phy->rfatt = b43legacy_default_radio_attenuation(dev);
2859         phy->txctl1 = b43legacy_default_txctl1(dev);
2860         phy->txpwr_offset = 0;
2861
2862         /* NRSSI */
2863         phy->nrssislope = 0;
2864         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
2865                 phy->nrssi[i] = -1000;
2866         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
2867                 phy->nrssi_lt[i] = i;
2868
2869         phy->lofcal = 0xFFFF;
2870         phy->initval = 0xFFFF;
2871
2872         spin_lock_init(&phy->lock);
2873         phy->interfmode = B43legacy_INTERFMODE_NONE;
2874         phy->channel = 0xFF;
2875 }
2876
2877 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
2878 {
2879         /* Flags */
2880         dev->reg124_set_0x4 = 0;
2881
2882         /* Stats */
2883         memset(&dev->stats, 0, sizeof(dev->stats));
2884
2885         setup_struct_phy_for_init(dev, &dev->phy);
2886
2887         /* IRQ related flags */
2888         dev->irq_reason = 0;
2889         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
2890         dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
2891
2892         dev->mac_suspended = 1;
2893
2894         /* Noise calculation context */
2895         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
2896 }
2897
2898 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
2899 {
2900 #ifdef CONFIG_SSB_DRIVER_PCICORE
2901         struct ssb_bus *bus = dev->dev->bus;
2902         u32 tmp;
2903
2904         if (bus->pcicore.dev &&
2905             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
2906             bus->pcicore.dev->id.revision <= 5) {
2907                 /* IMCFGLO timeouts workaround. */
2908                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
2909                 tmp &= ~SSB_IMCFGLO_REQTO;
2910                 tmp &= ~SSB_IMCFGLO_SERTO;
2911                 switch (bus->bustype) {
2912                 case SSB_BUSTYPE_PCI:
2913                 case SSB_BUSTYPE_PCMCIA:
2914                         tmp |= 0x32;
2915                         break;
2916                 case SSB_BUSTYPE_SSB:
2917                         tmp |= 0x53;
2918                         break;
2919                 }
2920                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
2921         }
2922 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2923 }
2924
2925 /* Write the short and long frame retry limit values. */
2926 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2927                                        unsigned int short_retry,
2928                                        unsigned int long_retry)
2929 {
2930         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2931          * the chip-internal counter. */
2932         short_retry = min(short_retry, (unsigned int)0xF);
2933         long_retry = min(long_retry, (unsigned int)0xF);
2934
2935         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2936         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2937 }
2938
2939 /* Shutdown a wireless core */
2940 /* Locking: wl->mutex */
2941 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
2942 {
2943         struct b43legacy_wl *wl = dev->wl;
2944         struct b43legacy_phy *phy = &dev->phy;
2945
2946         B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
2947         if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
2948                 return;
2949         b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
2950
2951         mutex_unlock(&wl->mutex);
2952         /* Must unlock as it would otherwise deadlock. No races here.
2953          * Cancel possibly pending workqueues. */
2954         cancel_work_sync(&dev->restart_work);
2955         mutex_lock(&wl->mutex);
2956
2957         mutex_unlock(&dev->wl->mutex);
2958         b43legacy_rfkill_exit(dev);
2959         mutex_lock(&dev->wl->mutex);
2960
2961         b43legacy_rng_exit(dev->wl);
2962         b43legacy_pio_free(dev);
2963         b43legacy_dma_free(dev);
2964         b43legacy_chip_exit(dev);
2965         b43legacy_radio_turn_off(dev, 1);
2966         b43legacy_switch_analog(dev, 0);
2967         if (phy->dyn_tssi_tbl)
2968                 kfree(phy->tssi2dbm);
2969         kfree(phy->lo_control);
2970         phy->lo_control = NULL;
2971         ssb_device_disable(dev->dev, 0);
2972         ssb_bus_may_powerdown(dev->dev->bus);
2973 }
2974
2975 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
2976 {
2977         struct b43legacy_phy *phy = &dev->phy;
2978         int i;
2979
2980         /* Set default attenuation values. */
2981         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
2982         phy->rfatt = b43legacy_default_radio_attenuation(dev);
2983         phy->txctl1 = b43legacy_default_txctl1(dev);
2984         phy->txctl2 = 0xFFFF;
2985         phy->txpwr_offset = 0;
2986
2987         /* NRSSI */
2988         phy->nrssislope = 0;
2989         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
2990                 phy->nrssi[i] = -1000;
2991         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
2992                 phy->nrssi_lt[i] = i;
2993
2994         phy->lofcal = 0xFFFF;
2995         phy->initval = 0xFFFF;
2996
2997         phy->aci_enable = 0;
2998         phy->aci_wlan_automatic = 0;
2999         phy->aci_hw_rssi = 0;
3000
3001         phy->antenna_diversity = 0xFFFF;
3002         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3003         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3004
3005         /* Flags */
3006         phy->calibrated = 0;
3007         phy->locked = 0;
3008
3009         if (phy->_lo_pairs)
3010                 memset(phy->_lo_pairs, 0,
3011                        sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3012         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3013 }
3014
3015 /* Initialize a wireless core */
3016 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3017 {
3018         struct b43legacy_wl *wl = dev->wl;
3019         struct ssb_bus *bus = dev->dev->bus;
3020         struct b43legacy_phy *phy = &dev->phy;
3021         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3022         int err;
3023         u32 hf;
3024         u32 tmp;
3025
3026         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3027
3028         err = ssb_bus_powerup(bus, 0);
3029         if (err)
3030                 goto out;
3031         if (!ssb_device_is_enabled(dev->dev)) {
3032                 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3033                 b43legacy_wireless_core_reset(dev, tmp);
3034         }
3035
3036         if ((phy->type == B43legacy_PHYTYPE_B) ||
3037             (phy->type == B43legacy_PHYTYPE_G)) {
3038                 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3039                                          * B43legacy_LO_COUNT,
3040                                          GFP_KERNEL);
3041                 if (!phy->_lo_pairs)
3042                         return -ENOMEM;
3043         }
3044         setup_struct_wldev_for_init(dev);
3045
3046         err = b43legacy_phy_init_tssi2dbm_table(dev);
3047         if (err)
3048                 goto err_kfree_lo_control;
3049
3050         /* Enable IRQ routing to this device. */
3051         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3052
3053         b43legacy_imcfglo_timeouts_workaround(dev);
3054         prepare_phy_data_for_init(dev);
3055         b43legacy_phy_calibrate(dev);
3056         err = b43legacy_chip_init(dev);
3057         if (err)
3058                 goto err_kfree_tssitbl;
3059         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3060                               B43legacy_SHM_SH_WLCOREREV,
3061                               dev->dev->id.revision);
3062         hf = b43legacy_hf_read(dev);
3063         if (phy->type == B43legacy_PHYTYPE_G) {
3064                 hf |= B43legacy_HF_SYMW;
3065                 if (phy->rev == 1)
3066                         hf |= B43legacy_HF_GDCW;
3067                 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3068                         hf |= B43legacy_HF_OFDMPABOOST;
3069         } else if (phy->type == B43legacy_PHYTYPE_B) {
3070                 hf |= B43legacy_HF_SYMW;
3071                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3072                         hf &= ~B43legacy_HF_GDCW;
3073         }
3074         b43legacy_hf_write(dev, hf);
3075
3076         b43legacy_set_retry_limits(dev,
3077                                    B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3078                                    B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3079
3080         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3081                               0x0044, 3);
3082         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3083                               0x0046, 2);
3084
3085         /* Disable sending probe responses from firmware.
3086          * Setting the MaxTime to one usec will always trigger
3087          * a timeout, so we never send any probe resp.
3088          * A timeout of zero is infinite. */
3089         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3090                               B43legacy_SHM_SH_PRMAXTIME, 1);
3091
3092         b43legacy_rate_memory_init(dev);
3093
3094         /* Minimum Contention Window */
3095         if (phy->type == B43legacy_PHYTYPE_B)
3096                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3097                                       0x0003, 31);
3098         else
3099                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3100                                       0x0003, 15);
3101         /* Maximum Contention Window */
3102         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3103                               0x0004, 1023);
3104
3105         do {
3106                 if (b43legacy_using_pio(dev))
3107                         err = b43legacy_pio_init(dev);
3108                 else {
3109                         err = b43legacy_dma_init(dev);
3110                         if (!err)
3111                                 b43legacy_qos_init(dev);
3112                 }
3113         } while (err == -EAGAIN);
3114         if (err)
3115                 goto err_chip_exit;
3116
3117         b43legacy_write16(dev, 0x0612, 0x0050);
3118         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
3119         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
3120
3121         ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3122         memset(wl->bssid, 0, ETH_ALEN);
3123         memset(wl->mac_addr, 0, ETH_ALEN);
3124         b43legacy_upload_card_macaddress(dev);
3125         b43legacy_security_init(dev);
3126         b43legacy_rfkill_init(dev);
3127         b43legacy_rng_init(wl);
3128
3129         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3130
3131 out:
3132         return err;
3133
3134 err_chip_exit:
3135         b43legacy_chip_exit(dev);
3136 err_kfree_tssitbl:
3137         if (phy->dyn_tssi_tbl)
3138                 kfree(phy->tssi2dbm);
3139 err_kfree_lo_control:
3140         kfree(phy->lo_control);
3141         phy->lo_control = NULL;