b43/legacy: Fix usage of host_pci pointer
[linux-2.6.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2  *
3  *  Broadcom B43legacy wireless driver
4  *
5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7  *  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11  *
12  *  Some parts of the code in this file are derived from the ipw2200
13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  *  This program is free software; you can redistribute it and/or modify
16  *  it under the terms of the GNU General Public License as published by
17  *  the Free Software Foundation; either version 2 of the License, or
18  *  (at your option) any later version.
19  *
20  *  This program is distributed in the hope that it will be useful,
21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *  GNU General Public License for more details.
24  *
25  *  You should have received a copy of the GNU General Public License
26  *  along with this program; see the file COPYING.  If not, write to
27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  *  Boston, MA 02110-1301, USA.
29  *
30  */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/moduleparam.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/dst.h>
43 #include <asm/unaligned.h>
44
45 #include "b43legacy.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "pio.h"
51 #include "sysfs.h"
52 #include "xmit.h"
53 #include "radio.h"
54
55
56 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
61
62 MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
63
64 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
65 static int modparam_pio;
66 module_param_named(pio, modparam_pio, int, 0444);
67 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
68 #elif defined(CONFIG_B43LEGACY_DMA)
69 # define modparam_pio   0
70 #elif defined(CONFIG_B43LEGACY_PIO)
71 # define modparam_pio   1
72 #endif
73
74 static int modparam_bad_frames_preempt;
75 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
76 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
77                  " Preemption");
78
79 static char modparam_fwpostfix[16];
80 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
81 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
82
83 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
84 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
86         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
87         SSB_DEVTABLE_END
88 };
89 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
90
91
92 /* Channel and ratetables are shared for all devices.
93  * They can't be const, because ieee80211 puts some precalculated
94  * data in there. This data is the same for all devices, so we don't
95  * get concurrency issues */
96 #define RATETAB_ENT(_rateid, _flags) \
97         {                                                               \
98                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
99                 .hw_value       = (_rateid),                            \
100                 .flags          = (_flags),                             \
101         }
102 /*
103  * NOTE: When changing this, sync with xmit.c's
104  *       b43legacy_plcp_get_bitrate_idx_* functions!
105  */
106 static struct ieee80211_rate __b43legacy_ratetable[] = {
107         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
108         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
109         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
110         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
111         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
112         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
113         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
114         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
115         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
116         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
117         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
118         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
119 };
120 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
121 #define b43legacy_b_ratetable_size      4
122 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
123 #define b43legacy_g_ratetable_size      12
124
125 #define CHANTAB_ENT(_chanid, _freq) \
126         {                                                       \
127                 .center_freq    = (_freq),                      \
128                 .hw_value       = (_chanid),                    \
129         }
130 static struct ieee80211_channel b43legacy_bg_chantable[] = {
131         CHANTAB_ENT(1, 2412),
132         CHANTAB_ENT(2, 2417),
133         CHANTAB_ENT(3, 2422),
134         CHANTAB_ENT(4, 2427),
135         CHANTAB_ENT(5, 2432),
136         CHANTAB_ENT(6, 2437),
137         CHANTAB_ENT(7, 2442),
138         CHANTAB_ENT(8, 2447),
139         CHANTAB_ENT(9, 2452),
140         CHANTAB_ENT(10, 2457),
141         CHANTAB_ENT(11, 2462),
142         CHANTAB_ENT(12, 2467),
143         CHANTAB_ENT(13, 2472),
144         CHANTAB_ENT(14, 2484),
145 };
146
147 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
148         .channels = b43legacy_bg_chantable,
149         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
150         .bitrates = b43legacy_b_ratetable,
151         .n_bitrates = b43legacy_b_ratetable_size,
152 };
153
154 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
155         .channels = b43legacy_bg_chantable,
156         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
157         .bitrates = b43legacy_g_ratetable,
158         .n_bitrates = b43legacy_g_ratetable_size,
159 };
160
161 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
162 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
163 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
164 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
165
166
167 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
168 {
169         if (!wl || !wl->current_dev)
170                 return 1;
171         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
172                 return 1;
173         /* We are up and running.
174          * Ratelimit the messages to avoid DoS over the net. */
175         return net_ratelimit();
176 }
177
178 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
179 {
180         va_list args;
181
182         if (!b43legacy_ratelimit(wl))
183                 return;
184         va_start(args, fmt);
185         printk(KERN_INFO "b43legacy-%s: ",
186                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
187         vprintk(fmt, args);
188         va_end(args);
189 }
190
191 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
192 {
193         va_list args;
194
195         if (!b43legacy_ratelimit(wl))
196                 return;
197         va_start(args, fmt);
198         printk(KERN_ERR "b43legacy-%s ERROR: ",
199                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
200         vprintk(fmt, args);
201         va_end(args);
202 }
203
204 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
205 {
206         va_list args;
207
208         if (!b43legacy_ratelimit(wl))
209                 return;
210         va_start(args, fmt);
211         printk(KERN_WARNING "b43legacy-%s warning: ",
212                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
213         vprintk(fmt, args);
214         va_end(args);
215 }
216
217 #if B43legacy_DEBUG
218 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
219 {
220         va_list args;
221
222         va_start(args, fmt);
223         printk(KERN_DEBUG "b43legacy-%s debug: ",
224                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
225         vprintk(fmt, args);
226         va_end(args);
227 }
228 #endif /* DEBUG */
229
230 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
231                                 u32 val)
232 {
233         u32 status;
234
235         B43legacy_WARN_ON(offset % 4 != 0);
236
237         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
238         if (status & B43legacy_MACCTL_BE)
239                 val = swab32(val);
240
241         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
242         mmiowb();
243         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
244 }
245
246 static inline
247 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
248                                 u16 routing, u16 offset)
249 {
250         u32 control;
251
252         /* "offset" is the WORD offset. */
253
254         control = routing;
255         control <<= 16;
256         control |= offset;
257         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
258 }
259
260 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
261                        u16 routing, u16 offset)
262 {
263         u32 ret;
264
265         if (routing == B43legacy_SHM_SHARED) {
266                 B43legacy_WARN_ON((offset & 0x0001) != 0);
267                 if (offset & 0x0003) {
268                         /* Unaligned access */
269                         b43legacy_shm_control_word(dev, routing, offset >> 2);
270                         ret = b43legacy_read16(dev,
271                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
272                         ret <<= 16;
273                         b43legacy_shm_control_word(dev, routing,
274                                                      (offset >> 2) + 1);
275                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
276
277                         return ret;
278                 }
279                 offset >>= 2;
280         }
281         b43legacy_shm_control_word(dev, routing, offset);
282         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
283
284         return ret;
285 }
286
287 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
288                            u16 routing, u16 offset)
289 {
290         u16 ret;
291
292         if (routing == B43legacy_SHM_SHARED) {
293                 B43legacy_WARN_ON((offset & 0x0001) != 0);
294                 if (offset & 0x0003) {
295                         /* Unaligned access */
296                         b43legacy_shm_control_word(dev, routing, offset >> 2);
297                         ret = b43legacy_read16(dev,
298                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
299
300                         return ret;
301                 }
302                 offset >>= 2;
303         }
304         b43legacy_shm_control_word(dev, routing, offset);
305         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
306
307         return ret;
308 }
309
310 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
311                            u16 routing, u16 offset,
312                            u32 value)
313 {
314         if (routing == B43legacy_SHM_SHARED) {
315                 B43legacy_WARN_ON((offset & 0x0001) != 0);
316                 if (offset & 0x0003) {
317                         /* Unaligned access */
318                         b43legacy_shm_control_word(dev, routing, offset >> 2);
319                         mmiowb();
320                         b43legacy_write16(dev,
321                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
322                                           (value >> 16) & 0xffff);
323                         mmiowb();
324                         b43legacy_shm_control_word(dev, routing,
325                                                    (offset >> 2) + 1);
326                         mmiowb();
327                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
328                                           value & 0xffff);
329                         return;
330                 }
331                 offset >>= 2;
332         }
333         b43legacy_shm_control_word(dev, routing, offset);
334         mmiowb();
335         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
336 }
337
338 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
339                            u16 value)
340 {
341         if (routing == B43legacy_SHM_SHARED) {
342                 B43legacy_WARN_ON((offset & 0x0001) != 0);
343                 if (offset & 0x0003) {
344                         /* Unaligned access */
345                         b43legacy_shm_control_word(dev, routing, offset >> 2);
346                         mmiowb();
347                         b43legacy_write16(dev,
348                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
349                                           value);
350                         return;
351                 }
352                 offset >>= 2;
353         }
354         b43legacy_shm_control_word(dev, routing, offset);
355         mmiowb();
356         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
357 }
358
359 /* Read HostFlags */
360 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
361 {
362         u32 ret;
363
364         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
365                                    B43legacy_SHM_SH_HOSTFHI);
366         ret <<= 16;
367         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
368                                     B43legacy_SHM_SH_HOSTFLO);
369
370         return ret;
371 }
372
373 /* Write HostFlags */
374 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
375 {
376         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
377                               B43legacy_SHM_SH_HOSTFLO,
378                               (value & 0x0000FFFF));
379         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
380                               B43legacy_SHM_SH_HOSTFHI,
381                               ((value & 0xFFFF0000) >> 16));
382 }
383
384 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
385 {
386         /* We need to be careful. As we read the TSF from multiple
387          * registers, we should take care of register overflows.
388          * In theory, the whole tsf read process should be atomic.
389          * We try to be atomic here, by restaring the read process,
390          * if any of the high registers changed (overflew).
391          */
392         if (dev->dev->id.revision >= 3) {
393                 u32 low;
394                 u32 high;
395                 u32 high2;
396
397                 do {
398                         high = b43legacy_read32(dev,
399                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
400                         low = b43legacy_read32(dev,
401                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
402                         high2 = b43legacy_read32(dev,
403                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
404                 } while (unlikely(high != high2));
405
406                 *tsf = high;
407                 *tsf <<= 32;
408                 *tsf |= low;
409         } else {
410                 u64 tmp;
411                 u16 v0;
412                 u16 v1;
413                 u16 v2;
414                 u16 v3;
415                 u16 test1;
416                 u16 test2;
417                 u16 test3;
418
419                 do {
420                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
421                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
422                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
423                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
424
425                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
426                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
427                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
428                 } while (v3 != test3 || v2 != test2 || v1 != test1);
429
430                 *tsf = v3;
431                 *tsf <<= 48;
432                 tmp = v2;
433                 tmp <<= 32;
434                 *tsf |= tmp;
435                 tmp = v1;
436                 tmp <<= 16;
437                 *tsf |= tmp;
438                 *tsf |= v0;
439         }
440 }
441
442 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
443 {
444         u32 status;
445
446         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
447         status |= B43legacy_MACCTL_TBTTHOLD;
448         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
449         mmiowb();
450 }
451
452 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
453 {
454         u32 status;
455
456         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
457         status &= ~B43legacy_MACCTL_TBTTHOLD;
458         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
459 }
460
461 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
462 {
463         /* Be careful with the in-progress timer.
464          * First zero out the low register, so we have a full
465          * register-overflow duration to complete the operation.
466          */
467         if (dev->dev->id.revision >= 3) {
468                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
469                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
470
471                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
472                 mmiowb();
473                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
474                                     hi);
475                 mmiowb();
476                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
477                                     lo);
478         } else {
479                 u16 v0 = (tsf & 0x000000000000FFFFULL);
480                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
481                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
482                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483
484                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
485                 mmiowb();
486                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
487                 mmiowb();
488                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
489                 mmiowb();
490                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
491                 mmiowb();
492                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
493         }
494 }
495
496 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
497 {
498         b43legacy_time_lock(dev);
499         b43legacy_tsf_write_locked(dev, tsf);
500         b43legacy_time_unlock(dev);
501 }
502
503 static
504 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
505                              u16 offset, const u8 *mac)
506 {
507         static const u8 zero_addr[ETH_ALEN] = { 0 };
508         u16 data;
509
510         if (!mac)
511                 mac = zero_addr;
512
513         offset |= 0x0020;
514         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
515
516         data = mac[0];
517         data |= mac[1] << 8;
518         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
519         data = mac[2];
520         data |= mac[3] << 8;
521         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
522         data = mac[4];
523         data |= mac[5] << 8;
524         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
525 }
526
527 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
528 {
529         static const u8 zero_addr[ETH_ALEN] = { 0 };
530         const u8 *mac = dev->wl->mac_addr;
531         const u8 *bssid = dev->wl->bssid;
532         u8 mac_bssid[ETH_ALEN * 2];
533         int i;
534         u32 tmp;
535
536         if (!bssid)
537                 bssid = zero_addr;
538         if (!mac)
539                 mac = zero_addr;
540
541         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
542
543         memcpy(mac_bssid, mac, ETH_ALEN);
544         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
545
546         /* Write our MAC address and BSSID to template ram */
547         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
548                 tmp =  (u32)(mac_bssid[i + 0]);
549                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
550                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
551                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
552                 b43legacy_ram_write(dev, 0x20 + i, tmp);
553                 b43legacy_ram_write(dev, 0x78 + i, tmp);
554                 b43legacy_ram_write(dev, 0x478 + i, tmp);
555         }
556 }
557
558 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
559 {
560         b43legacy_write_mac_bssid_templates(dev);
561         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
562                                 dev->wl->mac_addr);
563 }
564
565 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
566                                     u16 slot_time)
567 {
568         /* slot_time is in usec. */
569         if (dev->phy.type != B43legacy_PHYTYPE_G)
570                 return;
571         b43legacy_write16(dev, 0x684, 510 + slot_time);
572         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
573                               slot_time);
574 }
575
576 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
577 {
578         b43legacy_set_slot_time(dev, 9);
579 }
580
581 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
582 {
583         b43legacy_set_slot_time(dev, 20);
584 }
585
586 /* Synchronize IRQ top- and bottom-half.
587  * IRQs must be masked before calling this.
588  * This must not be called with the irq_lock held.
589  */
590 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
591 {
592         synchronize_irq(dev->dev->irq);
593         tasklet_kill(&dev->isr_tasklet);
594 }
595
596 /* DummyTransmission function, as documented on
597  * http://bcm-specs.sipsolutions.net/DummyTransmission
598  */
599 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
600 {
601         struct b43legacy_phy *phy = &dev->phy;
602         unsigned int i;
603         unsigned int max_loop;
604         u16 value;
605         u32 buffer[5] = {
606                 0x00000000,
607                 0x00D40000,
608                 0x00000000,
609                 0x01000000,
610                 0x00000000,
611         };
612
613         switch (phy->type) {
614         case B43legacy_PHYTYPE_B:
615         case B43legacy_PHYTYPE_G:
616                 max_loop = 0xFA;
617                 buffer[0] = 0x000B846E;
618                 break;
619         default:
620                 B43legacy_BUG_ON(1);
621                 return;
622         }
623
624         for (i = 0; i < 5; i++)
625                 b43legacy_ram_write(dev, i * 4, buffer[i]);
626
627         /* dummy read follows */
628         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
629
630         b43legacy_write16(dev, 0x0568, 0x0000);
631         b43legacy_write16(dev, 0x07C0, 0x0000);
632         b43legacy_write16(dev, 0x050C, 0x0000);
633         b43legacy_write16(dev, 0x0508, 0x0000);
634         b43legacy_write16(dev, 0x050A, 0x0000);
635         b43legacy_write16(dev, 0x054C, 0x0000);
636         b43legacy_write16(dev, 0x056A, 0x0014);
637         b43legacy_write16(dev, 0x0568, 0x0826);
638         b43legacy_write16(dev, 0x0500, 0x0000);
639         b43legacy_write16(dev, 0x0502, 0x0030);
640
641         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
642                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
643         for (i = 0x00; i < max_loop; i++) {
644                 value = b43legacy_read16(dev, 0x050E);
645                 if (value & 0x0080)
646                         break;
647                 udelay(10);
648         }
649         for (i = 0x00; i < 0x0A; i++) {
650                 value = b43legacy_read16(dev, 0x050E);
651                 if (value & 0x0400)
652                         break;
653                 udelay(10);
654         }
655         for (i = 0x00; i < 0x0A; i++) {
656                 value = b43legacy_read16(dev, 0x0690);
657                 if (!(value & 0x0100))
658                         break;
659                 udelay(10);
660         }
661         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
662                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
663 }
664
665 /* Turn the Analog ON/OFF */
666 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
667 {
668         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
669 }
670
671 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
672 {
673         u32 tmslow;
674         u32 macctl;
675
676         flags |= B43legacy_TMSLOW_PHYCLKEN;
677         flags |= B43legacy_TMSLOW_PHYRESET;
678         ssb_device_enable(dev->dev, flags);
679         msleep(2); /* Wait for the PLL to turn on. */
680
681         /* Now take the PHY out of Reset again */
682         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
683         tmslow |= SSB_TMSLOW_FGC;
684         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
685         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
686         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
687         msleep(1);
688         tmslow &= ~SSB_TMSLOW_FGC;
689         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
690         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
691         msleep(1);
692
693         /* Turn Analog ON */
694         b43legacy_switch_analog(dev, 1);
695
696         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
697         macctl &= ~B43legacy_MACCTL_GMODE;
698         if (flags & B43legacy_TMSLOW_GMODE) {
699                 macctl |= B43legacy_MACCTL_GMODE;
700                 dev->phy.gmode = 1;
701         } else
702                 dev->phy.gmode = 0;
703         macctl |= B43legacy_MACCTL_IHR_ENABLED;
704         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
705 }
706
707 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
708 {
709         u32 v0;
710         u32 v1;
711         u16 tmp;
712         struct b43legacy_txstatus stat;
713
714         while (1) {
715                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
716                 if (!(v0 & 0x00000001))
717                         break;
718                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
719
720                 stat.cookie = (v0 >> 16);
721                 stat.seq = (v1 & 0x0000FFFF);
722                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
723                 tmp = (v0 & 0x0000FFFF);
724                 stat.frame_count = ((tmp & 0xF000) >> 12);
725                 stat.rts_count = ((tmp & 0x0F00) >> 8);
726                 stat.supp_reason = ((tmp & 0x001C) >> 2);
727                 stat.pm_indicated = !!(tmp & 0x0080);
728                 stat.intermediate = !!(tmp & 0x0040);
729                 stat.for_ampdu = !!(tmp & 0x0020);
730                 stat.acked = !!(tmp & 0x0002);
731
732                 b43legacy_handle_txstatus(dev, &stat);
733         }
734 }
735
736 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
737 {
738         u32 dummy;
739
740         if (dev->dev->id.revision < 5)
741                 return;
742         /* Read all entries from the microcode TXstatus FIFO
743          * and throw them away.
744          */
745         while (1) {
746                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
747                 if (!(dummy & 0x00000001))
748                         break;
749                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
750         }
751 }
752
753 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
754 {
755         u32 val = 0;
756
757         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
758         val <<= 16;
759         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
760
761         return val;
762 }
763
764 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
765 {
766         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
767                               (jssi & 0x0000FFFF));
768         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
769                               (jssi & 0xFFFF0000) >> 16);
770 }
771
772 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
773 {
774         b43legacy_jssi_write(dev, 0x7F7F7F7F);
775         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
776                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
777                           | B43legacy_MACCMD_BGNOISE);
778         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
779                             dev->phy.channel);
780 }
781
782 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
783 {
784         /* Top half of Link Quality calculation. */
785
786         if (dev->noisecalc.calculation_running)
787                 return;
788         dev->noisecalc.channel_at_start = dev->phy.channel;
789         dev->noisecalc.calculation_running = 1;
790         dev->noisecalc.nr_samples = 0;
791
792         b43legacy_generate_noise_sample(dev);
793 }
794
795 static void handle_irq_noise(struct b43legacy_wldev *dev)
796 {
797         struct b43legacy_phy *phy = &dev->phy;
798         u16 tmp;
799         u8 noise[4];
800         u8 i;
801         u8 j;
802         s32 average;
803
804         /* Bottom half of Link Quality calculation. */
805
806         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
807         if (dev->noisecalc.channel_at_start != phy->channel)
808                 goto drop_calculation;
809         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
810         if (noise[0] == 0x7F || noise[1] == 0x7F ||
811             noise[2] == 0x7F || noise[3] == 0x7F)
812                 goto generate_new;
813
814         /* Get the noise samples. */
815         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
816         i = dev->noisecalc.nr_samples;
817         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
818         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
819         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
820         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
821         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
822         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
823         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
824         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
825         dev->noisecalc.nr_samples++;
826         if (dev->noisecalc.nr_samples == 8) {
827                 /* Calculate the Link Quality by the noise samples. */
828                 average = 0;
829                 for (i = 0; i < 8; i++) {
830                         for (j = 0; j < 4; j++)
831                                 average += dev->noisecalc.samples[i][j];
832                 }
833                 average /= (8 * 4);
834                 average *= 125;
835                 average += 64;
836                 average /= 128;
837                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
838                                              0x40C);
839                 tmp = (tmp / 128) & 0x1F;
840                 if (tmp >= 8)
841                         average += 2;
842                 else
843                         average -= 25;
844                 if (tmp == 8)
845                         average -= 72;
846                 else
847                         average -= 48;
848
849                 dev->stats.link_noise = average;
850 drop_calculation:
851                 dev->noisecalc.calculation_running = 0;
852                 return;
853         }
854 generate_new:
855         b43legacy_generate_noise_sample(dev);
856 }
857
858 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
859 {
860         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
861                 /* TODO: PS TBTT */
862         } else {
863                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
864                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
865         }
866         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
867                 dev->dfq_valid = 1;
868 }
869
870 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
871 {
872         if (dev->dfq_valid) {
873                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
874                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
875                                   | B43legacy_MACCMD_DFQ_VALID);
876                 dev->dfq_valid = 0;
877         }
878 }
879
880 static void handle_irq_pmq(struct b43legacy_wldev *dev)
881 {
882         u32 tmp;
883
884         /* TODO: AP mode. */
885
886         while (1) {
887                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
888                 if (!(tmp & 0x00000008))
889                         break;
890         }
891         /* 16bit write is odd, but correct. */
892         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
893 }
894
895 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
896                                             const u8 *data, u16 size,
897                                             u16 ram_offset,
898                                             u16 shm_size_offset, u8 rate)
899 {
900         u32 i;
901         u32 tmp;
902         struct b43legacy_plcp_hdr4 plcp;
903
904         plcp.data = 0;
905         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
906         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
907         ram_offset += sizeof(u32);
908         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
909          * So leave the first two bytes of the next write blank.
910          */
911         tmp = (u32)(data[0]) << 16;
912         tmp |= (u32)(data[1]) << 24;
913         b43legacy_ram_write(dev, ram_offset, tmp);
914         ram_offset += sizeof(u32);
915         for (i = 2; i < size; i += sizeof(u32)) {
916                 tmp = (u32)(data[i + 0]);
917                 if (i + 1 < size)
918                         tmp |= (u32)(data[i + 1]) << 8;
919                 if (i + 2 < size)
920                         tmp |= (u32)(data[i + 2]) << 16;
921                 if (i + 3 < size)
922                         tmp |= (u32)(data[i + 3]) << 24;
923                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
924         }
925         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
926                               size + sizeof(struct b43legacy_plcp_hdr6));
927 }
928
929 /* Convert a b43legacy antenna number value to the PHY TX control value. */
930 static u16 b43legacy_antenna_to_phyctl(int antenna)
931 {
932         switch (antenna) {
933         case B43legacy_ANTENNA0:
934                 return B43legacy_TX4_PHY_ANT0;
935         case B43legacy_ANTENNA1:
936                 return B43legacy_TX4_PHY_ANT1;
937         }
938         return B43legacy_TX4_PHY_ANTLAST;
939 }
940
941 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
942                                             u16 ram_offset,
943                                             u16 shm_size_offset)
944 {
945
946         unsigned int i, len, variable_len;
947         const struct ieee80211_mgmt *bcn;
948         const u8 *ie;
949         bool tim_found = 0;
950         unsigned int rate;
951         u16 ctl;
952         int antenna;
953         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
954
955         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
956         len = min((size_t)dev->wl->current_beacon->len,
957                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
958         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
959
960         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
961                                         shm_size_offset, rate);
962
963         /* Write the PHY TX control parameters. */
964         antenna = B43legacy_ANTENNA_DEFAULT;
965         antenna = b43legacy_antenna_to_phyctl(antenna);
966         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
967                                    B43legacy_SHM_SH_BEACPHYCTL);
968         /* We can't send beacons with short preamble. Would get PHY errors. */
969         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
970         ctl &= ~B43legacy_TX4_PHY_ANT;
971         ctl &= ~B43legacy_TX4_PHY_ENC;
972         ctl |= antenna;
973         ctl |= B43legacy_TX4_PHY_ENC_CCK;
974         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
975                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
976
977         /* Find the position of the TIM and the DTIM_period value
978          * and write them to SHM. */
979         ie = bcn->u.beacon.variable;
980         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
981         for (i = 0; i < variable_len - 2; ) {
982                 uint8_t ie_id, ie_len;
983
984                 ie_id = ie[i];
985                 ie_len = ie[i + 1];
986                 if (ie_id == 5) {
987                         u16 tim_position;
988                         u16 dtim_period;
989                         /* This is the TIM Information Element */
990
991                         /* Check whether the ie_len is in the beacon data range. */
992                         if (variable_len < ie_len + 2 + i)
993                                 break;
994                         /* A valid TIM is at least 4 bytes long. */
995                         if (ie_len < 4)
996                                 break;
997                         tim_found = 1;
998
999                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1000                         tim_position += offsetof(struct ieee80211_mgmt,
1001                                                  u.beacon.variable);
1002                         tim_position += i;
1003
1004                         dtim_period = ie[i + 3];
1005
1006                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1007                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1008                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1009                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1010                         break;
1011                 }
1012                 i += ie_len + 2;
1013         }
1014         if (!tim_found) {
1015                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1016                               "beacon template packet. AP or IBSS operation "
1017                               "may be broken.\n");
1018         } else
1019                 b43legacydbg(dev->wl, "Updated beacon template\n");
1020 }
1021
1022 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1023                                             u16 shm_offset, u16 size,
1024                                             struct ieee80211_rate *rate)
1025 {
1026         struct b43legacy_plcp_hdr4 plcp;
1027         u32 tmp;
1028         __le16 dur;
1029
1030         plcp.data = 0;
1031         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1032         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1033                                                dev->wl->vif,
1034                                                size,
1035                                                rate);
1036         /* Write PLCP in two parts and timing for packet transfer */
1037         tmp = le32_to_cpu(plcp.data);
1038         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1039                               tmp & 0xFFFF);
1040         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1041                               tmp >> 16);
1042         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1043                               le16_to_cpu(dur));
1044 }
1045
1046 /* Instead of using custom probe response template, this function
1047  * just patches custom beacon template by:
1048  * 1) Changing packet type
1049  * 2) Patching duration field
1050  * 3) Stripping TIM
1051  */
1052 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1053                                                u16 *dest_size,
1054                                                struct ieee80211_rate *rate)
1055 {
1056         const u8 *src_data;
1057         u8 *dest_data;
1058         u16 src_size, elem_size, src_pos, dest_pos;
1059         __le16 dur;
1060         struct ieee80211_hdr *hdr;
1061         size_t ie_start;
1062
1063         src_size = dev->wl->current_beacon->len;
1064         src_data = (const u8 *)dev->wl->current_beacon->data;
1065
1066         /* Get the start offset of the variable IEs in the packet. */
1067         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1068         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1069                                                u.beacon.variable));
1070
1071         if (B43legacy_WARN_ON(src_size < ie_start))
1072                 return NULL;
1073
1074         dest_data = kmalloc(src_size, GFP_ATOMIC);
1075         if (unlikely(!dest_data))
1076                 return NULL;
1077
1078         /* Copy the static data and all Information Elements, except the TIM. */
1079         memcpy(dest_data, src_data, ie_start);
1080         src_pos = ie_start;
1081         dest_pos = ie_start;
1082         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1083                 elem_size = src_data[src_pos + 1] + 2;
1084                 if (src_data[src_pos] == 5) {
1085                         /* This is the TIM. */
1086                         continue;
1087                 }
1088                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1089                 dest_pos += elem_size;
1090         }
1091         *dest_size = dest_pos;
1092         hdr = (struct ieee80211_hdr *)dest_data;
1093
1094         /* Set the frame control. */
1095         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1096                                          IEEE80211_STYPE_PROBE_RESP);
1097         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1098                                                dev->wl->vif,
1099                                                *dest_size,
1100                                                rate);
1101         hdr->duration_id = dur;
1102
1103         return dest_data;
1104 }
1105
1106 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1107                                                 u16 ram_offset,
1108                                                 u16 shm_size_offset,
1109                                                 struct ieee80211_rate *rate)
1110 {
1111         const u8 *probe_resp_data;
1112         u16 size;
1113
1114         size = dev->wl->current_beacon->len;
1115         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1116         if (unlikely(!probe_resp_data))
1117                 return;
1118
1119         /* Looks like PLCP headers plus packet timings are stored for
1120          * all possible basic rates
1121          */
1122         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1123                                         &b43legacy_b_ratetable[0]);
1124         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1125                                         &b43legacy_b_ratetable[1]);
1126         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1127                                         &b43legacy_b_ratetable[2]);
1128         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1129                                         &b43legacy_b_ratetable[3]);
1130
1131         size = min((size_t)size,
1132                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1133         b43legacy_write_template_common(dev, probe_resp_data,
1134                                         size, ram_offset,
1135                                         shm_size_offset, rate->hw_value);
1136         kfree(probe_resp_data);
1137 }
1138
1139 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1140 {
1141         struct b43legacy_wl *wl = dev->wl;
1142
1143         if (wl->beacon0_uploaded)
1144                 return;
1145         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1146         /* FIXME: Probe resp upload doesn't really belong here,
1147          *        but we don't use that feature anyway. */
1148         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1149                                       &__b43legacy_ratetable[3]);
1150         wl->beacon0_uploaded = 1;
1151 }
1152
1153 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1154 {
1155         struct b43legacy_wl *wl = dev->wl;
1156
1157         if (wl->beacon1_uploaded)
1158                 return;
1159         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1160         wl->beacon1_uploaded = 1;
1161 }
1162
1163 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1164 {
1165         struct b43legacy_wl *wl = dev->wl;
1166         u32 cmd, beacon0_valid, beacon1_valid;
1167
1168         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1169                 return;
1170
1171         /* This is the bottom half of the asynchronous beacon update. */
1172
1173         /* Ignore interrupt in the future. */
1174         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1175
1176         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1177         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1178         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1179
1180         /* Schedule interrupt manually, if busy. */
1181         if (beacon0_valid && beacon1_valid) {
1182                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1183                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1184                 return;
1185         }
1186
1187         if (unlikely(wl->beacon_templates_virgin)) {
1188                 /* We never uploaded a beacon before.
1189                  * Upload both templates now, but only mark one valid. */
1190                 wl->beacon_templates_virgin = 0;
1191                 b43legacy_upload_beacon0(dev);
1192                 b43legacy_upload_beacon1(dev);
1193                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1194                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1195                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1196         } else {
1197                 if (!beacon0_valid) {
1198                         b43legacy_upload_beacon0(dev);
1199                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1200                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1201                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1202                 } else if (!beacon1_valid) {
1203                         b43legacy_upload_beacon1(dev);
1204                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1205                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1206                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1207                 }
1208         }
1209 }
1210
1211 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1212 {
1213         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1214                                          beacon_update_trigger);
1215         struct b43legacy_wldev *dev;
1216
1217         mutex_lock(&wl->mutex);
1218         dev = wl->current_dev;
1219         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1220                 spin_lock_irq(&wl->irq_lock);
1221                 /* Update beacon right away or defer to IRQ. */
1222                 handle_irq_beacon(dev);
1223                 /* The handler might have updated the IRQ mask. */
1224                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1225                                   dev->irq_mask);
1226                 mmiowb();
1227                 spin_unlock_irq(&wl->irq_lock);
1228         }
1229         mutex_unlock(&wl->mutex);
1230 }
1231
1232 /* Asynchronously update the packet templates in template RAM.
1233  * Locking: Requires wl->irq_lock to be locked. */
1234 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1235 {
1236         struct sk_buff *beacon;
1237         /* This is the top half of the ansynchronous beacon update. The bottom
1238          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1239          * sending an invalid beacon. This can happen for example, if the
1240          * firmware transmits a beacon while we are updating it. */
1241
1242         /* We could modify the existing beacon and set the aid bit in the TIM
1243          * field, but that would probably require resizing and moving of data
1244          * within the beacon template. Simply request a new beacon and let
1245          * mac80211 do the hard work. */
1246         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1247         if (unlikely(!beacon))
1248                 return;
1249
1250         if (wl->current_beacon)
1251                 dev_kfree_skb_any(wl->current_beacon);
1252         wl->current_beacon = beacon;
1253         wl->beacon0_uploaded = 0;
1254         wl->beacon1_uploaded = 0;
1255         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1256 }
1257
1258 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1259                                      u16 beacon_int)
1260 {
1261         b43legacy_time_lock(dev);
1262         if (dev->dev->id.revision >= 3) {
1263                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1264                                  (beacon_int << 16));
1265                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1266                                  (beacon_int << 10));
1267         } else {
1268                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1269                 b43legacy_write16(dev, 0x610, beacon_int);
1270         }
1271         b43legacy_time_unlock(dev);
1272         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1273 }
1274
1275 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1276 {
1277 }
1278
1279 /* Interrupt handler bottom-half */
1280 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1281 {
1282         u32 reason;
1283         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1284         u32 merged_dma_reason = 0;
1285         int i;
1286         unsigned long flags;
1287
1288         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1289
1290         B43legacy_WARN_ON(b43legacy_status(dev) <
1291                           B43legacy_STAT_INITIALIZED);
1292
1293         reason = dev->irq_reason;
1294         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1295                 dma_reason[i] = dev->dma_reason[i];
1296                 merged_dma_reason |= dma_reason[i];
1297         }
1298
1299         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1300                 b43legacyerr(dev->wl, "MAC transmission error\n");
1301
1302         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1303                 b43legacyerr(dev->wl, "PHY transmission error\n");
1304                 rmb();
1305                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1306                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1307                                               "restarting the controller\n");
1308                         b43legacy_controller_restart(dev, "PHY TX errors");
1309                 }
1310         }
1311
1312         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1313                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1314                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1315                         b43legacyerr(dev->wl, "Fatal DMA error: "
1316                                "0x%08X, 0x%08X, 0x%08X, "
1317                                "0x%08X, 0x%08X, 0x%08X\n",
1318                                dma_reason[0], dma_reason[1],
1319                                dma_reason[2], dma_reason[3],
1320                                dma_reason[4], dma_reason[5]);
1321                         b43legacy_controller_restart(dev, "DMA error");
1322                         mmiowb();
1323                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1324                         return;
1325                 }
1326                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1327                         b43legacyerr(dev->wl, "DMA error: "
1328                                "0x%08X, 0x%08X, 0x%08X, "
1329                                "0x%08X, 0x%08X, 0x%08X\n",
1330                                dma_reason[0], dma_reason[1],
1331                                dma_reason[2], dma_reason[3],
1332                                dma_reason[4], dma_reason[5]);
1333         }
1334
1335         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1336                 handle_irq_ucode_debug(dev);
1337         if (reason & B43legacy_IRQ_TBTT_INDI)
1338                 handle_irq_tbtt_indication(dev);
1339         if (reason & B43legacy_IRQ_ATIM_END)
1340                 handle_irq_atim_end(dev);
1341         if (reason & B43legacy_IRQ_BEACON)
1342                 handle_irq_beacon(dev);
1343         if (reason & B43legacy_IRQ_PMQ)
1344                 handle_irq_pmq(dev);
1345         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1346                 ;/*TODO*/
1347         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1348                 handle_irq_noise(dev);
1349
1350         /* Check the DMA reason registers for received data. */
1351         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1352                 if (b43legacy_using_pio(dev))
1353                         b43legacy_pio_rx(dev->pio.queue0);
1354                 else
1355                         b43legacy_dma_rx(dev->dma.rx_ring0);
1356         }
1357         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1358         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1359         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1360                 if (b43legacy_using_pio(dev))
1361                         b43legacy_pio_rx(dev->pio.queue3);
1362                 else
1363                         b43legacy_dma_rx(dev->dma.rx_ring3);
1364         }
1365         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1366         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1367
1368         if (reason & B43legacy_IRQ_TX_OK)
1369                 handle_irq_transmit_status(dev);
1370
1371         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1372         mmiowb();
1373         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1374 }
1375
1376 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1377                                u16 base, int queueidx)
1378 {
1379         u16 rxctl;
1380
1381         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1382         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1383                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1384         else
1385                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1386 }
1387
1388 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1389 {
1390         if (b43legacy_using_pio(dev) &&
1391             (dev->dev->id.revision < 3) &&
1392             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1393                 /* Apply a PIO specific workaround to the dma_reasons */
1394                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1395                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1396                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1397                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1398         }
1399
1400         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1401
1402         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1403                           dev->dma_reason[0]);
1404         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1405                           dev->dma_reason[1]);
1406         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1407                           dev->dma_reason[2]);
1408         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1409                           dev->dma_reason[3]);
1410         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1411                           dev->dma_reason[4]);
1412         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1413                           dev->dma_reason[5]);
1414 }
1415
1416 /* Interrupt handler top-half */
1417 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1418 {
1419         irqreturn_t ret = IRQ_NONE;
1420         struct b43legacy_wldev *dev = dev_id;
1421         u32 reason;
1422
1423         B43legacy_WARN_ON(!dev);
1424
1425         spin_lock(&dev->wl->irq_lock);
1426
1427         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1428                 /* This can only happen on shared IRQ lines. */
1429                 goto out;
1430         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1431         if (reason == 0xffffffff) /* shared IRQ */
1432                 goto out;
1433         ret = IRQ_HANDLED;
1434         reason &= dev->irq_mask;
1435         if (!reason)
1436                 goto out;
1437
1438         dev->dma_reason[0] = b43legacy_read32(dev,
1439                                               B43legacy_MMIO_DMA0_REASON)
1440                                               & 0x0001DC00;
1441         dev->dma_reason[1] = b43legacy_read32(dev,
1442                                               B43legacy_MMIO_DMA1_REASON)
1443                                               & 0x0000DC00;
1444         dev->dma_reason[2] = b43legacy_read32(dev,
1445                                               B43legacy_MMIO_DMA2_REASON)
1446                                               & 0x0000DC00;
1447         dev->dma_reason[3] = b43legacy_read32(dev,
1448                                               B43legacy_MMIO_DMA3_REASON)
1449                                               & 0x0001DC00;
1450         dev->dma_reason[4] = b43legacy_read32(dev,
1451                                               B43legacy_MMIO_DMA4_REASON)
1452                                               & 0x0000DC00;
1453         dev->dma_reason[5] = b43legacy_read32(dev,
1454                                               B43legacy_MMIO_DMA5_REASON)
1455                                               & 0x0000DC00;
1456
1457         b43legacy_interrupt_ack(dev, reason);
1458         /* Disable all IRQs. They are enabled again in the bottom half. */
1459         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1460         /* Save the reason code and call our bottom half. */
1461         dev->irq_reason = reason;
1462         tasklet_schedule(&dev->isr_tasklet);
1463 out:
1464         mmiowb();
1465         spin_unlock(&dev->wl->irq_lock);
1466
1467         return ret;
1468 }
1469
1470 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1471 {
1472         release_firmware(dev->fw.ucode);
1473         dev->fw.ucode = NULL;
1474         release_firmware(dev->fw.pcm);
1475         dev->fw.pcm = NULL;
1476         release_firmware(dev->fw.initvals);
1477         dev->fw.initvals = NULL;
1478         release_firmware(dev->fw.initvals_band);
1479         dev->fw.initvals_band = NULL;
1480 }
1481
1482 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1483 {
1484         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1485                      "Drivers/b43#devicefirmware "
1486                      "and download the correct firmware (version 3).\n");
1487 }
1488
1489 static int do_request_fw(struct b43legacy_wldev *dev,
1490                          const char *name,
1491                          const struct firmware **fw)
1492 {
1493         char path[sizeof(modparam_fwpostfix) + 32];
1494         struct b43legacy_fw_header *hdr;
1495         u32 size;
1496         int err;
1497
1498         if (!name)
1499                 return 0;
1500
1501         snprintf(path, ARRAY_SIZE(path),
1502                  "b43legacy%s/%s.fw",
1503                  modparam_fwpostfix, name);
1504         err = request_firmware(fw, path, dev->dev->dev);
1505         if (err) {
1506                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1507                        "or load failed.\n", path);
1508                 return err;
1509         }
1510         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1511                 goto err_format;
1512         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1513         switch (hdr->type) {
1514         case B43legacy_FW_TYPE_UCODE:
1515         case B43legacy_FW_TYPE_PCM:
1516                 size = be32_to_cpu(hdr->size);
1517                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1518                         goto err_format;
1519                 /* fallthrough */
1520         case B43legacy_FW_TYPE_IV:
1521                 if (hdr->ver != 1)
1522                         goto err_format;
1523                 break;
1524         default:
1525                 goto err_format;
1526         }
1527
1528         return err;
1529
1530 err_format:
1531         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1532         return -EPROTO;
1533 }
1534
1535 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1536 {
1537         struct b43legacy_firmware *fw = &dev->fw;
1538         const u8 rev = dev->dev->id.revision;
1539         const char *filename;
1540         u32 tmshigh;
1541         int err;
1542
1543         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1544         if (!fw->ucode) {
1545                 if (rev == 2)
1546                         filename = "ucode2";
1547                 else if (rev == 4)
1548                         filename = "ucode4";
1549                 else
1550                         filename = "ucode5";
1551                 err = do_request_fw(dev, filename, &fw->ucode);
1552                 if (err)
1553                         goto err_load;
1554         }
1555         if (!fw->pcm) {
1556                 if (rev < 5)
1557                         filename = "pcm4";
1558                 else
1559                         filename = "pcm5";
1560                 err = do_request_fw(dev, filename, &fw->pcm);
1561                 if (err)
1562                         goto err_load;
1563         }
1564         if (!fw->initvals) {
1565                 switch (dev->phy.type) {
1566                 case B43legacy_PHYTYPE_B:
1567                 case B43legacy_PHYTYPE_G:
1568                         if ((rev >= 5) && (rev <= 10))
1569                                 filename = "b0g0initvals5";
1570                         else if (rev == 2 || rev == 4)
1571                                 filename = "b0g0initvals2";
1572                         else
1573                                 goto err_no_initvals;
1574                         break;
1575                 default:
1576                         goto err_no_initvals;
1577                 }
1578                 err = do_request_fw(dev, filename, &fw->initvals);
1579                 if (err)
1580                         goto err_load;
1581         }
1582         if (!fw->initvals_band) {
1583                 switch (dev->phy.type) {
1584                 case B43legacy_PHYTYPE_B:
1585                 case B43legacy_PHYTYPE_G:
1586                         if ((rev >= 5) && (rev <= 10))
1587                                 filename = "b0g0bsinitvals5";
1588                         else if (rev >= 11)
1589                                 filename = NULL;
1590                         else if (rev == 2 || rev == 4)
1591                                 filename = NULL;
1592                         else
1593                                 goto err_no_initvals;
1594                         break;
1595                 default:
1596                         goto err_no_initvals;
1597                 }
1598                 err = do_request_fw(dev, filename, &fw->initvals_band);
1599                 if (err)
1600                         goto err_load;
1601         }
1602
1603         return 0;
1604
1605 err_load:
1606         b43legacy_print_fw_helptext(dev->wl);
1607         goto error;
1608
1609 err_no_initvals:
1610         err = -ENODEV;
1611         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1612                "core rev %u\n", dev->phy.type, rev);
1613         goto error;
1614
1615 error:
1616         b43legacy_release_firmware(dev);
1617         return err;
1618 }
1619
1620 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1621 {
1622         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1623         const __be32 *data;
1624         unsigned int i;
1625         unsigned int len;
1626         u16 fwrev;
1627         u16 fwpatch;
1628         u16 fwdate;
1629         u16 fwtime;
1630         u32 tmp, macctl;
1631         int err = 0;
1632
1633         /* Jump the microcode PSM to offset 0 */
1634         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1635         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1636         macctl |= B43legacy_MACCTL_PSM_JMP0;
1637         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1638         /* Zero out all microcode PSM registers and shared memory. */
1639         for (i = 0; i < 64; i++)
1640                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1641         for (i = 0; i < 4096; i += 2)
1642                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1643
1644         /* Upload Microcode. */
1645         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1646         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1647         b43legacy_shm_control_word(dev,
1648                                    B43legacy_SHM_UCODE |
1649                                    B43legacy_SHM_AUTOINC_W,
1650                                    0x0000);
1651         for (i = 0; i < len; i++) {
1652                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1653                                     be32_to_cpu(data[i]));
1654                 udelay(10);
1655         }
1656
1657         if (dev->fw.pcm) {
1658                 /* Upload PCM data. */
1659                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1660                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1661                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1662                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1663                 /* No need for autoinc bit in SHM_HW */
1664                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1665                 for (i = 0; i < len; i++) {
1666                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1667                                           be32_to_cpu(data[i]));
1668                         udelay(10);
1669                 }
1670         }
1671
1672         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1673                           B43legacy_IRQ_ALL);
1674
1675         /* Start the microcode PSM */
1676         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1677         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1678         macctl |= B43legacy_MACCTL_PSM_RUN;
1679         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1680
1681         /* Wait for the microcode to load and respond */
1682         i = 0;
1683         while (1) {
1684                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1685                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1686                         break;
1687                 i++;
1688                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1689                         b43legacyerr(dev->wl, "Microcode not responding\n");
1690                         b43legacy_print_fw_helptext(dev->wl);
1691                         err = -ENODEV;
1692                         goto error;
1693                 }
1694                 msleep_interruptible(50);
1695                 if (signal_pending(current)) {
1696                         err = -EINTR;
1697                         goto error;
1698                 }
1699         }
1700         /* dummy read follows */
1701         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1702
1703         /* Get and check the revisions. */
1704         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1705                                      B43legacy_SHM_SH_UCODEREV);
1706         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1707                                        B43legacy_SHM_SH_UCODEPATCH);
1708         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1709                                       B43legacy_SHM_SH_UCODEDATE);
1710         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1711                                       B43legacy_SHM_SH_UCODETIME);
1712
1713         if (fwrev > 0x128) {
1714                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1715                              " Only firmware from binary drivers version 3.x"
1716                              " is supported. You must change your firmware"
1717                              " files.\n");
1718                 b43legacy_print_fw_helptext(dev->wl);
1719                 err = -EOPNOTSUPP;
1720                 goto error;
1721         }
1722         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1723                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1724                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1725                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1726                       fwtime & 0x1F);
1727
1728         dev->fw.rev = fwrev;
1729         dev->fw.patch = fwpatch;
1730
1731         return 0;
1732
1733 error:
1734         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1735         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1736         macctl |= B43legacy_MACCTL_PSM_JMP0;
1737         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1738
1739         return err;
1740 }
1741
1742 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1743                                     const struct b43legacy_iv *ivals,
1744                                     size_t count,
1745                                     size_t array_size)
1746 {
1747         const struct b43legacy_iv *iv;
1748         u16 offset;
1749         size_t i;
1750         bool bit32;
1751
1752         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1753         iv = ivals;
1754         for (i = 0; i < count; i++) {
1755                 if (array_size < sizeof(iv->offset_size))
1756                         goto err_format;
1757                 array_size -= sizeof(iv->offset_size);
1758                 offset = be16_to_cpu(iv->offset_size);
1759                 bit32 = !!(offset & B43legacy_IV_32BIT);
1760                 offset &= B43legacy_IV_OFFSET_MASK;
1761                 if (offset >= 0x1000)
1762                         goto err_format;
1763                 if (bit32) {
1764                         u32 value;
1765
1766                         if (array_size < sizeof(iv->data.d32))
1767                                 goto err_format;
1768                         array_size -= sizeof(iv->data.d32);
1769
1770                         value = get_unaligned_be32(&iv->data.d32);
1771                         b43legacy_write32(dev, offset, value);
1772
1773                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1774                                                         sizeof(__be16) +
1775                                                         sizeof(__be32));
1776                 } else {
1777                         u16 value;
1778
1779                         if (array_size < sizeof(iv->data.d16))
1780                                 goto err_format;
1781                         array_size -= sizeof(iv->data.d16);
1782
1783                         value = be16_to_cpu(iv->data.d16);
1784                         b43legacy_write16(dev, offset, value);
1785
1786                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1787                                                         sizeof(__be16) +
1788                                                         sizeof(__be16));
1789                 }
1790         }
1791         if (array_size)
1792                 goto err_format;
1793
1794         return 0;
1795
1796 err_format:
1797         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1798         b43legacy_print_fw_helptext(dev->wl);
1799
1800         return -EPROTO;
1801 }
1802
1803 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1804 {
1805         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1806         const struct b43legacy_fw_header *hdr;
1807         struct b43legacy_firmware *fw = &dev->fw;
1808         const struct b43legacy_iv *ivals;
1809         size_t count;
1810         int err;
1811
1812         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1813         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1814         count = be32_to_cpu(hdr->size);
1815         err = b43legacy_write_initvals(dev, ivals, count,
1816                                  fw->initvals->size - hdr_len);
1817         if (err)
1818                 goto out;
1819         if (fw->initvals_band) {
1820                 hdr = (const struct b43legacy_fw_header *)
1821                       (fw->initvals_band->data);
1822                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1823                         + hdr_len);
1824                 count = be32_to_cpu(hdr->size);
1825                 err = b43legacy_write_initvals(dev, ivals, count,
1826                                          fw->initvals_band->size - hdr_len);
1827                 if (err)
1828                         goto out;
1829         }
1830 out:
1831
1832         return err;
1833 }
1834
1835 /* Initialize the GPIOs
1836  * http://bcm-specs.sipsolutions.net/GPIO
1837  */
1838 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1839 {
1840         struct ssb_bus *bus = dev->dev->bus;
1841         struct ssb_device *gpiodev, *pcidev = NULL;
1842         u32 mask;
1843         u32 set;
1844
1845         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1846                           b43legacy_read32(dev,
1847                           B43legacy_MMIO_MACCTL)
1848                           & 0xFFFF3FFF);
1849
1850         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1851                           b43legacy_read16(dev,
1852                           B43legacy_MMIO_GPIO_MASK)
1853                           | 0x000F);
1854
1855         mask = 0x0000001F;
1856         set = 0x0000000F;
1857         if (dev->dev->bus->chip_id == 0x4301) {
1858                 mask |= 0x0060;
1859                 set |= 0x0060;
1860         }
1861         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1862                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1863                                   b43legacy_read16(dev,
1864                                   B43legacy_MMIO_GPIO_MASK)
1865                                   | 0x0200);
1866                 mask |= 0x0200;
1867                 set |= 0x0200;
1868         }
1869         if (dev->dev->id.revision >= 2)
1870                 mask  |= 0x0010; /* FIXME: This is redundant. */
1871
1872 #ifdef CONFIG_SSB_DRIVER_PCICORE
1873         pcidev = bus->pcicore.dev;
1874 #endif
1875         gpiodev = bus->chipco.dev ? : pcidev;
1876         if (!gpiodev)
1877                 return 0;
1878         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1879                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1880                      & mask) | set);
1881
1882         return 0;
1883 }
1884
1885 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1886 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1887 {
1888         struct ssb_bus *bus = dev->dev->bus;
1889         struct ssb_device *gpiodev, *pcidev = NULL;
1890
1891 #ifdef CONFIG_SSB_DRIVER_PCICORE
1892         pcidev = bus->pcicore.dev;
1893 #endif
1894         gpiodev = bus->chipco.dev ? : pcidev;
1895         if (!gpiodev)
1896                 return;
1897         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1898 }
1899
1900 /* http://bcm-specs.sipsolutions.net/EnableMac */
1901 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1902 {
1903         dev->mac_suspended--;
1904         B43legacy_WARN_ON(dev->mac_suspended < 0);
1905         B43legacy_WARN_ON(irqs_disabled());
1906         if (dev->mac_suspended == 0) {
1907                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1908                                   b43legacy_read32(dev,
1909                                   B43legacy_MMIO_MACCTL)
1910                                   | B43legacy_MACCTL_ENABLED);
1911                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1912                                   B43legacy_IRQ_MAC_SUSPENDED);
1913                 /* the next two are dummy reads */
1914                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1915                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1916                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1917
1918                 /* Re-enable IRQs. */
1919                 spin_lock_irq(&dev->wl->irq_lock);
1920                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1921                                   dev->irq_mask);
1922                 spin_unlock_irq(&dev->wl->irq_lock);
1923         }
1924 }
1925
1926 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1927 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1928 {
1929         int i;
1930         u32 tmp;
1931
1932         might_sleep();
1933         B43legacy_WARN_ON(irqs_disabled());
1934         B43legacy_WARN_ON(dev->mac_suspended < 0);
1935
1936         if (dev->mac_suspended == 0) {
1937                 /* Mask IRQs before suspending MAC. Otherwise
1938                  * the MAC stays busy and won't suspend. */
1939                 spin_lock_irq(&dev->wl->irq_lock);
1940                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1941                 spin_unlock_irq(&dev->wl->irq_lock);
1942                 b43legacy_synchronize_irq(dev);
1943
1944                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1945                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1946                                   b43legacy_read32(dev,
1947                                   B43legacy_MMIO_MACCTL)
1948                                   & ~B43legacy_MACCTL_ENABLED);
1949                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1950                 for (i = 40; i; i--) {
1951                         tmp = b43legacy_read32(dev,
1952                                                B43legacy_MMIO_GEN_IRQ_REASON);
1953                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1954                                 goto out;
1955                         msleep(1);
1956                 }
1957                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1958         }
1959 out:
1960         dev->mac_suspended++;
1961 }
1962
1963 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1964 {
1965         struct b43legacy_wl *wl = dev->wl;
1966         u32 ctl;
1967         u16 cfp_pretbtt;
1968
1969         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1970         /* Reset status to STA infrastructure mode. */
1971         ctl &= ~B43legacy_MACCTL_AP;
1972         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1973         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1974         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1975         ctl &= ~B43legacy_MACCTL_PROMISC;
1976         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
1977         ctl |= B43legacy_MACCTL_INFRA;
1978
1979         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1980                 ctl |= B43legacy_MACCTL_AP;
1981         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
1982                 ctl &= ~B43legacy_MACCTL_INFRA;
1983
1984         if (wl->filter_flags & FIF_CONTROL)
1985                 ctl |= B43legacy_MACCTL_KEEP_CTL;
1986         if (wl->filter_flags & FIF_FCSFAIL)
1987                 ctl |= B43legacy_MACCTL_KEEP_BAD;
1988         if (wl->filter_flags & FIF_PLCPFAIL)
1989                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1990         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
1991                 ctl |= B43legacy_MACCTL_PROMISC;
1992         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1993                 ctl |= B43legacy_MACCTL_BEACPROMISC;
1994
1995         /* Workaround: On old hardware the HW-MAC-address-filter
1996          * doesn't work properly, so always run promisc in filter
1997          * it in software. */
1998         if (dev->dev->id.revision <= 4)
1999                 ctl |= B43legacy_MACCTL_PROMISC;
2000
2001         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2002
2003         cfp_pretbtt = 2;
2004         if ((ctl & B43legacy_MACCTL_INFRA) &&
2005             !(ctl & B43legacy_MACCTL_AP)) {
2006                 if (dev->dev->bus->chip_id == 0x4306 &&
2007                     dev->dev->bus->chip_rev == 3)
2008                         cfp_pretbtt = 100;
2009                 else
2010                         cfp_pretbtt = 50;
2011         }
2012         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2013 }
2014
2015 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2016                                         u16 rate,
2017                                         int is_ofdm)
2018 {
2019         u16 offset;
2020
2021         if (is_ofdm) {
2022                 offset = 0x480;
2023                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2024         } else {
2025                 offset = 0x4C0;
2026                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2027         }
2028         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2029                               b43legacy_shm_read16(dev,
2030                               B43legacy_SHM_SHARED, offset));
2031 }
2032
2033 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2034 {
2035         switch (dev->phy.type) {
2036         case B43legacy_PHYTYPE_G:
2037                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2038                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2039                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2040                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2041                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2042                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2043                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2044                 /* fallthrough */
2045         case B43legacy_PHYTYPE_B:
2046                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2047                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2048                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2049                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2050                 break;
2051         default:
2052                 B43legacy_BUG_ON(1);
2053         }
2054 }
2055
2056 /* Set the TX-Antenna for management frames sent by firmware. */
2057 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2058                                           int antenna)
2059 {
2060         u16 ant = 0;
2061         u16 tmp;
2062
2063         switch (antenna) {
2064         case B43legacy_ANTENNA0:
2065                 ant |= B43legacy_TX4_PHY_ANT0;
2066                 break;
2067         case B43legacy_ANTENNA1:
2068                 ant |= B43legacy_TX4_PHY_ANT1;
2069                 break;
2070         case B43legacy_ANTENNA_AUTO:
2071                 ant |= B43legacy_TX4_PHY_ANTLAST;
2072                 break;
2073         default:
2074                 B43legacy_BUG_ON(1);
2075         }
2076
2077         /* FIXME We also need to set the other flags of the PHY control
2078          * field somewhere. */
2079
2080         /* For Beacons */
2081         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2082                                    B43legacy_SHM_SH_BEACPHYCTL);
2083         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2084         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2085                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2086         /* For ACK/CTS */
2087         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2088                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2089         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2090         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2091                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2092         /* For Probe Resposes */
2093         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2094                                    B43legacy_SHM_SH_PRPHYCTL);
2095         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2096         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2097                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2098 }
2099
2100 /* This is the opposite of b43legacy_chip_init() */
2101 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2102 {
2103         b43legacy_radio_turn_off(dev, 1);
2104         b43legacy_gpio_cleanup(dev);
2105         /* firmware is released later */
2106 }
2107
2108 /* Initialize the chip
2109  * http://bcm-specs.sipsolutions.net/ChipInit
2110  */
2111 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2112 {
2113         struct b43legacy_phy *phy = &dev->phy;
2114         int err;
2115         int tmp;
2116         u32 value32, macctl;
2117         u16 value16;
2118
2119         /* Initialize the MAC control */
2120         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2121         if (dev->phy.gmode)
2122                 macctl |= B43legacy_MACCTL_GMODE;
2123         macctl |= B43legacy_MACCTL_INFRA;
2124         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2125
2126         err = b43legacy_request_firmware(dev);
2127         if (err)
2128                 goto out;
2129         err = b43legacy_upload_microcode(dev);
2130         if (err)
2131                 goto out; /* firmware is released later */
2132
2133         err = b43legacy_gpio_init(dev);
2134         if (err)
2135                 goto out; /* firmware is released later */
2136
2137         err = b43legacy_upload_initvals(dev);
2138         if (err)
2139                 goto err_gpio_clean;
2140         b43legacy_radio_turn_on(dev);
2141
2142         b43legacy_write16(dev, 0x03E6, 0x0000);
2143         err = b43legacy_phy_init(dev);
2144         if (err)
2145                 goto err_radio_off;
2146
2147         /* Select initial Interference Mitigation. */
2148         tmp = phy->interfmode;
2149         phy->interfmode = B43legacy_INTERFMODE_NONE;
2150         b43legacy_radio_set_interference_mitigation(dev, tmp);
2151
2152         b43legacy_phy_set_antenna_diversity(dev);
2153         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2154
2155         if (phy->type == B43legacy_PHYTYPE_B) {
2156                 value16 = b43legacy_read16(dev, 0x005E);
2157                 value16 |= 0x0004;
2158                 b43legacy_write16(dev, 0x005E, value16);
2159         }
2160         b43legacy_write32(dev, 0x0100, 0x01000000);
2161         if (dev->dev->id.revision < 5)
2162                 b43legacy_write32(dev, 0x010C, 0x01000000);
2163
2164         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2165         value32 &= ~B43legacy_MACCTL_INFRA;
2166         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2167         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2168         value32 |= B43legacy_MACCTL_INFRA;
2169         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2170
2171         if (b43legacy_using_pio(dev)) {
2172                 b43legacy_write32(dev, 0x0210, 0x00000100);
2173                 b43legacy_write32(dev, 0x0230, 0x00000100);
2174                 b43legacy_write32(dev, 0x0250, 0x00000100);
2175                 b43legacy_write32(dev, 0x0270, 0x00000100);
2176                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2177                                       0x0000);
2178         }
2179
2180         /* Probe Response Timeout value */
2181         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2182         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2183
2184         /* Initially set the wireless operation mode. */
2185         b43legacy_adjust_opmode(dev);
2186
2187         if (dev->dev->id.revision < 3) {
2188                 b43legacy_write16(dev, 0x060E, 0x0000);
2189                 b43legacy_write16(dev, 0x0610, 0x8000);
2190                 b43legacy_write16(dev, 0x0604, 0x0000);
2191                 b43legacy_write16(dev, 0x0606, 0x0200);
2192         } else {
2193                 b43legacy_write32(dev, 0x0188, 0x80000000);
2194                 b43legacy_write32(dev, 0x018C, 0x02000000);
2195         }
2196         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2197         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2198         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2199         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2200         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2201         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2202         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2203
2204         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2205         value32 |= 0x00100000;
2206         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2207
2208         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2209                           dev->dev->bus->chipco.fast_pwrup_delay);
2210
2211         /* PHY TX errors counter. */
2212         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2213
2214         B43legacy_WARN_ON(err != 0);
2215         b43legacydbg(dev->wl, "Chip initialized\n");
2216 out:
2217         return err;
2218
2219 err_radio_off:
2220         b43legacy_radio_turn_off(dev, 1);
2221 err_gpio_clean:
2222         b43legacy_gpio_cleanup(dev);
2223         goto out;
2224 }
2225
2226 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2227 {
2228         struct b43legacy_phy *phy = &dev->phy;
2229
2230         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2231                 return;
2232
2233         b43legacy_mac_suspend(dev);
2234         b43legacy_phy_lo_g_measure(dev);
2235         b43legacy_mac_enable(dev);
2236 }
2237
2238 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2239 {
2240         b43legacy_phy_lo_mark_all_unused(dev);
2241         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2242                 b43legacy_mac_suspend(dev);
2243                 b43legacy_calc_nrssi_slope(dev);
2244                 b43legacy_mac_enable(dev);
2245         }
2246 }
2247
2248 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2249 {
2250         /* Update device statistics. */
2251         b43legacy_calculate_link_quality(dev);
2252 }
2253
2254 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2255 {
2256         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2257
2258         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2259         wmb();
2260 }
2261
2262 static void do_periodic_work(struct b43legacy_wldev *dev)
2263 {
2264         unsigned int state;
2265
2266         state = dev->periodic_state;
2267         if (state % 8 == 0)
2268                 b43legacy_periodic_every120sec(dev);
2269         if (state % 4 == 0)
2270                 b43legacy_periodic_every60sec(dev);
2271         if (state % 2 == 0)
2272                 b43legacy_periodic_every30sec(dev);
2273         b43legacy_periodic_every15sec(dev);
2274 }
2275
2276 /* Periodic work locking policy:
2277  *      The whole periodic work handler is protected by
2278  *      wl->mutex. If another lock is needed somewhere in the
2279  *      pwork callchain, it's aquired in-place, where it's needed.
2280  */
2281 static void b43legacy_periodic_work_handler(struct work_struct *work)
2282 {
2283         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2284                                              periodic_work.work);
2285         struct b43legacy_wl *wl = dev->wl;
2286         unsigned long delay;
2287
2288         mutex_lock(&wl->mutex);
2289
2290         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2291                 goto out;
2292         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2293                 goto out_requeue;
2294
2295         do_periodic_work(dev);
2296
2297         dev->periodic_state++;
2298 out_requeue:
2299         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2300                 delay = msecs_to_jiffies(50);
2301         else
2302                 delay = round_jiffies_relative(HZ * 15);
2303         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2304 out:
2305         mutex_unlock(&wl->mutex);
2306 }
2307
2308 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2309 {
2310         struct delayed_work *work = &dev->periodic_work;
2311
2312         dev->periodic_state = 0;
2313         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2314         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2315 }
2316
2317 /* Validate access to the chip (SHM) */
2318 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2319 {
2320         u32 value;
2321         u32 shm_backup;
2322
2323         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2324         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2325         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2326                                  0xAA5555AA)
2327                 goto error;
2328         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2329         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2330                                  0x55AAAA55)
2331                 goto error;
2332         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2333
2334         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2335         if ((value | B43legacy_MACCTL_GMODE) !=
2336             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2337                 goto error;
2338
2339         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2340         if (value)
2341                 goto error;
2342
2343         return 0;
2344 error:
2345         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2346         return -ENODEV;
2347 }
2348
2349 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2350 {
2351         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2352         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2353         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2354                                         0x0056);
2355         /* KTP is a word address, but we address SHM bytewise.
2356          * So multiply by two.
2357          */
2358         dev->ktp *= 2;
2359         if (dev->dev->id.revision >= 5)
2360                 /* Number of RCMTA address slots */
2361                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2362                                   dev->max_nr_keys - 8);
2363 }
2364
2365 #ifdef CONFIG_B43LEGACY_HWRNG
2366 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2367 {
2368         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2369         unsigned long flags;
2370
2371         /* Don't take wl->mutex here, as it could deadlock with
2372          * hwrng internal locking. It's not needed to take
2373          * wl->mutex here, anyway. */
2374
2375         spin_lock_irqsave(&wl->irq_lock, flags);
2376         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2377         spin_unlock_irqrestore(&wl->irq_lock, flags);
2378
2379         return (sizeof(u16));
2380 }
2381 #endif
2382
2383 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2384 {
2385 #ifdef CONFIG_B43LEGACY_HWRNG
2386         if (wl->rng_initialized)
2387                 hwrng_unregister(&wl->rng);
2388 #endif
2389 }
2390
2391 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2392 {
2393         int err = 0;
2394
2395 #ifdef CONFIG_B43LEGACY_HWRNG
2396         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2397                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2398         wl->rng.name = wl->rng_name;
2399         wl->rng.data_read = b43legacy_rng_read;
2400         wl->rng.priv = (unsigned long)wl;
2401         wl->rng_initialized = 1;
2402         err = hwrng_register(&wl->rng);
2403         if (err) {
2404                 wl->rng_initialized = 0;
2405                 b43legacyerr(wl, "Failed to register the random "
2406                        "number generator (%d)\n", err);
2407         }
2408
2409 #endif
2410         return err;
2411 }
2412
2413 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2414                            struct sk_buff *skb)
2415 {
2416         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2417         struct b43legacy_wldev *dev = wl->current_dev;
2418         int err = -ENODEV;
2419         unsigned long flags;
2420
2421         if (unlikely(!dev))
2422                 goto out;
2423         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2424                 goto out;
2425         /* DMA-TX is done without a global lock. */
2426         if (b43legacy_using_pio(dev)) {
2427                 spin_lock_irqsave(&wl->irq_lock, flags);
2428                 err = b43legacy_pio_tx(dev, skb);
2429                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2430         } else
2431                 err = b43legacy_dma_tx(dev, skb);
2432 out:
2433         if (unlikely(err)) {
2434                 /* Drop the packet. */
2435                 dev_kfree_skb_any(skb);
2436         }
2437         return NETDEV_TX_OK;
2438 }
2439
2440 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2441                                 const struct ieee80211_tx_queue_params *params)
2442 {
2443         return 0;
2444 }
2445
2446 static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2447                                      struct ieee80211_tx_queue_stats *stats)
2448 {
2449         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2450         struct b43legacy_wldev *dev = wl->current_dev;
2451         unsigned long flags;
2452         int err = -ENODEV;
2453
2454         if (!dev)
2455                 goto out;
2456         spin_lock_irqsave(&wl->irq_lock, flags);
2457         if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2458                 if (b43legacy_using_pio(dev))
2459                         b43legacy_pio_get_tx_stats(dev, stats);
2460                 else
2461                         b43legacy_dma_get_tx_stats(dev, stats);
2462                 err = 0;
2463         }
2464         spin_unlock_irqrestore(&wl->irq_lock, flags);
2465 out:
2466         return err;
2467 }
2468
2469 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2470                                   struct ieee80211_low_level_stats *stats)
2471 {
2472         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2473         unsigned long flags;
2474
2475         spin_lock_irqsave(&wl->irq_lock, flags);
2476         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2477         spin_unlock_irqrestore(&wl->irq_lock, flags);
2478
2479         return 0;
2480 }
2481
2482 static const char *phymode_to_string(unsigned int phymode)
2483 {
2484         switch (phymode) {
2485         case B43legacy_PHYMODE_B:
2486                 return "B";
2487         case B43legacy_PHYMODE_G:
2488                 return "G";
2489         default:
2490                 B43legacy_BUG_ON(1);
2491         }
2492         return "";
2493 }
2494
2495 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2496                                   unsigned int phymode,
2497                                   struct b43legacy_wldev **dev,
2498                                   bool *gmode)
2499 {
2500         struct b43legacy_wldev *d;
2501
2502         list_for_each_entry(d, &wl->devlist, list) {
2503                 if (d->phy.possible_phymodes & phymode) {
2504                         /* Ok, this device supports the PHY-mode.
2505                          * Set the gmode bit. */
2506                         *gmode = 1;
2507                         *dev = d;
2508
2509                         return 0;
2510                 }
2511         }
2512
2513         return -ESRCH;
2514 }
2515
2516 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2517 {
2518         struct ssb_device *sdev = dev->dev;
2519         u32 tmslow;
2520
2521         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2522         tmslow &= ~B43legacy_TMSLOW_GMODE;
2523         tmslow |= B43legacy_TMSLOW_PHYRESET;
2524         tmslow |= SSB_TMSLOW_FGC;
2525         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2526         msleep(1);
2527
2528         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2529         tmslow &= ~SSB_TMSLOW_FGC;
2530         tmslow |= B43legacy_TMSLOW_PHYRESET;
2531         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2532         msleep(1);
2533 }
2534
2535 /* Expects wl->mutex locked */
2536 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2537                                       unsigned int new_mode)
2538 {
2539         struct b43legacy_wldev *uninitialized_var(up_dev);
2540         struct b43legacy_wldev *down_dev;
2541         int err;
2542         bool gmode = 0;
2543         int prev_status;
2544
2545         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2546         if (err) {
2547                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2548                        phymode_to_string(new_mode));
2549                 return err;
2550         }
2551         if ((up_dev == wl->current_dev) &&
2552             (!!wl->current_dev->phy.gmode == !!gmode))
2553                 /* This device is already running. */
2554                 return 0;
2555         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2556                phymode_to_string(new_mode));
2557         down_dev = wl->current_dev;
2558
2559         prev_status = b43legacy_status(down_dev);
2560         /* Shutdown the currently running core. */
2561         if (prev_status >= B43legacy_STAT_STARTED)
2562                 b43legacy_wireless_core_stop(down_dev);
2563         if (prev_status >= B43legacy_STAT_INITIALIZED)
2564                 b43legacy_wireless_core_exit(down_dev);
2565
2566         if (down_dev != up_dev)
2567                 /* We switch to a different core, so we put PHY into
2568                  * RESET on the old core. */
2569                 b43legacy_put_phy_into_reset(down_dev);
2570
2571         /* Now start the new core. */
2572         up_dev->phy.gmode = gmode;
2573         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2574                 err = b43legacy_wireless_core_init(up_dev);
2575                 if (err) {
2576                         b43legacyerr(wl, "Fatal: Could not initialize device"
2577                                      " for newly selected %s-PHY mode\n",
2578                                      phymode_to_string(new_mode));
2579                         goto init_failure;
2580                 }
2581         }
2582         if (prev_status >= B43legacy_STAT_STARTED) {
2583                 err = b43legacy_wireless_core_start(up_dev);
2584                 if (err) {
2585                         b43legacyerr(wl, "Fatal: Coult not start device for "
2586                                "newly selected %s-PHY mode\n",
2587                                phymode_to_string(new_mode));
2588                         b43legacy_wireless_core_exit(up_dev);
2589                         goto init_failure;
2590                 }
2591         }
2592         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2593
2594         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2595
2596         wl->current_dev = up_dev;
2597
2598         return 0;
2599 init_failure:
2600         /* Whoops, failed to init the new core. No core is operating now. */
2601         wl->current_dev = NULL;
2602         return err;
2603 }
2604
2605 /* Write the short and long frame retry limit values. */
2606 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2607                                        unsigned int short_retry,
2608                                        unsigned int long_retry)
2609 {
2610         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2611          * the chip-internal counter. */
2612         short_retry = min(short_retry, (unsigned int)0xF);
2613         long_retry = min(long_retry, (unsigned int)0xF);
2614
2615         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2616         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2617 }
2618
2619 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2620                                    u32 changed)
2621 {
2622         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2623         struct b43legacy_wldev *dev;
2624         struct b43legacy_phy *phy;
2625         struct ieee80211_conf *conf = &hw->conf;
2626         unsigned long flags;
2627         unsigned int new_phymode = 0xFFFF;
2628         int antenna_tx;
2629         int antenna_rx;
2630         int err = 0;
2631
2632         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2633         antenna_rx = B43legacy_ANTENNA_DEFAULT;
2634
2635         mutex_lock(&wl->mutex);
2636         dev = wl->current_dev;
2637         phy = &dev->phy;
2638
2639         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2640                 b43legacy_set_retry_limits(dev,
2641                                            conf->short_frame_max_tx_count,
2642                                            conf->long_frame_max_tx_count);
2643         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2644         if (!changed)
2645                 goto out_unlock_mutex;
2646
2647         /* Switch the PHY mode (if necessary). */
2648         switch (conf->channel->band) {
2649         case IEEE80211_BAND_2GHZ:
2650                 if (phy->type == B43legacy_PHYTYPE_B)
2651                         new_phymode = B43legacy_PHYMODE_B;
2652                 else
2653                         new_phymode = B43legacy_PHYMODE_G;
2654                 break;
2655         default:
2656                 B43legacy_WARN_ON(1);
2657         }
2658         err = b43legacy_switch_phymode(wl, new_phymode);
2659         if (err)
2660                 goto out_unlock_mutex;
2661
2662         /* Disable IRQs while reconfiguring the device.
2663          * This makes it possible to drop the spinlock throughout
2664          * the reconfiguration process. */
2665         spin_lock_irqsave(&wl->irq_lock, flags);
2666         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2667                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2668                 goto out_unlock_mutex;
2669         }
2670         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2671         spin_unlock_irqrestore(&wl->irq_lock, flags);
2672         b43legacy_synchronize_irq(dev);
2673
2674         /* Switch to the requested channel.
2675          * The firmware takes care of races with the TX handler. */
2676         if (conf->channel->hw_value != phy->channel)
2677                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2678
2679         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2680
2681         /* Adjust the desired TX power level. */
2682         if (conf->power_level != 0) {
2683                 if (conf->power_level != phy->power_level) {
2684                         phy->power_level = conf->power_level;
2685                         b43legacy_phy_xmitpower(dev);
2686                 }
2687         }
2688
2689         /* Antennas for RX and management frame TX. */
2690         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2691
2692         if (wl->radio_enabled != phy->radio_on) {
2693                 if (wl->radio_enabled) {
2694                         b43legacy_radio_turn_on(dev);
2695                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2696                         if (!dev->radio_hw_enable)
2697                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2698                                               " button still turns the radio"
2699                                               " physically off. Press the"
2700                                               " button to turn it on.\n");
2701                 } else {
2702                         b43legacy_radio_turn_off(dev, 0);
2703                         b43legacyinfo(dev->wl, "Radio turned off by"
2704                                       " software\n");
2705                 }
2706         }
2707
2708         spin_lock_irqsave(&wl->irq_lock, flags);
2709         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2710         mmiowb();
2711         spin_unlock_irqrestore(&wl->irq_lock, flags);
2712 out_unlock_mutex:
2713         mutex_unlock(&wl->mutex);
2714
2715         return err;
2716 }
2717
2718 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2719 {
2720         struct ieee80211_supported_band *sband =
2721                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2722         struct ieee80211_rate *rate;
2723         int i;
2724         u16 basic, direct, offset, basic_offset, rateptr;
2725
2726         for (i = 0; i < sband->n_bitrates; i++) {
2727                 rate = &sband->bitrates[i];
2728
2729                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2730                         direct = B43legacy_SHM_SH_CCKDIRECT;
2731                         basic = B43legacy_SHM_SH_CCKBASIC;
2732                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2733                         offset &= 0xF;
2734                 } else {
2735                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2736                         basic = B43legacy_SHM_SH_OFDMBASIC;
2737                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2738                         offset &= 0xF;
2739                 }
2740
2741                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2742
2743                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2744                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2745                         basic_offset &= 0xF;
2746                 } else {
2747                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2748                         basic_offset &= 0xF;
2749                 }
2750
2751                 /*
2752                  * Get the pointer that we need to point to
2753                  * from the direct map
2754                  */
2755                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2756                                                direct + 2 * basic_offset);
2757                 /* and write it to the basic map */
2758                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2759                                       basic + 2 * offset, rateptr);
2760         }
2761 }
2762
2763 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2764                                     struct ieee80211_vif *vif,
2765                                     struct ieee80211_bss_conf *conf,
2766                                     u32 changed)
2767 {
2768         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2769         struct b43legacy_wldev *dev;
2770         struct b43legacy_phy *phy;
2771         unsigned long flags;
2772
2773         mutex_lock(&wl->mutex);
2774         B43legacy_WARN_ON(wl->vif != vif);
2775
2776         dev = wl->current_dev;
2777         phy = &dev->phy;
2778
2779         /* Disable IRQs while reconfiguring the device.
2780          * This makes it possible to drop the spinlock throughout
2781          * the reconfiguration process. */
2782         spin_lock_irqsave(&wl->irq_lock, flags);
2783         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2784                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2785                 goto out_unlock_mutex;
2786         }
2787         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2788
2789         if (changed & BSS_CHANGED_BSSID) {
2790                 b43legacy_synchronize_irq(dev);
2791
2792                 if (conf->bssid)
2793                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2794                 else
2795                         memset(wl->bssid, 0, ETH_ALEN);
2796         }
2797
2798         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2799                 if (changed & BSS_CHANGED_BEACON &&
2800                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2801                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2802                         b43legacy_update_templates(wl);
2803
2804                 if (changed & BSS_CHANGED_BSSID)
2805                         b43legacy_write_mac_bssid_templates(dev);
2806         }
2807         spin_unlock_irqrestore(&wl->irq_lock, flags);
2808
2809         b43legacy_mac_suspend(dev);
2810
2811         if (changed & BSS_CHANGED_BEACON_INT &&
2812             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2813              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2814                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2815
2816         if (changed & BSS_CHANGED_BASIC_RATES)
2817                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2818
2819         if (changed & BSS_CHANGED_ERP_SLOT) {
2820                 if (conf->use_short_slot)
2821                         b43legacy_short_slot_timing_enable(dev);
2822                 else
2823                         b43legacy_short_slot_timing_disable(dev);
2824         }
2825
2826         b43legacy_mac_enable(dev);
2827
2828         spin_lock_irqsave(&wl->irq_lock, flags);
2829         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2830         /* XXX: why? */
2831         mmiowb();
2832         spin_unlock_irqrestore(&wl->irq_lock, flags);
2833  out_unlock_mutex:
2834         mutex_unlock(&wl->mutex);
2835 }
2836
2837 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2838                                           unsigned int changed,
2839                                           unsigned int *fflags,u64 multicast)
2840 {
2841         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2842         struct b43legacy_wldev *dev = wl->current_dev;
2843         unsigned long flags;
2844
2845         if (!dev) {
2846                 *fflags = 0;
2847                 return;
2848         }
2849
2850         spin_lock_irqsave(&wl->irq_lock, flags);
2851         *fflags &= FIF_PROMISC_IN_BSS |
2852                   FIF_ALLMULTI |
2853                   FIF_FCSFAIL |
2854                   FIF_PLCPFAIL |
2855                   FIF_CONTROL |
2856                   FIF_OTHER_BSS |
2857                   FIF_BCN_PRBRESP_PROMISC;
2858
2859         changed &= FIF_PROMISC_IN_BSS |
2860                    FIF_ALLMULTI |
2861                    FIF_FCSFAIL |
2862                    FIF_PLCPFAIL |
2863                    FIF_CONTROL |
2864                    FIF_OTHER_BSS |
2865                    FIF_BCN_PRBRESP_PROMISC;
2866
2867         wl->filter_flags = *fflags;
2868
2869         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2870                 b43legacy_adjust_opmode(dev);
2871         spin_unlock_irqrestore(&wl->irq_lock, flags);
2872 }
2873
2874 /* Locking: wl->mutex */
2875 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2876 {
2877         struct b43legacy_wl *wl = dev->wl;
2878         unsigned long flags;
2879
2880         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2881                 return;
2882
2883         /* Disable and sync interrupts. We must do this before than
2884          * setting the status to INITIALIZED, as the interrupt handler
2885          * won't care about IRQs then. */
2886         spin_lock_irqsave(&wl->irq_lock, flags);
2887         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2888         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2889         spin_unlock_irqrestore(&wl->irq_lock, flags);
2890         b43legacy_synchronize_irq(dev);
2891
2892         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2893
2894         mutex_unlock(&wl->mutex);
2895         /* Must unlock as it would otherwise deadlock. No races here.
2896          * Cancel the possibly running self-rearming periodic work. */
2897         cancel_delayed_work_sync(&dev->periodic_work);
2898         mutex_lock(&wl->mutex);
2899
2900         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2901
2902         b43legacy_mac_suspend(dev);
2903         free_irq(dev->dev->irq, dev);
2904         b43legacydbg(wl, "Wireless interface stopped\n");
2905 }
2906
2907 /* Locking: wl->mutex */
2908 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2909 {
2910         int err;
2911
2912         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2913
2914         drain_txstatus_queue(dev);
2915         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2916                           IRQF_SHARED, KBUILD_MODNAME, dev);
2917         if (err) {
2918                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2919                        dev->dev->irq);
2920                 goto out;
2921         }
2922         /* We are ready to run. */
2923         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2924
2925         /* Start data flow (TX/RX) */
2926         b43legacy_mac_enable(dev);
2927         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2928
2929         /* Start maintenance work */
2930         b43legacy_periodic_tasks_setup(dev);
2931
2932         b43legacydbg(dev->wl, "Wireless interface started\n");
2933 out:
2934         return err;
2935 }
2936
2937 /* Get PHY and RADIO versioning numbers */
2938 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2939 {
2940         struct b43legacy_phy *phy = &dev->phy;
2941         u32 tmp;
2942         u8 analog_type;
2943         u8 phy_type;
2944         u8 phy_rev;
2945         u16 radio_manuf;
2946         u16 radio_ver;
2947         u16 radio_rev;
2948         int unsupported = 0;
2949
2950         /* Get PHY versioning */
2951         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2952         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2953                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2954         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2955         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2956         switch (phy_type) {
2957         case B43legacy_PHYTYPE_B:
2958                 if (phy_rev != 2 && phy_rev != 4
2959                     && phy_rev != 6 && phy_rev != 7)
2960                         unsupported = 1;
2961                 break;
2962         case B43legacy_PHYTYPE_G:
2963                 if (phy_rev > 8)
2964                         unsupported = 1;
2965                 break;
2966         default:
2967                 unsupported = 1;
2968         };
2969         if (unsupported) {
2970                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2971                        "(Analog %u, Type %u, Revision %u)\n",
2972                        analog_type, phy_type, phy_rev);
2973                 return -EOPNOTSUPP;
2974         }
2975         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2976                analog_type, phy_type, phy_rev);
2977
2978
2979         /* Get RADIO versioning */
2980         if (dev->dev->bus->chip_id == 0x4317) {
2981                 if (dev->dev->bus->chip_rev == 0)
2982                         tmp = 0x3205017F;
2983                 else if (dev->dev->bus->chip_rev == 1)
2984                         tmp = 0x4205017F;
2985                 else
2986                         tmp = 0x5205017F;
2987         } else {
2988                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2989                                   B43legacy_RADIOCTL_ID);
2990                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2991                 tmp <<= 16;
2992                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2993                                   B43legacy_RADIOCTL_ID);
2994                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2995         }
2996         radio_manuf = (tmp & 0x00000FFF);
2997         radio_ver = (tmp & 0x0FFFF000) >> 12;
2998         radio_rev = (tmp & 0xF0000000) >> 28;
2999         switch (phy_type) {
3000         case B43legacy_PHYTYPE_B:
3001                 if ((radio_ver & 0xFFF0) != 0x2050)
3002                         unsupported = 1;
3003                 break;
3004         case B43legacy_PHYTYPE_G:
3005                 if (radio_ver != 0x2050)
3006                         unsupported = 1;
3007                 break;
3008         default:
3009                 B43legacy_BUG_ON(1);
3010         }
3011         if (unsupported) {
3012                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3013                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3014                        radio_manuf, radio_ver, radio_rev);
3015                 return -EOPNOTSUPP;
3016         }
3017         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3018                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3019
3020
3021         phy->radio_manuf = radio_manuf;
3022         phy->radio_ver = radio_ver;
3023         phy->radio_rev = radio_rev;
3024
3025         phy->analog = analog_type;
3026         phy->type = phy_type;
3027         phy->rev = phy_rev;
3028
3029         return 0;
3030 }
3031
3032 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3033                                       struct b43legacy_phy *phy)
3034 {
3035         struct b43legacy_lopair *lo;
3036         int i;
3037
3038         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3039         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3040
3041         /* Assume the radio is enabled. If it's not enabled, the state will
3042          * immediately get fixed on the first periodic work run. */
3043         dev->radio_hw_enable = 1;
3044
3045         phy->savedpctlreg = 0xFFFF;
3046         phy->aci_enable = 0;
3047         phy->aci_wlan_automatic = 0;
3048         phy->aci_hw_rssi = 0;
3049
3050         lo = phy->_lo_pairs;
3051         if (lo)
3052                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3053                                      B43legacy_LO_COUNT);
3054         phy->max_lb_gain = 0;
3055         phy->trsw_rx_gain = 0;
3056
3057         /* Set default attenuation values. */
3058         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3059         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3060         phy->txctl1 = b43legacy_default_txctl1(dev);
3061         phy->txpwr_offset = 0;
3062
3063         /* NRSSI */
3064         phy->nrssislope = 0;
3065         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3066                 phy->nrssi[i] = -1000;
3067         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3068                 phy->nrssi_lt[i] = i;
3069
3070         phy->lofcal = 0xFFFF;
3071         phy->initval = 0xFFFF;
3072
3073         phy->interfmode = B43legacy_INTERFMODE_NONE;
3074         phy->channel = 0xFF;
3075 }
3076
3077 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3078 {
3079         /* Flags */
3080         dev->dfq_valid = 0;
3081
3082         /* Stats */
3083         memset(&dev->stats, 0, sizeof(dev->stats));
3084
3085         setup_struct_phy_for_init(dev, &dev->phy);
3086
3087         /* IRQ related flags */
3088         dev->irq_reason = 0;
3089         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3090         dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3091
3092         dev->mac_suspended = 1;
3093
3094         /* Noise calculation context */
3095         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3096 }
3097
3098 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3099 {
3100 #ifdef CONFIG_SSB_DRIVER_PCICORE
3101         struct ssb_bus *bus = dev->dev->bus;
3102         u32 tmp;
3103
3104         if (bus->pcicore.dev &&
3105             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3106             bus->pcicore.dev->id.revision <= 5) {
3107                 /* IMCFGLO timeouts workaround. */
3108                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3109                 switch (bus->bustype) {
3110                 case SSB_BUSTYPE_PCI:
3111                 case SSB_BUSTYPE_PCMCIA:
3112                         tmp &= ~SSB_IMCFGLO_REQTO;
3113                         tmp &= ~SSB_IMCFGLO_SERTO;
3114                         tmp |= 0x32;
3115                         break;
3116                 case SSB_BUSTYPE_SSB:
3117                         tmp &= ~SSB_IMCFGLO_REQTO;
3118                         tmp &= ~SSB_IMCFGLO_SERTO;
3119                         tmp |= 0x53;
3120                         break;
3121                 default:
3122                         break;
3123                 }
3124                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3125         }
3126 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3127 }
3128
3129 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,