ath9k: INI update for AR9285 and periodic PA offset caliberation
[linux-2.6.git] / drivers / net / wireless / ath9k / hw.c
1 /*
2  * Copyright (c) 2008 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK            22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33                               enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35                               struct ar5416_eeprom_def *pEepData,
36                               u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48         if (!ah->curchan) /* should really check for CCK instead */
49                 return clks / ATH9K_CLOCK_RATE_CCK;
50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60         if (conf_is_ht40(conf))
61                 return ath9k_hw_mac_usec(ah, clks) / 2;
62         else
63                 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70         if (!ah->curchan) /* should really check for CCK instead */
71                 return usecs *ATH9K_CLOCK_RATE_CCK;
72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81         if (conf_is_ht40(conf))
82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
83         else
84                 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
88 {
89         int i;
90
91         BUG_ON(timeout < AH_TIME_QUANTUM);
92
93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94                 if ((REG_READ(ah, reg) & mask) == val)
95                         return true;
96
97                 udelay(AH_TIME_QUANTUM);
98         }
99
100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102                 timeout, reg, REG_READ(ah, reg), mask, val);
103
104         return false;
105 }
106
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
108 {
109         u32 retval;
110         int i;
111
112         for (i = 0, retval = 0; i < n; i++) {
113                 retval = (retval << 1) | (val & 1);
114                 val >>= 1;
115         }
116         return retval;
117 }
118
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
120                              u16 flags, u16 *low,
121                              u16 *high)
122 {
123         struct ath9k_hw_capabilities *pCap = &ah->caps;
124
125         if (flags & CHANNEL_5GHZ) {
126                 *low = pCap->low_5ghz_chan;
127                 *high = pCap->high_5ghz_chan;
128                 return true;
129         }
130         if ((flags & CHANNEL_2GHZ)) {
131                 *low = pCap->low_2ghz_chan;
132                 *high = pCap->high_2ghz_chan;
133                 return true;
134         }
135         return false;
136 }
137
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139                            struct ath_rate_table *rates,
140                            u32 frameLen, u16 rateix,
141                            bool shortPreamble)
142 {
143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
144         u32 kbps;
145
146         kbps = rates->info[rateix].ratekbps;
147
148         if (kbps == 0)
149                 return 0;
150
151         switch (rates->info[rateix].phy) {
152         case WLAN_RC_PHY_CCK:
153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154                 if (shortPreamble && rates->info[rateix].short_preamble)
155                         phyTime >>= 1;
156                 numBits = frameLen << 3;
157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
158                 break;
159         case WLAN_RC_PHY_OFDM:
160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164                         txTime = OFDM_SIFS_TIME_QUARTER
165                                 + OFDM_PREAMBLE_TIME_QUARTER
166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167                 } else if (ah->curchan &&
168                            IS_CHAN_HALF_RATE(ah->curchan)) {
169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172                         txTime = OFDM_SIFS_TIME_HALF +
173                                 OFDM_PREAMBLE_TIME_HALF
174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
175                 } else {
176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180                                 + (numSymbols * OFDM_SYMBOL_TIME);
181                 }
182                 break;
183         default:
184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
185                         "Unknown phy %u (rate ix %u)\n",
186                         rates->info[rateix].phy, rateix);
187                 txTime = 0;
188                 break;
189         }
190
191         return txTime;
192 }
193
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195                                   struct ath9k_channel *chan,
196                                   struct chan_centers *centers)
197 {
198         int8_t extoff;
199
200         if (!IS_CHAN_HT40(chan)) {
201                 centers->ctl_center = centers->ext_center =
202                         centers->synth_center = chan->channel;
203                 return;
204         }
205
206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208                 centers->synth_center =
209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
210                 extoff = 1;
211         } else {
212                 centers->synth_center =
213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214                 extoff = -1;
215         }
216
217         centers->ctl_center =
218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219         centers->ext_center =
220                 centers->synth_center + (extoff *
221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222                           HT40_CHANNEL_CENTER_SHIFT : 15));
223 }
224
225 /******************/
226 /* Chip Revisions */
227 /******************/
228
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
230 {
231         u32 val;
232
233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
234
235         if (val == 0xFF) {
236                 val = REG_READ(ah, AR_SREV);
237                 ah->hw_version.macVersion =
238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
241         } else {
242                 if (!AR_SREV_9100(ah))
243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
244
245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
246
247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248                         ah->is_pciexpress = true;
249         }
250 }
251
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
253 {
254         u32 val;
255         int i;
256
257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
258
259         for (i = 0; i < 8; i++)
260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
263
264         return ath9k_hw_reverse_bits(val, 8);
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273         if (AR_SREV_9100(ah))
274                 return;
275
276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
290 {
291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
292         u32 regHold[2];
293         u32 patternData[4] = { 0x55555555,
294                                0xaaaaaaaa,
295                                0x66666666,
296                                0x99999999 };
297         int i, j;
298
299         for (i = 0; i < 2; i++) {
300                 u32 addr = regAddr[i];
301                 u32 wrData, rdData;
302
303                 regHold[i] = REG_READ(ah, addr);
304                 for (j = 0; j < 0x100; j++) {
305                         wrData = (j << 16) | j;
306                         REG_WRITE(ah, addr, wrData);
307                         rdData = REG_READ(ah, addr);
308                         if (rdData != wrData) {
309                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
310                                         "address test failed "
311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312                                         addr, wrData, rdData);
313                                 return false;
314                         }
315                 }
316                 for (j = 0; j < 4; j++) {
317                         wrData = patternData[j];
318                         REG_WRITE(ah, addr, wrData);
319                         rdData = REG_READ(ah, addr);
320                         if (wrData != rdData) {
321                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
322                                         "address test failed "
323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324                                         addr, wrData, rdData);
325                                 return false;
326                         }
327                 }
328                 REG_WRITE(ah, regAddr[i], regHold[i]);
329         }
330         udelay(100);
331
332         return true;
333 }
334
335 static const char *ath9k_hw_devname(u16 devid)
336 {
337         switch (devid) {
338         case AR5416_DEVID_PCI:
339                 return "Atheros 5416";
340         case AR5416_DEVID_PCIE:
341                 return "Atheros 5418";
342         case AR9160_DEVID_PCI:
343                 return "Atheros 9160";
344         case AR5416_AR9100_DEVID:
345                 return "Atheros 9100";
346         case AR9280_DEVID_PCI:
347         case AR9280_DEVID_PCIE:
348                 return "Atheros 9280";
349         case AR9285_DEVID_PCIE:
350                 return "Atheros 9285";
351         }
352
353         return NULL;
354 }
355
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
357 {
358         int i;
359
360         ah->config.dma_beacon_response_time = 2;
361         ah->config.sw_beacon_response_time = 10;
362         ah->config.additional_swba_backoff = 0;
363         ah->config.ack_6mb = 0x0;
364         ah->config.cwm_ignore_extcca = 0;
365         ah->config.pcie_powersave_enable = 0;
366         ah->config.pcie_l1skp_enable = 0;
367         ah->config.pcie_clock_req = 0;
368         ah->config.pcie_power_reset = 0x100;
369         ah->config.pcie_restore = 0;
370         ah->config.pcie_waen = 0;
371         ah->config.analog_shiftreg = 1;
372         ah->config.ht_enable = 1;
373         ah->config.ofdm_trig_low = 200;
374         ah->config.ofdm_trig_high = 500;
375         ah->config.cck_trig_high = 200;
376         ah->config.cck_trig_low = 100;
377         ah->config.enable_ani = 1;
378         ah->config.noise_immunity_level = 4;
379         ah->config.ofdm_weaksignal_det = 1;
380         ah->config.cck_weaksignal_thr = 0;
381         ah->config.spur_immunity_level = 2;
382         ah->config.firstep_level = 0;
383         ah->config.rssi_thr_high = 40;
384         ah->config.rssi_thr_low = 7;
385         ah->config.diversity_control = 0;
386         ah->config.antenna_switch_swap = 0;
387
388         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
389                 ah->config.spurchans[i][0] = AR_NO_SPUR;
390                 ah->config.spurchans[i][1] = AR_NO_SPUR;
391         }
392
393         ah->config.intr_mitigation = 1;
394 }
395
396 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
397                                         int *status)
398 {
399         struct ath_hw *ah;
400
401         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
402         if (ah == NULL) {
403                 DPRINTF(sc, ATH_DBG_FATAL,
404                         "Cannot allocate memory for state block\n");
405                 *status = -ENOMEM;
406                 return NULL;
407         }
408
409         ah->ah_sc = sc;
410         ah->hw_version.magic = AR5416_MAGIC;
411         ah->regulatory.country_code = CTRY_DEFAULT;
412         ah->hw_version.devid = devid;
413         ah->hw_version.subvendorid = 0;
414
415         ah->ah_flags = 0;
416         if ((devid == AR5416_AR9100_DEVID))
417                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
418         if (!AR_SREV_9100(ah))
419                 ah->ah_flags = AH_USE_EEPROM;
420
421         ah->regulatory.power_limit = MAX_RATE_POWER;
422         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
423         ah->atim_window = 0;
424         ah->diversity_control = ah->config.diversity_control;
425         ah->antenna_switch_swap =
426                 ah->config.antenna_switch_swap;
427         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
428         ah->beacon_interval = 100;
429         ah->enable_32kHz_clock = DONT_USE_32KHZ;
430         ah->slottime = (u32) -1;
431         ah->acktimeout = (u32) -1;
432         ah->ctstimeout = (u32) -1;
433         ah->globaltxtimeout = (u32) -1;
434
435         ah->gbeacon_rate = 0;
436
437         return ah;
438 }
439
440 static int ath9k_hw_rfattach(struct ath_hw *ah)
441 {
442         bool rfStatus = false;
443         int ecode = 0;
444
445         rfStatus = ath9k_hw_init_rf(ah, &ecode);
446         if (!rfStatus) {
447                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
448                         "RF setup failed, status %u\n", ecode);
449                 return ecode;
450         }
451
452         return 0;
453 }
454
455 static int ath9k_hw_rf_claim(struct ath_hw *ah)
456 {
457         u32 val;
458
459         REG_WRITE(ah, AR_PHY(0), 0x00000007);
460
461         val = ath9k_hw_get_radiorev(ah);
462         switch (val & AR_RADIO_SREV_MAJOR) {
463         case 0:
464                 val = AR_RAD5133_SREV_MAJOR;
465                 break;
466         case AR_RAD5133_SREV_MAJOR:
467         case AR_RAD5122_SREV_MAJOR:
468         case AR_RAD2133_SREV_MAJOR:
469         case AR_RAD2122_SREV_MAJOR:
470                 break;
471         default:
472                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
473                         "5G Radio Chip Rev 0x%02X is not "
474                         "supported by this driver\n",
475                         ah->hw_version.analog5GhzRev);
476                 return -EOPNOTSUPP;
477         }
478
479         ah->hw_version.analog5GhzRev = val;
480
481         return 0;
482 }
483
484 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
485 {
486         u32 sum;
487         int i;
488         u16 eeval;
489
490         sum = 0;
491         for (i = 0; i < 3; i++) {
492                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
493                 sum += eeval;
494                 ah->macaddr[2 * i] = eeval >> 8;
495                 ah->macaddr[2 * i + 1] = eeval & 0xff;
496         }
497         if (sum == 0 || sum == 0xffff * 3) {
498                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
499                         "mac address read failed: %pM\n",
500                         ah->macaddr);
501                 return -EADDRNOTAVAIL;
502         }
503
504         return 0;
505 }
506
507 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
508 {
509         u32 rxgain_type;
510
511         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
512                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
513
514                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
515                         INIT_INI_ARRAY(&ah->iniModesRxGain,
516                         ar9280Modes_backoff_13db_rxgain_9280_2,
517                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
518                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
519                         INIT_INI_ARRAY(&ah->iniModesRxGain,
520                         ar9280Modes_backoff_23db_rxgain_9280_2,
521                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
522                 else
523                         INIT_INI_ARRAY(&ah->iniModesRxGain,
524                         ar9280Modes_original_rxgain_9280_2,
525                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
526         } else {
527                 INIT_INI_ARRAY(&ah->iniModesRxGain,
528                         ar9280Modes_original_rxgain_9280_2,
529                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
530         }
531 }
532
533 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
534 {
535         u32 txgain_type;
536
537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
538                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
539
540                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
541                         INIT_INI_ARRAY(&ah->iniModesTxGain,
542                         ar9280Modes_high_power_tx_gain_9280_2,
543                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
544                 else
545                         INIT_INI_ARRAY(&ah->iniModesTxGain,
546                         ar9280Modes_original_tx_gain_9280_2,
547                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
548         } else {
549                 INIT_INI_ARRAY(&ah->iniModesTxGain,
550                 ar9280Modes_original_tx_gain_9280_2,
551                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
552         }
553 }
554
555 static int ath9k_hw_post_attach(struct ath_hw *ah)
556 {
557         int ecode;
558
559         if (!ath9k_hw_chip_test(ah)) {
560                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
561                         "hardware self-test failed\n");
562                 return -ENODEV;
563         }
564
565         ecode = ath9k_hw_rf_claim(ah);
566         if (ecode != 0)
567                 return ecode;
568
569         ecode = ath9k_hw_eeprom_attach(ah);
570         if (ecode != 0)
571                 return ecode;
572         ecode = ath9k_hw_rfattach(ah);
573         if (ecode != 0)
574                 return ecode;
575
576         if (!AR_SREV_9100(ah)) {
577                 ath9k_hw_ani_setup(ah);
578                 ath9k_hw_ani_attach(ah);
579         }
580
581         return 0;
582 }
583
584 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
585                                          int *status)
586 {
587         struct ath_hw *ah;
588         int ecode;
589         u32 i, j;
590
591         ah = ath9k_hw_newstate(devid, sc, status);
592         if (ah == NULL)
593                 return NULL;
594
595         ath9k_hw_set_defaults(ah);
596
597         if (ah->config.intr_mitigation != 0)
598                 ah->intr_mitigation = true;
599
600         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
601                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
602                 ecode = -EIO;
603                 goto bad;
604         }
605
606         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
607                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
608                 ecode = -EIO;
609                 goto bad;
610         }
611
612         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
613                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
614                         ah->config.serialize_regmode =
615                                 SER_REG_MODE_ON;
616                 } else {
617                         ah->config.serialize_regmode =
618                                 SER_REG_MODE_OFF;
619                 }
620         }
621
622         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
623                 ah->config.serialize_regmode);
624
625         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
626             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
627             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
628             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
629                 DPRINTF(sc, ATH_DBG_RESET,
630                         "Mac Chip Rev 0x%02x.%x is not supported by "
631                         "this driver\n", ah->hw_version.macVersion,
632                         ah->hw_version.macRev);
633                 ecode = -EOPNOTSUPP;
634                 goto bad;
635         }
636
637         if (AR_SREV_9100(ah)) {
638                 ah->iq_caldata.calData = &iq_cal_multi_sample;
639                 ah->supp_cals = IQ_MISMATCH_CAL;
640                 ah->is_pciexpress = false;
641         }
642         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
643
644         if (AR_SREV_9160_10_OR_LATER(ah)) {
645                 if (AR_SREV_9280_10_OR_LATER(ah)) {
646                         ah->iq_caldata.calData = &iq_cal_single_sample;
647                         ah->adcgain_caldata.calData =
648                                 &adc_gain_cal_single_sample;
649                         ah->adcdc_caldata.calData =
650                                 &adc_dc_cal_single_sample;
651                         ah->adcdc_calinitdata.calData =
652                                 &adc_init_dc_cal;
653                 } else {
654                         ah->iq_caldata.calData = &iq_cal_multi_sample;
655                         ah->adcgain_caldata.calData =
656                                 &adc_gain_cal_multi_sample;
657                         ah->adcdc_caldata.calData =
658                                 &adc_dc_cal_multi_sample;
659                         ah->adcdc_calinitdata.calData =
660                                 &adc_init_dc_cal;
661                 }
662                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
663         }
664
665         if (AR_SREV_9160(ah)) {
666                 ah->config.enable_ani = 1;
667                 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
668                                         ATH9K_ANI_FIRSTEP_LEVEL);
669         } else {
670                 ah->ani_function = ATH9K_ANI_ALL;
671                 if (AR_SREV_9280_10_OR_LATER(ah)) {
672                         ah->ani_function &=     ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
673                 }
674         }
675
676         DPRINTF(sc, ATH_DBG_RESET,
677                 "This Mac Chip Rev 0x%02x.%x is \n",
678                 ah->hw_version.macVersion, ah->hw_version.macRev);
679
680         if (AR_SREV_9285_12_OR_LATER(ah)) {
681
682                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
683                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
684                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
685                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
686
687                 if (ah->config.pcie_clock_req) {
688                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
689                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
690                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
691                 } else {
692                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
693                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
694                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
695                                   2);
696                 }
697         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
698                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
699                                ARRAY_SIZE(ar9285Modes_9285), 6);
700                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
701                                ARRAY_SIZE(ar9285Common_9285), 2);
702
703                 if (ah->config.pcie_clock_req) {
704                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
705                         ar9285PciePhy_clkreq_off_L1_9285,
706                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
707                 } else {
708                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
709                         ar9285PciePhy_clkreq_always_on_L1_9285,
710                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
711                 }
712         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
713                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
714                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
715                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
716                                ARRAY_SIZE(ar9280Common_9280_2), 2);
717
718                 if (ah->config.pcie_clock_req) {
719                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
720                                ar9280PciePhy_clkreq_off_L1_9280,
721                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
722                 } else {
723                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
724                                ar9280PciePhy_clkreq_always_on_L1_9280,
725                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
726                 }
727                 INIT_INI_ARRAY(&ah->iniModesAdditional,
728                                ar9280Modes_fast_clock_9280_2,
729                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
730         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
731                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
732                                ARRAY_SIZE(ar9280Modes_9280), 6);
733                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
734                                ARRAY_SIZE(ar9280Common_9280), 2);
735         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
736                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
737                                ARRAY_SIZE(ar5416Modes_9160), 6);
738                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
739                                ARRAY_SIZE(ar5416Common_9160), 2);
740                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
741                                ARRAY_SIZE(ar5416Bank0_9160), 2);
742                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
743                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
744                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
745                                ARRAY_SIZE(ar5416Bank1_9160), 2);
746                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
747                                ARRAY_SIZE(ar5416Bank2_9160), 2);
748                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
749                                ARRAY_SIZE(ar5416Bank3_9160), 3);
750                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
751                                ARRAY_SIZE(ar5416Bank6_9160), 3);
752                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
753                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
754                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
755                                ARRAY_SIZE(ar5416Bank7_9160), 2);
756                 if (AR_SREV_9160_11(ah)) {
757                         INIT_INI_ARRAY(&ah->iniAddac,
758                                        ar5416Addac_91601_1,
759                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
760                 } else {
761                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
762                                        ARRAY_SIZE(ar5416Addac_9160), 2);
763                 }
764         } else if (AR_SREV_9100_OR_LATER(ah)) {
765                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
766                                ARRAY_SIZE(ar5416Modes_9100), 6);
767                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
768                                ARRAY_SIZE(ar5416Common_9100), 2);
769                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
770                                ARRAY_SIZE(ar5416Bank0_9100), 2);
771                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
772                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
773                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
774                                ARRAY_SIZE(ar5416Bank1_9100), 2);
775                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
776                                ARRAY_SIZE(ar5416Bank2_9100), 2);
777                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
778                                ARRAY_SIZE(ar5416Bank3_9100), 3);
779                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
780                                ARRAY_SIZE(ar5416Bank6_9100), 3);
781                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
782                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
783                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
784                                ARRAY_SIZE(ar5416Bank7_9100), 2);
785                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
786                                ARRAY_SIZE(ar5416Addac_9100), 2);
787         } else {
788                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
789                                ARRAY_SIZE(ar5416Modes), 6);
790                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
791                                ARRAY_SIZE(ar5416Common), 2);
792                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
793                                ARRAY_SIZE(ar5416Bank0), 2);
794                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
795                                ARRAY_SIZE(ar5416BB_RfGain), 3);
796                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
797                                ARRAY_SIZE(ar5416Bank1), 2);
798                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
799                                ARRAY_SIZE(ar5416Bank2), 2);
800                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
801                                ARRAY_SIZE(ar5416Bank3), 3);
802                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
803                                ARRAY_SIZE(ar5416Bank6), 3);
804                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
805                                ARRAY_SIZE(ar5416Bank6TPC), 3);
806                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
807                                ARRAY_SIZE(ar5416Bank7), 2);
808                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
809                                ARRAY_SIZE(ar5416Addac), 2);
810         }
811
812         if (ah->is_pciexpress)
813                 ath9k_hw_configpcipowersave(ah, 0);
814         else
815                 ath9k_hw_disablepcie(ah);
816
817         ecode = ath9k_hw_post_attach(ah);
818         if (ecode != 0)
819                 goto bad;
820
821         if (AR_SREV_9285_12_OR_LATER(ah)) {
822                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
823
824                 /* txgain table */
825                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
826                         INIT_INI_ARRAY(&ah->iniModesTxGain,
827                         ar9285Modes_high_power_tx_gain_9285_1_2,
828                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
829                 } else {
830                         INIT_INI_ARRAY(&ah->iniModesTxGain,
831                         ar9285Modes_original_tx_gain_9285_1_2,
832                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
833                 }
834
835         }
836
837         /* rxgain table */
838         if (AR_SREV_9280_20(ah))
839                 ath9k_hw_init_rxgain_ini(ah);
840
841         /* txgain table */
842         if (AR_SREV_9280_20(ah))
843                 ath9k_hw_init_txgain_ini(ah);
844
845         if (!ath9k_hw_fill_cap_info(ah)) {
846                 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
847                 ecode = -EINVAL;
848                 goto bad;
849         }
850
851         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
852             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
853
854                 /* EEPROM Fixup */
855                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
856                         u32 reg = INI_RA(&ah->iniModes, i, 0);
857
858                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
859                                 u32 val = INI_RA(&ah->iniModes, i, j);
860
861                                 INI_RA(&ah->iniModes, i, j) =
862                                         ath9k_hw_ini_fixup(ah,
863                                                            &ah->eeprom.def,
864                                                            reg, val);
865                         }
866                 }
867         }
868
869         ecode = ath9k_hw_init_macaddr(ah);
870         if (ecode != 0) {
871                 DPRINTF(sc, ATH_DBG_RESET,
872                         "failed initializing mac address\n");
873                 goto bad;
874         }
875
876         if (AR_SREV_9285(ah))
877                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
878         else
879                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
880
881         ath9k_init_nfcal_hist_buffer(ah);
882
883         return ah;
884 bad:
885         if (ah)
886                 ath9k_hw_detach(ah);
887         if (status)
888                 *status = ecode;
889
890         return NULL;
891 }
892
893 static void ath9k_hw_init_bb(struct ath_hw *ah,
894                              struct ath9k_channel *chan)
895 {
896         u32 synthDelay;
897
898         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
899         if (IS_CHAN_B(chan))
900                 synthDelay = (4 * synthDelay) / 22;
901         else
902                 synthDelay /= 10;
903
904         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
905
906         udelay(synthDelay + BASE_ACTIVATE_DELAY);
907 }
908
909 static void ath9k_hw_init_qos(struct ath_hw *ah)
910 {
911         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
912         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
913
914         REG_WRITE(ah, AR_QOS_NO_ACK,
915                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
916                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
917                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
918
919         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
920         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
921         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
922         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
923         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
924 }
925
926 static void ath9k_hw_init_pll(struct ath_hw *ah,
927                               struct ath9k_channel *chan)
928 {
929         u32 pll;
930
931         if (AR_SREV_9100(ah)) {
932                 if (chan && IS_CHAN_5GHZ(chan))
933                         pll = 0x1450;
934                 else
935                         pll = 0x1458;
936         } else {
937                 if (AR_SREV_9280_10_OR_LATER(ah)) {
938                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
939
940                         if (chan && IS_CHAN_HALF_RATE(chan))
941                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
942                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
943                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
944
945                         if (chan && IS_CHAN_5GHZ(chan)) {
946                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
947
948
949                                 if (AR_SREV_9280_20(ah)) {
950                                         if (((chan->channel % 20) == 0)
951                                             || ((chan->channel % 10) == 0))
952                                                 pll = 0x2850;
953                                         else
954                                                 pll = 0x142c;
955                                 }
956                         } else {
957                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
958                         }
959
960                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
961
962                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
963
964                         if (chan && IS_CHAN_HALF_RATE(chan))
965                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
966                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
967                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
968
969                         if (chan && IS_CHAN_5GHZ(chan))
970                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
971                         else
972                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
973                 } else {
974                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
975
976                         if (chan && IS_CHAN_HALF_RATE(chan))
977                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
978                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
979                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
980
981                         if (chan && IS_CHAN_5GHZ(chan))
982                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
983                         else
984                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
985                 }
986         }
987         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
988
989         udelay(RTC_PLL_SETTLE_DELAY);
990
991         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
992 }
993
994 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
995 {
996         int rx_chainmask, tx_chainmask;
997
998         rx_chainmask = ah->rxchainmask;
999         tx_chainmask = ah->txchainmask;
1000
1001         switch (rx_chainmask) {
1002         case 0x5:
1003                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1004                             AR_PHY_SWAP_ALT_CHAIN);
1005         case 0x3:
1006                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1007                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1008                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1009                         break;
1010                 }
1011         case 0x1:
1012         case 0x2:
1013         case 0x7:
1014                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1015                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1016                 break;
1017         default:
1018                 break;
1019         }
1020
1021         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1022         if (tx_chainmask == 0x5) {
1023                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1024                             AR_PHY_SWAP_ALT_CHAIN);
1025         }
1026         if (AR_SREV_9100(ah))
1027                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1028                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1029 }
1030
1031 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1032                                           enum nl80211_iftype opmode)
1033 {
1034         ah->mask_reg = AR_IMR_TXERR |
1035                 AR_IMR_TXURN |
1036                 AR_IMR_RXERR |
1037                 AR_IMR_RXORN |
1038                 AR_IMR_BCNMISC;
1039
1040         if (ah->intr_mitigation)
1041                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1042         else
1043                 ah->mask_reg |= AR_IMR_RXOK;
1044
1045         ah->mask_reg |= AR_IMR_TXOK;
1046
1047         if (opmode == NL80211_IFTYPE_AP)
1048                 ah->mask_reg |= AR_IMR_MIB;
1049
1050         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1051         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1052
1053         if (!AR_SREV_9100(ah)) {
1054                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1055                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1056                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1057         }
1058 }
1059
1060 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1061 {
1062         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1063                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1064                 ah->acktimeout = (u32) -1;
1065                 return false;
1066         } else {
1067                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1068                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1069                 ah->acktimeout = us;
1070                 return true;
1071         }
1072 }
1073
1074 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1075 {
1076         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1077                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1078                 ah->ctstimeout = (u32) -1;
1079                 return false;
1080         } else {
1081                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1082                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1083                 ah->ctstimeout = us;
1084                 return true;
1085         }
1086 }
1087
1088 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1089 {
1090         if (tu > 0xFFFF) {
1091                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1092                         "bad global tx timeout %u\n", tu);
1093                 ah->globaltxtimeout = (u32) -1;
1094                 return false;
1095         } else {
1096                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1097                 ah->globaltxtimeout = tu;
1098                 return true;
1099         }
1100 }
1101
1102 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1103 {
1104         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1105                 ah->misc_mode);
1106
1107         if (ah->misc_mode != 0)
1108                 REG_WRITE(ah, AR_PCU_MISC,
1109                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1110         if (ah->slottime != (u32) -1)
1111                 ath9k_hw_setslottime(ah, ah->slottime);
1112         if (ah->acktimeout != (u32) -1)
1113                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1114         if (ah->ctstimeout != (u32) -1)
1115                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1116         if (ah->globaltxtimeout != (u32) -1)
1117                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1118 }
1119
1120 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1121 {
1122         return vendorid == ATHEROS_VENDOR_ID ?
1123                 ath9k_hw_devname(devid) : NULL;
1124 }
1125
1126 void ath9k_hw_detach(struct ath_hw *ah)
1127 {
1128         if (!AR_SREV_9100(ah))
1129                 ath9k_hw_ani_detach(ah);
1130
1131         ath9k_hw_rfdetach(ah);
1132         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1133         kfree(ah);
1134 }
1135
1136 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1137 {
1138         struct ath_hw *ah = NULL;
1139
1140         switch (devid) {
1141         case AR5416_DEVID_PCI:
1142         case AR5416_DEVID_PCIE:
1143         case AR5416_AR9100_DEVID:
1144         case AR9160_DEVID_PCI:
1145         case AR9280_DEVID_PCI:
1146         case AR9280_DEVID_PCIE:
1147         case AR9285_DEVID_PCIE:
1148                 ah = ath9k_hw_do_attach(devid, sc, error);
1149                 break;
1150         default:
1151                 *error = -ENXIO;
1152                 break;
1153         }
1154
1155         return ah;
1156 }
1157
1158 /*******/
1159 /* INI */
1160 /*******/
1161
1162 static void ath9k_hw_override_ini(struct ath_hw *ah,
1163                                   struct ath9k_channel *chan)
1164 {
1165         /*
1166          * Set the RX_ABORT and RX_DIS and clear if off only after
1167          * RXE is set for MAC. This prevents frames with corrupted
1168          * descriptor status.
1169          */
1170         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1171
1172
1173         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1174             AR_SREV_9280_10_OR_LATER(ah))
1175                 return;
1176
1177         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1178 }
1179
1180 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1181                               struct ar5416_eeprom_def *pEepData,
1182                               u32 reg, u32 value)
1183 {
1184         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1185
1186         switch (ah->hw_version.devid) {
1187         case AR9280_DEVID_PCI:
1188                 if (reg == 0x7894) {
1189                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1190                                 "ini VAL: %x  EEPROM: %x\n", value,
1191                                 (pBase->version & 0xff));
1192
1193                         if ((pBase->version & 0xff) > 0x0a) {
1194                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1195                                         "PWDCLKIND: %d\n",
1196                                         pBase->pwdclkind);
1197                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1198                                 value |= AR_AN_TOP2_PWDCLKIND &
1199                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1200                         } else {
1201                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1202                                         "PWDCLKIND Earlier Rev\n");
1203                         }
1204
1205                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1206                                 "final ini VAL: %x\n", value);
1207                 }
1208                 break;
1209         }
1210
1211         return value;
1212 }
1213
1214 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1215                               struct ar5416_eeprom_def *pEepData,
1216                               u32 reg, u32 value)
1217 {
1218         if (ah->eep_map == EEP_MAP_4KBITS)
1219                 return value;
1220         else
1221                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1222 }
1223
1224 static void ath9k_olc_init(struct ath_hw *ah)
1225 {
1226         u32 i;
1227
1228         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1229                 ah->originalGain[i] =
1230                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1231                                         AR_PHY_TX_GAIN);
1232         ah->PDADCdelta = 0;
1233 }
1234
1235 static int ath9k_hw_process_ini(struct ath_hw *ah,
1236                                 struct ath9k_channel *chan,
1237                                 enum ath9k_ht_macmode macmode)
1238 {
1239         int i, regWrites = 0;
1240         struct ieee80211_channel *channel = chan->chan;
1241         u32 modesIndex, freqIndex;
1242         int status;
1243
1244         switch (chan->chanmode) {
1245         case CHANNEL_A:
1246         case CHANNEL_A_HT20:
1247                 modesIndex = 1;
1248                 freqIndex = 1;
1249                 break;
1250         case CHANNEL_A_HT40PLUS:
1251         case CHANNEL_A_HT40MINUS:
1252                 modesIndex = 2;
1253                 freqIndex = 1;
1254                 break;
1255         case CHANNEL_G:
1256         case CHANNEL_G_HT20:
1257         case CHANNEL_B:
1258                 modesIndex = 4;
1259                 freqIndex = 2;
1260                 break;
1261         case CHANNEL_G_HT40PLUS:
1262         case CHANNEL_G_HT40MINUS:
1263                 modesIndex = 3;
1264                 freqIndex = 2;
1265                 break;
1266
1267         default:
1268                 return -EINVAL;
1269         }
1270
1271         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1272         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1273         ah->eep_ops->set_addac(ah, chan);
1274
1275         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1276                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1277         } else {
1278                 struct ar5416IniArray temp;
1279                 u32 addacSize =
1280                         sizeof(u32) * ah->iniAddac.ia_rows *
1281                         ah->iniAddac.ia_columns;
1282
1283                 memcpy(ah->addac5416_21,
1284                        ah->iniAddac.ia_array, addacSize);
1285
1286                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1287
1288                 temp.ia_array = ah->addac5416_21;
1289                 temp.ia_columns = ah->iniAddac.ia_columns;
1290                 temp.ia_rows = ah->iniAddac.ia_rows;
1291                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1292         }
1293
1294         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1295
1296         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1297                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1298                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1299
1300                 REG_WRITE(ah, reg, val);
1301
1302                 if (reg >= 0x7800 && reg < 0x78a0
1303                     && ah->config.analog_shiftreg) {
1304                         udelay(100);
1305                 }
1306
1307                 DO_DELAY(regWrites);
1308         }
1309
1310         if (AR_SREV_9280(ah))
1311                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1312
1313         if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1314             AR_SREV_9285_12_OR_LATER(ah)))
1315                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1316
1317         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1318                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1319                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1320
1321                 REG_WRITE(ah, reg, val);
1322
1323                 if (reg >= 0x7800 && reg < 0x78a0
1324                     && ah->config.analog_shiftreg) {
1325                         udelay(100);
1326                 }
1327
1328                 DO_DELAY(regWrites);
1329         }
1330
1331         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1332
1333         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1334                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1335                                 regWrites);
1336         }
1337
1338         ath9k_hw_override_ini(ah, chan);
1339         ath9k_hw_set_regs(ah, chan, macmode);
1340         ath9k_hw_init_chain_masks(ah);
1341
1342         if (OLC_FOR_AR9280_20_LATER)
1343                 ath9k_olc_init(ah);
1344
1345         status = ah->eep_ops->set_txpower(ah, chan,
1346                                   ath9k_regd_get_ctl(ah, chan),
1347                                   channel->max_antenna_gain * 2,
1348                                   channel->max_power * 2,
1349                                   min((u32) MAX_RATE_POWER,
1350                                       (u32) ah->regulatory.power_limit));
1351         if (status != 0) {
1352                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1353                         "error init'ing transmit power\n");
1354                 return -EIO;
1355         }
1356
1357         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1358                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1359                         "ar5416SetRfRegs failed\n");
1360                 return -EIO;
1361         }
1362
1363         return 0;
1364 }
1365
1366 /****************************************/
1367 /* Reset and Channel Switching Routines */
1368 /****************************************/
1369
1370 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1371 {
1372         u32 rfMode = 0;
1373
1374         if (chan == NULL)
1375                 return;
1376
1377         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1378                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1379
1380         if (!AR_SREV_9280_10_OR_LATER(ah))
1381                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1382                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1383
1384         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1385                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1386
1387         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1388 }
1389
1390 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1391 {
1392         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1393 }
1394
1395 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1396 {
1397         u32 regval;
1398
1399         regval = REG_READ(ah, AR_AHB_MODE);
1400         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1401
1402         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1403         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1404
1405         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1406
1407         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1408         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1409
1410         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1411
1412         if (AR_SREV_9285(ah)) {
1413                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1414                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1415         } else {
1416                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1417                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1418         }
1419 }
1420
1421 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1422 {
1423         u32 val;
1424
1425         val = REG_READ(ah, AR_STA_ID1);
1426         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1427         switch (opmode) {
1428         case NL80211_IFTYPE_AP:
1429                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1430                           | AR_STA_ID1_KSRCH_MODE);
1431                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1432                 break;
1433         case NL80211_IFTYPE_ADHOC:
1434                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1435                           | AR_STA_ID1_KSRCH_MODE);
1436                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1437                 break;
1438         case NL80211_IFTYPE_STATION:
1439         case NL80211_IFTYPE_MONITOR:
1440                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1441                 break;
1442         }
1443 }
1444
1445 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1446                                                  u32 coef_scaled,
1447                                                  u32 *coef_mantissa,
1448                                                  u32 *coef_exponent)
1449 {
1450         u32 coef_exp, coef_man;
1451
1452         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1453                 if ((coef_scaled >> coef_exp) & 0x1)
1454                         break;
1455
1456         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1457
1458         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1459
1460         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1461         *coef_exponent = coef_exp - 16;
1462 }
1463
1464 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1465                                      struct ath9k_channel *chan)
1466 {
1467         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1468         u32 clockMhzScaled = 0x64000000;
1469         struct chan_centers centers;
1470
1471         if (IS_CHAN_HALF_RATE(chan))
1472                 clockMhzScaled = clockMhzScaled >> 1;
1473         else if (IS_CHAN_QUARTER_RATE(chan))
1474                 clockMhzScaled = clockMhzScaled >> 2;
1475
1476         ath9k_hw_get_channel_centers(ah, chan, &centers);
1477         coef_scaled = clockMhzScaled / centers.synth_center;
1478
1479         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1480                                       &ds_coef_exp);
1481
1482         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1483                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1484         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1485                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1486
1487         coef_scaled = (9 * coef_scaled) / 10;
1488
1489         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1490                                       &ds_coef_exp);
1491
1492         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1493                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1494         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1495                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1496 }
1497
1498 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1499 {
1500         u32 rst_flags;
1501         u32 tmpReg;
1502
1503         if (AR_SREV_9100(ah)) {
1504                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1505                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1506                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1507                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1508                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1509         }
1510
1511         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1512                   AR_RTC_FORCE_WAKE_ON_INT);
1513
1514         if (AR_SREV_9100(ah)) {
1515                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1516                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1517         } else {
1518                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1519                 if (tmpReg &
1520                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1521                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1522                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1523                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1524                 } else {
1525                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1526                 }
1527
1528                 rst_flags = AR_RTC_RC_MAC_WARM;
1529                 if (type == ATH9K_RESET_COLD)
1530                         rst_flags |= AR_RTC_RC_MAC_COLD;
1531         }
1532
1533         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1534         udelay(50);
1535
1536         REG_WRITE(ah, AR_RTC_RC, 0);
1537         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1538                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1539                         "RTC stuck in MAC reset\n");
1540                 return false;
1541         }
1542
1543         if (!AR_SREV_9100(ah))
1544                 REG_WRITE(ah, AR_RC, 0);
1545
1546         ath9k_hw_init_pll(ah, NULL);
1547
1548         if (AR_SREV_9100(ah))
1549                 udelay(50);
1550
1551         return true;
1552 }
1553
1554 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1555 {
1556         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1557                   AR_RTC_FORCE_WAKE_ON_INT);
1558
1559         REG_WRITE(ah, AR_RTC_RESET, 0);
1560         udelay(2);
1561         REG_WRITE(ah, AR_RTC_RESET, 1);
1562
1563         if (!ath9k_hw_wait(ah,
1564                            AR_RTC_STATUS,
1565                            AR_RTC_STATUS_M,
1566                            AR_RTC_STATUS_ON,
1567                            AH_WAIT_TIMEOUT)) {
1568                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1569                 return false;
1570         }
1571
1572         ath9k_hw_read_revisions(ah);
1573
1574         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1575 }
1576
1577 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1578 {
1579         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1580                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1581
1582         switch (type) {
1583         case ATH9K_RESET_POWER_ON:
1584                 return ath9k_hw_set_reset_power_on(ah);
1585                 break;
1586         case ATH9K_RESET_WARM:
1587         case ATH9K_RESET_COLD:
1588                 return ath9k_hw_set_reset(ah, type);
1589                 break;
1590         default:
1591                 return false;
1592         }
1593 }
1594
1595 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1596                               enum ath9k_ht_macmode macmode)
1597 {
1598         u32 phymode;
1599         u32 enableDacFifo = 0;
1600
1601         if (AR_SREV_9285_10_OR_LATER(ah))
1602                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1603                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1604
1605         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1606                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1607
1608         if (IS_CHAN_HT40(chan)) {
1609                 phymode |= AR_PHY_FC_DYN2040_EN;
1610
1611                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1612                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1613                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1614
1615                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1616                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1617         }
1618         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1619
1620         ath9k_hw_set11nmac2040(ah, macmode);
1621
1622         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1623         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1624 }
1625
1626 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1627                                 struct ath9k_channel *chan)
1628 {
1629         if (OLC_FOR_AR9280_20_LATER) {
1630                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1631                         return false;
1632         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1633                 return false;
1634
1635         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1636                 return false;
1637
1638         ah->chip_fullsleep = false;
1639         ath9k_hw_init_pll(ah, chan);
1640         ath9k_hw_set_rfmode(ah, chan);
1641
1642         return true;
1643 }
1644
1645 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1646                                     struct ath9k_channel *chan,
1647                                     enum ath9k_ht_macmode macmode)
1648 {
1649         struct ieee80211_channel *channel = chan->chan;
1650         u32 synthDelay, qnum;
1651
1652         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1653                 if (ath9k_hw_numtxpending(ah, qnum)) {
1654                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1655                                 "Transmit frames pending on queue %d\n", qnum);
1656                         return false;
1657                 }
1658         }
1659
1660         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1661         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1662                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1663                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1664                         "Could not kill baseband RX\n");
1665                 return false;
1666         }
1667
1668         ath9k_hw_set_regs(ah, chan, macmode);
1669
1670         if (AR_SREV_9280_10_OR_LATER(ah)) {
1671                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1672                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1673                                 "failed to set channel\n");
1674                         return false;
1675                 }
1676         } else {
1677                 if (!(ath9k_hw_set_channel(ah, chan))) {
1678                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1679                                 "failed to set channel\n");
1680                         return false;
1681                 }
1682         }
1683
1684         if (ah->eep_ops->set_txpower(ah, chan,
1685                              ath9k_regd_get_ctl(ah, chan),
1686                              channel->max_antenna_gain * 2,
1687                              channel->max_power * 2,
1688                              min((u32) MAX_RATE_POWER,
1689                                  (u32) ah->regulatory.power_limit)) != 0) {
1690                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1691                         "error init'ing transmit power\n");
1692                 return false;
1693         }
1694
1695         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1696         if (IS_CHAN_B(chan))
1697                 synthDelay = (4 * synthDelay) / 22;
1698         else
1699                 synthDelay /= 10;
1700
1701         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1702
1703         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1704
1705         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1706                 ath9k_hw_set_delta_slope(ah, chan);
1707
1708         if (AR_SREV_9280_10_OR_LATER(ah))
1709                 ath9k_hw_9280_spur_mitigate(ah, chan);
1710         else
1711                 ath9k_hw_spur_mitigate(ah, chan);
1712
1713         if (!chan->oneTimeCalsDone)
1714                 chan->oneTimeCalsDone = true;
1715
1716         return true;
1717 }
1718
1719 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1720 {
1721         int bb_spur = AR_NO_SPUR;
1722         int freq;
1723         int bin, cur_bin;
1724         int bb_spur_off, spur_subchannel_sd;
1725         int spur_freq_sd;
1726         int spur_delta_phase;
1727         int denominator;
1728         int upper, lower, cur_vit_mask;
1729         int tmp, newVal;
1730         int i;
1731         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1732                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1733         };
1734         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1735                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1736         };
1737         int inc[4] = { 0, 100, 0, 0 };
1738         struct chan_centers centers;
1739
1740         int8_t mask_m[123];
1741         int8_t mask_p[123];
1742         int8_t mask_amt;
1743         int tmp_mask;
1744         int cur_bb_spur;
1745         bool is2GHz = IS_CHAN_2GHZ(chan);
1746
1747         memset(&mask_m, 0, sizeof(int8_t) * 123);
1748         memset(&mask_p, 0, sizeof(int8_t) * 123);
1749
1750         ath9k_hw_get_channel_centers(ah, chan, &centers);
1751         freq = centers.synth_center;
1752
1753         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1754         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1755                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1756
1757                 if (is2GHz)
1758                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1759                 else
1760                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1761
1762                 if (AR_NO_SPUR == cur_bb_spur)
1763                         break;
1764                 cur_bb_spur = cur_bb_spur - freq;
1765
1766                 if (IS_CHAN_HT40(chan)) {
1767                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1768                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1769                                 bb_spur = cur_bb_spur;
1770                                 break;
1771                         }
1772                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1773                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1774                         bb_spur = cur_bb_spur;
1775                         break;
1776                 }
1777         }
1778
1779         if (AR_NO_SPUR == bb_spur) {
1780                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1781                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1782                 return;
1783         } else {
1784                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1785                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1786         }
1787
1788         bin = bb_spur * 320;
1789
1790         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1791
1792         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1793                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1794                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1795                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1796         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1797
1798         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1799                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1800                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1801                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1802                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1803         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1804
1805         if (IS_CHAN_HT40(chan)) {
1806                 if (bb_spur < 0) {
1807                         spur_subchannel_sd = 1;
1808                         bb_spur_off = bb_spur + 10;
1809                 } else {
1810                         spur_subchannel_sd = 0;
1811                         bb_spur_off = bb_spur - 10;
1812                 }
1813         } else {
1814                 spur_subchannel_sd = 0;
1815                 bb_spur_off = bb_spur;
1816         }
1817
1818         if (IS_CHAN_HT40(chan))
1819                 spur_delta_phase =
1820                         ((bb_spur * 262144) /
1821                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1822         else
1823                 spur_delta_phase =
1824                         ((bb_spur * 524288) /
1825                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1826
1827         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1828         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1829
1830         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1831                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1832                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1833         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1834
1835         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1836         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1837
1838         cur_bin = -6000;
1839         upper = bin + 100;
1840         lower = bin - 100;
1841
1842         for (i = 0; i < 4; i++) {
1843                 int pilot_mask = 0;
1844                 int chan_mask = 0;
1845                 int bp = 0;
1846                 for (bp = 0; bp < 30; bp++) {
1847                         if ((cur_bin > lower) && (cur_bin < upper)) {
1848                                 pilot_mask = pilot_mask | 0x1 << bp;
1849                                 chan_mask = chan_mask | 0x1 << bp;
1850                         }
1851                         cur_bin += 100;
1852                 }
1853                 cur_bin += inc[i];
1854                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1855                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1856         }
1857
1858         cur_vit_mask = 6100;
1859         upper = bin + 120;
1860         lower = bin - 120;
1861
1862         for (i = 0; i < 123; i++) {
1863                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1864
1865                         /* workaround for gcc bug #37014 */
1866                         volatile int tmp_v = abs(cur_vit_mask - bin);
1867
1868                         if (tmp_v < 75)
1869                                 mask_amt = 1;
1870                         else
1871                                 mask_amt = 0;
1872                         if (cur_vit_mask < 0)
1873                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1874                         else
1875                                 mask_p[cur_vit_mask / 100] = mask_amt;
1876                 }
1877                 cur_vit_mask -= 100;
1878         }
1879
1880         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1881                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1882                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1883                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1884                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1885                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1886                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1887                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1888         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1889         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1890
1891         tmp_mask = (mask_m[31] << 28)
1892                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1893                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1894                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1895                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1896                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1897                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1898                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1899         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1900         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1901
1902         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1903                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1904                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1905                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1906                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1907                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1908                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1909                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1910         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1911         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1912
1913         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1914                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1915                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1916                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1917                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1918                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1919                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1920                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1921         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1922         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1923
1924         tmp_mask = (mask_p[15] << 28)
1925                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1926                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1927                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1928                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1929                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1930                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1931                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1932         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1933         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1934
1935         tmp_mask = (mask_p[30] << 28)
1936                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1937                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1938                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1939                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1940                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1941                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1942                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1943         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1945
1946         tmp_mask = (mask_p[45] << 28)
1947                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1948                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1949                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1950                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1951                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1952                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1953                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1954         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1955         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1956
1957         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1958                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1959                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1960                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1961                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1962                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1963                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1964                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1965         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1966         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1967 }
1968
1969 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1970 {
1971         int bb_spur = AR_NO_SPUR;
1972         int bin, cur_bin;
1973         int spur_freq_sd;
1974         int spur_delta_phase;
1975         int denominator;
1976         int upper, lower, cur_vit_mask;
1977         int tmp, new;
1978         int i;
1979         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1980                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1981         };
1982         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1983                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1984         };
1985         int inc[4] = { 0, 100, 0, 0 };
1986
1987         int8_t mask_m[123];
1988         int8_t mask_p[123];
1989         int8_t mask_amt;
1990         int tmp_mask;
1991         int cur_bb_spur;
1992         bool is2GHz = IS_CHAN_2GHZ(chan);
1993
1994         memset(&mask_m, 0, sizeof(int8_t) * 123);
1995         memset(&mask_p, 0, sizeof(int8_t) * 123);
1996
1997         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1998                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1999                 if (AR_NO_SPUR == cur_bb_spur)
2000                         break;
2001                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2002                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2003                         bb_spur = cur_bb_spur;
2004                         break;
2005                 }
2006         }
2007
2008         if (AR_NO_SPUR == bb_spur)
2009                 return;
2010
2011         bin = bb_spur * 32;
2012
2013         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2014         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2015                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2016                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2017                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2018
2019         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2020
2021         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2022                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2023                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2024                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2025                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2026         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2027
2028         spur_delta_phase = ((bb_spur * 524288) / 100) &
2029                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2030
2031         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2032         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2033
2034         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2035                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2036                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2037         REG_WRITE(ah, AR_PHY_TIMING11, new);
2038
2039         cur_bin = -6000;
2040         upper = bin + 100;
2041         lower = bin - 100;
2042
2043         for (i = 0; i < 4; i++) {
2044                 int pilot_mask = 0;
2045                 int chan_mask = 0;
2046                 int bp = 0;
2047                 for (bp = 0; bp < 30; bp++) {
2048                         if ((cur_bin > lower) && (cur_bin < upper)) {
2049                                 pilot_mask = pilot_mask | 0x1 << bp;
2050                                 chan_mask = chan_mask | 0x1 << bp;
2051                         }
2052                         cur_bin += 100;
2053                 }
2054                 cur_bin += inc[i];
2055                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2056                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2057         }
2058
2059         cur_vit_mask = 6100;
2060         upper = bin + 120;
2061         lower = bin - 120;
2062
2063         for (i = 0; i < 123; i++) {
2064                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2065
2066                         /* workaround for gcc bug #37014 */
2067                         volatile int tmp_v = abs(cur_vit_mask - bin);
2068
2069                         if (tmp_v < 75)
2070                                 mask_amt = 1;
2071                         else
2072                                 mask_amt = 0;
2073                         if (cur_vit_mask < 0)
2074                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2075                         else
2076                                 mask_p[cur_vit_mask / 100] = mask_amt;
2077                 }
2078                 cur_vit_mask -= 100;
2079         }
2080
2081         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2082                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2083                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2084                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2085                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2086                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2087                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2088                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2089         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2090         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2091
2092         tmp_mask = (mask_m[31] << 28)
2093                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2094                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2095                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2096                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2097                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2098                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2099                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2100         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2101         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2102
2103         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2104                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2105                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2106                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2107                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2108                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2109                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2110                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2111         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2112         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2113
2114         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2115                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2116                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2117                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2118                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2119                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2120                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2121                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2122         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2123         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2124
2125         tmp_mask = (mask_p[15] << 28)
2126                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2127                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2128                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2129                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2130                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2131                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2132                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2133         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2134         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2135
2136         tmp_mask = (mask_p[30] << 28)
2137                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2138                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2139                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2140                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2141                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2142                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2143                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2144         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2146
2147         tmp_mask = (mask_p[45] << 28)
2148                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2149                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2150                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2151                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2152                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2153                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2154                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2155         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2156         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2157
2158         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2159                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2160                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2161                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2162                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2163                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2164                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2165                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2166         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2167         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2168 }
2169
2170 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2171                     bool bChannelChange)
2172 {
2173         u32 saveLedState;
2174         struct ath_softc *sc = ah->ah_sc;
2175         struct ath9k_channel *curchan = ah->curchan;
2176         u32 saveDefAntenna;
2177         u32 macStaId1;
2178         int i, rx_chainmask, r;
2179
2180         ah->extprotspacing = sc->ht_extprotspacing;
2181         ah->txchainmask = sc->tx_chainmask;
2182         ah->rxchainmask = sc->rx_chainmask;
2183
2184         if (AR_SREV_9285(ah)) {
2185                 ah->txchainmask &= 0x1;
2186                 ah->rxchainmask &= 0x1;
2187         } else if (AR_SREV_9280(ah)) {
2188                 ah->txchainmask &= 0x3;
2189                 ah->rxchainmask &= 0x3;
2190         }
2191
2192         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2193                 return -EIO;
2194
2195         if (curchan)
2196                 ath9k_hw_getnf(ah, curchan);
2197
2198         if (bChannelChange &&
2199             (ah->chip_fullsleep != true) &&
2200             (ah->curchan != NULL) &&
2201             (chan->channel != ah->curchan->channel) &&
2202             ((chan->channelFlags & CHANNEL_ALL) ==
2203              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2204             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2205                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2206
2207                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2208                         ath9k_hw_loadnf(ah, ah->curchan);
2209                         ath9k_hw_start_nfcal(ah);
2210                         return 0;
2211                 }
2212         }
2213
2214         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2215         if (saveDefAntenna == 0)
2216                 saveDefAntenna = 1;
2217
2218         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2219
2220         saveLedState = REG_READ(ah, AR_CFG_LED) &
2221                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2222                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2223
2224         ath9k_hw_mark_phy_inactive(ah);
2225
2226         if (!ath9k_hw_chip_reset(ah, chan)) {
2227                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2228                 return -EINVAL;
2229         }
2230
2231         if (AR_SREV_9280_10_OR_LATER(ah))
2232                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2233
2234         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2235         if (r)
2236                 return r;
2237
2238         /* Setup MFP options for CCMP */
2239         if (AR_SREV_9280_20_OR_LATER(ah)) {
2240                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2241                  * frames when constructing CCMP AAD. */
2242                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2243                               0xc7ff);
2244                 ah->sw_mgmt_crypto = false;
2245         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2246                 /* Disable hardware crypto for management frames */
2247                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2248                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2249                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2250                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2251                 ah->sw_mgmt_crypto = true;
2252         } else
2253                 ah->sw_mgmt_crypto = true;
2254
2255         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2256                 ath9k_hw_set_delta_slope(ah, chan);
2257
2258         if (AR_SREV_9280_10_OR_LATER(ah))
2259                 ath9k_hw_9280_spur_mitigate(ah, chan);
2260         else
2261                 ath9k_hw_spur_mitigate(ah, chan);
2262
2263         if (!ah->eep_ops->set_board_values(ah, chan)) {
2264                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2265                         "error setting board options\n");
2266                 return -EIO;
2267         }
2268
2269         ath9k_hw_decrease_chain_power(ah, chan);
2270
2271         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2272         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2273                   | macStaId1
2274                   | AR_STA_ID1_RTS_USE_DEF
2275                   | (ah->config.
2276                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2277                   | ah->sta_id1_defaults);
2278         ath9k_hw_set_operating_mode(ah, ah->opmode);
2279
2280         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2281         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2282
2283         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2284
2285         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2286         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2287                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2288
2289         REG_WRITE(ah, AR_ISR, ~0);
2290
2291         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2292
2293         if (AR_SREV_9280_10_OR_LATER(ah)) {
2294                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2295                         return -EIO;
2296         } else {
2297                 if (!(ath9k_hw_set_channel(ah, chan)))
2298                         return -EIO;
2299         }
2300
2301         for (i = 0; i < AR_NUM_DCU; i++)
2302                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2303
2304         ah->intr_txqs = 0;
2305         for (i = 0; i < ah->caps.total_queues; i++)
2306                 ath9k_hw_resettxqueue(ah, i);
2307
2308         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2309         ath9k_hw_init_qos(ah);
2310
2311 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2312         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2313                 ath9k_enable_rfkill(ah);
2314 #endif
2315         ath9k_hw_init_user_settings(ah);
2316
2317         REG_WRITE(ah, AR_STA_ID1,
2318                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2319
2320         ath9k_hw_set_dma(ah);
2321
2322         REG_WRITE(ah, AR_OBS, 8);
2323
2324         if (ah->intr_mitigation) {
2325
2326                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2327                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2328         }
2329
2330         ath9k_hw_init_bb(ah, chan);
2331
2332         if (!ath9k_hw_init_cal(ah, chan))
2333                 return -EIO;;
2334
2335         rx_chainmask = ah->rxchainmask;
2336         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2337                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2338                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2339         }
2340
2341         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2342
2343         if (AR_SREV_9100(ah)) {
2344                 u32 mask;
2345                 mask = REG_READ(ah, AR_CFG);
2346                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2347                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2348                                 "CFG Byte Swap Set 0x%x\n", mask);
2349                 } else {
2350                         mask =
2351                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2352                         REG_WRITE(ah, AR_CFG, mask);
2353                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2354                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2355                 }
2356         } else {
2357 #ifdef __BIG_ENDIAN
2358                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2359 #endif
2360         }
2361
2362         return 0;
2363 }
2364
2365 /************************/
2366 /* Key Cache Management */
2367 /************************/
2368
2369 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2370 {
2371         u32 keyType;
2372
2373         if (entry >= ah->caps.keycache_size) {
2374                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2375                         "entry %u out of range\n", entry);
2376                 return false;
2377         }
2378
2379         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2380
2381         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2382         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2383         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2384         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2385         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2386         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2387         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2388         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2389
2390         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2391                 u16 micentry = entry + 64;
2392
2393                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2394                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2395                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2396                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2397
2398         }
2399
2400         if (ah->curchan == NULL)
2401                 return true;
2402
2403         return true;
2404 }
2405
2406 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2407 {
2408         u32 macHi, macLo;
2409
2410         if (entry >= ah->caps.keycache_size) {
2411                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2412                         "entry %u out of range\n", entry);
2413                 return false;
2414         }
2415
2416         if (mac != NULL) {
2417                 macHi = (mac[5] << 8) | mac[4];
2418                 macLo = (mac[3] << 24) |
2419                         (mac[2] << 16) |
2420                         (mac[1] << 8) |
2421                         mac[0];
2422                 macLo >>= 1;
2423                 macLo |= (macHi & 1) << 31;
2424                 macHi >>= 1;
2425         } else {
2426                 macLo = macHi = 0;
2427         }
2428         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2429         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2430
2431         return true;
2432 }
2433
2434 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2435                                  const struct ath9k_keyval *k,
2436                                  const u8 *mac)
2437 {
2438         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2439         u32 key0, key1, key2, key3, key4;
2440         u32 keyType;
2441
2442         if (entry >= pCap->keycache_size) {
2443                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2444                         "entry %u out of range\n", entry);
2445                 return false;
2446         }
2447
2448         switch (k->kv_type) {
2449         case ATH9K_CIPHER_AES_OCB:
2450                 keyType = AR_KEYTABLE_TYPE_AES;
2451                 break;
2452         case ATH9K_CIPHER_AES_CCM:
2453                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2454                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2455                                 "AES-CCM not supported by mac rev 0x%x\n",
2456                                 ah->hw_version.macRev);
2457                         return false;
2458                 }
2459                 keyType = AR_KEYTABLE_TYPE_CCM;
2460                 break;
2461         case ATH9K_CIPHER_TKIP:
2462                 keyType = AR_KEYTABLE_TYPE_TKIP;
2463                 if (ATH9K_IS_MIC_ENABLED(ah)
2464                     && entry + 64 >= pCap->keycache_size) {
2465                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2466                                 "entry %u inappropriate for TKIP\n", entry);
2467                         return false;
2468                 }
2469                 break;
2470         case ATH9K_CIPHER_WEP:
2471                 if (k->kv_len < LEN_WEP40) {
2472                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2473                                 "WEP key length %u too small\n", k->kv_len);
2474                         return false;
2475                 }
2476                 if (k->kv_len <= LEN_WEP40)
2477                         keyType = AR_KEYTABLE_TYPE_40;
2478                 else if (k->kv_len <= LEN_WEP104)
2479                         keyType = AR_KEYTABLE_TYPE_104;
2480                 else
2481                         keyType = AR_KEYTABLE_TYPE_128;
2482                 break;
2483         case ATH9K_CIPHER_CLR:
2484                 keyType = AR_KEYTABLE_TYPE_CLR;
2485                 break;
2486         default:
2487                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2488                         "cipher %u not supported\n", k->kv_type);
2489                 return false;
2490         }
2491
2492         key0 = get_unaligned_le32(k->kv_val + 0);
2493         key1 = get_unaligned_le16(k->kv_val + 4);
2494         key2 = get_unaligned_le32(k->kv_val + 6);
2495         key3 = get_unaligned_le16(k->kv_val + 10);
2496         key4 = get_unaligned_le32(k->kv_val + 12);
2497         if (k->kv_len <= LEN_WEP104)
2498                 key4 &= 0xff;
2499
2500         /*
2501          * Note: Key cache registers access special memory area that requires
2502          * two 32-bit writes to actually update the values in the internal
2503          * memory. Consequently, the exact order and pairs used here must be
2504          * maintained.
2505          */
2506
2507         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2508                 u16 micentry = entry + 64;
2509
2510                 /*
2511                  * Write inverted key[47:0] first to avoid Michael MIC errors
2512                  * on frames that could be sent or received at the same time.
2513                  * The correct key will be written in the end once everything
2514                  * else is ready.
2515                  */
2516                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2517                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2518
2519                 /* Write key[95:48] */
2520                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2521                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2522
2523                 /* Write key[127:96] and key type */
2524                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2525                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2526
2527                 /* Write MAC address for the entry */
2528                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2529
2530                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2531                         /*
2532                          * TKIP uses two key cache entries:
2533                          * Michael MIC TX/RX keys in the same key cache entry
2534                          * (idx = main index + 64):
2535                          * key0 [31:0] = RX key [31:0]
2536                          * key1 [15:0] = TX key [31:16]
2537                          * key1 [31:16] = reserved
2538                          * key2 [31:0] = RX key [63:32]
2539                          * key3 [15:0] = TX key [15:0]
2540                          * key3 [31:16] = reserved
2541                          * key4 [31:0] = TX key [63:32]
2542                          */
2543                         u32 mic0, mic1, mic2, mic3, mic4;
2544
2545                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2546                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2547                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2548                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2549                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2550
2551                         /* Write RX[31:0] and TX[31:16] */
2552                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2553                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2554
2555                         /* Write RX[63:32] and TX[15:0] */
2556                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2557                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2558
2559                         /* Write TX[63:32] and keyType(reserved) */
2560                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2561                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2562                                   AR_KEYTABLE_TYPE_CLR);
2563
2564                 } else {
2565                         /*
2566                          * TKIP uses four key cache entries (two for group
2567                          * keys):
2568                          * Michael MIC TX/RX keys are in different key cache
2569                          * entries (idx = main index + 64 for TX and
2570                          * main index + 32 + 96 for RX):
2571                          * key0 [31:0] = TX/RX MIC key [31:0]
2572                          * key1 [31:0] = reserved
2573                          * key2 [31:0] = TX/RX MIC key [63:32]
2574                          * key3 [31:0] = reserved
2575                          * key4 [31:0] = reserved
2576                          *
2577                          * Upper layer code will call this function separately
2578                          * for TX and RX keys when these registers offsets are
2579                          * used.
2580                          */
2581                         u32 mic0, mic2;
2582
2583                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2584                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2585
2586                         /* Write MIC key[31:0] */
2587                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2588                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2589
2590                         /* Write MIC key[63:32] */
2591                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2592                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2593
2594                         /* Write TX[63:32] and keyType(reserved) */
2595                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2596                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2597                                   AR_KEYTABLE_TYPE_CLR);
2598                 }
2599
2600                 /* MAC address registers are reserved for the MIC entry */
2601                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2602                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2603
2604                 /*
2605                  * Write the correct (un-inverted) key[47:0] last to enable
2606                  * TKIP now that all other registers are set with correct
2607                  * values.
2608                  */
2609                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2610                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2611         } else {
2612                 /* Write key[47:0] */
2613                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2614                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2615
2616                 /* Write key[95:48] */
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2619
2620                 /* Write key[127:96] and key type */
2621                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2622                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2623
2624                 /* Write MAC address for the entry */
2625                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2626         }
2627
2628         return true;
2629 }
2630
2631 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2632 {
2633         if (entry < ah->caps.keycache_size) {
2634                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2635                 if (val & AR_KEYTABLE_VALID)
2636                         return true;
2637         }
2638         return false;
2639 }
2640
2641 /******************************/
2642 /* Power Management (Chipset) */
2643 /******************************/
2644
2645 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2646 {
2647         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2648         if (setChip) {
2649                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2650                             AR_RTC_FORCE_WAKE_EN);
2651                 if (!AR_SREV_9100(ah))
2652                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2653
2654                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2655                             AR_RTC_RESET_EN);
2656         }
2657 }
2658
2659 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2660 {
2661         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2662         if (setChip) {
2663                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2664
2665                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2666                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2667                                   AR_RTC_FORCE_WAKE_ON_INT);
2668                 } else {
2669                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2670                                     AR_RTC_FORCE_WAKE_EN);
2671                 }
2672         }
2673 }
2674
2675 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2676 {
2677         u32 val;
2678         int i;
2679
2680         if (setChip) {
2681                 if ((REG_READ(ah, AR_RTC_STATUS) &
2682                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2683                         if (ath9k_hw_set_reset_reg(ah,
2684                                            ATH9K_RESET_POWER_ON) != true) {
2685                                 return false;
2686                         }
2687                 }
2688                 if (AR_SREV_9100(ah))
2689                         REG_SET_BIT(ah, AR_RTC_RESET,
2690                                     AR_RTC_RESET_EN);
2691
2692                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2693                             AR_RTC_FORCE_WAKE_EN);
2694                 udelay(50);
2695
2696                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2697                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2698                         if (val == AR_RTC_STATUS_ON)
2699                                 break;
2700                         udelay(50);
2701                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2702                                     AR_RTC_FORCE_WAKE_EN);
2703                 }
2704                 if (i == 0) {
2705                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2706                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2707                         return false;
2708                 }
2709         }
2710
2711         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2712
2713         return true;
2714 }
2715
2716 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2717 {
2718         int status = true, setChip = true;
2719         static const char *modes[] = {
2720                 "AWAKE",
2721                 "FULL-SLEEP",
2722                 "NETWORK SLEEP",
2723                 "UNDEFINED"
2724         };
2725
2726         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2727                 modes[ah->power_mode], modes[mode],
2728                 setChip ? "set chip " : "");
2729
2730         switch (mode) {
2731         case ATH9K_PM_AWAKE:
2732                 status = ath9k_hw_set_power_awake(ah, setChip);
2733                 break;
2734         case ATH9K_PM_FULL_SLEEP:
2735                 ath9k_set_power_sleep(ah, setChip);
2736                 ah->chip_fullsleep = true;
2737                 break;
2738         case ATH9K_PM_NETWORK_SLEEP:
2739                 ath9k_set_power_network_sleep(ah, setChip);
2740                 break;
2741         default:
2742                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2743                         "Unknown power mode %u\n", mode);
2744                 return false;
2745         }
2746         ah->power_mode = mode;
2747
2748         return status;
2749 }
2750
2751 /*
2752  * Helper for ASPM support.
2753  *
2754  * Disable PLL when in L0s as well as receiver clock when in L1.
2755  * This power saving option must be enabled through the SerDes.
2756  *
2757  * Programming the SerDes must go through the same 288 bit serial shift
2758  * register as the other analog registers.  Hence the 9 writes.
2759  */
2760 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2761 {
2762         u8 i;
2763
2764         if (ah->is_pciexpress != true)
2765                 return;
2766
2767         /* Do not touch SerDes registers */
2768         if (ah->config.pcie_powersave_enable == 2)
2769                 return;
2770
2771         /* Nothing to do on restore for 11N */
2772         if (restore)
2773                 return;
2774
2775         if (AR_SREV_9280_20_OR_LATER(ah)) {
2776                 /*
2777                  * AR9280 2.0 or later chips use SerDes values from the
2778                  * initvals.h initialized depending on chipset during
2779                  * ath9k_hw_do_attach()
2780                  */
2781                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2782                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2783                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2784                 }
2785         } else if (AR_SREV_9280(ah) &&
2786                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2787                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2788                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2789
2790                 /* RX shut off when elecidle is asserted */
2791                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2792                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2793                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2794
2795                 /* Shut off CLKREQ active in L1 */
2796                 if (ah->config.pcie_clock_req)
2797                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2798                 else
2799                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2800
2801                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2802                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2803                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2804
2805                 /* Load the new settings */
2806                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2807
2808         } else {
2809                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2810                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2811
2812                 /* RX shut off when elecidle is asserted */
2813                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2814                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2815                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2816
2817                 /*
2818                  * Ignore ah->ah_config.pcie_clock_req setting for
2819                  * pre-AR9280 11n
2820                  */
2821                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2822
2823                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2824                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2825                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2826
2827                 /* Load the new settings */
2828                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2829         }
2830
2831         udelay(1000);
2832
2833         /* set bit 19 to allow forcing of pcie core into L1 state */
2834         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2835
2836         /* Several PCIe massages to ensure proper behaviour */
2837         if (ah->config.pcie_waen) {
2838                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2839         } else {
2840                 if (AR_SREV_9285(ah))
2841                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2842                 /*
2843                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2844                  * otherwise card may disappear.
2845                  */
2846                 else if (AR_SREV_9280(ah))
2847                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2848                 else
2849                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2850         }
2851 }
2852
2853 /**********************/
2854 /* Interrupt Handling */
2855 /**********************/
2856
2857 bool ath9k_hw_intrpend(struct ath_hw *ah)
2858 {
2859         u32 host_isr;
2860
2861         if (AR_SREV_9100(ah))
2862                 return true;
2863
2864         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2865         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2866                 return true;
2867
2868         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2869         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2870             && (host_isr != AR_INTR_SPURIOUS))
2871                 return true;
2872
2873         return false;
2874 }
2875
2876 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2877 {
2878         u32 isr = 0;
2879         u32 mask2 = 0;
2880         struct ath9k_hw_capabilities *pCap = &ah->caps;
2881         u32 sync_cause = 0;
2882         bool fatal_int = false;
2883
2884         if (!AR_SREV_9100(ah)) {
2885                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2886                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2887                             == AR_RTC_STATUS_ON) {
2888                                 isr = REG_READ(ah, AR_ISR);
2889                         }
2890                 }
2891
2892                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2893                         AR_INTR_SYNC_DEFAULT;
2894
2895                 *masked = 0;
2896
2897                 if (!isr && !sync_cause)
2898                         return false;
2899         } else {
2900                 *masked = 0;
2901                 isr = REG_READ(ah, AR_ISR);
2902         }
2903
2904         if (isr) {
2905                 if (isr & AR_ISR_BCNMISC) {
2906                         u32 isr2;
2907                         isr2 = REG_READ(ah, AR_ISR_S2);
2908                         if (isr2 & AR_ISR_S2_TIM)
2909                                 mask2 |= ATH9K_INT_TIM;
2910                         if (isr2 & AR_ISR_S2_DTIM)
2911                                 mask2 |= ATH9K_INT_DTIM;
2912                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2913                                 mask2 |= ATH9K_INT_DTIMSYNC;
2914                         if (isr2 & (AR_ISR_S2_CABEND))
2915                                 mask2 |= ATH9K_INT_CABEND;
2916                         if (isr2 & AR_ISR_S2_GTT)
2917                                 mask2 |= ATH9K_INT_GTT;
2918                         if (isr2 & AR_ISR_S2_CST)
2919                                 mask2 |= ATH9K_INT_CST;
2920                         if (isr2 & AR_ISR_S2_TSFOOR)
2921                                 mask2 |= ATH9K_INT_TSFOOR;
2922                 }
2923
2924                 isr = REG_READ(ah, AR_ISR_RAC);
2925                 if (isr == 0xffffffff) {
2926                         *masked = 0;
2927                         return false;
2928                 }
2929
2930                 *masked = isr & ATH9K_INT_COMMON;
2931
2932                 if (ah->intr_mitigation) {
2933                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2934                                 *masked |= ATH9K_INT_RX;
2935                 }
2936
2937                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2938                         *masked |= ATH9K_INT_RX;
2939                 if (isr &
2940                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2941                      AR_ISR_TXEOL)) {
2942                         u32 s0_s, s1_s;
2943
2944                         *masked |= ATH9K_INT_TX;
2945
2946                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2947                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2948                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2949
2950                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2951                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2952                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2953                 }
2954
2955                 if (isr & AR_ISR_RXORN) {
2956                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2957                                 "receive FIFO overrun interrupt\n");
2958                 }
2959
2960                 if (!AR_SREV_9100(ah)) {
2961                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2962                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2963                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2964                                         *masked |= ATH9K_INT_TIM_TIMER;
2965                         }
2966                 }
2967
2968                 *masked |= mask2;
2969         }
2970
2971         if (AR_SREV_9100(ah))
2972                 return true;
2973
2974         if (sync_cause) {
2975                 fatal_int =
2976                         (sync_cause &
2977                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2978                         ? true : false;
2979
2980                 if (fatal_int) {
2981                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2982                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2983                                         "received PCI FATAL interrupt\n");
2984                         }
2985                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2986                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2987                                         "received PCI PERR interrupt\n");
2988                         }
2989                 }
2990                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2991                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2992                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2993                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2994                         REG_WRITE(ah, AR_RC, 0);
2995                         *masked |= ATH9K_INT_FATAL;
2996                 }
2997                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2998                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2999                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3000                 }
3001
3002                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3003                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3004         }
3005
3006         return true;
3007 }
3008
3009 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3010 {
3011         return ah->mask_reg;
3012 }
3013
3014 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3015 {
3016         u32 omask = ah->mask_reg;
3017         u32 mask, mask2;
3018         struct ath9k_hw_capabilities *pCap = &ah->caps;
3019
3020         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3021
3022         if (omask & ATH9K_INT_GLOBAL) {
3023                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3024                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3025                 (void) REG_READ(ah, AR_IER);
3026                 if (!AR_SREV_9100(ah)) {
3027                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3028                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3029
3030                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3031                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3032                 }
3033         }
3034
3035         mask = ints & ATH9K_INT_COMMON;
3036         mask2 = 0;
3037
3038         if (ints & ATH9K_INT_TX) {
3039                 if (ah->txok_interrupt_mask)
3040                         mask |= AR_IMR_TXOK;
3041                 if (ah->txdesc_interrupt_mask)
3042                         mask |= AR_IMR_TXDESC;
3043                 if (ah->txerr_interrupt_mask)
3044                         mask |= AR_IMR_TXERR;
3045                 if (ah->txeol_interrupt_mask)
3046                         mask |= AR_IMR_TXEOL;
3047         }
3048         if (ints & ATH9K_INT_RX) {
3049                 mask |= AR_IMR_RXERR;
3050                 if (ah->intr_mitigation)
3051                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3052                 else
3053                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3054                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3055                         mask |= AR_IMR_GENTMR;
3056         }
3057
3058         if (ints & (ATH9K_INT_BMISC)) {
3059                 mask |= AR_IMR_BCNMISC;
3060                 if (ints & ATH9K_INT_TIM)
3061                         mask2 |= AR_IMR_S2_TIM;
3062                 if (ints & ATH9K_INT_DTIM)
3063                         mask2 |= AR_IMR_S2_DTIM;
3064                 if (ints & ATH9K_INT_DTIMSYNC)
3065                         mask2 |= AR_IMR_S2_DTIMSYNC;
3066                 if (ints & ATH9K_INT_CABEND)
3067                         mask2 |= AR_IMR_S2_CABEND;
3068                 if (ints & ATH9K_INT_TSFOOR)
3069                         mask2 |= AR_IMR_S2_TSFOOR;
3070         }
3071
3072         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3073                 mask |= AR_IMR_BCNMISC;
3074                 if (ints & ATH9K_INT_GTT)
3075                         mask2 |= AR_IMR_S2_GTT;
3076                 if (ints & ATH9K_INT_CST)
3077                         mask2 |= AR_IMR_S2_CST;
3078         }
3079
3080         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3081         REG_WRITE(ah, AR_IMR, mask);
3082         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3083                                            AR_IMR_S2_DTIM |
3084                                            AR_IMR_S2_DTIMSYNC |
3085                                            AR_IMR_S2_CABEND |
3086                                            AR_IMR_S2_CABTO |
3087                                            AR_IMR_S2_TSFOOR |
3088                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3089         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3090         ah->mask_reg = ints;
3091
3092         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3093                 if (ints & ATH9K_INT_TIM_TIMER)
3094                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_