drivers/net/wireless/ath/ath9k/phy.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18
  19 void
  20 ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
  21                     int regWrites)
  22 {
  23         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  24 }
  25
  26 bool
  27 ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  28 {
  29         struct ath_common *common = ath9k_hw_common(ah);
  30         u32 channelSel = 0;
  31         u32 bModeSynth = 0;
  32         u32 aModeRefSel = 0;
  33         u32 reg32 = 0;
  34         u16 freq;
  35         struct chan_centers centers;
  36
  37         ath9k_hw_get_channel_centers(ah, chan, &centers);
  38         freq = centers.synth_center;
  39
  40         if (freq < 4800) {
  41                 u32 txctl;
  42
  43                 if (((freq - 2192) % 5) == 0) {
  44                         channelSel = ((freq - 672) * 2 - 3040) / 10;
  45                         bModeSynth = 0;
  46                 } else if (((freq - 2224) % 5) == 0) {
  47                         channelSel = ((freq - 704) * 2 - 3040) / 10;
  48                         bModeSynth = 1;
  49                 } else {
  50                         ath_print(common, ATH_DBG_FATAL,
  51                                   "Invalid channel %u MHz\n", freq);
  52                         return false;
  53                 }
  54
  55                 channelSel = (channelSel << 2) & 0xff;
  56                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  57
  58                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  59                 if (freq == 2484) {
  60
  61                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  62                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  63                 } else {
  64                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  65                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  66                 }
  67
  68         } else if ((freq % 20) == 0 && freq >= 5120) {
  69                 channelSel =
  70                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  71                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  72         } else if ((freq % 10) == 0) {
  73                 channelSel =
  74                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  75                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  76                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  77                 else
  78                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  79         } else if ((freq % 5) == 0) {
  80                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  81                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  82         } else {
  83                 ath_print(common, ATH_DBG_FATAL,
  84                           "Invalid channel %u MHz\n", freq);
  85                 return false;
  86         }
  87
  88         reg32 =
  89             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  90             (1 << 5) | 0x1;
  91
  92         REG_WRITE(ah, AR_PHY(0x37), reg32);
  93
  94         ah->curchan = chan;
  95         ah->curchan_rad_index = -1;
  96
  97         return true;
  98 }
  99
 100 void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
 101                                  struct ath9k_channel *chan)
 102 {
 103         u16 bMode, fracMode, aModeRefSel = 0;
 104         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 105         struct chan_centers centers;
 106         u32 refDivA = 24;
 107
 108         ath9k_hw_get_channel_centers(ah, chan, &centers);
 109         freq = centers.synth_center;
 110
 111         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 112         reg32 &= 0xc0000000;
 113
 114         if (freq < 4800) {
 115                 u32 txctl;
 116
 117                 bMode = 1;
 118                 fracMode = 1;
 119                 aModeRefSel = 0;
 120                 channelSel = (freq * 0x10000) / 15;
 121
 122                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 123                 if (freq == 2484) {
 124
 125                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 126                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 127                 } else {
 128                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 129                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 130                 }
 131         } else {
 132                 bMode = 0;
 133                 fracMode = 0;
 134
 135                 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
 136                 case 0:
 137                         if ((freq % 20) == 0) {
 138                                 aModeRefSel = 3;
 139                         } else if ((freq % 10) == 0) {
 140                                 aModeRefSel = 2;
 141                         }
 142                         if (aModeRefSel)
 143                                 break;
 144                 case 1:
 145                 default:
 146                         aModeRefSel = 0;
 147                         fracMode = 1;
 148                         refDivA = 1;
 149                         channelSel = (freq * 0x8000) / 15;
 150
 151                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 152                                       AR_AN_SYNTH9_REFDIVA, refDivA);
 153
 154                 }
 155
 156                 if (!fracMode) {
 157                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
 158                         channelSel = ndiv & 0x1ff;
 159                         channelFrac = (ndiv & 0xfffffe00) * 2;
 160                         channelSel = (channelSel << 17) | channelFrac;
 161                 }
 162         }
 163
 164         reg32 = reg32 |
 165             (bMode << 29) |
 166             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
 167
 168         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 169
 170         ah->curchan = chan;
 171         ah->curchan_rad_index = -1;
 172 }
 173
 174 static void
 175 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
 176                            u32 numBits, u32 firstBit,
 177                            u32 column)
 178 {
 179         u32 tmp32, mask, arrayEntry, lastBit;
 180         int32_t bitPosition, bitsLeft;
 181
 182         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
 183         arrayEntry = (firstBit - 1) / 8;
 184         bitPosition = (firstBit - 1) % 8;
 185         bitsLeft = numBits;
 186         while (bitsLeft > 0) {
 187                 lastBit = (bitPosition + bitsLeft > 8) ?
 188                     8 : bitPosition + bitsLeft;
 189                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
 190                     (column * 8);
 191                 rfBuf[arrayEntry] &= ~mask;
 192                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
 193                                       (column * 8)) & mask;
 194                 bitsLeft -= 8 - bitPosition;
 195                 tmp32 = tmp32 >> (8 - bitPosition);
 196                 bitPosition = 0;
 197                 arrayEntry++;
 198         }
 199 }
 200
 201 bool
 202 ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
 203                      u16 modesIndex)
 204 {
 205         u32 eepMinorRev;
 206         u32 ob5GHz = 0, db5GHz = 0;
 207         u32 ob2GHz = 0, db2GHz = 0;
 208         int regWrites = 0;
 209
 210         if (AR_SREV_9280_10_OR_LATER(ah))
 211                 return true;
 212
 213         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 214
 215         RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
 216
 217         RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 218
 219         RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 220
 221         RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 222                       modesIndex);
 223         {
 224                 int i;
 225                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
 226                         ah->analogBank6Data[i] =
 227                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
 228                 }
 229         }
 230
 231         if (eepMinorRev >= 2) {
 232                 if (IS_CHAN_2GHZ(chan)) {
 233                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
 234                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
 235                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 236                                                    ob2GHz, 3, 197, 0);
 237                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 238                                                    db2GHz, 3, 194, 0);
 239                 } else {
 240                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
 241                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
 242                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 243                                                    ob5GHz, 3, 203, 0);
 244                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 245                                                    db5GHz, 3, 200, 0);
 246                 }
 247         }
 248
 249         RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 250
 251         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 252                            regWrites);
 253         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
 254                            regWrites);
 255         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
 256                            regWrites);
 257         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
 258                            regWrites);
 259         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
 260                            regWrites);
 261         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
 262                            regWrites);
 263
 264         return true;
 265 }
 266
 267 void
 268 ath9k_hw_rf_free(struct ath_hw *ah)
 269 {
 270 #define ATH_FREE_BANK(bank) do { \
 271                 kfree(bank); \
 272                 bank = NULL; \
 273         } while (0);
 274
 275         ATH_FREE_BANK(ah->analogBank0Data);
 276         ATH_FREE_BANK(ah->analogBank1Data);
 277         ATH_FREE_BANK(ah->analogBank2Data);
 278         ATH_FREE_BANK(ah->analogBank3Data);
 279         ATH_FREE_BANK(ah->analogBank6Data);
 280         ATH_FREE_BANK(ah->analogBank6TPCData);
 281         ATH_FREE_BANK(ah->analogBank7Data);
 282         ATH_FREE_BANK(ah->addac5416_21);
 283         ATH_FREE_BANK(ah->bank6Temp);
 284 #undef ATH_FREE_BANK
 285 }
 286
 287 bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
 288 {
 289         struct ath_common *common = ath9k_hw_common(ah);
 290
 291         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 292                 ah->analogBank0Data =
 293                     kzalloc((sizeof(u32) *
 294                              ah->iniBank0.ia_rows), GFP_KERNEL);
 295                 ah->analogBank1Data =
 296                     kzalloc((sizeof(u32) *
 297                              ah->iniBank1.ia_rows), GFP_KERNEL);
 298                 ah->analogBank2Data =
 299                     kzalloc((sizeof(u32) *
 300                              ah->iniBank2.ia_rows), GFP_KERNEL);
 301                 ah->analogBank3Data =
 302                     kzalloc((sizeof(u32) *
 303                              ah->iniBank3.ia_rows), GFP_KERNEL);
 304                 ah->analogBank6Data =
 305                     kzalloc((sizeof(u32) *
 306                              ah->iniBank6.ia_rows), GFP_KERNEL);
 307                 ah->analogBank6TPCData =
 308                     kzalloc((sizeof(u32) *
 309                              ah->iniBank6TPC.ia_rows), GFP_KERNEL);
 310                 ah->analogBank7Data =
 311                     kzalloc((sizeof(u32) *
 312                              ah->iniBank7.ia_rows), GFP_KERNEL);
 313
 314                 if (ah->analogBank0Data == NULL
 315                     || ah->analogBank1Data == NULL
 316                     || ah->analogBank2Data == NULL
 317                     || ah->analogBank3Data == NULL
 318                     || ah->analogBank6Data == NULL
 319                     || ah->analogBank6TPCData == NULL
 320                     || ah->analogBank7Data == NULL) {
 321                         ath_print(common, ATH_DBG_FATAL,
 322                                   "Cannot allocate RF banks\n");
 323                         *status = -ENOMEM;
 324                         return false;
 325                 }
 326
 327                 ah->addac5416_21 =
 328                     kzalloc((sizeof(u32) *
 329                              ah->iniAddac.ia_rows *
 330                              ah->iniAddac.ia_columns), GFP_KERNEL);
 331                 if (ah->addac5416_21 == NULL) {
 332                         ath_print(common, ATH_DBG_FATAL,
 333                                   "Cannot allocate addac5416_21\n");
 334                         *status = -ENOMEM;
 335                         return false;
 336                 }
 337
 338                 ah->bank6Temp =
 339                     kzalloc((sizeof(u32) *
 340                              ah->iniBank6.ia_rows), GFP_KERNEL);
 341                 if (ah->bank6Temp == NULL) {
 342                         ath_print(common, ATH_DBG_FATAL,
 343                                   "Cannot allocate bank6Temp\n");
 344                         *status = -ENOMEM;
 345                         return false;
 346                 }
 347         }
 348
 349         return true;
 350 }
 351
 352 void
 353 ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
 354 {
 355         int i, regWrites = 0;
 356         u32 bank6SelMask;
 357         u32 *bank6Temp = ah->bank6Temp;
 358
 359         switch (ah->config.diversity_control) {
 360         case ATH9K_ANT_FIXED_A:
 361                 bank6SelMask =
 362                     (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
 363                         REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
 364                 break;
 365         case ATH9K_ANT_FIXED_B:
 366                 bank6SelMask =
 367                     (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
 368                         REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
 369                 break;
 370         case ATH9K_ANT_VARIABLE:
 371                 return;
 372                 break;
 373         default:
 374                 return;
 375                 break;
 376         }
 377
 378         for (i = 0; i < ah->iniBank6.ia_rows; i++)
 379                 bank6Temp[i] = ah->analogBank6Data[i];
 380
 381         REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
 382
 383         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
 384         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
 385         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
 386         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
 387         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
 388         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
 389         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
 390         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
 391         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
 392
 393         REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
 394
 395         REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
 396 #ifdef ALTER_SWITCH
 397         REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
 398                   (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
 399                   | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
 400 #endif
 401 }