2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
21 static char *dev_info = "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 /* We use the hw_value as an index into our private channel structure */
34 #define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
40 #define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
47 /* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
103 static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
119 sc->hw_rate_table[ATH9K_MODE_11G];
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
133 sc->hw_rate_table[ATH9K_MODE_11A];
141 static void ath_update_txpow(struct ath_softc *sc)
143 struct ath_hw *ah = sc->sc_ah;
146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
150 sc->curtxpow = txpow;
154 static u8 parse_mpdudensity(u8 mpdudensity)
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
167 switch (mpdudensity) {
173 /* Our lower layer calculations limit our precision to
189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 const struct ath_rate_table *rate_table = NULL;
192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
207 if (rate_table == NULL)
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
216 maxrates = rate_table->rate_cnt;
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
228 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
229 rate[i].bitrate / 10, rate[i].hw_value);
233 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234 struct ieee80211_hw *hw)
236 struct ieee80211_channel *curchan = hw->conf.channel;
237 struct ath9k_channel *channel;
240 chan_idx = curchan->hw_value;
241 channel = &sc->sc_ah->channels[chan_idx];
242 ath9k_update_ichannel(sc, hw, channel);
246 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
251 spin_lock_irqsave(&sc->sc_pm_lock, flags);
252 ret = ath9k_hw_setpower(sc->sc_ah, mode);
253 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
258 void ath9k_ps_wakeup(struct ath_softc *sc)
262 spin_lock_irqsave(&sc->sc_pm_lock, flags);
263 if (++sc->ps_usecount != 1)
266 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
269 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
272 void ath9k_ps_restore(struct ath_softc *sc)
276 spin_lock_irqsave(&sc->sc_pm_lock, flags);
277 if (--sc->ps_usecount != 0)
280 if (sc->ps_enabled &&
281 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
283 SC_OP_WAIT_FOR_PSPOLL_DATA |
284 SC_OP_WAIT_FOR_TX_ACK)))
285 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
288 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
292 * Set/change channels. If the channel is really being changed, it's done
293 * by reseting the chip. To accomplish this we must first cleanup any pending
294 * DMA, then restart stuff.
296 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
297 struct ath9k_channel *hchan)
299 struct ath_hw *ah = sc->sc_ah;
300 bool fastcc = true, stopped;
301 struct ieee80211_channel *channel = hw->conf.channel;
304 if (sc->sc_flags & SC_OP_INVALID)
310 * This is only performed if the channel settings have
313 * To switch channels clear any pending DMA operations;
314 * wait long enough for the RX fifo to drain, reset the
315 * hardware at the new frequency, and then re-enable
316 * the relevant bits of the h/w.
318 ath9k_hw_set_interrupts(ah, 0);
319 ath_drain_all_txq(sc, false);
320 stopped = ath_stoprecv(sc);
322 /* XXX: do not flush receive queue here. We don't want
323 * to flush data frames already in queue because of
324 * changing channel. */
326 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
329 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
330 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
331 sc->sc_ah->curchan->channel,
332 channel->center_freq, sc->tx_chan_width);
334 spin_lock_bh(&sc->sc_resetlock);
336 r = ath9k_hw_reset(ah, hchan, fastcc);
338 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
339 "Unable to reset channel (%u Mhz) "
341 channel->center_freq, r);
342 spin_unlock_bh(&sc->sc_resetlock);
345 spin_unlock_bh(&sc->sc_resetlock);
347 sc->sc_flags &= ~SC_OP_FULL_RESET;
349 if (ath_startrecv(sc) != 0) {
350 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
351 "Unable to restart recv logic\n");
356 ath_cache_conf_rate(sc, &hw->conf);
357 ath_update_txpow(sc);
358 ath9k_hw_set_interrupts(ah, sc->imask);
361 ath9k_ps_restore(sc);
366 * This routine performs the periodic noise floor calibration function
367 * that is used to adjust and optimize the chip performance. This
368 * takes environmental changes (location, temperature) into account.
369 * When the task is complete, it reschedules itself depending on the
370 * appropriate interval that was calculated.
372 static void ath_ani_calibrate(unsigned long data)
374 struct ath_softc *sc = (struct ath_softc *)data;
375 struct ath_hw *ah = sc->sc_ah;
376 bool longcal = false;
377 bool shortcal = false;
378 bool aniflag = false;
379 unsigned int timestamp = jiffies_to_msecs(jiffies);
380 u32 cal_interval, short_cal_interval;
382 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
383 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
386 * don't calibrate when we're scanning.
387 * we are most likely not on our home channel.
389 spin_lock(&sc->ani_lock);
390 if (sc->sc_flags & SC_OP_SCANNING)
393 /* Only calibrate if awake */
394 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
399 /* Long calibration runs independently of short calibration. */
400 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
402 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
403 sc->ani.longcal_timer = timestamp;
406 /* Short calibration applies only while caldone is false */
407 if (!sc->ani.caldone) {
408 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
410 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
411 sc->ani.shortcal_timer = timestamp;
412 sc->ani.resetcal_timer = timestamp;
415 if ((timestamp - sc->ani.resetcal_timer) >=
416 ATH_RESTART_CALINTERVAL) {
417 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
419 sc->ani.resetcal_timer = timestamp;
423 /* Verify whether we must check ANI */
424 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
426 sc->ani.checkani_timer = timestamp;
429 /* Skip all processing if there's nothing to do. */
430 if (longcal || shortcal || aniflag) {
431 /* Call ANI routine if necessary */
433 ath9k_hw_ani_monitor(ah, ah->curchan);
435 /* Perform calibration if necessary */
436 if (longcal || shortcal) {
437 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
438 sc->rx_chainmask, longcal);
441 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
444 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
445 ah->curchan->channel, ah->curchan->channelFlags,
446 sc->ani.noise_floor);
450 ath9k_ps_restore(sc);
453 spin_unlock(&sc->ani_lock);
455 * Set timer interval based on previous results.
456 * The interval must be the shortest necessary to satisfy ANI,
457 * short calibration and long calibration.
459 cal_interval = ATH_LONG_CALINTERVAL;
460 if (sc->sc_ah->config.enable_ani)
461 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
462 if (!sc->ani.caldone)
463 cal_interval = min(cal_interval, (u32)short_cal_interval);
465 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
468 static void ath_start_ani(struct ath_softc *sc)
470 unsigned long timestamp = jiffies_to_msecs(jiffies);
472 sc->ani.longcal_timer = timestamp;
473 sc->ani.shortcal_timer = timestamp;
474 sc->ani.checkani_timer = timestamp;
476 mod_timer(&sc->ani.timer,
477 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
481 * Update tx/rx chainmask. For legacy association,
482 * hard code chainmask to 1x1, for 11n association, use
483 * the chainmask configuration, for bt coexistence, use
484 * the chainmask configuration even in legacy mode.
486 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
488 struct ath_hw *ah = sc->sc_ah;
490 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
491 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
492 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
493 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
495 sc->tx_chainmask = 1;
496 sc->rx_chainmask = 1;
499 DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
500 sc->tx_chainmask, sc->rx_chainmask);
503 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
507 an = (struct ath_node *)sta->drv_priv;
509 if (sc->sc_flags & SC_OP_TXAGGR) {
510 ath_tx_node_init(sc, an);
511 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
512 sta->ht_cap.ampdu_factor);
513 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
514 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
518 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
520 struct ath_node *an = (struct ath_node *)sta->drv_priv;
522 if (sc->sc_flags & SC_OP_TXAGGR)
523 ath_tx_node_cleanup(sc, an);
526 static void ath9k_tasklet(unsigned long data)
528 struct ath_softc *sc = (struct ath_softc *)data;
529 struct ath_hw *ah = sc->sc_ah;
531 u32 status = sc->intrstatus;
535 if (status & ATH9K_INT_FATAL) {
536 ath_reset(sc, false);
537 ath9k_ps_restore(sc);
541 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
542 spin_lock_bh(&sc->rx.rxflushlock);
543 ath_rx_tasklet(sc, 0);
544 spin_unlock_bh(&sc->rx.rxflushlock);
547 if (status & ATH9K_INT_TX)
550 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
552 * TSF sync does not look correct; remain awake to sync with
555 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
556 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
559 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
560 if (status & ATH9K_INT_GENTIMER)
561 ath_gen_timer_isr(sc->sc_ah);
563 /* re-enable hardware interrupt */
564 ath9k_hw_set_interrupts(ah, sc->imask);
565 ath9k_ps_restore(sc);
568 irqreturn_t ath_isr(int irq, void *dev)
570 #define SCHED_INTR ( \
581 struct ath_softc *sc = dev;
582 struct ath_hw *ah = sc->sc_ah;
583 enum ath9k_int status;
587 * The hardware is not ready/present, don't
588 * touch anything. Note this can happen early
589 * on if the IRQ is shared.
591 if (sc->sc_flags & SC_OP_INVALID)
595 /* shared irq, not for us */
597 if (!ath9k_hw_intrpend(ah))
601 * Figure out the reason(s) for the interrupt. Note
602 * that the hal returns a pseudo-ISR that may include
603 * bits we haven't explicitly enabled so we mask the
604 * value to insure we only process bits we requested.
606 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
607 status &= sc->imask; /* discard unasked-for bits */
610 * If there are no status bits set, then this interrupt was not
611 * for me (should have been caught above).
616 /* Cache the status */
617 sc->intrstatus = status;
619 if (status & SCHED_INTR)
623 * If a FATAL or RXORN interrupt is received, we have to reset the
626 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
629 if (status & ATH9K_INT_SWBA)
630 tasklet_schedule(&sc->bcon_tasklet);
632 if (status & ATH9K_INT_TXURN)
633 ath9k_hw_updatetxtriglevel(ah, true);
635 if (status & ATH9K_INT_MIB) {
637 * Disable interrupts until we service the MIB
638 * interrupt; otherwise it will continue to
641 ath9k_hw_set_interrupts(ah, 0);
643 * Let the hal handle the event. We assume
644 * it will clear whatever condition caused
647 ath9k_hw_procmibevent(ah);
648 ath9k_hw_set_interrupts(ah, sc->imask);
651 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
652 if (status & ATH9K_INT_TIM_TIMER) {
653 /* Clear RxAbort bit so that we can
655 ath9k_setpower(sc, ATH9K_PM_AWAKE);
656 ath9k_hw_setrxabort(sc->sc_ah, 0);
657 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
662 ath_debug_stat_interrupt(sc, status);
665 /* turn off every interrupt except SWBA */
666 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
667 tasklet_schedule(&sc->intr_tq);
675 static u32 ath_get_extchanmode(struct ath_softc *sc,
676 struct ieee80211_channel *chan,
677 enum nl80211_channel_type channel_type)
681 switch (chan->band) {
682 case IEEE80211_BAND_2GHZ:
683 switch(channel_type) {
684 case NL80211_CHAN_NO_HT:
685 case NL80211_CHAN_HT20:
686 chanmode = CHANNEL_G_HT20;
688 case NL80211_CHAN_HT40PLUS:
689 chanmode = CHANNEL_G_HT40PLUS;
691 case NL80211_CHAN_HT40MINUS:
692 chanmode = CHANNEL_G_HT40MINUS;
696 case IEEE80211_BAND_5GHZ:
697 switch(channel_type) {
698 case NL80211_CHAN_NO_HT:
699 case NL80211_CHAN_HT20:
700 chanmode = CHANNEL_A_HT20;
702 case NL80211_CHAN_HT40PLUS:
703 chanmode = CHANNEL_A_HT40PLUS;
705 case NL80211_CHAN_HT40MINUS:
706 chanmode = CHANNEL_A_HT40MINUS;
717 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
718 struct ath9k_keyval *hk, const u8 *addr,
724 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
725 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
729 * Group key installation - only two key cache entries are used
730 * regardless of splitmic capability since group key is only
731 * used either for TX or RX.
734 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
735 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
737 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
738 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
740 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
743 /* TX and RX keys share the same key cache entry. */
744 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
745 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
746 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
749 /* Separate key cache entries for TX and RX */
751 /* TX key goes at first index, RX key at +32. */
752 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
753 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
754 /* TX MIC entry failed. No need to proceed further */
755 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
756 "Setting TX MIC Key Failed\n");
760 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
761 /* XXX delete tx key on failure? */
762 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
765 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
769 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
770 if (test_bit(i, sc->keymap) ||
771 test_bit(i + 64, sc->keymap))
772 continue; /* At least one part of TKIP key allocated */
774 (test_bit(i + 32, sc->keymap) ||
775 test_bit(i + 64 + 32, sc->keymap)))
776 continue; /* At least one part of TKIP key allocated */
778 /* Found a free slot for a TKIP key */
784 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
788 /* First, try to find slots that would not be available for TKIP. */
790 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
791 if (!test_bit(i, sc->keymap) &&
792 (test_bit(i + 32, sc->keymap) ||
793 test_bit(i + 64, sc->keymap) ||
794 test_bit(i + 64 + 32, sc->keymap)))
796 if (!test_bit(i + 32, sc->keymap) &&
797 (test_bit(i, sc->keymap) ||
798 test_bit(i + 64, sc->keymap) ||
799 test_bit(i + 64 + 32, sc->keymap)))
801 if (!test_bit(i + 64, sc->keymap) &&
802 (test_bit(i , sc->keymap) ||
803 test_bit(i + 32, sc->keymap) ||
804 test_bit(i + 64 + 32, sc->keymap)))
806 if (!test_bit(i + 64 + 32, sc->keymap) &&
807 (test_bit(i, sc->keymap) ||
808 test_bit(i + 32, sc->keymap) ||
809 test_bit(i + 64, sc->keymap)))
813 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
814 if (!test_bit(i, sc->keymap) &&
815 test_bit(i + 64, sc->keymap))
817 if (test_bit(i, sc->keymap) &&
818 !test_bit(i + 64, sc->keymap))
823 /* No partially used TKIP slots, pick any available slot */
824 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
825 /* Do not allow slots that could be needed for TKIP group keys
826 * to be used. This limitation could be removed if we know that
827 * TKIP will not be used. */
828 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
831 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
833 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
837 if (!test_bit(i, sc->keymap))
838 return i; /* Found a free slot for a key */
841 /* No free slot found */
845 static int ath_key_config(struct ath_softc *sc,
846 struct ieee80211_vif *vif,
847 struct ieee80211_sta *sta,
848 struct ieee80211_key_conf *key)
850 struct ath9k_keyval hk;
851 const u8 *mac = NULL;
855 memset(&hk, 0, sizeof(hk));
859 hk.kv_type = ATH9K_CIPHER_WEP;
862 hk.kv_type = ATH9K_CIPHER_TKIP;
865 hk.kv_type = ATH9K_CIPHER_AES_CCM;
871 hk.kv_len = key->keylen;
872 memcpy(hk.kv_val, key->key, key->keylen);
874 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
875 /* For now, use the default keys for broadcast keys. This may
876 * need to change with virtual interfaces. */
878 } else if (key->keyidx) {
883 if (vif->type != NL80211_IFTYPE_AP) {
884 /* Only keyidx 0 should be used with unicast key, but
885 * allow this for client mode for now. */
894 if (key->alg == ALG_TKIP)
895 idx = ath_reserve_key_cache_slot_tkip(sc);
897 idx = ath_reserve_key_cache_slot(sc);
899 return -ENOSPC; /* no free key cache entries */
902 if (key->alg == ALG_TKIP)
903 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
904 vif->type == NL80211_IFTYPE_AP);
906 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
911 set_bit(idx, sc->keymap);
912 if (key->alg == ALG_TKIP) {
913 set_bit(idx + 64, sc->keymap);
915 set_bit(idx + 32, sc->keymap);
916 set_bit(idx + 64 + 32, sc->keymap);
923 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
925 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
926 if (key->hw_key_idx < IEEE80211_WEP_NKID)
929 clear_bit(key->hw_key_idx, sc->keymap);
930 if (key->alg != ALG_TKIP)
933 clear_bit(key->hw_key_idx + 64, sc->keymap);
935 clear_bit(key->hw_key_idx + 32, sc->keymap);
936 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
940 static void setup_ht_cap(struct ath_softc *sc,
941 struct ieee80211_sta_ht_cap *ht_info)
943 u8 tx_streams, rx_streams;
945 ht_info->ht_supported = true;
946 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
947 IEEE80211_HT_CAP_SM_PS |
948 IEEE80211_HT_CAP_SGI_40 |
949 IEEE80211_HT_CAP_DSSSCCK40;
951 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
952 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
954 /* set up supported mcs set */
955 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
956 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
957 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
959 if (tx_streams != rx_streams) {
960 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
961 tx_streams, rx_streams);
962 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
963 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
964 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
967 ht_info->mcs.rx_mask[0] = 0xff;
969 ht_info->mcs.rx_mask[1] = 0xff;
971 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
974 static void ath9k_bss_assoc_info(struct ath_softc *sc,
975 struct ieee80211_vif *vif,
976 struct ieee80211_bss_conf *bss_conf)
978 struct ath_hw *ah = sc->sc_ah;
979 struct ath_common *common = ath9k_hw_common(ah);
981 if (bss_conf->assoc) {
982 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
983 bss_conf->aid, common->curbssid);
985 /* New association, store aid */
986 common->curaid = bss_conf->aid;
987 ath9k_hw_write_associd(ah);
990 * Request a re-configuration of Beacon related timers
991 * on the receipt of the first Beacon frame (i.e.,
992 * after time sync with the AP).
994 sc->sc_flags |= SC_OP_BEACON_SYNC;
996 /* Configure the beacon */
997 ath_beacon_config(sc, vif);
999 /* Reset rssi stats */
1000 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1004 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1007 del_timer_sync(&sc->ani.timer);
1011 /********************************/
1013 /********************************/
1015 static void ath_led_blink_work(struct work_struct *work)
1017 struct ath_softc *sc = container_of(work, struct ath_softc,
1018 ath_led_blink_work.work);
1020 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1023 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1024 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1025 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1027 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1028 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1030 ieee80211_queue_delayed_work(sc->hw,
1031 &sc->ath_led_blink_work,
1032 (sc->sc_flags & SC_OP_LED_ON) ?
1033 msecs_to_jiffies(sc->led_off_duration) :
1034 msecs_to_jiffies(sc->led_on_duration));
1036 sc->led_on_duration = sc->led_on_cnt ?
1037 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1038 ATH_LED_ON_DURATION_IDLE;
1039 sc->led_off_duration = sc->led_off_cnt ?
1040 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1041 ATH_LED_OFF_DURATION_IDLE;
1042 sc->led_on_cnt = sc->led_off_cnt = 0;
1043 if (sc->sc_flags & SC_OP_LED_ON)
1044 sc->sc_flags &= ~SC_OP_LED_ON;
1046 sc->sc_flags |= SC_OP_LED_ON;
1049 static void ath_led_brightness(struct led_classdev *led_cdev,
1050 enum led_brightness brightness)
1052 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1053 struct ath_softc *sc = led->sc;
1055 switch (brightness) {
1057 if (led->led_type == ATH_LED_ASSOC ||
1058 led->led_type == ATH_LED_RADIO) {
1059 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1060 (led->led_type == ATH_LED_RADIO));
1061 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062 if (led->led_type == ATH_LED_RADIO)
1063 sc->sc_flags &= ~SC_OP_LED_ON;
1069 if (led->led_type == ATH_LED_ASSOC) {
1070 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1071 ieee80211_queue_delayed_work(sc->hw,
1072 &sc->ath_led_blink_work, 0);
1073 } else if (led->led_type == ATH_LED_RADIO) {
1074 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1075 sc->sc_flags |= SC_OP_LED_ON;
1085 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1091 led->led_cdev.name = led->name;
1092 led->led_cdev.default_trigger = trigger;
1093 led->led_cdev.brightness_set = ath_led_brightness;
1095 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1097 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1098 "Failed to register led:%s", led->name);
1100 led->registered = 1;
1104 static void ath_unregister_led(struct ath_led *led)
1106 if (led->registered) {
1107 led_classdev_unregister(&led->led_cdev);
1108 led->registered = 0;
1112 static void ath_deinit_leds(struct ath_softc *sc)
1114 ath_unregister_led(&sc->assoc_led);
1115 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1116 ath_unregister_led(&sc->tx_led);
1117 ath_unregister_led(&sc->rx_led);
1118 ath_unregister_led(&sc->radio_led);
1119 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1122 static void ath_init_leds(struct ath_softc *sc)
1127 if (AR_SREV_9287(sc->sc_ah))
1128 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1130 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1132 /* Configure gpio 1 for output */
1133 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1134 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1135 /* LED off, active low */
1136 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1138 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1140 trigger = ieee80211_get_radio_led_name(sc->hw);
1141 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1142 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1143 ret = ath_register_led(sc, &sc->radio_led, trigger);
1144 sc->radio_led.led_type = ATH_LED_RADIO;
1148 trigger = ieee80211_get_assoc_led_name(sc->hw);
1149 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1150 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1151 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1152 sc->assoc_led.led_type = ATH_LED_ASSOC;
1156 trigger = ieee80211_get_tx_led_name(sc->hw);
1157 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1158 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1159 ret = ath_register_led(sc, &sc->tx_led, trigger);
1160 sc->tx_led.led_type = ATH_LED_TX;
1164 trigger = ieee80211_get_rx_led_name(sc->hw);
1165 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1166 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1167 ret = ath_register_led(sc, &sc->rx_led, trigger);
1168 sc->rx_led.led_type = ATH_LED_RX;
1175 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1176 ath_deinit_leds(sc);
1179 void ath_radio_enable(struct ath_softc *sc)
1181 struct ath_hw *ah = sc->sc_ah;
1182 struct ieee80211_channel *channel = sc->hw->conf.channel;
1185 ath9k_ps_wakeup(sc);
1186 ath9k_hw_configpcipowersave(ah, 0, 0);
1189 ah->curchan = ath_get_curchannel(sc, sc->hw);
1191 spin_lock_bh(&sc->sc_resetlock);
1192 r = ath9k_hw_reset(ah, ah->curchan, false);
1194 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1195 "Unable to reset channel %u (%uMhz) ",
1196 "reset status %d\n",
1197 channel->center_freq, r);
1199 spin_unlock_bh(&sc->sc_resetlock);
1201 ath_update_txpow(sc);
1202 if (ath_startrecv(sc) != 0) {
1203 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1204 "Unable to restart recv logic\n");
1208 if (sc->sc_flags & SC_OP_BEACONS)
1209 ath_beacon_config(sc, NULL); /* restart beacons */
1211 /* Re-Enable interrupts */
1212 ath9k_hw_set_interrupts(ah, sc->imask);
1215 ath9k_hw_cfg_output(ah, ah->led_pin,
1216 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1217 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1219 ieee80211_wake_queues(sc->hw);
1220 ath9k_ps_restore(sc);
1223 void ath_radio_disable(struct ath_softc *sc)
1225 struct ath_hw *ah = sc->sc_ah;
1226 struct ieee80211_channel *channel = sc->hw->conf.channel;
1229 ath9k_ps_wakeup(sc);
1230 ieee80211_stop_queues(sc->hw);
1233 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1234 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1236 /* Disable interrupts */
1237 ath9k_hw_set_interrupts(ah, 0);
1239 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1240 ath_stoprecv(sc); /* turn off frame recv */
1241 ath_flushrecv(sc); /* flush recv queue */
1244 ah->curchan = ath_get_curchannel(sc, sc->hw);
1246 spin_lock_bh(&sc->sc_resetlock);
1247 r = ath9k_hw_reset(ah, ah->curchan, false);
1249 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1250 "Unable to reset channel %u (%uMhz) "
1251 "reset status %d\n",
1252 channel->center_freq, r);
1254 spin_unlock_bh(&sc->sc_resetlock);
1256 ath9k_hw_phy_disable(ah);
1257 ath9k_hw_configpcipowersave(ah, 1, 1);
1258 ath9k_ps_restore(sc);
1259 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1262 /*******************/
1264 /*******************/
1266 static bool ath_is_rfkill_set(struct ath_softc *sc)
1268 struct ath_hw *ah = sc->sc_ah;
1270 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1271 ah->rfkill_polarity;
1274 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1276 struct ath_wiphy *aphy = hw->priv;
1277 struct ath_softc *sc = aphy->sc;
1278 bool blocked = !!ath_is_rfkill_set(sc);
1280 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1283 static void ath_start_rfkill_poll(struct ath_softc *sc)
1285 struct ath_hw *ah = sc->sc_ah;
1287 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288 wiphy_rfkill_start_polling(sc->hw->wiphy);
1291 void ath_cleanup(struct ath_softc *sc)
1294 free_irq(sc->irq, sc);
1295 ath_bus_cleanup(sc);
1296 kfree(sc->sec_wiphy);
1297 ieee80211_free_hw(sc->hw);
1300 void ath_detach(struct ath_softc *sc)
1302 struct ieee80211_hw *hw = sc->hw;
1303 struct ath_hw *ah = sc->sc_ah;
1306 ath9k_ps_wakeup(sc);
1308 dev_dbg(sc->dev, "Detach ATH hw\n");
1310 ath_deinit_leds(sc);
1311 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1313 for (i = 0; i < sc->num_sec_wiphy; i++) {
1314 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1317 sc->sec_wiphy[i] = NULL;
1318 ieee80211_unregister_hw(aphy->hw);
1319 ieee80211_free_hw(aphy->hw);
1321 ieee80211_unregister_hw(hw);
1325 tasklet_kill(&sc->intr_tq);
1326 tasklet_kill(&sc->bcon_tasklet);
1328 if (!(sc->sc_flags & SC_OP_INVALID))
1329 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1331 /* cleanup tx queues */
1332 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1333 if (ATH_TXQ_SETUP(sc, i))
1334 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1336 if ((sc->btcoex.no_stomp_timer) &&
1337 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1338 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1340 ath9k_hw_detach(ah);
1341 ath9k_exit_debug(ah);
1345 static int ath9k_reg_notifier(struct wiphy *wiphy,
1346 struct regulatory_request *request)
1348 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1349 struct ath_wiphy *aphy = hw->priv;
1350 struct ath_softc *sc = aphy->sc;
1351 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1353 return ath_reg_notifier_apply(wiphy, request, reg);
1357 * Detects if there is any priority bt traffic
1359 static void ath_detect_bt_priority(struct ath_softc *sc)
1361 struct ath_btcoex *btcoex = &sc->btcoex;
1362 struct ath_hw *ah = sc->sc_ah;
1364 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1365 btcoex->bt_priority_cnt++;
1367 if (time_after(jiffies, btcoex->bt_priority_time +
1368 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1369 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1370 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1371 "BT priority traffic detected");
1372 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1374 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1377 btcoex->bt_priority_cnt = 0;
1378 btcoex->bt_priority_time = jiffies;
1383 * Configures appropriate weight based on stomp type.
1385 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1386 enum ath_stomp_type stomp_type)
1388 struct ath_hw *ah = sc->sc_ah;
1390 switch (stomp_type) {
1391 case ATH_BTCOEX_STOMP_ALL:
1392 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1393 AR_STOMP_ALL_WLAN_WGHT);
1395 case ATH_BTCOEX_STOMP_LOW:
1396 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1397 AR_STOMP_LOW_WLAN_WGHT);
1399 case ATH_BTCOEX_STOMP_NONE:
1400 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1401 AR_STOMP_NONE_WLAN_WGHT);
1404 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1408 ath9k_hw_btcoex_enable(ah);
1412 * This is the master bt coex timer which runs for every
1413 * 45ms, bt traffic will be given priority during 55% of this
1414 * period while wlan gets remaining 45%
1416 static void ath_btcoex_period_timer(unsigned long data)
1418 struct ath_softc *sc = (struct ath_softc *) data;
1419 struct ath_hw *ah = sc->sc_ah;
1420 struct ath_btcoex *btcoex = &sc->btcoex;
1422 ath_detect_bt_priority(sc);
1424 spin_lock_bh(&btcoex->btcoex_lock);
1426 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1428 spin_unlock_bh(&btcoex->btcoex_lock);
1430 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1431 if (btcoex->hw_timer_enabled)
1432 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1434 ath_gen_timer_start(ah,
1435 btcoex->no_stomp_timer,
1436 (ath9k_hw_gettsf32(ah) +
1437 btcoex->btcoex_no_stomp),
1438 btcoex->btcoex_no_stomp * 10);
1439 btcoex->hw_timer_enabled = true;
1442 mod_timer(&btcoex->period_timer, jiffies +
1443 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1447 * Generic tsf based hw timer which configures weight
1448 * registers to time slice between wlan and bt traffic
1450 static void ath_btcoex_no_stomp_timer(void *arg)
1452 struct ath_softc *sc = (struct ath_softc *)arg;
1453 struct ath_hw *ah = sc->sc_ah;
1454 struct ath_btcoex *btcoex = &sc->btcoex;
1456 DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1458 spin_lock_bh(&btcoex->btcoex_lock);
1460 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1461 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1462 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1463 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1465 spin_unlock_bh(&btcoex->btcoex_lock);
1468 static int ath_init_btcoex_timer(struct ath_softc *sc)
1470 struct ath_btcoex *btcoex = &sc->btcoex;
1472 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1473 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1474 btcoex->btcoex_period / 100;
1476 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1477 (unsigned long) sc);
1479 spin_lock_init(&btcoex->btcoex_lock);
1481 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1482 ath_btcoex_no_stomp_timer,
1483 ath_btcoex_no_stomp_timer,
1484 (void *) sc, AR_FIRST_NDP_TIMER);
1486 if (!btcoex->no_stomp_timer)
1493 * Read and write, they both share the same lock. We do this to serialize
1494 * reads and writes on Atheros 802.11n PCI devices only. This is required
1495 * as the FIFO on these devices can only accept sanely 2 requests. After
1496 * that the device goes bananas. Serializing the reads/writes prevents this
1500 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1502 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1504 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1505 unsigned long flags;
1506 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1507 iowrite32(val, ah->ah_sc->mem + reg_offset);
1508 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1510 iowrite32(val, ah->ah_sc->mem + reg_offset);
1513 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1515 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1518 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1519 unsigned long flags;
1520 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1521 val = ioread32(ah->ah_sc->mem + reg_offset);
1522 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1524 val = ioread32(ah->ah_sc->mem + reg_offset);
1528 static struct ath_ops ath9k_common_ops = {
1529 .read = ath9k_ioread32,
1530 .write = ath9k_iowrite32,
1534 * Initialize and fill ath_softc, ath_sofct is the
1535 * "Software Carrier" struct. Historically it has existed
1536 * to allow the separation between hardware specific
1537 * variables (now in ath_hw) and driver specific variables.
1539 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1541 struct ath_hw *ah = NULL;
1542 struct ath_common *common;
1547 /* XXX: hardware will not be ready until ath_open() being called */
1548 sc->sc_flags |= SC_OP_INVALID;
1550 spin_lock_init(&sc->wiphy_lock);
1551 spin_lock_init(&sc->sc_resetlock);
1552 spin_lock_init(&sc->sc_serial_rw);
1553 spin_lock_init(&sc->ani_lock);
1554 spin_lock_init(&sc->sc_pm_lock);
1555 mutex_init(&sc->mutex);
1556 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1557 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1560 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1567 ah->hw_version.devid = devid;
1568 ah->hw_version.subsysid = subsysid;
1571 common = ath9k_hw_common(ah);
1572 common->ops = &ath9k_common_ops;
1576 * Cache line size is used to size and align various
1577 * structures used to communicate with the hardware.
1579 ath_read_cachesize(sc, &csz);
1580 /* XXX assert csz is non-zero */
1581 common->cachelsz = csz << 2; /* convert to bytes */
1583 if (ath9k_init_debug(ah) < 0)
1584 dev_err(sc->dev, "Unable to create debugfs files\n");
1586 r = ath9k_hw_init(ah);
1588 DPRINTF(ah, ATH_DBG_FATAL,
1589 "Unable to initialize hardware; "
1590 "initialization status: %d\n", r);
1594 /* Get the hardware key cache size. */
1595 sc->keymax = ah->caps.keycache_size;
1596 if (sc->keymax > ATH_KEYMAX) {
1597 DPRINTF(ah, ATH_DBG_ANY,
1598 "Warning, using only %u entries in %u key cache\n",
1599 ATH_KEYMAX, sc->keymax);
1600 sc->keymax = ATH_KEYMAX;
1604 * Reset the key cache since some parts do not
1605 * reset the contents on initial power up.
1607 for (i = 0; i < sc->keymax; i++)
1608 ath9k_hw_keyreset(ah, (u16) i);
1610 /* default to MONITOR mode */
1611 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1613 /* Setup rate tables */
1615 ath_rate_attach(sc);
1616 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1617 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1620 * Allocate hardware transmit queues: one queue for
1621 * beacon frames and one data queue for each QoS
1622 * priority. Note that the hal handles reseting
1623 * these queues at the needed time.
1625 sc->beacon.beaconq = ath_beaconq_setup(ah);
1626 if (sc->beacon.beaconq == -1) {
1627 DPRINTF(ah, ATH_DBG_FATAL,
1628 "Unable to setup a beacon xmit queue\n");
1632 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1633 if (sc->beacon.cabq == NULL) {
1634 DPRINTF(ah, ATH_DBG_FATAL,
1635 "Unable to setup CAB xmit queue\n");
1640 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1641 ath_cabq_update(sc);
1643 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1644 sc->tx.hwq_map[i] = -1;
1646 /* Setup data queues */
1647 /* NB: ensure BK queue is the lowest priority h/w queue */
1648 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1649 DPRINTF(ah, ATH_DBG_FATAL,
1650 "Unable to setup xmit queue for BK traffic\n");
1655 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1656 DPRINTF(ah, ATH_DBG_FATAL,
1657 "Unable to setup xmit queue for BE traffic\n");
1661 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1662 DPRINTF(ah, ATH_DBG_FATAL,
1663 "Unable to setup xmit queue for VI traffic\n");
1667 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1668 DPRINTF(ah, ATH_DBG_FATAL,
1669 "Unable to setup xmit queue for VO traffic\n");
1674 /* Initializes the noise floor to a reasonable default value.
1675 * Later on this will be updated during ANI processing. */
1677 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1678 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1680 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1681 ATH9K_CIPHER_TKIP, NULL)) {
1683 * Whether we should enable h/w TKIP MIC.
1684 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1685 * report WMM capable, so it's always safe to turn on
1686 * TKIP MIC in this case.
1688 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1693 * Check whether the separate key cache entries
1694 * are required to handle both tx+rx MIC keys.
1695 * With split mic keys the number of stations is limited
1696 * to 27 otherwise 59.
1698 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1699 ATH9K_CIPHER_TKIP, NULL)
1700 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1701 ATH9K_CIPHER_MIC, NULL)
1702 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1706 /* turn on mcast key search if possible */
1707 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1708 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1711 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1713 /* 11n Capabilities */
1714 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1715 sc->sc_flags |= SC_OP_TXAGGR;
1716 sc->sc_flags |= SC_OP_RXAGGR;
1719 sc->tx_chainmask = ah->caps.tx_chainmask;
1720 sc->rx_chainmask = ah->caps.rx_chainmask;
1722 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1723 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1725 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1726 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1728 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1730 /* initialize beacon slots */
1731 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1732 sc->beacon.bslot[i] = NULL;
1733 sc->beacon.bslot_aphy[i] = NULL;
1736 /* setup channels and rates */
1738 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1739 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1740 sc->rates[IEEE80211_BAND_2GHZ];
1741 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1742 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1743 ARRAY_SIZE(ath9k_2ghz_chantable);
1745 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1746 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1747 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1748 sc->rates[IEEE80211_BAND_5GHZ];
1749 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1750 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1751 ARRAY_SIZE(ath9k_5ghz_chantable);
1754 switch (ah->btcoex_hw.scheme) {
1755 case ATH_BTCOEX_CFG_NONE:
1757 case ATH_BTCOEX_CFG_2WIRE:
1758 ath9k_hw_btcoex_init_2wire(ah);
1760 case ATH_BTCOEX_CFG_3WIRE:
1761 ath9k_hw_btcoex_init_3wire(ah);
1762 r = ath_init_btcoex_timer(sc);
1765 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1766 ath9k_hw_init_btcoex_hw(ah, qnum);
1767 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1776 /* cleanup tx queues */
1777 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1778 if (ATH_TXQ_SETUP(sc, i))
1779 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1781 ath9k_hw_detach(ah);
1783 ath9k_exit_debug(sc->sc_ah);
1789 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1791 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1792 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1793 IEEE80211_HW_SIGNAL_DBM |
1794 IEEE80211_HW_AMPDU_AGGREGATION |
1795 IEEE80211_HW_SUPPORTS_PS |
1796 IEEE80211_HW_PS_NULLFUNC_STACK |
1797 IEEE80211_HW_SPECTRUM_MGMT;
1799 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1800 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1802 hw->wiphy->interface_modes =
1803 BIT(NL80211_IFTYPE_AP) |
1804 BIT(NL80211_IFTYPE_STATION) |
1805 BIT(NL80211_IFTYPE_ADHOC) |
1806 BIT(NL80211_IFTYPE_MESH_POINT);
1810 hw->channel_change_time = 5000;
1811 hw->max_listen_interval = 10;
1812 /* Hardware supports 10 but we use 4 */
1813 hw->max_rate_tries = 4;
1814 hw->sta_data_size = sizeof(struct ath_node);
1815 hw->vif_data_size = sizeof(struct ath_vif);
1817 hw->rate_control_algorithm = "ath9k_rate_control";
1819 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1820 &sc->sbands[IEEE80211_BAND_2GHZ];
1821 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1822 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1823 &sc->sbands[IEEE80211_BAND_5GHZ];
1826 /* Device driver core initialization */
1827 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1829 struct ieee80211_hw *hw = sc->hw;
1830 struct ath_common *common;
1833 struct ath_regulatory *reg;
1835 dev_dbg(sc->dev, "Attach ATH hw\n");
1837 error = ath_init_softc(devid, sc, subsysid);
1842 common = ath9k_hw_common(ah);
1844 /* get mac address from hardware and set in mac80211 */
1846 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1848 ath_set_hw_capab(sc, hw);
1850 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1851 ath9k_reg_notifier);
1855 reg = &common->regulatory;
1857 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1858 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1859 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1860 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1863 /* initialize tx/rx engine */
1864 error = ath_tx_init(sc, ATH_TXBUF);
1868 error = ath_rx_init(sc, ATH_RXBUF);
1872 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1873 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1874 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1876 error = ieee80211_register_hw(hw);
1878 if (!ath_is_world_regd(reg)) {
1879 error = regulatory_hint(hw->wiphy, reg->alpha2);
1884 /* Initialize LED control */
1887 ath_start_rfkill_poll(sc);
1892 /* cleanup tx queues */
1893 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1894 if (ATH_TXQ_SETUP(sc, i))
1895 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1897 ath9k_hw_detach(ah);
1898 ath9k_exit_debug(ah);
1904 int ath_reset(struct ath_softc *sc, bool retry_tx)
1906 struct ath_hw *ah = sc->sc_ah;
1907 struct ieee80211_hw *hw = sc->hw;
1910 ath9k_hw_set_interrupts(ah, 0);
1911 ath_drain_all_txq(sc, retry_tx);
1915 spin_lock_bh(&sc->sc_resetlock);
1916 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1918 DPRINTF(ah, ATH_DBG_FATAL,
1919 "Unable to reset hardware; reset status %d\n", r);
1920 spin_unlock_bh(&sc->sc_resetlock);
1922 if (ath_startrecv(sc) != 0)
1923 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1926 * We may be doing a reset in response to a request
1927 * that changes the channel so update any state that
1928 * might change as a result.
1930 ath_cache_conf_rate(sc, &hw->conf);
1932 ath_update_txpow(sc);
1934 if (sc->sc_flags & SC_OP_BEACONS)
1935 ath_beacon_config(sc, NULL); /* restart beacons */
1937 ath9k_hw_set_interrupts(ah, sc->imask);
1941 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1942 if (ATH_TXQ_SETUP(sc, i)) {
1943 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1944 ath_txq_schedule(sc, &sc->tx.txq[i]);
1945 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1954 * This function will allocate both the DMA descriptor structure, and the
1955 * buffers it contains. These are used to contain the descriptors used
1958 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1959 struct list_head *head, const char *name,
1960 int nbuf, int ndesc)
1962 #define DS2PHYS(_dd, _ds) \
1963 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1964 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1965 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1967 struct ath_desc *ds;
1969 int i, bsize, error;
1971 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1974 INIT_LIST_HEAD(head);
1975 /* ath_desc must be a multiple of DWORDs */
1976 if ((sizeof(struct ath_desc) % 4) != 0) {
1977 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1978 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1983 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1986 * Need additional DMA memory because we can't use
1987 * descriptors that cross the 4K page boundary. Assume
1988 * one skipped descriptor per 4K page.
1990 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1992 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1995 while (ndesc_skipped) {
1996 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1997 dd->dd_desc_len += dma_len;
1999 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2003 /* allocate descriptors */
2004 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2005 &dd->dd_desc_paddr, GFP_KERNEL);
2006 if (dd->dd_desc == NULL) {
2011 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2012 name, ds, (u32) dd->dd_desc_len,
2013 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2015 /* allocate buffers */
2016 bsize = sizeof(struct ath_buf) * nbuf;
2017 bf = kzalloc(bsize, GFP_KERNEL);
2024 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2026 bf->bf_daddr = DS2PHYS(dd, ds);
2028 if (!(sc->sc_ah->caps.hw_caps &
2029 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2031 * Skip descriptor addresses which can cause 4KB
2032 * boundary crossing (addr + length) with a 32 dword
2035 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2036 ASSERT((caddr_t) bf->bf_desc <
2037 ((caddr_t) dd->dd_desc +
2042 bf->bf_daddr = DS2PHYS(dd, ds);
2045 list_add_tail(&bf->list, head);
2049 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2052 memset(dd, 0, sizeof(*dd));
2054 #undef ATH_DESC_4KB_BOUND_CHECK
2055 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2059 void ath_descdma_cleanup(struct ath_softc *sc,
2060 struct ath_descdma *dd,
2061 struct list_head *head)
2063 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2066 INIT_LIST_HEAD(head);
2067 kfree(dd->dd_bufptr);
2068 memset(dd, 0, sizeof(*dd));
2071 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2077 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2080 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2083 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2086 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2089 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2096 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2101 case ATH9K_WME_AC_VO:
2104 case ATH9K_WME_AC_VI:
2107 case ATH9K_WME_AC_BE:
2110 case ATH9K_WME_AC_BK:
2121 /* XXX: Remove me once we don't depend on ath9k_channel for all
2122 * this redundant data */
2123 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2124 struct ath9k_channel *ichan)
2126 struct ieee80211_channel *chan = hw->conf.channel;
2127 struct ieee80211_conf *conf = &hw->conf;
2129 ichan->channel = chan->center_freq;
2132 if (chan->band == IEEE80211_BAND_2GHZ) {
2133 ichan->chanmode = CHANNEL_G;
2134 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2136 ichan->chanmode = CHANNEL_A;
2137 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2140 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2142 if (conf_is_ht(conf)) {
2143 if (conf_is_ht40(conf))
2144 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2146 ichan->chanmode = ath_get_extchanmode(sc, chan,
2147 conf->channel_type);
2151 /**********************/
2152 /* mac80211 callbacks */
2153 /**********************/
2156 * (Re)start btcoex timers
2158 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2160 struct ath_btcoex *btcoex = &sc->btcoex;
2161 struct ath_hw *ah = sc->sc_ah;
2163 DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2165 /* make sure duty cycle timer is also stopped when resuming */
2166 if (btcoex->hw_timer_enabled)
2167 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2169 btcoex->bt_priority_cnt = 0;
2170 btcoex->bt_priority_time = jiffies;
2171 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2173 mod_timer(&btcoex->period_timer, jiffies);
2176 static int ath9k_start(struct ieee80211_hw *hw)
2178 struct ath_wiphy *aphy = hw->priv;
2179 struct ath_softc *sc = aphy->sc;
2180 struct ath_hw *ah = sc->sc_ah;
2181 struct ieee80211_channel *curchan = hw->conf.channel;
2182 struct ath9k_channel *init_channel;
2185 DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
2186 "initial channel: %d MHz\n", curchan->center_freq);
2188 mutex_lock(&sc->mutex);
2190 if (ath9k_wiphy_started(sc)) {
2191 if (sc->chan_idx == curchan->hw_value) {
2193 * Already on the operational channel, the new wiphy
2194 * can be marked active.
2196 aphy->state = ATH_WIPHY_ACTIVE;
2197 ieee80211_wake_queues(hw);
2200 * Another wiphy is on another channel, start the new
2201 * wiphy in paused state.
2203 aphy->state = ATH_WIPHY_PAUSED;
2204 ieee80211_stop_queues(hw);
2206 mutex_unlock(&sc->mutex);
2209 aphy->state = ATH_WIPHY_ACTIVE;
2211 /* setup initial channel */
2213 sc->chan_idx = curchan->hw_value;
2215 init_channel = ath_get_curchannel(sc, hw);
2217 /* Reset SERDES registers */
2218 ath9k_hw_configpcipowersave(ah, 0, 0);
2221 * The basic interface to setting the hardware in a good
2222 * state is ``reset''. On return the hardware is known to
2223 * be powered up and with interrupts disabled. This must
2224 * be followed by initialization of the appropriate bits
2225 * and then setup of the interrupt mask.
2227 spin_lock_bh(&sc->sc_resetlock);
2228 r = ath9k_hw_reset(ah, init_channel, false);
2230 DPRINTF(ah, ATH_DBG_FATAL,
2231 "Unable to reset hardware; reset status %d "
2232 "(freq %u MHz)\n", r,
2233 curchan->center_freq);
2234 spin_unlock_bh(&sc->sc_resetlock);
2237 spin_unlock_bh(&sc->sc_resetlock);
2240 * This is needed only to setup initial state
2241 * but it's best done after a reset.
2243 ath_update_txpow(sc);
2246 * Setup the hardware after reset:
2247 * The receive engine is set going.
2248 * Frame transmit is handled entirely
2249 * in the frame output path; there's nothing to do
2250 * here except setup the interrupt mask.
2252 if (ath_startrecv(sc) != 0) {
2253 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
2258 /* Setup our intr mask. */
2259 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2260 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2261 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2263 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2264 sc->imask |= ATH9K_INT_GTT;
2266 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2267 sc->imask |= ATH9K_INT_CST;
2269 ath_cache_conf_rate(sc, &hw->conf);
2271 sc->sc_flags &= ~SC_OP_INVALID;
2273 /* Disable BMISS interrupt when we're not associated */
2274 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2275 ath9k_hw_set_interrupts(ah, sc->imask);
2277 ieee80211_wake_queues(hw);
2279 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2281 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2282 !ah->btcoex_hw.enabled) {
2283 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2284 AR_STOMP_LOW_WLAN_WGHT);
2285 ath9k_hw_btcoex_enable(ah);
2287 if (sc->bus_ops->bt_coex_prep)
2288 sc->bus_ops->bt_coex_prep(sc);
2289 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2290 ath9k_btcoex_timer_resume(sc);
2294 mutex_unlock(&sc->mutex);
2299 static int ath9k_tx(struct ieee80211_hw *hw,
2300 struct sk_buff *skb)
2302 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2303 struct ath_wiphy *aphy = hw->priv;
2304 struct ath_softc *sc = aphy->sc;
2305 struct ath_tx_control txctl;
2306 int hdrlen, padsize;
2308 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2309 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2310 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2314 if (sc->ps_enabled) {
2315 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2317 * mac80211 does not set PM field for normal data frames, so we
2318 * need to update that based on the current PS mode.
2320 if (ieee80211_is_data(hdr->frame_control) &&
2321 !ieee80211_is_nullfunc(hdr->frame_control) &&
2322 !ieee80211_has_pm(hdr->frame_control)) {
2323 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2324 "while in PS mode\n");
2325 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2329 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2331 * We are using PS-Poll and mac80211 can request TX while in
2332 * power save mode. Need to wake up hardware for the TX to be
2333 * completed and if needed, also for RX of buffered frames.
2335 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2336 ath9k_ps_wakeup(sc);
2337 ath9k_hw_setrxabort(sc->sc_ah, 0);
2338 if (ieee80211_is_pspoll(hdr->frame_control)) {
2339 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2340 "buffered frame\n");
2341 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2343 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2344 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2347 * The actual restore operation will happen only after
2348 * the sc_flags bit is cleared. We are just dropping
2349 * the ps_usecount here.
2351 ath9k_ps_restore(sc);
2354 memset(&txctl, 0, sizeof(struct ath_tx_control));
2357 * As a temporary workaround, assign seq# here; this will likely need
2358 * to be cleaned up to work better with Beacon transmission and virtual
2361 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2362 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2363 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2364 sc->tx.seq_no += 0x10;
2365 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2366 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2369 /* Add the padding after the header if this is not already done */
2370 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2372 padsize = hdrlen % 4;
2373 if (skb_headroom(skb) < padsize)
2375 skb_push(skb, padsize);
2376 memmove(skb->data, skb->data + padsize, hdrlen);
2379 /* Check if a tx queue is available */
2381 txctl.txq = ath_test_get_txq(sc, skb);
2385 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2387 if (ath_tx_start(hw, skb, &txctl) != 0) {
2388 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2394 dev_kfree_skb_any(skb);
2399 * Pause btcoex timer and bt duty cycle timer
2401 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2403 struct ath_btcoex *btcoex = &sc->btcoex;
2404 struct ath_hw *ah = sc->sc_ah;
2406 del_timer_sync(&btcoex->period_timer);
2408 if (btcoex->hw_timer_enabled)
2409 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2411 btcoex->hw_timer_enabled = false;
2414 static void ath9k_stop(struct ieee80211_hw *hw)
2416 struct ath_wiphy *aphy = hw->priv;
2417 struct ath_softc *sc = aphy->sc;
2418 struct ath_hw *ah = sc->sc_ah;
2420 mutex_lock(&sc->mutex);
2422 aphy->state = ATH_WIPHY_INACTIVE;
2424 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2425 cancel_delayed_work_sync(&sc->tx_complete_work);
2427 if (!sc->num_sec_wiphy) {
2428 cancel_delayed_work_sync(&sc->wiphy_work);
2429 cancel_work_sync(&sc->chan_work);
2432 if (sc->sc_flags & SC_OP_INVALID) {
2433 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
2434 mutex_unlock(&sc->mutex);
2438 if (ath9k_wiphy_started(sc)) {
2439 mutex_unlock(&sc->mutex);
2440 return; /* another wiphy still in use */
2443 if (ah->btcoex_hw.enabled) {
2444 ath9k_hw_btcoex_disable(ah);
2445 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2446 ath9k_btcoex_timer_pause(sc);
2449 /* make sure h/w will not generate any interrupt
2450 * before setting the invalid flag. */
2451 ath9k_hw_set_interrupts(ah, 0);
2453 if (!(sc->sc_flags & SC_OP_INVALID)) {
2454 ath_drain_all_txq(sc, false);
2456 ath9k_hw_phy_disable(ah);
2458 sc->rx.rxlink = NULL;
2460 /* disable HAL and put h/w to sleep */
2461 ath9k_hw_disable(ah);
2462 ath9k_hw_configpcipowersave(ah, 1, 1);
2463 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2465 sc->sc_flags |= SC_OP_INVALID;
2467 mutex_unlock(&sc->mutex);
2469 DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
2472 static int ath9k_add_interface(struct ieee80211_hw *hw,
2473 struct ieee80211_if_init_conf *conf)
2475 struct ath_wiphy *aphy = hw->priv;
2476 struct ath_softc *sc = aphy->sc;
2477 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2478 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2481 mutex_lock(&sc->mutex);
2483 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2489 switch (conf->type) {
2490 case NL80211_IFTYPE_STATION:
2491 ic_opmode = NL80211_IFTYPE_STATION;
2493 case NL80211_IFTYPE_ADHOC:
2494 case NL80211_IFTYPE_AP:
2495 case NL80211_IFTYPE_MESH_POINT:
2496 if (sc->nbcnvifs >= ATH_BCBUF) {
2500 ic_opmode = conf->type;
2503 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2504 "Interface type %d not yet supported\n", conf->type);
2509 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2511 /* Set the VIF opmode */
2512 avp->av_opmode = ic_opmode;
2517 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2518 ath9k_set_bssid_mask(hw);
2521 goto out; /* skip global settings for secondary vif */
2523 if (ic_opmode == NL80211_IFTYPE_AP) {
2524 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2525 sc->sc_flags |= SC_OP_TSF_RESET;
2528 /* Set the device opmode */
2529 sc->sc_ah->opmode = ic_opmode;
2532 * Enable MIB interrupts when there are hardware phy counters.
2533 * Note we only do this (at the moment) for station mode.
2535 if ((conf->type == NL80211_IFTYPE_STATION) ||
2536 (conf->type == NL80211_IFTYPE_ADHOC) ||
2537 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2538 sc->imask |= ATH9K_INT_MIB;
2539 sc->imask |= ATH9K_INT_TSFOOR;
2542 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2544 if (conf->type == NL80211_IFTYPE_AP ||
2545 conf->type == NL80211_IFTYPE_ADHOC ||
2546 conf->type == NL80211_IFTYPE_MONITOR)
2550 mutex_unlock(&sc->mutex);
2554 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2555 struct ieee80211_if_init_conf *conf)
2557 struct ath_wiphy *aphy = hw->priv;
2558 struct ath_softc *sc = aphy->sc;
2559 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2562 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2564 mutex_lock(&sc->mutex);
2567 del_timer_sync(&sc->ani.timer);
2569 /* Reclaim beacon resources */
2570 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2571 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2572 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2573 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2574 ath_beacon_return(sc, avp);
2577 sc->sc_flags &= ~SC_OP_BEACONS;
2579 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2580 if (sc->beacon.bslot[i] == conf->vif) {
2581 printk(KERN_DEBUG "%s: vif had allocated beacon "
2582 "slot\n", __func__);
2583 sc->beacon.bslot[i] = NULL;
2584 sc->beacon.bslot_aphy[i] = NULL;
2590 mutex_unlock(&sc->mutex);
2593 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2595 struct ath_wiphy *aphy = hw->priv;
2596 struct ath_softc *sc = aphy->sc;
2597 struct ieee80211_conf *conf = &hw->conf;
2598 struct ath_hw *ah = sc->sc_ah;
2599 bool all_wiphys_idle = false, disable_radio = false;
2601 mutex_lock(&sc->mutex);
2603 /* Leave this as the first check */
2604 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2606 spin_lock_bh(&sc->wiphy_lock);
2607 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2608 spin_unlock_bh(&sc->wiphy_lock);
2610 if (conf->flags & IEEE80211_CONF_IDLE){
2611 if (all_wiphys_idle)
2612 disable_radio = true;
2614 else if (all_wiphys_idle) {
2615 ath_radio_enable(sc);
2616 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2617 "not-idle: enabling radio\n");
2621 if (changed & IEEE80211_CONF_CHANGE_PS) {
2622 if (conf->flags & IEEE80211_CONF_PS) {
2623 if (!(ah->caps.hw_caps &
2624 ATH9K_HW_CAP_AUTOSLEEP)) {
2625 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2626 sc->imask |= ATH9K_INT_TIM_TIMER;
2627 ath9k_hw_set_interrupts(sc->sc_ah,
2630 ath9k_hw_setrxabort(sc->sc_ah, 1);
2632 sc->ps_enabled = true;
2634 sc->ps_enabled = false;
2635 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2636 if (!(ah->caps.hw_caps &
2637 ATH9K_HW_CAP_AUTOSLEEP)) {
2638 ath9k_hw_setrxabort(sc->sc_ah, 0);
2639 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2640 SC_OP_WAIT_FOR_CAB |
2641 SC_OP_WAIT_FOR_PSPOLL_DATA |
2642 SC_OP_WAIT_FOR_TX_ACK);
2643 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2644 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2645 ath9k_hw_set_interrupts(sc->sc_ah,
2652 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2653 struct ieee80211_channel *curchan = hw->conf.channel;
2654 int pos = curchan->hw_value;
2656 aphy->chan_idx = pos;
2657 aphy->chan_is_ht = conf_is_ht(conf);
2659 if (aphy->state == ATH_WIPHY_SCAN ||
2660 aphy->state == ATH_WIPHY_ACTIVE)
2661 ath9k_wiphy_pause_all_forced(sc, aphy);
2664 * Do not change operational channel based on a paused
2667 goto skip_chan_change;
2670 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2671 curchan->center_freq);
2673 /* XXX: remove me eventualy */
2674 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2676 ath_update_chainmask(sc, conf_is_ht(conf));
2678 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2679 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2680 mutex_unlock(&sc->mutex);
2686 if (changed & IEEE80211_CONF_CHANGE_POWER)
2687 sc->config.txpowlimit = 2 * conf->power_level;
2689 if (disable_radio) {
2690 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2691 ath_radio_disable(sc);
2694 mutex_unlock(&sc->mutex);
2699 #define SUPPORTED_FILTERS \
2700 (FIF_PROMISC_IN_BSS | \
2705 FIF_BCN_PRBRESP_PROMISC | \
2708 /* FIXME: sc->sc_full_reset ? */
2709 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2710 unsigned int changed_flags,
2711 unsigned int *total_flags,
2714 struct ath_wiphy *aphy = hw->priv;
2715 struct ath_softc *sc = aphy->sc;
2718 changed_flags &= SUPPORTED_FILTERS;
2719 *total_flags &= SUPPORTED_FILTERS;
2721 sc->rx.rxfilter = *total_flags;
2722 ath9k_ps_wakeup(sc);
2723 rfilt = ath_calcrxfilter(sc);
2724 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2725 ath9k_ps_restore(sc);
2727 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2730 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2731 struct ieee80211_vif *vif,
2732 enum sta_notify_cmd cmd,
2733 struct ieee80211_sta *sta)
2735 struct ath_wiphy *aphy = hw->priv;
2736 struct ath_softc *sc = aphy->sc;
2739 case STA_NOTIFY_ADD:
2740 ath_node_attach(sc, sta);
2742 case STA_NOTIFY_REMOVE:
2743 ath_node_detach(sc, sta);
2750 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2751 const struct ieee80211_tx_queue_params *params)
2753 struct ath_wiphy *aphy = hw->priv;
2754 struct ath_softc *sc = aphy->sc;
2755 struct ath9k_tx_queue_info qi;
2758 if (queue >= WME_NUM_AC)
2761 mutex_lock(&sc->mutex);
2763 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2765 qi.tqi_aifs = params->aifs;
2766 qi.tqi_cwmin = params->cw_min;
2767 qi.tqi_cwmax = params->cw_max;
2768 qi.tqi_burstTime = params->txop;
2769 qnum = ath_get_hal_qnum(queue, sc);
2771 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2772 "Configure tx [queue/halq] [%d/%d], "
2773 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2774 queue, qnum, params->aifs, params->cw_min,
2775 params->cw_max, params->txop);
2777 ret = ath_txq_update(sc, qnum, &qi);
2779 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2781 mutex_unlock(&sc->mutex);
2786 static int ath9k_set_key(struct ieee80211_hw *hw,
2787 enum set_key_cmd cmd,
2788 struct ieee80211_vif *vif,
2789 struct ieee80211_sta *sta,
2790 struct ieee80211_key_conf *key)
2792 struct ath_wiphy *aphy = hw->priv;
2793 struct ath_softc *sc = aphy->sc;
2796 if (modparam_nohwcrypt)
2799 mutex_lock(&sc->mutex);
2800 ath9k_ps_wakeup(sc);
2801 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2805 ret = ath_key_config(sc, vif, sta, key);
2807 key->hw_key_idx = ret;
2808 /* push IV and Michael MIC generation to stack */
2809 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2810 if (key->alg == ALG_TKIP)
2811 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2812 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2813 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2818 ath_key_delete(sc, key);
2824 ath9k_ps_restore(sc);
2825 mutex_unlock(&sc->mutex);
2830 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2831 struct ieee80211_vif *vif,
2832 struct ieee80211_bss_conf *bss_conf,
2835 struct ath_wiphy *aphy = hw->priv;
2836 struct ath_softc *sc = aphy->sc;
2837 struct ath_hw *ah = sc->sc_ah;
2838 struct ath_common *common = ath9k_hw_common(ah);
2839 struct ath_vif *avp = (void *)vif->drv_priv;
2843 mutex_lock(&sc->mutex);
2846 * TODO: Need to decide which hw opmode to use for
2847 * multi-interface cases
2848 * XXX: This belongs into add_interface!
2850 if (vif->type == NL80211_IFTYPE_AP &&
2851 ah->opmode != NL80211_IFTYPE_AP) {
2852 ah->opmode = NL80211_IFTYPE_STATION;
2853 ath9k_hw_setopmode(ah);
2854 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2856 ath9k_hw_write_associd(ah);
2857 /* Request full reset to get hw opmode changed properly */
2858 sc->sc_flags |= SC_OP_FULL_RESET;
2861 if ((changed & BSS_CHANGED_BSSID) &&
2862 !is_zero_ether_addr(bss_conf->bssid)) {
2863 switch (vif->type) {
2864 case NL80211_IFTYPE_STATION:
2865 case NL80211_IFTYPE_ADHOC:
2866 case NL80211_IFTYPE_MESH_POINT:
2868 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2869 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2871 ath9k_hw_write_associd(ah);
2873 /* Set aggregation protection mode parameters */
2874 sc->config.ath_aggr_prot = 0;
2876 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2877 "RX filter 0x%x bssid %pM aid 0x%x\n",
2878 rfilt, common->curbssid, common->curaid);
2880 /* need to reconfigure the beacon */
2881 sc->sc_flags &= ~SC_OP_BEACONS ;
2889 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2890 (vif->type == NL80211_IFTYPE_AP) ||
2891 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2892 if ((changed & BSS_CHANGED_BEACON) ||
2893 (changed & BSS_CHANGED_BEACON_ENABLED &&
2894 bss_conf->enable_beacon)) {
2896 * Allocate and setup the beacon frame.
2898 * Stop any previous beacon DMA. This may be
2899 * necessary, for example, when an ibss merge
2900 * causes reconfiguration; we may be called
2901 * with beacon transmission active.
2903 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2905 error = ath_beacon_alloc(aphy, vif);
2907 ath_beacon_config(sc, vif);
2911 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2912 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2913 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2914 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2915 ath9k_hw_keysetmac(sc->sc_ah,
2920 /* Only legacy IBSS for now */
2921 if (vif->type == NL80211_IFTYPE_ADHOC)
2922 ath_update_chainmask(sc, 0);
2924 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2925 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2926 bss_conf->use_short_preamble);
2927 if (bss_conf->use_short_preamble)
2928 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2930 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2933 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2934 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2935 bss_conf->use_cts_prot);
2936 if (bss_conf->use_cts_prot &&
2937 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2938 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2940 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2943 if (changed & BSS_CHANGED_ASSOC) {
2944 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2946 ath9k_bss_assoc_info(sc, vif, bss_conf);
2950 * The HW TSF has to be reset when the beacon interval changes.
2951 * We set the flag here, and ath_beacon_config_ap() would take this
2952 * into account when it gets called through the subsequent
2953 * config_interface() call - with IFCC_BEACON in the changed field.
2956 if (changed & BSS_CHANGED_BEACON_INT) {
2957 sc->sc_flags |= SC_OP_TSF_RESET;
2958 sc->beacon_interval = bss_conf->beacon_int;
2961 mutex_unlock(&sc->mutex);
2964 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2967 struct ath_wiphy *aphy = hw->priv;
2968 struct ath_softc *sc = aphy->sc;
2970 mutex_lock(&sc->mutex);
2971 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2972 mutex_unlock(&sc->mutex);
2977 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2979 struct ath_wiphy *aphy = hw->priv;
2980 struct ath_softc *sc = aphy->sc;
2982 mutex_lock(&sc->mutex);
2983 ath9k_hw_settsf64(sc->sc_ah, tsf);
2984 mutex_unlock(&sc->mutex);
2987 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2989 struct ath_wiphy *aphy = hw->priv;
2990 struct ath_softc *sc = aphy->sc;
2992 mutex_lock(&sc->mutex);
2994 ath9k_ps_wakeup(sc);
2995 ath9k_hw_reset_tsf(sc->sc_ah);
2996 ath9k_ps_restore(sc);
2998 mutex_unlock(&sc->mutex);
3001 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3002 enum ieee80211_ampdu_mlme_action action,
3003 struct ieee80211_sta *sta,
3006 struct ath_wiphy *aphy = hw->priv;
3007 struct ath_softc *sc = aphy->sc;
3011 case IEEE80211_AMPDU_RX_START:
3012 if (!(sc->sc_flags & SC_OP_RXAGGR))
3015 case IEEE80211_AMPDU_RX_STOP:
3017 case IEEE80211_AMPDU_TX_START:
3018 ath_tx_aggr_start(sc, sta, tid, ssn);
3019 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3021 case IEEE80211_AMPDU_TX_STOP:
3022 ath_tx_aggr_stop(sc, sta, tid);
3023 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3025 case IEEE80211_AMPDU_TX_OPERATIONAL:
3026 ath_tx_aggr_resume(sc, sta, tid);
3029 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
3035 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3037 struct ath_wiphy *aphy = hw->priv;
3038 struct ath_softc *sc = aphy->sc;
3040 mutex_lock(&sc->mutex);
3041 if (ath9k_wiphy_scanning(sc)) {
3042 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3045 * Do not allow the concurrent scanning state for now. This
3046 * could be improved with scanning control moved into ath9k.
3048 mutex_unlock(&sc->mutex);
3052 aphy->state = ATH_WIPHY_SCAN;
3053 ath9k_wiphy_pause_all_forced(sc, aphy);
3055 spin_lock_bh(&sc->ani_lock);
3056 sc->sc_flags |= SC_OP_SCANNING;
3057 spin_unlock_bh(&sc->ani_lock);
3058 mutex_unlock(&sc->mutex);
3061 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3063 struct ath_wiphy *aphy = hw->priv;
3064 struct ath_softc *sc = aphy->sc;
3066 mutex_lock(&sc->mutex);
3067 spin_lock_bh(&sc->ani_lock);
3068 aphy->state = ATH_WIPHY_ACTIVE;
3069 sc->sc_flags &= ~SC_OP_SCANNING;
3070 sc->sc_flags |= SC_OP_FULL_RESET;
3071 spin_unlock_bh(&sc->ani_lock);
3072 ath_beacon_config(sc, NULL);
3073 mutex_unlock(&sc->mutex);
3076 struct ieee80211_ops ath9k_ops = {
3078 .start = ath9k_start,
3080 .add_interface = ath9k_add_interface,
3081 .remove_interface = ath9k_remove_interface,
3082 .config = ath9k_config,
3083 .configure_filter = ath9k_configure_filter,
3084 .sta_notify = ath9k_sta_notify,
3085 .conf_tx = ath9k_conf_tx,
3086 .bss_info_changed = ath9k_bss_info_changed,
3087 .set_key = ath9k_set_key,
3088 .get_tsf = ath9k_get_tsf,
3089 .set_tsf = ath9k_set_tsf,
3090 .reset_tsf = ath9k_reset_tsf,
3091 .ampdu_action = ath9k_ampdu_action,
3092 .sw_scan_start = ath9k_sw_scan_start,
3093 .sw_scan_complete = ath9k_sw_scan_complete,
3094 .rfkill_poll = ath9k_rfkill_poll_state,
3100 } ath_mac_bb_names[] = {
3101 { AR_SREV_VERSION_5416_PCI, "5416" },
3102 { AR_SREV_VERSION_5416_PCIE, "5418" },
3103 { AR_SREV_VERSION_9100, "9100" },
3104 { AR_SREV_VERSION_9160, "9160" },
3105 { AR_SREV_VERSION_9280, "9280" },
3106 { AR_SREV_VERSION_9285, "9285" },
3107 { AR_SREV_VERSION_9287, "9287" }
3113 } ath_rf_names[] = {
3115 { AR_RAD5133_SREV_MAJOR, "5133" },
3116 { AR_RAD5122_SREV_MAJOR, "5122" },
3117 { AR_RAD2133_SREV_MAJOR, "2133" },
3118 { AR_RAD2122_SREV_MAJOR, "2122" }
3122 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3125 ath_mac_bb_name(u32 mac_bb_version)
3129 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3130 if (ath_mac_bb_names[i].version == mac_bb_version) {
3131 return ath_mac_bb_names[i].name;
3139 * Return the RF name. "????" is returned if the RF is unknown.
3142 ath_rf_name(u16 rf_version)
3146 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3147 if (ath_rf_names[i].version == rf_version) {
3148 return ath_rf_names[i].name;
3155 static int __init ath9k_init(void)
3159 /* Register rate control algorithm */
3160 error = ath_rate_control_register();
3163 "ath9k: Unable to register rate control "
3169 error = ath9k_debug_create_root();
3172 "ath9k: Unable to create debugfs root: %d\n",
3174 goto err_rate_unregister;
3177 error = ath_pci_init();
3180 "ath9k: No PCI devices found, driver not installed.\n");
3182 goto err_remove_root;
3185 error = ath_ahb_init();
3197 ath9k_debug_remove_root();
3198 err_rate_unregister:
3199 ath_rate_control_unregister();
3203 module_init(ath9k_init);
3205 static void __exit ath9k_exit(void)
3209 ath9k_debug_remove_root();
3210 ath_rate_control_unregister();
3211 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3213 module_exit(ath9k_exit);