]> nv-tegra.nvidia Code Review - linux-2.6.git/blob - drivers/net/wireless/ath/ath9k/main.c
ath9k: distinguish between device initialization and ath_softc init
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 static char *dev_info = "ath9k";
21
22 MODULE_AUTHOR("Atheros Communications");
23 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25 MODULE_LICENSE("Dual BSD/GPL");
26
27 static int modparam_nohwcrypt;
28 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31 /* We use the hw_value as an index into our private channel structure */
32
33 #define CHAN2G(_freq, _idx)  { \
34         .center_freq = (_freq), \
35         .hw_value = (_idx), \
36         .max_power = 20, \
37 }
38
39 #define CHAN5G(_freq, _idx) { \
40         .band = IEEE80211_BAND_5GHZ, \
41         .center_freq = (_freq), \
42         .hw_value = (_idx), \
43         .max_power = 20, \
44 }
45
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47  * on 5 MHz steps, we support the channels which we know
48  * we have calibration data for all cards though to make
49  * this static */
50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51         CHAN2G(2412, 0), /* Channel 1 */
52         CHAN2G(2417, 1), /* Channel 2 */
53         CHAN2G(2422, 2), /* Channel 3 */
54         CHAN2G(2427, 3), /* Channel 4 */
55         CHAN2G(2432, 4), /* Channel 5 */
56         CHAN2G(2437, 5), /* Channel 6 */
57         CHAN2G(2442, 6), /* Channel 7 */
58         CHAN2G(2447, 7), /* Channel 8 */
59         CHAN2G(2452, 8), /* Channel 9 */
60         CHAN2G(2457, 9), /* Channel 10 */
61         CHAN2G(2462, 10), /* Channel 11 */
62         CHAN2G(2467, 11), /* Channel 12 */
63         CHAN2G(2472, 12), /* Channel 13 */
64         CHAN2G(2484, 13), /* Channel 14 */
65 };
66
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68  * on 5 MHz steps, we support the channels which we know
69  * we have calibration data for all cards though to make
70  * this static */
71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72         /* _We_ call this UNII 1 */
73         CHAN5G(5180, 14), /* Channel 36 */
74         CHAN5G(5200, 15), /* Channel 40 */
75         CHAN5G(5220, 16), /* Channel 44 */
76         CHAN5G(5240, 17), /* Channel 48 */
77         /* _We_ call this UNII 2 */
78         CHAN5G(5260, 18), /* Channel 52 */
79         CHAN5G(5280, 19), /* Channel 56 */
80         CHAN5G(5300, 20), /* Channel 60 */
81         CHAN5G(5320, 21), /* Channel 64 */
82         /* _We_ call this "Middle band" */
83         CHAN5G(5500, 22), /* Channel 100 */
84         CHAN5G(5520, 23), /* Channel 104 */
85         CHAN5G(5540, 24), /* Channel 108 */
86         CHAN5G(5560, 25), /* Channel 112 */
87         CHAN5G(5580, 26), /* Channel 116 */
88         CHAN5G(5600, 27), /* Channel 120 */
89         CHAN5G(5620, 28), /* Channel 124 */
90         CHAN5G(5640, 29), /* Channel 128 */
91         CHAN5G(5660, 30), /* Channel 132 */
92         CHAN5G(5680, 31), /* Channel 136 */
93         CHAN5G(5700, 32), /* Channel 140 */
94         /* _We_ call this UNII 3 */
95         CHAN5G(5745, 33), /* Channel 149 */
96         CHAN5G(5765, 34), /* Channel 153 */
97         CHAN5G(5785, 35), /* Channel 157 */
98         CHAN5G(5805, 36), /* Channel 161 */
99         CHAN5G(5825, 37), /* Channel 165 */
100 };
101
102 static void ath_cache_conf_rate(struct ath_softc *sc,
103                                 struct ieee80211_conf *conf)
104 {
105         switch (conf->channel->band) {
106         case IEEE80211_BAND_2GHZ:
107                 if (conf_is_ht20(conf))
108                         sc->cur_rate_table =
109                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110                 else if (conf_is_ht40_minus(conf))
111                         sc->cur_rate_table =
112                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113                 else if (conf_is_ht40_plus(conf))
114                         sc->cur_rate_table =
115                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116                 else
117                         sc->cur_rate_table =
118                           sc->hw_rate_table[ATH9K_MODE_11G];
119                 break;
120         case IEEE80211_BAND_5GHZ:
121                 if (conf_is_ht20(conf))
122                         sc->cur_rate_table =
123                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124                 else if (conf_is_ht40_minus(conf))
125                         sc->cur_rate_table =
126                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127                 else if (conf_is_ht40_plus(conf))
128                         sc->cur_rate_table =
129                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130                 else
131                         sc->cur_rate_table =
132                           sc->hw_rate_table[ATH9K_MODE_11A];
133                 break;
134         default:
135                 BUG_ON(1);
136                 break;
137         }
138 }
139
140 static void ath_update_txpow(struct ath_softc *sc)
141 {
142         struct ath_hw *ah = sc->sc_ah;
143         u32 txpow;
144
145         if (sc->curtxpow != sc->config.txpowlimit) {
146                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
147                 /* read back in case value is clamped */
148                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149                 sc->curtxpow = txpow;
150         }
151 }
152
153 static u8 parse_mpdudensity(u8 mpdudensity)
154 {
155         /*
156          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157          *   0 for no restriction
158          *   1 for 1/4 us
159          *   2 for 1/2 us
160          *   3 for 1 us
161          *   4 for 2 us
162          *   5 for 4 us
163          *   6 for 8 us
164          *   7 for 16 us
165          */
166         switch (mpdudensity) {
167         case 0:
168                 return 0;
169         case 1:
170         case 2:
171         case 3:
172                 /* Our lower layer calculations limit our precision to
173                    1 microsecond */
174                 return 1;
175         case 4:
176                 return 2;
177         case 5:
178                 return 4;
179         case 6:
180                 return 8;
181         case 7:
182                 return 16;
183         default:
184                 return 0;
185         }
186 }
187
188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189 {
190         const struct ath_rate_table *rate_table = NULL;
191         struct ieee80211_supported_band *sband;
192         struct ieee80211_rate *rate;
193         int i, maxrates;
194
195         switch (band) {
196         case IEEE80211_BAND_2GHZ:
197                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198                 break;
199         case IEEE80211_BAND_5GHZ:
200                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201                 break;
202         default:
203                 break;
204         }
205
206         if (rate_table == NULL)
207                 return;
208
209         sband = &sc->sbands[band];
210         rate = sc->rates[band];
211
212         if (rate_table->rate_cnt > ATH_RATE_MAX)
213                 maxrates = ATH_RATE_MAX;
214         else
215                 maxrates = rate_table->rate_cnt;
216
217         for (i = 0; i < maxrates; i++) {
218                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219                 rate[i].hw_value = rate_table->info[i].ratecode;
220                 if (rate_table->info[i].short_preamble) {
221                         rate[i].hw_value_short = rate_table->info[i].ratecode |
222                                 rate_table->info[i].short_preamble;
223                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224                 }
225                 sband->n_bitrates++;
226
227                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228                         rate[i].bitrate / 10, rate[i].hw_value);
229         }
230 }
231
232 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233                                                 struct ieee80211_hw *hw)
234 {
235         struct ieee80211_channel *curchan = hw->conf.channel;
236         struct ath9k_channel *channel;
237         u8 chan_idx;
238
239         chan_idx = curchan->hw_value;
240         channel = &sc->sc_ah->channels[chan_idx];
241         ath9k_update_ichannel(sc, hw, channel);
242         return channel;
243 }
244
245 /*
246  * Set/change channels.  If the channel is really being changed, it's done
247  * by reseting the chip.  To accomplish this we must first cleanup any pending
248  * DMA, then restart stuff.
249 */
250 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251                     struct ath9k_channel *hchan)
252 {
253         struct ath_hw *ah = sc->sc_ah;
254         bool fastcc = true, stopped;
255         struct ieee80211_channel *channel = hw->conf.channel;
256         int r;
257
258         if (sc->sc_flags & SC_OP_INVALID)
259                 return -EIO;
260
261         ath9k_ps_wakeup(sc);
262
263         /*
264          * This is only performed if the channel settings have
265          * actually changed.
266          *
267          * To switch channels clear any pending DMA operations;
268          * wait long enough for the RX fifo to drain, reset the
269          * hardware at the new frequency, and then re-enable
270          * the relevant bits of the h/w.
271          */
272         ath9k_hw_set_interrupts(ah, 0);
273         ath_drain_all_txq(sc, false);
274         stopped = ath_stoprecv(sc);
275
276         /* XXX: do not flush receive queue here. We don't want
277          * to flush data frames already in queue because of
278          * changing channel. */
279
280         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281                 fastcc = false;
282
283         DPRINTF(sc, ATH_DBG_CONFIG,
284                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
285                 sc->sc_ah->curchan->channel,
286                 channel->center_freq, sc->tx_chan_width);
287
288         spin_lock_bh(&sc->sc_resetlock);
289
290         r = ath9k_hw_reset(ah, hchan, fastcc);
291         if (r) {
292                 DPRINTF(sc, ATH_DBG_FATAL,
293                         "Unable to reset channel (%u Mhz) "
294                         "reset status %d\n",
295                         channel->center_freq, r);
296                 spin_unlock_bh(&sc->sc_resetlock);
297                 goto ps_restore;
298         }
299         spin_unlock_bh(&sc->sc_resetlock);
300
301         sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303         if (ath_startrecv(sc) != 0) {
304                 DPRINTF(sc, ATH_DBG_FATAL,
305                         "Unable to restart recv logic\n");
306                 r = -EIO;
307                 goto ps_restore;
308         }
309
310         ath_cache_conf_rate(sc, &hw->conf);
311         ath_update_txpow(sc);
312         ath9k_hw_set_interrupts(ah, sc->imask);
313
314  ps_restore:
315         ath9k_ps_restore(sc);
316         return r;
317 }
318
319 /*
320  *  This routine performs the periodic noise floor calibration function
321  *  that is used to adjust and optimize the chip performance.  This
322  *  takes environmental changes (location, temperature) into account.
323  *  When the task is complete, it reschedules itself depending on the
324  *  appropriate interval that was calculated.
325  */
326 static void ath_ani_calibrate(unsigned long data)
327 {
328         struct ath_softc *sc = (struct ath_softc *)data;
329         struct ath_hw *ah = sc->sc_ah;
330         bool longcal = false;
331         bool shortcal = false;
332         bool aniflag = false;
333         unsigned int timestamp = jiffies_to_msecs(jiffies);
334         u32 cal_interval, short_cal_interval;
335
336         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
338
339         /*
340         * don't calibrate when we're scanning.
341         * we are most likely not on our home channel.
342         */
343         spin_lock(&sc->ani_lock);
344         if (sc->sc_flags & SC_OP_SCANNING)
345                 goto set_timer;
346
347         /* Only calibrate if awake */
348         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349                 goto set_timer;
350
351         ath9k_ps_wakeup(sc);
352
353         /* Long calibration runs independently of short calibration. */
354         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355                 longcal = true;
356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357                 sc->ani.longcal_timer = timestamp;
358         }
359
360         /* Short calibration applies only while caldone is false */
361         if (!sc->ani.caldone) {
362                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
363                         shortcal = true;
364                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
365                         sc->ani.shortcal_timer = timestamp;
366                         sc->ani.resetcal_timer = timestamp;
367                 }
368         } else {
369                 if ((timestamp - sc->ani.resetcal_timer) >=
370                     ATH_RESTART_CALINTERVAL) {
371                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372                         if (sc->ani.caldone)
373                                 sc->ani.resetcal_timer = timestamp;
374                 }
375         }
376
377         /* Verify whether we must check ANI */
378         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
379                 aniflag = true;
380                 sc->ani.checkani_timer = timestamp;
381         }
382
383         /* Skip all processing if there's nothing to do. */
384         if (longcal || shortcal || aniflag) {
385                 /* Call ANI routine if necessary */
386                 if (aniflag)
387                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
388
389                 /* Perform calibration if necessary */
390                 if (longcal || shortcal) {
391                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392                                                      sc->rx_chainmask, longcal);
393
394                         if (longcal)
395                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396                                                                      ah->curchan);
397
398                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399                                 ah->curchan->channel, ah->curchan->channelFlags,
400                                 sc->ani.noise_floor);
401                 }
402         }
403
404         ath9k_ps_restore(sc);
405
406 set_timer:
407         spin_unlock(&sc->ani_lock);
408         /*
409         * Set timer interval based on previous results.
410         * The interval must be the shortest necessary to satisfy ANI,
411         * short calibration and long calibration.
412         */
413         cal_interval = ATH_LONG_CALINTERVAL;
414         if (sc->sc_ah->config.enable_ani)
415                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416         if (!sc->ani.caldone)
417                 cal_interval = min(cal_interval, (u32)short_cal_interval);
418
419         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
420 }
421
422 static void ath_start_ani(struct ath_softc *sc)
423 {
424         unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426         sc->ani.longcal_timer = timestamp;
427         sc->ani.shortcal_timer = timestamp;
428         sc->ani.checkani_timer = timestamp;
429
430         mod_timer(&sc->ani.timer,
431                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432 }
433
434 /*
435  * Update tx/rx chainmask. For legacy association,
436  * hard code chainmask to 1x1, for 11n association, use
437  * the chainmask configuration, for bt coexistence, use
438  * the chainmask configuration even in legacy mode.
439  */
440 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
441 {
442         if (is_ht ||
443             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
446         } else {
447                 sc->tx_chainmask = 1;
448                 sc->rx_chainmask = 1;
449         }
450
451         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
452                 sc->tx_chainmask, sc->rx_chainmask);
453 }
454
455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456 {
457         struct ath_node *an;
458
459         an = (struct ath_node *)sta->drv_priv;
460
461         if (sc->sc_flags & SC_OP_TXAGGR) {
462                 ath_tx_node_init(sc, an);
463                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
464                                      sta->ht_cap.ampdu_factor);
465                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
467         }
468 }
469
470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471 {
472         struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474         if (sc->sc_flags & SC_OP_TXAGGR)
475                 ath_tx_node_cleanup(sc, an);
476 }
477
478 static void ath9k_tasklet(unsigned long data)
479 {
480         struct ath_softc *sc = (struct ath_softc *)data;
481         u32 status = sc->intrstatus;
482
483         ath9k_ps_wakeup(sc);
484
485         if (status & ATH9K_INT_FATAL) {
486                 ath_reset(sc, false);
487                 ath9k_ps_restore(sc);
488                 return;
489         }
490
491         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492                 spin_lock_bh(&sc->rx.rxflushlock);
493                 ath_rx_tasklet(sc, 0);
494                 spin_unlock_bh(&sc->rx.rxflushlock);
495         }
496
497         if (status & ATH9K_INT_TX)
498                 ath_tx_tasklet(sc);
499
500         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
501                 /*
502                  * TSF sync does not look correct; remain awake to sync with
503                  * the next Beacon.
504                  */
505                 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
506                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
507         }
508
509         /* re-enable hardware interrupt */
510         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
511         ath9k_ps_restore(sc);
512 }
513
514 irqreturn_t ath_isr(int irq, void *dev)
515 {
516 #define SCHED_INTR (                            \
517                 ATH9K_INT_FATAL |               \
518                 ATH9K_INT_RXORN |               \
519                 ATH9K_INT_RXEOL |               \
520                 ATH9K_INT_RX |                  \
521                 ATH9K_INT_TX |                  \
522                 ATH9K_INT_BMISS |               \
523                 ATH9K_INT_CST |                 \
524                 ATH9K_INT_TSFOOR)
525
526         struct ath_softc *sc = dev;
527         struct ath_hw *ah = sc->sc_ah;
528         enum ath9k_int status;
529         bool sched = false;
530
531         /*
532          * The hardware is not ready/present, don't
533          * touch anything. Note this can happen early
534          * on if the IRQ is shared.
535          */
536         if (sc->sc_flags & SC_OP_INVALID)
537                 return IRQ_NONE;
538
539
540         /* shared irq, not for us */
541
542         if (!ath9k_hw_intrpend(ah))
543                 return IRQ_NONE;
544
545         /*
546          * Figure out the reason(s) for the interrupt.  Note
547          * that the hal returns a pseudo-ISR that may include
548          * bits we haven't explicitly enabled so we mask the
549          * value to insure we only process bits we requested.
550          */
551         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
552         status &= sc->imask;    /* discard unasked-for bits */
553
554         /*
555          * If there are no status bits set, then this interrupt was not
556          * for me (should have been caught above).
557          */
558         if (!status)
559                 return IRQ_NONE;
560
561         /* Cache the status */
562         sc->intrstatus = status;
563
564         if (status & SCHED_INTR)
565                 sched = true;
566
567         /*
568          * If a FATAL or RXORN interrupt is received, we have to reset the
569          * chip immediately.
570          */
571         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572                 goto chip_reset;
573
574         if (status & ATH9K_INT_SWBA)
575                 tasklet_schedule(&sc->bcon_tasklet);
576
577         if (status & ATH9K_INT_TXURN)
578                 ath9k_hw_updatetxtriglevel(ah, true);
579
580         if (status & ATH9K_INT_MIB) {
581                 /*
582                  * Disable interrupts until we service the MIB
583                  * interrupt; otherwise it will continue to
584                  * fire.
585                  */
586                 ath9k_hw_set_interrupts(ah, 0);
587                 /*
588                  * Let the hal handle the event. We assume
589                  * it will clear whatever condition caused
590                  * the interrupt.
591                  */
592                 ath9k_hw_procmibevent(ah, &sc->nodestats);
593                 ath9k_hw_set_interrupts(ah, sc->imask);
594         }
595
596         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597                 if (status & ATH9K_INT_TIM_TIMER) {
598                         /* Clear RxAbort bit so that we can
599                          * receive frames */
600                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
601                         ath9k_hw_setrxabort(sc->sc_ah, 0);
602                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
603                 }
604
605 chip_reset:
606
607         ath_debug_stat_interrupt(sc, status);
608
609         if (sched) {
610                 /* turn off every interrupt except SWBA */
611                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
612                 tasklet_schedule(&sc->intr_tq);
613         }
614
615         return IRQ_HANDLED;
616
617 #undef SCHED_INTR
618 }
619
620 static u32 ath_get_extchanmode(struct ath_softc *sc,
621                                struct ieee80211_channel *chan,
622                                enum nl80211_channel_type channel_type)
623 {
624         u32 chanmode = 0;
625
626         switch (chan->band) {
627         case IEEE80211_BAND_2GHZ:
628                 switch(channel_type) {
629                 case NL80211_CHAN_NO_HT:
630                 case NL80211_CHAN_HT20:
631                         chanmode = CHANNEL_G_HT20;
632                         break;
633                 case NL80211_CHAN_HT40PLUS:
634                         chanmode = CHANNEL_G_HT40PLUS;
635                         break;
636                 case NL80211_CHAN_HT40MINUS:
637                         chanmode = CHANNEL_G_HT40MINUS;
638                         break;
639                 }
640                 break;
641         case IEEE80211_BAND_5GHZ:
642                 switch(channel_type) {
643                 case NL80211_CHAN_NO_HT:
644                 case NL80211_CHAN_HT20:
645                         chanmode = CHANNEL_A_HT20;
646                         break;
647                 case NL80211_CHAN_HT40PLUS:
648                         chanmode = CHANNEL_A_HT40PLUS;
649                         break;
650                 case NL80211_CHAN_HT40MINUS:
651                         chanmode = CHANNEL_A_HT40MINUS;
652                         break;
653                 }
654                 break;
655         default:
656                 break;
657         }
658
659         return chanmode;
660 }
661
662 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
663                            struct ath9k_keyval *hk, const u8 *addr,
664                            bool authenticator)
665 {
666         const u8 *key_rxmic;
667         const u8 *key_txmic;
668
669         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
671
672         if (addr == NULL) {
673                 /*
674                  * Group key installation - only two key cache entries are used
675                  * regardless of splitmic capability since group key is only
676                  * used either for TX or RX.
677                  */
678                 if (authenticator) {
679                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681                 } else {
682                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684                 }
685                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
686         }
687         if (!sc->splitmic) {
688                 /* TX and RX keys share the same key cache entry. */
689                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
691                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
692         }
693
694         /* Separate key cache entries for TX and RX */
695
696         /* TX key goes at first index, RX key at +32. */
697         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
698         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699                 /* TX MIC entry failed. No need to proceed further */
700                 DPRINTF(sc, ATH_DBG_FATAL,
701                         "Setting TX MIC Key Failed\n");
702                 return 0;
703         }
704
705         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706         /* XXX delete tx key on failure? */
707         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
708 }
709
710 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711 {
712         int i;
713
714         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715                 if (test_bit(i, sc->keymap) ||
716                     test_bit(i + 64, sc->keymap))
717                         continue; /* At least one part of TKIP key allocated */
718                 if (sc->splitmic &&
719                     (test_bit(i + 32, sc->keymap) ||
720                      test_bit(i + 64 + 32, sc->keymap)))
721                         continue; /* At least one part of TKIP key allocated */
722
723                 /* Found a free slot for a TKIP key */
724                 return i;
725         }
726         return -1;
727 }
728
729 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730 {
731         int i;
732
733         /* First, try to find slots that would not be available for TKIP. */
734         if (sc->splitmic) {
735                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736                         if (!test_bit(i, sc->keymap) &&
737                             (test_bit(i + 32, sc->keymap) ||
738                              test_bit(i + 64, sc->keymap) ||
739                              test_bit(i + 64 + 32, sc->keymap)))
740                                 return i;
741                         if (!test_bit(i + 32, sc->keymap) &&
742                             (test_bit(i, sc->keymap) ||
743                              test_bit(i + 64, sc->keymap) ||
744                              test_bit(i + 64 + 32, sc->keymap)))
745                                 return i + 32;
746                         if (!test_bit(i + 64, sc->keymap) &&
747                             (test_bit(i , sc->keymap) ||
748                              test_bit(i + 32, sc->keymap) ||
749                              test_bit(i + 64 + 32, sc->keymap)))
750                                 return i + 64;
751                         if (!test_bit(i + 64 + 32, sc->keymap) &&
752                             (test_bit(i, sc->keymap) ||
753                              test_bit(i + 32, sc->keymap) ||
754                              test_bit(i + 64, sc->keymap)))
755                                 return i + 64 + 32;
756                 }
757         } else {
758                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759                         if (!test_bit(i, sc->keymap) &&
760                             test_bit(i + 64, sc->keymap))
761                                 return i;
762                         if (test_bit(i, sc->keymap) &&
763                             !test_bit(i + 64, sc->keymap))
764                                 return i + 64;
765                 }
766         }
767
768         /* No partially used TKIP slots, pick any available slot */
769         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
770                 /* Do not allow slots that could be needed for TKIP group keys
771                  * to be used. This limitation could be removed if we know that
772                  * TKIP will not be used. */
773                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774                         continue;
775                 if (sc->splitmic) {
776                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777                                 continue;
778                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779                                 continue;
780                 }
781
782                 if (!test_bit(i, sc->keymap))
783                         return i; /* Found a free slot for a key */
784         }
785
786         /* No free slot found */
787         return -1;
788 }
789
790 static int ath_key_config(struct ath_softc *sc,
791                           struct ieee80211_vif *vif,
792                           struct ieee80211_sta *sta,
793                           struct ieee80211_key_conf *key)
794 {
795         struct ath9k_keyval hk;
796         const u8 *mac = NULL;
797         int ret = 0;
798         int idx;
799
800         memset(&hk, 0, sizeof(hk));
801
802         switch (key->alg) {
803         case ALG_WEP:
804                 hk.kv_type = ATH9K_CIPHER_WEP;
805                 break;
806         case ALG_TKIP:
807                 hk.kv_type = ATH9K_CIPHER_TKIP;
808                 break;
809         case ALG_CCMP:
810                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811                 break;
812         default:
813                 return -EOPNOTSUPP;
814         }
815
816         hk.kv_len = key->keylen;
817         memcpy(hk.kv_val, key->key, key->keylen);
818
819         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820                 /* For now, use the default keys for broadcast keys. This may
821                  * need to change with virtual interfaces. */
822                 idx = key->keyidx;
823         } else if (key->keyidx) {
824                 if (WARN_ON(!sta))
825                         return -EOPNOTSUPP;
826                 mac = sta->addr;
827
828                 if (vif->type != NL80211_IFTYPE_AP) {
829                         /* Only keyidx 0 should be used with unicast key, but
830                          * allow this for client mode for now. */
831                         idx = key->keyidx;
832                 } else
833                         return -EIO;
834         } else {
835                 if (WARN_ON(!sta))
836                         return -EOPNOTSUPP;
837                 mac = sta->addr;
838
839                 if (key->alg == ALG_TKIP)
840                         idx = ath_reserve_key_cache_slot_tkip(sc);
841                 else
842                         idx = ath_reserve_key_cache_slot(sc);
843                 if (idx < 0)
844                         return -ENOSPC; /* no free key cache entries */
845         }
846
847         if (key->alg == ALG_TKIP)
848                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849                                       vif->type == NL80211_IFTYPE_AP);
850         else
851                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
852
853         if (!ret)
854                 return -EIO;
855
856         set_bit(idx, sc->keymap);
857         if (key->alg == ALG_TKIP) {
858                 set_bit(idx + 64, sc->keymap);
859                 if (sc->splitmic) {
860                         set_bit(idx + 32, sc->keymap);
861                         set_bit(idx + 64 + 32, sc->keymap);
862                 }
863         }
864
865         return idx;
866 }
867
868 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869 {
870         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871         if (key->hw_key_idx < IEEE80211_WEP_NKID)
872                 return;
873
874         clear_bit(key->hw_key_idx, sc->keymap);
875         if (key->alg != ALG_TKIP)
876                 return;
877
878         clear_bit(key->hw_key_idx + 64, sc->keymap);
879         if (sc->splitmic) {
880                 clear_bit(key->hw_key_idx + 32, sc->keymap);
881                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
882         }
883 }
884
885 static void setup_ht_cap(struct ath_softc *sc,
886                          struct ieee80211_sta_ht_cap *ht_info)
887 {
888         u8 tx_streams, rx_streams;
889
890         ht_info->ht_supported = true;
891         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
892                        IEEE80211_HT_CAP_SM_PS |
893                        IEEE80211_HT_CAP_SGI_40 |
894                        IEEE80211_HT_CAP_DSSSCCK40;
895
896         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
897         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
898
899         /* set up supported mcs set */
900         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
901         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
902         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
903
904         if (tx_streams != rx_streams) {
905                 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
906                         tx_streams, rx_streams);
907                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
908                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
909                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
910         }
911
912         ht_info->mcs.rx_mask[0] = 0xff;
913         if (rx_streams >= 2)
914                 ht_info->mcs.rx_mask[1] = 0xff;
915
916         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
917 }
918
919 static void ath9k_bss_assoc_info(struct ath_softc *sc,
920                                  struct ieee80211_vif *vif,
921                                  struct ieee80211_bss_conf *bss_conf)
922 {
923
924         if (bss_conf->assoc) {
925                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
926                         bss_conf->aid, sc->curbssid);
927
928                 /* New association, store aid */
929                 sc->curaid = bss_conf->aid;
930                 ath9k_hw_write_associd(sc);
931
932                 /*
933                  * Request a re-configuration of Beacon related timers
934                  * on the receipt of the first Beacon frame (i.e.,
935                  * after time sync with the AP).
936                  */
937                 sc->sc_flags |= SC_OP_BEACON_SYNC;
938
939                 /* Configure the beacon */
940                 ath_beacon_config(sc, vif);
941
942                 /* Reset rssi stats */
943                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
947
948                 ath_start_ani(sc);
949         } else {
950                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
951                 sc->curaid = 0;
952                 /* Stop ANI */
953                 del_timer_sync(&sc->ani.timer);
954         }
955 }
956
957 /********************************/
958 /*       LED functions          */
959 /********************************/
960
961 static void ath_led_blink_work(struct work_struct *work)
962 {
963         struct ath_softc *sc = container_of(work, struct ath_softc,
964                                             ath_led_blink_work.work);
965
966         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967                 return;
968
969         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
970             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
971                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
972         else
973                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
974                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
975
976         ieee80211_queue_delayed_work(sc->hw,
977                                      &sc->ath_led_blink_work,
978                                      (sc->sc_flags & SC_OP_LED_ON) ?
979                                         msecs_to_jiffies(sc->led_off_duration) :
980                                         msecs_to_jiffies(sc->led_on_duration));
981
982         sc->led_on_duration = sc->led_on_cnt ?
983                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
984                         ATH_LED_ON_DURATION_IDLE;
985         sc->led_off_duration = sc->led_off_cnt ?
986                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
987                         ATH_LED_OFF_DURATION_IDLE;
988         sc->led_on_cnt = sc->led_off_cnt = 0;
989         if (sc->sc_flags & SC_OP_LED_ON)
990                 sc->sc_flags &= ~SC_OP_LED_ON;
991         else
992                 sc->sc_flags |= SC_OP_LED_ON;
993 }
994
995 static void ath_led_brightness(struct led_classdev *led_cdev,
996                                enum led_brightness brightness)
997 {
998         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
999         struct ath_softc *sc = led->sc;
1000
1001         switch (brightness) {
1002         case LED_OFF:
1003                 if (led->led_type == ATH_LED_ASSOC ||
1004                     led->led_type == ATH_LED_RADIO) {
1005                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1006                                 (led->led_type == ATH_LED_RADIO));
1007                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1008                         if (led->led_type == ATH_LED_RADIO)
1009                                 sc->sc_flags &= ~SC_OP_LED_ON;
1010                 } else {
1011                         sc->led_off_cnt++;
1012                 }
1013                 break;
1014         case LED_FULL:
1015                 if (led->led_type == ATH_LED_ASSOC) {
1016                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1017                         ieee80211_queue_delayed_work(sc->hw,
1018                                                      &sc->ath_led_blink_work, 0);
1019                 } else if (led->led_type == ATH_LED_RADIO) {
1020                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1021                         sc->sc_flags |= SC_OP_LED_ON;
1022                 } else {
1023                         sc->led_on_cnt++;
1024                 }
1025                 break;
1026         default:
1027                 break;
1028         }
1029 }
1030
1031 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1032                             char *trigger)
1033 {
1034         int ret;
1035
1036         led->sc = sc;
1037         led->led_cdev.name = led->name;
1038         led->led_cdev.default_trigger = trigger;
1039         led->led_cdev.brightness_set = ath_led_brightness;
1040
1041         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1042         if (ret)
1043                 DPRINTF(sc, ATH_DBG_FATAL,
1044                         "Failed to register led:%s", led->name);
1045         else
1046                 led->registered = 1;
1047         return ret;
1048 }
1049
1050 static void ath_unregister_led(struct ath_led *led)
1051 {
1052         if (led->registered) {
1053                 led_classdev_unregister(&led->led_cdev);
1054                 led->registered = 0;
1055         }
1056 }
1057
1058 static void ath_deinit_leds(struct ath_softc *sc)
1059 {
1060         ath_unregister_led(&sc->assoc_led);
1061         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062         ath_unregister_led(&sc->tx_led);
1063         ath_unregister_led(&sc->rx_led);
1064         ath_unregister_led(&sc->radio_led);
1065         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1066 }
1067
1068 static void ath_init_leds(struct ath_softc *sc)
1069 {
1070         char *trigger;
1071         int ret;
1072
1073         /* Configure gpio 1 for output */
1074         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1075                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1076         /* LED off, active low */
1077         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1078
1079         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1080
1081         trigger = ieee80211_get_radio_led_name(sc->hw);
1082         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1083                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1084         ret = ath_register_led(sc, &sc->radio_led, trigger);
1085         sc->radio_led.led_type = ATH_LED_RADIO;
1086         if (ret)
1087                 goto fail;
1088
1089         trigger = ieee80211_get_assoc_led_name(sc->hw);
1090         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1091                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1092         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1093         sc->assoc_led.led_type = ATH_LED_ASSOC;
1094         if (ret)
1095                 goto fail;
1096
1097         trigger = ieee80211_get_tx_led_name(sc->hw);
1098         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1099                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1100         ret = ath_register_led(sc, &sc->tx_led, trigger);
1101         sc->tx_led.led_type = ATH_LED_TX;
1102         if (ret)
1103                 goto fail;
1104
1105         trigger = ieee80211_get_rx_led_name(sc->hw);
1106         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1107                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1108         ret = ath_register_led(sc, &sc->rx_led, trigger);
1109         sc->rx_led.led_type = ATH_LED_RX;
1110         if (ret)
1111                 goto fail;
1112
1113         return;
1114
1115 fail:
1116         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1117         ath_deinit_leds(sc);
1118 }
1119
1120 void ath_radio_enable(struct ath_softc *sc)
1121 {
1122         struct ath_hw *ah = sc->sc_ah;
1123         struct ieee80211_channel *channel = sc->hw->conf.channel;
1124         int r;
1125
1126         ath9k_ps_wakeup(sc);
1127         ath9k_hw_configpcipowersave(ah, 0);
1128
1129         if (!ah->curchan)
1130                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1131
1132         spin_lock_bh(&sc->sc_resetlock);
1133         r = ath9k_hw_reset(ah, ah->curchan, false);
1134         if (r) {
1135                 DPRINTF(sc, ATH_DBG_FATAL,
1136                         "Unable to reset channel %u (%uMhz) ",
1137                         "reset status %d\n",
1138                         channel->center_freq, r);
1139         }
1140         spin_unlock_bh(&sc->sc_resetlock);
1141
1142         ath_update_txpow(sc);
1143         if (ath_startrecv(sc) != 0) {
1144                 DPRINTF(sc, ATH_DBG_FATAL,
1145                         "Unable to restart recv logic\n");
1146                 return;
1147         }
1148
1149         if (sc->sc_flags & SC_OP_BEACONS)
1150                 ath_beacon_config(sc, NULL);    /* restart beacons */
1151
1152         /* Re-Enable  interrupts */
1153         ath9k_hw_set_interrupts(ah, sc->imask);
1154
1155         /* Enable LED */
1156         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1157                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1158         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1159
1160         ieee80211_wake_queues(sc->hw);
1161         ath9k_ps_restore(sc);
1162 }
1163
1164 void ath_radio_disable(struct ath_softc *sc)
1165 {
1166         struct ath_hw *ah = sc->sc_ah;
1167         struct ieee80211_channel *channel = sc->hw->conf.channel;
1168         int r;
1169
1170         ath9k_ps_wakeup(sc);
1171         ieee80211_stop_queues(sc->hw);
1172
1173         /* Disable LED */
1174         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1175         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1176
1177         /* Disable interrupts */
1178         ath9k_hw_set_interrupts(ah, 0);
1179
1180         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1181         ath_stoprecv(sc);               /* turn off frame recv */
1182         ath_flushrecv(sc);              /* flush recv queue */
1183
1184         if (!ah->curchan)
1185                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1186
1187         spin_lock_bh(&sc->sc_resetlock);
1188         r = ath9k_hw_reset(ah, ah->curchan, false);
1189         if (r) {
1190                 DPRINTF(sc, ATH_DBG_FATAL,
1191                         "Unable to reset channel %u (%uMhz) "
1192                         "reset status %d\n",
1193                         channel->center_freq, r);
1194         }
1195         spin_unlock_bh(&sc->sc_resetlock);
1196
1197         ath9k_hw_phy_disable(ah);
1198         ath9k_hw_configpcipowersave(ah, 1);
1199         ath9k_ps_restore(sc);
1200         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1201 }
1202
1203 /*******************/
1204 /*      Rfkill     */
1205 /*******************/
1206
1207 static bool ath_is_rfkill_set(struct ath_softc *sc)
1208 {
1209         struct ath_hw *ah = sc->sc_ah;
1210
1211         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1212                                   ah->rfkill_polarity;
1213 }
1214
1215 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1216 {
1217         struct ath_wiphy *aphy = hw->priv;
1218         struct ath_softc *sc = aphy->sc;
1219         bool blocked = !!ath_is_rfkill_set(sc);
1220
1221         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1222
1223         if (blocked)
1224                 ath_radio_disable(sc);
1225         else
1226                 ath_radio_enable(sc);
1227 }
1228
1229 static void ath_start_rfkill_poll(struct ath_softc *sc)
1230 {
1231         struct ath_hw *ah = sc->sc_ah;
1232
1233         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1234                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1235 }
1236
1237 void ath_cleanup(struct ath_softc *sc)
1238 {
1239         ath_detach(sc);
1240         free_irq(sc->irq, sc);
1241         ath_bus_cleanup(sc);
1242         kfree(sc->sec_wiphy);
1243         ieee80211_free_hw(sc->hw);
1244 }
1245
1246 void ath_detach(struct ath_softc *sc)
1247 {
1248         struct ieee80211_hw *hw = sc->hw;
1249         int i = 0;
1250
1251         ath9k_ps_wakeup(sc);
1252
1253         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1254
1255         ath_deinit_leds(sc);
1256
1257         for (i = 0; i < sc->num_sec_wiphy; i++) {
1258                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1259                 if (aphy == NULL)
1260                         continue;
1261                 sc->sec_wiphy[i] = NULL;
1262                 ieee80211_unregister_hw(aphy->hw);
1263                 ieee80211_free_hw(aphy->hw);
1264         }
1265         ieee80211_unregister_hw(hw);
1266         ath_rx_cleanup(sc);
1267         ath_tx_cleanup(sc);
1268
1269         tasklet_kill(&sc->intr_tq);
1270         tasklet_kill(&sc->bcon_tasklet);
1271
1272         if (!(sc->sc_flags & SC_OP_INVALID))
1273                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1274
1275         /* cleanup tx queues */
1276         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1277                 if (ATH_TXQ_SETUP(sc, i))
1278                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1279
1280         ath9k_hw_detach(sc->sc_ah);
1281         ath9k_exit_debug(sc);
1282 }
1283
1284 static int ath9k_reg_notifier(struct wiphy *wiphy,
1285                               struct regulatory_request *request)
1286 {
1287         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1288         struct ath_wiphy *aphy = hw->priv;
1289         struct ath_softc *sc = aphy->sc;
1290         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1291
1292         return ath_reg_notifier_apply(wiphy, request, reg);
1293 }
1294
1295 /*
1296  * Initialize and fill ath_softc, ath_sofct is the
1297  * "Software Carrier" struct. Historically it has existed
1298  * to allow the separation between hardware specific
1299  * variables (now in ath_hw) and driver specific variables.
1300  */
1301 static int ath_init_softc(u16 devid, struct ath_softc *sc)
1302 {
1303         struct ath_hw *ah = NULL;
1304         int r = 0, i;
1305         int csz = 0;
1306
1307         /* XXX: hardware will not be ready until ath_open() being called */
1308         sc->sc_flags |= SC_OP_INVALID;
1309
1310         if (ath9k_init_debug(sc) < 0)
1311                 printk(KERN_ERR "Unable to create debugfs files\n");
1312
1313         spin_lock_init(&sc->wiphy_lock);
1314         spin_lock_init(&sc->sc_resetlock);
1315         spin_lock_init(&sc->sc_serial_rw);
1316         spin_lock_init(&sc->ani_lock);
1317         spin_lock_init(&sc->sc_pm_lock);
1318         mutex_init(&sc->mutex);
1319         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1320         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1321                      (unsigned long)sc);
1322
1323         /*
1324          * Cache line size is used to size and align various
1325          * structures used to communicate with the hardware.
1326          */
1327         ath_read_cachesize(sc, &csz);
1328         /* XXX assert csz is non-zero */
1329         sc->cachelsz = csz << 2;        /* convert to bytes */
1330
1331         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1332         if (!ah) {
1333                 r = -ENOMEM;
1334                 goto bad_no_ah;
1335         }
1336
1337         ah->ah_sc = sc;
1338         ah->hw_version.devid = devid;
1339         sc->sc_ah = ah;
1340
1341         r = ath9k_hw_init(ah);
1342         if (r) {
1343                 DPRINTF(sc, ATH_DBG_FATAL,
1344                         "Unable to initialize hardware; "
1345                         "initialization status: %d\n", r);
1346                 goto bad;
1347         }
1348
1349         /* Get the hardware key cache size. */
1350         sc->keymax = ah->caps.keycache_size;
1351         if (sc->keymax > ATH_KEYMAX) {
1352                 DPRINTF(sc, ATH_DBG_ANY,
1353                         "Warning, using only %u entries in %u key cache\n",
1354                         ATH_KEYMAX, sc->keymax);
1355                 sc->keymax = ATH_KEYMAX;
1356         }
1357
1358         /*
1359          * Reset the key cache since some parts do not
1360          * reset the contents on initial power up.
1361          */
1362         for (i = 0; i < sc->keymax; i++)
1363                 ath9k_hw_keyreset(ah, (u16) i);
1364
1365         if (r)
1366                 goto bad;
1367
1368         /* default to MONITOR mode */
1369         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1370
1371         /* Setup rate tables */
1372
1373         ath_rate_attach(sc);
1374         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1375         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1376
1377         /*
1378          * Allocate hardware transmit queues: one queue for
1379          * beacon frames and one data queue for each QoS
1380          * priority.  Note that the hal handles reseting
1381          * these queues at the needed time.
1382          */
1383         sc->beacon.beaconq = ath_beaconq_setup(ah);
1384         if (sc->beacon.beaconq == -1) {
1385                 DPRINTF(sc, ATH_DBG_FATAL,
1386                         "Unable to setup a beacon xmit queue\n");
1387                 r = -EIO;
1388                 goto bad2;
1389         }
1390         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1391         if (sc->beacon.cabq == NULL) {
1392                 DPRINTF(sc, ATH_DBG_FATAL,
1393                         "Unable to setup CAB xmit queue\n");
1394                 r = -EIO;
1395                 goto bad2;
1396         }
1397
1398         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1399         ath_cabq_update(sc);
1400
1401         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1402                 sc->tx.hwq_map[i] = -1;
1403
1404         /* Setup data queues */
1405         /* NB: ensure BK queue is the lowest priority h/w queue */
1406         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1407                 DPRINTF(sc, ATH_DBG_FATAL,
1408                         "Unable to setup xmit queue for BK traffic\n");
1409                 r = -EIO;
1410                 goto bad2;
1411         }
1412
1413         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1414                 DPRINTF(sc, ATH_DBG_FATAL,
1415                         "Unable to setup xmit queue for BE traffic\n");
1416                 r = -EIO;
1417                 goto bad2;
1418         }
1419         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1420                 DPRINTF(sc, ATH_DBG_FATAL,
1421                         "Unable to setup xmit queue for VI traffic\n");
1422                 r = -EIO;
1423                 goto bad2;
1424         }
1425         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1426                 DPRINTF(sc, ATH_DBG_FATAL,
1427                         "Unable to setup xmit queue for VO traffic\n");
1428                 r = -EIO;
1429                 goto bad2;
1430         }
1431
1432         /* Initializes the noise floor to a reasonable default value.
1433          * Later on this will be updated during ANI processing. */
1434
1435         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1436         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1437
1438         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1439                                    ATH9K_CIPHER_TKIP, NULL)) {
1440                 /*
1441                  * Whether we should enable h/w TKIP MIC.
1442                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1443                  * report WMM capable, so it's always safe to turn on
1444                  * TKIP MIC in this case.
1445                  */
1446                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1447                                        0, 1, NULL);
1448         }
1449
1450         /*
1451          * Check whether the separate key cache entries
1452          * are required to handle both tx+rx MIC keys.
1453          * With split mic keys the number of stations is limited
1454          * to 27 otherwise 59.
1455          */
1456         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457                                    ATH9K_CIPHER_TKIP, NULL)
1458             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1459                                       ATH9K_CIPHER_MIC, NULL)
1460             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1461                                       0, NULL))
1462                 sc->splitmic = 1;
1463
1464         /* turn on mcast key search if possible */
1465         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1466                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1467                                              1, NULL);
1468
1469         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1470
1471         /* 11n Capabilities */
1472         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1473                 sc->sc_flags |= SC_OP_TXAGGR;
1474                 sc->sc_flags |= SC_OP_RXAGGR;
1475         }
1476
1477         sc->tx_chainmask = ah->caps.tx_chainmask;
1478         sc->rx_chainmask = ah->caps.rx_chainmask;
1479
1480         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1481         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1482
1483         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1484                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1485
1486         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1487
1488         /* initialize beacon slots */
1489         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1490                 sc->beacon.bslot[i] = NULL;
1491                 sc->beacon.bslot_aphy[i] = NULL;
1492         }
1493
1494         /* setup channels and rates */
1495
1496         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1497         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1498                 sc->rates[IEEE80211_BAND_2GHZ];
1499         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1500         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1501                 ARRAY_SIZE(ath9k_2ghz_chantable);
1502
1503         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1504                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1505                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1506                         sc->rates[IEEE80211_BAND_5GHZ];
1507                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1508                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1509                         ARRAY_SIZE(ath9k_5ghz_chantable);
1510         }
1511
1512         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1513                 ath9k_hw_btcoex_enable(sc->sc_ah);
1514
1515         return 0;
1516 bad2:
1517         /* cleanup tx queues */
1518         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1519                 if (ATH_TXQ_SETUP(sc, i))
1520                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1521 bad:
1522         if (ah)
1523                 ath9k_hw_detach(ah);
1524 bad_no_ah:
1525         ath9k_exit_debug(sc);
1526
1527         return r;
1528 }
1529
1530 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1531 {
1532         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1533                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1534                 IEEE80211_HW_SIGNAL_DBM |
1535                 IEEE80211_HW_AMPDU_AGGREGATION |
1536                 IEEE80211_HW_SUPPORTS_PS |
1537                 IEEE80211_HW_PS_NULLFUNC_STACK |
1538                 IEEE80211_HW_SPECTRUM_MGMT;
1539
1540         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1541                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1542
1543         hw->wiphy->interface_modes =
1544                 BIT(NL80211_IFTYPE_AP) |
1545                 BIT(NL80211_IFTYPE_STATION) |
1546                 BIT(NL80211_IFTYPE_ADHOC) |
1547                 BIT(NL80211_IFTYPE_MESH_POINT);
1548
1549         hw->queues = 4;
1550         hw->max_rates = 4;
1551         hw->channel_change_time = 5000;
1552         hw->max_listen_interval = 10;
1553         /* Hardware supports 10 but we use 4 */
1554         hw->max_rate_tries = 4;
1555         hw->sta_data_size = sizeof(struct ath_node);
1556         hw->vif_data_size = sizeof(struct ath_vif);
1557
1558         hw->rate_control_algorithm = "ath9k_rate_control";
1559
1560         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1561                 &sc->sbands[IEEE80211_BAND_2GHZ];
1562         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1563                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1564                         &sc->sbands[IEEE80211_BAND_5GHZ];
1565 }
1566
1567 /* Device driver core initialization */
1568 int ath_init_device(u16 devid, struct ath_softc *sc)
1569 {
1570         struct ieee80211_hw *hw = sc->hw;
1571         int error = 0, i;
1572         struct ath_regulatory *reg;
1573
1574         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1575
1576         error = ath_init_softc(devid, sc);
1577         if (error != 0)
1578                 return error;
1579
1580         /* get mac address from hardware and set in mac80211 */
1581
1582         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1583
1584         ath_set_hw_capab(sc, hw);
1585
1586         error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1587                               ath9k_reg_notifier);
1588         if (error)
1589                 return error;
1590
1591         reg = &sc->sc_ah->regulatory;
1592
1593         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1594                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1595                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1596                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1597         }
1598
1599         /* initialize tx/rx engine */
1600         error = ath_tx_init(sc, ATH_TXBUF);
1601         if (error != 0)
1602                 goto error_attach;
1603
1604         error = ath_rx_init(sc, ATH_RXBUF);
1605         if (error != 0)
1606                 goto error_attach;
1607
1608         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1609         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1610         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1611
1612         error = ieee80211_register_hw(hw);
1613
1614         if (!ath_is_world_regd(reg)) {
1615                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1616                 if (error)
1617                         goto error_attach;
1618         }
1619
1620         /* Initialize LED control */
1621         ath_init_leds(sc);
1622
1623         ath_start_rfkill_poll(sc);
1624
1625         return 0;
1626
1627 error_attach:
1628         /* cleanup tx queues */
1629         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1630                 if (ATH_TXQ_SETUP(sc, i))
1631                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1632
1633         ath9k_hw_detach(sc->sc_ah);
1634         ath9k_exit_debug(sc);
1635
1636         return error;
1637 }
1638
1639 int ath_reset(struct ath_softc *sc, bool retry_tx)
1640 {
1641         struct ath_hw *ah = sc->sc_ah;
1642         struct ieee80211_hw *hw = sc->hw;
1643         int r;
1644
1645         ath9k_hw_set_interrupts(ah, 0);
1646         ath_drain_all_txq(sc, retry_tx);
1647         ath_stoprecv(sc);
1648         ath_flushrecv(sc);
1649
1650         spin_lock_bh(&sc->sc_resetlock);
1651         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1652         if (r)
1653                 DPRINTF(sc, ATH_DBG_FATAL,
1654                         "Unable to reset hardware; reset status %d\n", r);
1655         spin_unlock_bh(&sc->sc_resetlock);
1656
1657         if (ath_startrecv(sc) != 0)
1658                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1659
1660         /*
1661          * We may be doing a reset in response to a request
1662          * that changes the channel so update any state that
1663          * might change as a result.
1664          */
1665         ath_cache_conf_rate(sc, &hw->conf);
1666
1667         ath_update_txpow(sc);
1668
1669         if (sc->sc_flags & SC_OP_BEACONS)
1670                 ath_beacon_config(sc, NULL);    /* restart beacons */
1671
1672         ath9k_hw_set_interrupts(ah, sc->imask);
1673
1674         if (retry_tx) {
1675                 int i;
1676                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1677                         if (ATH_TXQ_SETUP(sc, i)) {
1678                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1679                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1680                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1681                         }
1682                 }
1683         }
1684
1685         return r;
1686 }
1687
1688 /*
1689  *  This function will allocate both the DMA descriptor structure, and the
1690  *  buffers it contains.  These are used to contain the descriptors used
1691  *  by the system.
1692 */
1693 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1694                       struct list_head *head, const char *name,
1695                       int nbuf, int ndesc)
1696 {
1697 #define DS2PHYS(_dd, _ds)                                               \
1698         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1699 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1700 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1701
1702         struct ath_desc *ds;
1703         struct ath_buf *bf;
1704         int i, bsize, error;
1705
1706         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1707                 name, nbuf, ndesc);
1708
1709         INIT_LIST_HEAD(head);
1710         /* ath_desc must be a multiple of DWORDs */
1711         if ((sizeof(struct ath_desc) % 4) != 0) {
1712                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1713                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1714                 error = -ENOMEM;
1715                 goto fail;
1716         }
1717
1718         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1719
1720         /*
1721          * Need additional DMA memory because we can't use
1722          * descriptors that cross the 4K page boundary. Assume
1723          * one skipped descriptor per 4K page.
1724          */
1725         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1726                 u32 ndesc_skipped =
1727                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1728                 u32 dma_len;
1729
1730                 while (ndesc_skipped) {
1731                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1732                         dd->dd_desc_len += dma_len;
1733
1734                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1735                 };
1736         }
1737
1738         /* allocate descriptors */
1739         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1740                                          &dd->dd_desc_paddr, GFP_KERNEL);
1741         if (dd->dd_desc == NULL) {
1742                 error = -ENOMEM;
1743                 goto fail;
1744         }
1745         ds = dd->dd_desc;
1746         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1747                 name, ds, (u32) dd->dd_desc_len,
1748                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1749
1750         /* allocate buffers */
1751         bsize = sizeof(struct ath_buf) * nbuf;
1752         bf = kzalloc(bsize, GFP_KERNEL);
1753         if (bf == NULL) {
1754                 error = -ENOMEM;
1755                 goto fail2;
1756         }
1757         dd->dd_bufptr = bf;
1758
1759         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1760                 bf->bf_desc = ds;
1761                 bf->bf_daddr = DS2PHYS(dd, ds);
1762
1763                 if (!(sc->sc_ah->caps.hw_caps &
1764                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765                         /*
1766                          * Skip descriptor addresses which can cause 4KB
1767                          * boundary crossing (addr + length) with a 32 dword
1768                          * descriptor fetch.
1769                          */
1770                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1771                                 ASSERT((caddr_t) bf->bf_desc <
1772                                        ((caddr_t) dd->dd_desc +
1773                                         dd->dd_desc_len));
1774
1775                                 ds += ndesc;
1776                                 bf->bf_desc = ds;
1777                                 bf->bf_daddr = DS2PHYS(dd, ds);
1778                         }
1779                 }
1780                 list_add_tail(&bf->list, head);
1781         }
1782         return 0;
1783 fail2:
1784         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1785                           dd->dd_desc_paddr);
1786 fail:
1787         memset(dd, 0, sizeof(*dd));
1788         return error;
1789 #undef ATH_DESC_4KB_BOUND_CHECK
1790 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1791 #undef DS2PHYS
1792 }
1793
1794 void ath_descdma_cleanup(struct ath_softc *sc,
1795                          struct ath_descdma *dd,
1796                          struct list_head *head)
1797 {
1798         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1799                           dd->dd_desc_paddr);
1800
1801         INIT_LIST_HEAD(head);
1802         kfree(dd->dd_bufptr);
1803         memset(dd, 0, sizeof(*dd));
1804 }
1805
1806 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1807 {
1808         int qnum;
1809
1810         switch (queue) {
1811         case 0:
1812                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1813                 break;
1814         case 1:
1815                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1816                 break;
1817         case 2:
1818                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1819                 break;
1820         case 3:
1821                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1822                 break;
1823         default:
1824                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1825                 break;
1826         }
1827
1828         return qnum;
1829 }
1830
1831 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1832 {
1833         int qnum;
1834
1835         switch (queue) {
1836         case ATH9K_WME_AC_VO:
1837                 qnum = 0;
1838                 break;
1839         case ATH9K_WME_AC_VI:
1840                 qnum = 1;
1841                 break;
1842         case ATH9K_WME_AC_BE:
1843                 qnum = 2;
1844                 break;
1845         case ATH9K_WME_AC_BK:
1846                 qnum = 3;
1847                 break;
1848         default:
1849                 qnum = -1;
1850                 break;
1851         }
1852
1853         return qnum;
1854 }
1855
1856 /* XXX: Remove me once we don't depend on ath9k_channel for all
1857  * this redundant data */
1858 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1859                            struct ath9k_channel *ichan)
1860 {
1861         struct ieee80211_channel *chan = hw->conf.channel;
1862         struct ieee80211_conf *conf = &hw->conf;
1863
1864         ichan->channel = chan->center_freq;
1865         ichan->chan = chan;
1866
1867         if (chan->band == IEEE80211_BAND_2GHZ) {
1868                 ichan->chanmode = CHANNEL_G;
1869                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1870         } else {
1871                 ichan->chanmode = CHANNEL_A;
1872                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1873         }
1874
1875         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1876
1877         if (conf_is_ht(conf)) {
1878                 if (conf_is_ht40(conf))
1879                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1880
1881                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1882                                             conf->channel_type);
1883         }
1884 }
1885
1886 /**********************/
1887 /* mac80211 callbacks */
1888 /**********************/
1889
1890 static int ath9k_start(struct ieee80211_hw *hw)
1891 {
1892         struct ath_wiphy *aphy = hw->priv;
1893         struct ath_softc *sc = aphy->sc;
1894         struct ieee80211_channel *curchan = hw->conf.channel;
1895         struct ath9k_channel *init_channel;
1896         int r;
1897
1898         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1899                 "initial channel: %d MHz\n", curchan->center_freq);
1900
1901         mutex_lock(&sc->mutex);
1902
1903         if (ath9k_wiphy_started(sc)) {
1904                 if (sc->chan_idx == curchan->hw_value) {
1905                         /*
1906                          * Already on the operational channel, the new wiphy
1907                          * can be marked active.
1908                          */
1909                         aphy->state = ATH_WIPHY_ACTIVE;
1910                         ieee80211_wake_queues(hw);
1911                 } else {
1912                         /*
1913                          * Another wiphy is on another channel, start the new
1914                          * wiphy in paused state.
1915                          */
1916                         aphy->state = ATH_WIPHY_PAUSED;
1917                         ieee80211_stop_queues(hw);
1918                 }
1919                 mutex_unlock(&sc->mutex);
1920                 return 0;
1921         }
1922         aphy->state = ATH_WIPHY_ACTIVE;
1923
1924         /* setup initial channel */
1925
1926         sc->chan_idx = curchan->hw_value;
1927
1928         init_channel = ath_get_curchannel(sc, hw);
1929
1930         /* Reset SERDES registers */
1931         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1932
1933         /*
1934          * The basic interface to setting the hardware in a good
1935          * state is ``reset''.  On return the hardware is known to
1936          * be powered up and with interrupts disabled.  This must
1937          * be followed by initialization of the appropriate bits
1938          * and then setup of the interrupt mask.
1939          */
1940         spin_lock_bh(&sc->sc_resetlock);
1941         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1942         if (r) {
1943                 DPRINTF(sc, ATH_DBG_FATAL,
1944                         "Unable to reset hardware; reset status %d "
1945                         "(freq %u MHz)\n", r,
1946                         curchan->center_freq);
1947                 spin_unlock_bh(&sc->sc_resetlock);
1948                 goto mutex_unlock;
1949         }
1950         spin_unlock_bh(&sc->sc_resetlock);
1951
1952         /*
1953          * This is needed only to setup initial state
1954          * but it's best done after a reset.
1955          */
1956         ath_update_txpow(sc);
1957
1958         /*
1959          * Setup the hardware after reset:
1960          * The receive engine is set going.
1961          * Frame transmit is handled entirely
1962          * in the frame output path; there's nothing to do
1963          * here except setup the interrupt mask.
1964          */
1965         if (ath_startrecv(sc) != 0) {
1966                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1967                 r = -EIO;
1968                 goto mutex_unlock;
1969         }
1970
1971         /* Setup our intr mask. */
1972         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1973                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1974                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1975
1976         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1977                 sc->imask |= ATH9K_INT_GTT;
1978
1979         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1980                 sc->imask |= ATH9K_INT_CST;
1981
1982         ath_cache_conf_rate(sc, &hw->conf);
1983
1984         sc->sc_flags &= ~SC_OP_INVALID;
1985
1986         /* Disable BMISS interrupt when we're not associated */
1987         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1988         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1989
1990         ieee80211_wake_queues(hw);
1991
1992         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1993
1994 mutex_unlock:
1995         mutex_unlock(&sc->mutex);
1996
1997         return r;
1998 }
1999
2000 static int ath9k_tx(struct ieee80211_hw *hw,
2001                     struct sk_buff *skb)
2002 {
2003         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2004         struct ath_wiphy *aphy = hw->priv;
2005         struct ath_softc *sc = aphy->sc;
2006         struct ath_tx_control txctl;
2007         int hdrlen, padsize;
2008
2009         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2010                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2011                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2012                 goto exit;
2013         }
2014
2015         if (sc->ps_enabled) {
2016                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2017                 /*
2018                  * mac80211 does not set PM field for normal data frames, so we
2019                  * need to update that based on the current PS mode.
2020                  */
2021                 if (ieee80211_is_data(hdr->frame_control) &&
2022                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2023                     !ieee80211_has_pm(hdr->frame_control)) {
2024                         DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2025                                 "while in PS mode\n");
2026                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2027                 }
2028         }
2029
2030         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2031                 /*
2032                  * We are using PS-Poll and mac80211 can request TX while in
2033                  * power save mode. Need to wake up hardware for the TX to be
2034                  * completed and if needed, also for RX of buffered frames.
2035                  */
2036                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2037                 ath9k_ps_wakeup(sc);
2038                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2039                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2040                         DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2041                                 "buffered frame\n");
2042                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2043                 } else {
2044                         DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2045                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2046                 }
2047                 /*
2048                  * The actual restore operation will happen only after
2049                  * the sc_flags bit is cleared. We are just dropping
2050                  * the ps_usecount here.
2051                  */
2052                 ath9k_ps_restore(sc);
2053         }
2054
2055         memset(&txctl, 0, sizeof(struct ath_tx_control));
2056
2057         /*
2058          * As a temporary workaround, assign seq# here; this will likely need
2059          * to be cleaned up to work better with Beacon transmission and virtual
2060          * BSSes.
2061          */
2062         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2063                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2064                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2065                         sc->tx.seq_no += 0x10;
2066                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2067                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2068         }
2069
2070         /* Add the padding after the header if this is not already done */
2071         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2072         if (hdrlen & 3) {
2073                 padsize = hdrlen % 4;
2074                 if (skb_headroom(skb) < padsize)
2075                         return -1;
2076                 skb_push(skb, padsize);
2077                 memmove(skb->data, skb->data + padsize, hdrlen);
2078         }
2079
2080         /* Check if a tx queue is available */
2081
2082         txctl.txq = ath_test_get_txq(sc, skb);
2083         if (!txctl.txq)
2084                 goto exit;
2085
2086         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2087
2088         if (ath_tx_start(hw, skb, &txctl) != 0) {
2089                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2090                 goto exit;
2091         }
2092
2093         return 0;
2094 exit:
2095         dev_kfree_skb_any(skb);
2096         return 0;
2097 }
2098
2099 static void ath9k_stop(struct ieee80211_hw *hw)
2100 {
2101         struct ath_wiphy *aphy = hw->priv;
2102         struct ath_softc *sc = aphy->sc;
2103
2104         aphy->state = ATH_WIPHY_INACTIVE;
2105
2106         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2107         cancel_delayed_work_sync(&sc->tx_complete_work);
2108
2109         if (!sc->num_sec_wiphy) {
2110                 cancel_delayed_work_sync(&sc->wiphy_work);
2111                 cancel_work_sync(&sc->chan_work);
2112         }
2113
2114         if (sc->sc_flags & SC_OP_INVALID) {
2115                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2116                 return;
2117         }
2118
2119         mutex_lock(&sc->mutex);
2120
2121         if (ath9k_wiphy_started(sc)) {
2122                 mutex_unlock(&sc->mutex);
2123                 return; /* another wiphy still in use */
2124         }
2125
2126         /* make sure h/w will not generate any interrupt
2127          * before setting the invalid flag. */
2128         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2129
2130         if (!(sc->sc_flags & SC_OP_INVALID)) {
2131                 ath_drain_all_txq(sc, false);
2132                 ath_stoprecv(sc);
2133                 ath9k_hw_phy_disable(sc->sc_ah);
2134         } else
2135                 sc->rx.rxlink = NULL;
2136
2137         wiphy_rfkill_stop_polling(sc->hw->wiphy);
2138
2139         /* disable HAL and put h/w to sleep */
2140         ath9k_hw_disable(sc->sc_ah);
2141         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2142
2143         sc->sc_flags |= SC_OP_INVALID;
2144
2145         mutex_unlock(&sc->mutex);
2146
2147         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2148 }
2149
2150 static int ath9k_add_interface(struct ieee80211_hw *hw,
2151                                struct ieee80211_if_init_conf *conf)
2152 {
2153         struct ath_wiphy *aphy = hw->priv;
2154         struct ath_softc *sc = aphy->sc;
2155         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2156         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2157         int ret = 0;
2158
2159         mutex_lock(&sc->mutex);
2160
2161         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2162             sc->nvifs > 0) {
2163                 ret = -ENOBUFS;
2164                 goto out;
2165         }
2166
2167         switch (conf->type) {
2168         case NL80211_IFTYPE_STATION:
2169                 ic_opmode = NL80211_IFTYPE_STATION;
2170                 break;
2171         case NL80211_IFTYPE_ADHOC:
2172         case NL80211_IFTYPE_AP:
2173         case NL80211_IFTYPE_MESH_POINT:
2174                 if (sc->nbcnvifs >= ATH_BCBUF) {
2175                         ret = -ENOBUFS;
2176                         goto out;
2177                 }
2178                 ic_opmode = conf->type;
2179                 break;
2180         default:
2181                 DPRINTF(sc, ATH_DBG_FATAL,
2182                         "Interface type %d not yet supported\n", conf->type);
2183                 ret = -EOPNOTSUPP;
2184                 goto out;
2185         }
2186
2187         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2188
2189         /* Set the VIF opmode */
2190         avp->av_opmode = ic_opmode;
2191         avp->av_bslot = -1;
2192
2193         sc->nvifs++;
2194
2195         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2196                 ath9k_set_bssid_mask(hw);
2197
2198         if (sc->nvifs > 1)
2199                 goto out; /* skip global settings for secondary vif */
2200
2201         if (ic_opmode == NL80211_IFTYPE_AP) {
2202                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2203                 sc->sc_flags |= SC_OP_TSF_RESET;
2204         }
2205
2206         /* Set the device opmode */
2207         sc->sc_ah->opmode = ic_opmode;
2208
2209         /*
2210          * Enable MIB interrupts when there are hardware phy counters.
2211          * Note we only do this (at the moment) for station mode.
2212          */
2213         if ((conf->type == NL80211_IFTYPE_STATION) ||
2214             (conf->type == NL80211_IFTYPE_ADHOC) ||
2215             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2216                 if (ath9k_hw_phycounters(sc->sc_ah))
2217                         sc->imask |= ATH9K_INT_MIB;
2218                 sc->imask |= ATH9K_INT_TSFOOR;
2219         }
2220
2221         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2222
2223         if (conf->type == NL80211_IFTYPE_AP    ||
2224             conf->type == NL80211_IFTYPE_ADHOC ||
2225             conf->type == NL80211_IFTYPE_MONITOR)
2226                 ath_start_ani(sc);
2227
2228 out:
2229         mutex_unlock(&sc->mutex);
2230         return ret;
2231 }
2232
2233 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2234                                    struct ieee80211_if_init_conf *conf)
2235 {
2236         struct ath_wiphy *aphy = hw->priv;
2237         struct ath_softc *sc = aphy->sc;
2238         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2239         int i;
2240
2241         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2242
2243         mutex_lock(&sc->mutex);
2244
2245         /* Stop ANI */
2246         del_timer_sync(&sc->ani.timer);
2247
2248         /* Reclaim beacon resources */
2249         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2250             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2251             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2252                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2253                 ath_beacon_return(sc, avp);
2254         }
2255
2256         sc->sc_flags &= ~SC_OP_BEACONS;
2257
2258         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2259                 if (sc->beacon.bslot[i] == conf->vif) {
2260                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2261                                "slot\n", __func__);
2262                         sc->beacon.bslot[i] = NULL;
2263                         sc->beacon.bslot_aphy[i] = NULL;
2264                 }
2265         }
2266
2267         sc->nvifs--;
2268
2269         mutex_unlock(&sc->mutex);
2270 }
2271
2272 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2273 {
2274         struct ath_wiphy *aphy = hw->priv;
2275         struct ath_softc *sc = aphy->sc;
2276         struct ieee80211_conf *conf = &hw->conf;
2277         struct ath_hw *ah = sc->sc_ah;
2278         bool all_wiphys_idle = false, disable_radio = false;
2279
2280         mutex_lock(&sc->mutex);
2281
2282         /* Leave this as the first check */
2283         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2284
2285                 spin_lock_bh(&sc->wiphy_lock);
2286                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2287                 spin_unlock_bh(&sc->wiphy_lock);
2288
2289                 if (conf->flags & IEEE80211_CONF_IDLE){
2290                         if (all_wiphys_idle)
2291                                 disable_radio = true;
2292                 }
2293                 else if (all_wiphys_idle) {
2294                         ath_radio_enable(sc);
2295                         DPRINTF(sc, ATH_DBG_CONFIG,
2296                                 "not-idle: enabling radio\n");
2297                 }
2298         }
2299
2300         if (changed & IEEE80211_CONF_CHANGE_PS) {
2301                 if (conf->flags & IEEE80211_CONF_PS) {
2302                         if (!(ah->caps.hw_caps &
2303                               ATH9K_HW_CAP_AUTOSLEEP)) {
2304                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2305                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2306                                         ath9k_hw_set_interrupts(sc->sc_ah,
2307                                                         sc->imask);
2308                                 }
2309                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2310                         }
2311                         sc->ps_enabled = true;
2312                 } else {
2313                         sc->ps_enabled = false;
2314                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2315                         if (!(ah->caps.hw_caps &
2316                               ATH9K_HW_CAP_AUTOSLEEP)) {
2317                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2318                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2319                                                   SC_OP_WAIT_FOR_CAB |
2320                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2321                                                   SC_OP_WAIT_FOR_TX_ACK);
2322                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2323                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2324                                         ath9k_hw_set_interrupts(sc->sc_ah,
2325                                                         sc->imask);
2326                                 }
2327                         }
2328                 }
2329         }
2330
2331         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2332                 struct ieee80211_channel *curchan = hw->conf.channel;
2333                 int pos = curchan->hw_value;
2334
2335                 aphy->chan_idx = pos;
2336                 aphy->chan_is_ht = conf_is_ht(conf);
2337
2338                 if (aphy->state == ATH_WIPHY_SCAN ||
2339                     aphy->state == ATH_WIPHY_ACTIVE)
2340                         ath9k_wiphy_pause_all_forced(sc, aphy);
2341                 else {
2342                         /*
2343                          * Do not change operational channel based on a paused
2344                          * wiphy changes.
2345                          */
2346                         goto skip_chan_change;
2347                 }
2348
2349                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2350                         curchan->center_freq);
2351
2352                 /* XXX: remove me eventualy */
2353                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2354
2355                 ath_update_chainmask(sc, conf_is_ht(conf));
2356
2357                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2358                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2359                         mutex_unlock(&sc->mutex);
2360                         return -EINVAL;
2361                 }
2362         }
2363
2364 skip_chan_change:
2365         if (changed & IEEE80211_CONF_CHANGE_POWER)
2366                 sc->config.txpowlimit = 2 * conf->power_level;
2367
2368         if (disable_radio) {
2369                 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2370                 ath_radio_disable(sc);
2371         }
2372
2373         mutex_unlock(&sc->mutex);
2374
2375         return 0;
2376 }
2377
2378 #define SUPPORTED_FILTERS                       \
2379         (FIF_PROMISC_IN_BSS |                   \
2380         FIF_ALLMULTI |                          \
2381         FIF_CONTROL |                           \
2382         FIF_OTHER_BSS |                         \
2383         FIF_BCN_PRBRESP_PROMISC |               \
2384         FIF_FCSFAIL)
2385
2386 /* FIXME: sc->sc_full_reset ? */
2387 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2388                                    unsigned int changed_flags,
2389                                    unsigned int *total_flags,
2390                                    int mc_count,
2391                                    struct dev_mc_list *mclist)
2392 {
2393         struct ath_wiphy *aphy = hw->priv;
2394         struct ath_softc *sc = aphy->sc;
2395         u32 rfilt;
2396
2397         changed_flags &= SUPPORTED_FILTERS;
2398         *total_flags &= SUPPORTED_FILTERS;
2399
2400         sc->rx.rxfilter = *total_flags;
2401         ath9k_ps_wakeup(sc);
2402         rfilt = ath_calcrxfilter(sc);
2403         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2404         ath9k_ps_restore(sc);
2405
2406         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2407 }
2408
2409 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2410                              struct ieee80211_vif *vif,
2411                              enum sta_notify_cmd cmd,
2412                              struct ieee80211_sta *sta)
2413 {
2414         struct ath_wiphy *aphy = hw->priv;
2415         struct ath_softc *sc = aphy->sc;
2416
2417         switch (cmd) {
2418         case STA_NOTIFY_ADD:
2419                 ath_node_attach(sc, sta);
2420                 break;
2421         case STA_NOTIFY_REMOVE:
2422                 ath_node_detach(sc, sta);
2423                 break;
2424         default:
2425                 break;
2426         }
2427 }
2428
2429 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2430                          const struct ieee80211_tx_queue_params *params)
2431 {
2432         struct ath_wiphy *aphy = hw->priv;
2433         struct ath_softc *sc = aphy->sc;
2434         struct ath9k_tx_queue_info qi;
2435         int ret = 0, qnum;
2436
2437         if (queue >= WME_NUM_AC)
2438                 return 0;
2439
2440         mutex_lock(&sc->mutex);
2441
2442         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2443
2444         qi.tqi_aifs = params->aifs;
2445         qi.tqi_cwmin = params->cw_min;
2446         qi.tqi_cwmax = params->cw_max;
2447         qi.tqi_burstTime = params->txop;
2448         qnum = ath_get_hal_qnum(queue, sc);
2449
2450         DPRINTF(sc, ATH_DBG_CONFIG,
2451                 "Configure tx [queue/halq] [%d/%d],  "
2452                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2453                 queue, qnum, params->aifs, params->cw_min,
2454                 params->cw_max, params->txop);
2455
2456         ret = ath_txq_update(sc, qnum, &qi);
2457         if (ret)
2458                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2459
2460         mutex_unlock(&sc->mutex);
2461
2462         return ret;
2463 }
2464
2465 static int ath9k_set_key(struct ieee80211_hw *hw,
2466                          enum set_key_cmd cmd,
2467                          struct ieee80211_vif *vif,
2468                          struct ieee80211_sta *sta,
2469                          struct ieee80211_key_conf *key)
2470 {
2471         struct ath_wiphy *aphy = hw->priv;
2472         struct ath_softc *sc = aphy->sc;
2473         int ret = 0;
2474
2475         if (modparam_nohwcrypt)
2476                 return -ENOSPC;
2477
2478         mutex_lock(&sc->mutex);
2479         ath9k_ps_wakeup(sc);
2480         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2481
2482         switch (cmd) {
2483         case SET_KEY:
2484                 ret = ath_key_config(sc, vif, sta, key);
2485                 if (ret >= 0) {
2486                         key->hw_key_idx = ret;
2487                         /* push IV and Michael MIC generation to stack */
2488                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2489                         if (key->alg == ALG_TKIP)
2490                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2491                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2492                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2493                         ret = 0;
2494                 }
2495                 break;
2496         case DISABLE_KEY:
2497                 ath_key_delete(sc, key);
2498                 break;
2499         default:
2500                 ret = -EINVAL;
2501         }
2502
2503         ath9k_ps_restore(sc);
2504         mutex_unlock(&sc->mutex);
2505
2506         return ret;
2507 }
2508
2509 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2510                                    struct ieee80211_vif *vif,
2511                                    struct ieee80211_bss_conf *bss_conf,
2512                                    u32 changed)
2513 {
2514         struct ath_wiphy *aphy = hw->priv;
2515         struct ath_softc *sc = aphy->sc;
2516         struct ath_hw *ah = sc->sc_ah;
2517         struct ath_vif *avp = (void *)vif->drv_priv;
2518         u32 rfilt = 0;
2519         int error, i;
2520
2521         mutex_lock(&sc->mutex);
2522
2523         /*
2524          * TODO: Need to decide which hw opmode to use for
2525          *       multi-interface cases
2526          * XXX: This belongs into add_interface!
2527          */
2528         if (vif->type == NL80211_IFTYPE_AP &&
2529             ah->opmode != NL80211_IFTYPE_AP) {
2530                 ah->opmode = NL80211_IFTYPE_STATION;
2531                 ath9k_hw_setopmode(ah);
2532                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2533                 sc->curaid = 0;
2534                 ath9k_hw_write_associd(sc);
2535                 /* Request full reset to get hw opmode changed properly */
2536                 sc->sc_flags |= SC_OP_FULL_RESET;
2537         }
2538
2539         if ((changed & BSS_CHANGED_BSSID) &&
2540             !is_zero_ether_addr(bss_conf->bssid)) {
2541                 switch (vif->type) {
2542                 case NL80211_IFTYPE_STATION:
2543                 case NL80211_IFTYPE_ADHOC:
2544                 case NL80211_IFTYPE_MESH_POINT:
2545                         /* Set BSSID */
2546                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2547                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2548                         sc->curaid = 0;
2549                         ath9k_hw_write_associd(sc);
2550
2551                         /* Set aggregation protection mode parameters */
2552                         sc->config.ath_aggr_prot = 0;
2553
2554                         DPRINTF(sc, ATH_DBG_CONFIG,
2555                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2556                                 rfilt, sc->curbssid, sc->curaid);
2557
2558                         /* need to reconfigure the beacon */
2559                         sc->sc_flags &= ~SC_OP_BEACONS ;
2560
2561                         break;
2562                 default:
2563                         break;
2564                 }
2565         }
2566
2567         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2568             (vif->type == NL80211_IFTYPE_AP) ||
2569             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2570                 if ((changed & BSS_CHANGED_BEACON) ||
2571                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2572                      bss_conf->enable_beacon)) {
2573                         /*
2574                          * Allocate and setup the beacon frame.
2575                          *
2576                          * Stop any previous beacon DMA.  This may be
2577                          * necessary, for example, when an ibss merge
2578                          * causes reconfiguration; we may be called
2579                          * with beacon transmission active.
2580                          */
2581                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2582
2583                         error = ath_beacon_alloc(aphy, vif);
2584                         if (!error)
2585                                 ath_beacon_config(sc, vif);
2586                 }
2587         }
2588
2589         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2590         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2591                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2592                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2593                                 ath9k_hw_keysetmac(sc->sc_ah,
2594                                                    (u16)i,
2595                                                    sc->curbssid);
2596         }
2597
2598         /* Only legacy IBSS for now */
2599         if (vif->type == NL80211_IFTYPE_ADHOC)
2600                 ath_update_chainmask(sc, 0);
2601
2602         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2603                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2604                         bss_conf->use_short_preamble);
2605                 if (bss_conf->use_short_preamble)
2606                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2607                 else
2608                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2609         }
2610
2611         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2612                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2613                         bss_conf->use_cts_prot);
2614                 if (bss_conf->use_cts_prot &&
2615                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2616                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2617                 else
2618                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2619         }
2620
2621         if (changed & BSS_CHANGED_ASSOC) {
2622                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2623                         bss_conf->assoc);
2624                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2625         }
2626
2627         /*
2628          * The HW TSF has to be reset when the beacon interval changes.
2629          * We set the flag here, and ath_beacon_config_ap() would take this
2630          * into account when it gets called through the subsequent
2631          * config_interface() call - with IFCC_BEACON in the changed field.
2632          */
2633
2634         if (changed & BSS_CHANGED_BEACON_INT) {
2635                 sc->sc_flags |= SC_OP_TSF_RESET;
2636                 sc->beacon_interval = bss_conf->beacon_int;
2637         }
2638
2639         mutex_unlock(&sc->mutex);
2640 }
2641
2642 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2643 {
2644         u64 tsf;
2645         struct ath_wiphy *aphy = hw->priv;
2646         struct ath_softc *sc = aphy->sc;
2647
2648         mutex_lock(&sc->mutex);
2649         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2650         mutex_unlock(&sc->mutex);
2651
2652         return tsf;
2653 }
2654
2655 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2656 {
2657         struct ath_wiphy *aphy = hw->priv;
2658         struct ath_softc *sc = aphy->sc;
2659
2660         mutex_lock(&sc->mutex);
2661         ath9k_hw_settsf64(sc->sc_ah, tsf);
2662         mutex_unlock(&sc->mutex);
2663 }
2664
2665 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2666 {
2667         struct ath_wiphy *aphy = hw->priv;
2668         struct ath_softc *sc = aphy->sc;
2669
2670         mutex_lock(&sc->mutex);
2671         ath9k_hw_reset_tsf(sc->sc_ah);
2672         mutex_unlock(&sc->mutex);
2673 }
2674
2675 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2676                               enum ieee80211_ampdu_mlme_action action,
2677                               struct ieee80211_sta *sta,
2678                               u16 tid, u16 *ssn)
2679 {
2680         struct ath_wiphy *aphy = hw->priv;
2681         struct ath_softc *sc = aphy->sc;
2682         int ret = 0;
2683
2684         switch (action) {
2685         case IEEE80211_AMPDU_RX_START:
2686                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2687                         ret = -ENOTSUPP;
2688                 break;
2689         case IEEE80211_AMPDU_RX_STOP:
2690                 break;
2691         case IEEE80211_AMPDU_TX_START:
2692                 ath_tx_aggr_start(sc, sta, tid, ssn);
2693                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2694                 break;
2695         case IEEE80211_AMPDU_TX_STOP:
2696                 ath_tx_aggr_stop(sc, sta, tid);
2697                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2698                 break;
2699         case IEEE80211_AMPDU_TX_OPERATIONAL:
2700                 ath_tx_aggr_resume(sc, sta, tid);
2701                 break;
2702         default:
2703                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2704         }
2705
2706         return ret;
2707 }
2708
2709 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2710 {
2711         struct ath_wiphy *aphy = hw->priv;
2712         struct ath_softc *sc = aphy->sc;
2713
2714         if (ath9k_wiphy_scanning(sc)) {
2715                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2716                        "same time\n");
2717                 /*
2718                  * Do not allow the concurrent scanning state for now. This
2719                  * could be improved with scanning control moved into ath9k.
2720                  */
2721                 return;
2722         }
2723
2724         aphy->state = ATH_WIPHY_SCAN;
2725         ath9k_wiphy_pause_all_forced(sc, aphy);
2726
2727         spin_lock_bh(&sc->ani_lock);
2728         sc->sc_flags |= SC_OP_SCANNING;
2729         spin_unlock_bh(&sc->ani_lock);
2730 }
2731
2732 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2733 {
2734         struct ath_wiphy *aphy = hw->priv;
2735         struct ath_softc *sc = aphy->sc;
2736
2737         spin_lock_bh(&sc->ani_lock);
2738         aphy->state = ATH_WIPHY_ACTIVE;
2739         sc->sc_flags &= ~SC_OP_SCANNING;
2740         sc->sc_flags |= SC_OP_FULL_RESET;
2741         spin_unlock_bh(&sc->ani_lock);
2742 }
2743
2744 struct ieee80211_ops ath9k_ops = {
2745         .tx                 = ath9k_tx,
2746         .start              = ath9k_start,
2747         .stop               = ath9k_stop,
2748         .add_interface      = ath9k_add_interface,
2749         .remove_interface   = ath9k_remove_interface,
2750         .config             = ath9k_config,
2751         .configure_filter   = ath9k_configure_filter,
2752         .sta_notify         = ath9k_sta_notify,
2753         .conf_tx            = ath9k_conf_tx,
2754         .bss_info_changed   = ath9k_bss_info_changed,
2755         .set_key            = ath9k_set_key,
2756         .get_tsf            = ath9k_get_tsf,
2757         .set_tsf            = ath9k_set_tsf,
2758         .reset_tsf          = ath9k_reset_tsf,
2759         .ampdu_action       = ath9k_ampdu_action,
2760         .sw_scan_start      = ath9k_sw_scan_start,
2761         .sw_scan_complete   = ath9k_sw_scan_complete,
2762         .rfkill_poll        = ath9k_rfkill_poll_state,
2763 };
2764
2765 static struct {
2766         u32 version;
2767         const char * name;
2768 } ath_mac_bb_names[] = {
2769         { AR_SREV_VERSION_5416_PCI,     "5416" },
2770         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2771         { AR_SREV_VERSION_9100,         "9100" },
2772         { AR_SREV_VERSION_9160,         "9160" },
2773         { AR_SREV_VERSION_9280,         "9280" },
2774         { AR_SREV_VERSION_9285,         "9285" },
2775         { AR_SREV_VERSION_9287,         "9287" }
2776 };
2777
2778 static struct {
2779         u16 version;
2780         const char * name;
2781 } ath_rf_names[] = {
2782         { 0,                            "5133" },
2783         { AR_RAD5133_SREV_MAJOR,        "5133" },
2784         { AR_RAD5122_SREV_MAJOR,        "5122" },
2785         { AR_RAD2133_SREV_MAJOR,        "2133" },
2786         { AR_RAD2122_SREV_MAJOR,        "2122" }
2787 };
2788
2789 /*
2790  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2791  */
2792 const char *
2793 ath_mac_bb_name(u32 mac_bb_version)
2794 {
2795         int i;
2796
2797         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2798                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2799                         return ath_mac_bb_names[i].name;
2800                 }
2801         }
2802
2803         return "????";
2804 }
2805
2806 /*
2807  * Return the RF name. "????" is returned if the RF is unknown.
2808  */
2809 const char *
2810 ath_rf_name(u16 rf_version)
2811 {
2812         int i;
2813
2814         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2815                 if (ath_rf_names[i].version == rf_version) {
2816                         return ath_rf_names[i].name;
2817                 }
2818         }
2819
2820         return "????";
2821 }
2822
2823 static int __init ath9k_init(void)
2824 {
2825         int error;
2826
2827         /* Register rate control algorithm */
2828         error = ath_rate_control_register();
2829         if (error != 0) {
2830                 printk(KERN_ERR
2831                         "ath9k: Unable to register rate control "
2832                         "algorithm: %d\n",
2833                         error);
2834                 goto err_out;
2835         }
2836
2837         error = ath9k_debug_create_root();
2838         if (error) {
2839                 printk(KERN_ERR
2840                         "ath9k: Unable to create debugfs root: %d\n",
2841                         error);
2842                 goto err_rate_unregister;
2843         }
2844
2845         error = ath_pci_init();
2846         if (error < 0) {
2847                 printk(KERN_ERR
2848                         "ath9k: No PCI devices found, driver not installed.\n");
2849                 error = -ENODEV;
2850                 goto err_remove_root;
2851         }
2852
2853         error = ath_ahb_init();
2854         if (error < 0) {
2855                 error = -ENODEV;
2856                 goto err_pci_exit;
2857         }
2858
2859         return 0;
2860
2861  err_pci_exit:
2862         ath_pci_exit();
2863
2864  err_remove_root:
2865         ath9k_debug_remove_root();
2866  err_rate_unregister:
2867         ath_rate_control_unregister();
2868  err_out:
2869         return error;
2870 }
2871 module_init(ath9k_init);
2872
2873 static void __exit ath9k_exit(void)
2874 {
2875         ath_ahb_exit();
2876         ath_pci_exit();
2877         ath9k_debug_remove_root();
2878         ath_rate_control_unregister();
2879         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2880 }
2881 module_exit(ath9k_exit);