drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static char *dev_info = "ath9k";
  22
  23 MODULE_AUTHOR("Atheros Communications");
  24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  26 MODULE_LICENSE("Dual BSD/GPL");
  27
  28 static int modparam_nohwcrypt;
  29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  31
  32 /* We use the hw_value as an index into our private channel structure */
  33
  34 #define CHAN2G(_freq, _idx)  { \
  35         .center_freq = (_freq), \
  36         .hw_value = (_idx), \
  37         .max_power = 20, \
  38 }
  39
  40 #define CHAN5G(_freq, _idx) { \
  41         .band = IEEE80211_BAND_5GHZ, \
  42         .center_freq = (_freq), \
  43         .hw_value = (_idx), \
  44         .max_power = 20, \
  45 }
  46
  47 /* Some 2 GHz radios are actually tunable on 2312-2732
  48  * on 5 MHz steps, we support the channels which we know
  49  * we have calibration data for all cards though to make
  50  * this static */
  51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  52         CHAN2G(2412, 0), /* Channel 1 */
  53         CHAN2G(2417, 1), /* Channel 2 */
  54         CHAN2G(2422, 2), /* Channel 3 */
  55         CHAN2G(2427, 3), /* Channel 4 */
  56         CHAN2G(2432, 4), /* Channel 5 */
  57         CHAN2G(2437, 5), /* Channel 6 */
  58         CHAN2G(2442, 6), /* Channel 7 */
  59         CHAN2G(2447, 7), /* Channel 8 */
  60         CHAN2G(2452, 8), /* Channel 9 */
  61         CHAN2G(2457, 9), /* Channel 10 */
  62         CHAN2G(2462, 10), /* Channel 11 */
  63         CHAN2G(2467, 11), /* Channel 12 */
  64         CHAN2G(2472, 12), /* Channel 13 */
  65         CHAN2G(2484, 13), /* Channel 14 */
  66 };
  67
  68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  69  * on 5 MHz steps, we support the channels which we know
  70  * we have calibration data for all cards though to make
  71  * this static */
  72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  73         /* _We_ call this UNII 1 */
  74         CHAN5G(5180, 14), /* Channel 36 */
  75         CHAN5G(5200, 15), /* Channel 40 */
  76         CHAN5G(5220, 16), /* Channel 44 */
  77         CHAN5G(5240, 17), /* Channel 48 */
  78         /* _We_ call this UNII 2 */
  79         CHAN5G(5260, 18), /* Channel 52 */
  80         CHAN5G(5280, 19), /* Channel 56 */
  81         CHAN5G(5300, 20), /* Channel 60 */
  82         CHAN5G(5320, 21), /* Channel 64 */
  83         /* _We_ call this "Middle band" */
  84         CHAN5G(5500, 22), /* Channel 100 */
  85         CHAN5G(5520, 23), /* Channel 104 */
  86         CHAN5G(5540, 24), /* Channel 108 */
  87         CHAN5G(5560, 25), /* Channel 112 */
  88         CHAN5G(5580, 26), /* Channel 116 */
  89         CHAN5G(5600, 27), /* Channel 120 */
  90         CHAN5G(5620, 28), /* Channel 124 */
  91         CHAN5G(5640, 29), /* Channel 128 */
  92         CHAN5G(5660, 30), /* Channel 132 */
  93         CHAN5G(5680, 31), /* Channel 136 */
  94         CHAN5G(5700, 32), /* Channel 140 */
  95         /* _We_ call this UNII 3 */
  96         CHAN5G(5745, 33), /* Channel 149 */
  97         CHAN5G(5765, 34), /* Channel 153 */
  98         CHAN5G(5785, 35), /* Channel 157 */
  99         CHAN5G(5805, 36), /* Channel 161 */
 100         CHAN5G(5825, 37), /* Channel 165 */
 101 };
 102
 103 static void ath_cache_conf_rate(struct ath_softc *sc,
 104                                 struct ieee80211_conf *conf)
 105 {
 106         switch (conf->channel->band) {
 107         case IEEE80211_BAND_2GHZ:
 108                 if (conf_is_ht20(conf))
 109                         sc->cur_rate_table =
 110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 111                 else if (conf_is_ht40_minus(conf))
 112                         sc->cur_rate_table =
 113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 114                 else if (conf_is_ht40_plus(conf))
 115                         sc->cur_rate_table =
 116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 117                 else
 118                         sc->cur_rate_table =
 119                           sc->hw_rate_table[ATH9K_MODE_11G];
 120                 break;
 121         case IEEE80211_BAND_5GHZ:
 122                 if (conf_is_ht20(conf))
 123                         sc->cur_rate_table =
 124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 125                 else if (conf_is_ht40_minus(conf))
 126                         sc->cur_rate_table =
 127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 128                 else if (conf_is_ht40_plus(conf))
 129                         sc->cur_rate_table =
 130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 131                 else
 132                         sc->cur_rate_table =
 133                           sc->hw_rate_table[ATH9K_MODE_11A];
 134                 break;
 135         default:
 136                 BUG_ON(1);
 137                 break;
 138         }
 139 }
 140
 141 static void ath_update_txpow(struct ath_softc *sc)
 142 {
 143         struct ath_hw *ah = sc->sc_ah;
 144         u32 txpow;
 145
 146         if (sc->curtxpow != sc->config.txpowlimit) {
 147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 148                 /* read back in case value is clamped */
 149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 150                 sc->curtxpow = txpow;
 151         }
 152 }
 153
 154 static u8 parse_mpdudensity(u8 mpdudensity)
 155 {
 156         /*
 157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 158          *   0 for no restriction
 159          *   1 for 1/4 us
 160          *   2 for 1/2 us
 161          *   3 for 1 us
 162          *   4 for 2 us
 163          *   5 for 4 us
 164          *   6 for 8 us
 165          *   7 for 16 us
 166          */
 167         switch (mpdudensity) {
 168         case 0:
 169                 return 0;
 170         case 1:
 171         case 2:
 172         case 3:
 173                 /* Our lower layer calculations limit our precision to
 174                    1 microsecond */
 175                 return 1;
 176         case 4:
 177                 return 2;
 178         case 5:
 179                 return 4;
 180         case 6:
 181                 return 8;
 182         case 7:
 183                 return 16;
 184         default:
 185                 return 0;
 186         }
 187 }
 188
 189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 190 {
 191         const struct ath_rate_table *rate_table = NULL;
 192         struct ieee80211_supported_band *sband;
 193         struct ieee80211_rate *rate;
 194         int i, maxrates;
 195
 196         switch (band) {
 197         case IEEE80211_BAND_2GHZ:
 198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 199                 break;
 200         case IEEE80211_BAND_5GHZ:
 201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 202                 break;
 203         default:
 204                 break;
 205         }
 206
 207         if (rate_table == NULL)
 208                 return;
 209
 210         sband = &sc->sbands[band];
 211         rate = sc->rates[band];
 212
 213         if (rate_table->rate_cnt > ATH_RATE_MAX)
 214                 maxrates = ATH_RATE_MAX;
 215         else
 216                 maxrates = rate_table->rate_cnt;
 217
 218         for (i = 0; i < maxrates; i++) {
 219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 220                 rate[i].hw_value = rate_table->info[i].ratecode;
 221                 if (rate_table->info[i].short_preamble) {
 222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 223                                 rate_table->info[i].short_preamble;
 224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 225                 }
 226                 sband->n_bitrates++;
 227
 228                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 229                         rate[i].bitrate / 10, rate[i].hw_value);
 230         }
 231 }
 232
 233 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 234                                                 struct ieee80211_hw *hw)
 235 {
 236         struct ieee80211_channel *curchan = hw->conf.channel;
 237         struct ath9k_channel *channel;
 238         u8 chan_idx;
 239
 240         chan_idx = curchan->hw_value;
 241         channel = &sc->sc_ah->channels[chan_idx];
 242         ath9k_update_ichannel(sc, hw, channel);
 243         return channel;
 244 }
 245
 246 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 247 {
 248         unsigned long flags;
 249         bool ret;
 250
 251         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 252         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 253         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 254
 255         return ret;
 256 }
 257
 258 void ath9k_ps_wakeup(struct ath_softc *sc)
 259 {
 260         unsigned long flags;
 261
 262         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 263         if (++sc->ps_usecount != 1)
 264                 goto unlock;
 265
 266         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 267
 268  unlock:
 269         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 270 }
 271
 272 void ath9k_ps_restore(struct ath_softc *sc)
 273 {
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 277         if (--sc->ps_usecount != 0)
 278                 goto unlock;
 279
 280         if (sc->ps_enabled &&
 281             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 282                               SC_OP_WAIT_FOR_CAB |
 283                               SC_OP_WAIT_FOR_PSPOLL_DATA |
 284                               SC_OP_WAIT_FOR_TX_ACK)))
 285                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 286
 287  unlock:
 288         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 289 }
 290
 291 /*
 292  * Set/change channels.  If the channel is really being changed, it's done
 293  * by reseting the chip.  To accomplish this we must first cleanup any pending
 294  * DMA, then restart stuff.
 295 */
 296 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 297                     struct ath9k_channel *hchan)
 298 {
 299         struct ath_hw *ah = sc->sc_ah;
 300         bool fastcc = true, stopped;
 301         struct ieee80211_channel *channel = hw->conf.channel;
 302         int r;
 303
 304         if (sc->sc_flags & SC_OP_INVALID)
 305                 return -EIO;
 306
 307         ath9k_ps_wakeup(sc);
 308
 309         /*
 310          * This is only performed if the channel settings have
 311          * actually changed.
 312          *
 313          * To switch channels clear any pending DMA operations;
 314          * wait long enough for the RX fifo to drain, reset the
 315          * hardware at the new frequency, and then re-enable
 316          * the relevant bits of the h/w.
 317          */
 318         ath9k_hw_set_interrupts(ah, 0);
 319         ath_drain_all_txq(sc, false);
 320         stopped = ath_stoprecv(sc);
 321
 322         /* XXX: do not flush receive queue here. We don't want
 323          * to flush data frames already in queue because of
 324          * changing channel. */
 325
 326         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 327                 fastcc = false;
 328
 329         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
 330                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 331                 sc->sc_ah->curchan->channel,
 332                 channel->center_freq, sc->tx_chan_width);
 333
 334         spin_lock_bh(&sc->sc_resetlock);
 335
 336         r = ath9k_hw_reset(ah, hchan, fastcc);
 337         if (r) {
 338                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 339                         "Unable to reset channel (%u Mhz) "
 340                         "reset status %d\n",
 341                         channel->center_freq, r);
 342                 spin_unlock_bh(&sc->sc_resetlock);
 343                 goto ps_restore;
 344         }
 345         spin_unlock_bh(&sc->sc_resetlock);
 346
 347         sc->sc_flags &= ~SC_OP_FULL_RESET;
 348
 349         if (ath_startrecv(sc) != 0) {
 350                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 351                         "Unable to restart recv logic\n");
 352                 r = -EIO;
 353                 goto ps_restore;
 354         }
 355
 356         ath_cache_conf_rate(sc, &hw->conf);
 357         ath_update_txpow(sc);
 358         ath9k_hw_set_interrupts(ah, sc->imask);
 359
 360  ps_restore:
 361         ath9k_ps_restore(sc);
 362         return r;
 363 }
 364
 365 /*
 366  *  This routine performs the periodic noise floor calibration function
 367  *  that is used to adjust and optimize the chip performance.  This
 368  *  takes environmental changes (location, temperature) into account.
 369  *  When the task is complete, it reschedules itself depending on the
 370  *  appropriate interval that was calculated.
 371  */
 372 static void ath_ani_calibrate(unsigned long data)
 373 {
 374         struct ath_softc *sc = (struct ath_softc *)data;
 375         struct ath_hw *ah = sc->sc_ah;
 376         bool longcal = false;
 377         bool shortcal = false;
 378         bool aniflag = false;
 379         unsigned int timestamp = jiffies_to_msecs(jiffies);
 380         u32 cal_interval, short_cal_interval;
 381
 382         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 383                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 384
 385         /*
 386         * don't calibrate when we're scanning.
 387         * we are most likely not on our home channel.
 388         */
 389         spin_lock(&sc->ani_lock);
 390         if (sc->sc_flags & SC_OP_SCANNING)
 391                 goto set_timer;
 392
 393         /* Only calibrate if awake */
 394         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 395                 goto set_timer;
 396
 397         ath9k_ps_wakeup(sc);
 398
 399         /* Long calibration runs independently of short calibration. */
 400         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 401                 longcal = true;
 402                 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 403                 sc->ani.longcal_timer = timestamp;
 404         }
 405
 406         /* Short calibration applies only while caldone is false */
 407         if (!sc->ani.caldone) {
 408                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 409                         shortcal = true;
 410                         DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 411                         sc->ani.shortcal_timer = timestamp;
 412                         sc->ani.resetcal_timer = timestamp;
 413                 }
 414         } else {
 415                 if ((timestamp - sc->ani.resetcal_timer) >=
 416                     ATH_RESTART_CALINTERVAL) {
 417                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 418                         if (sc->ani.caldone)
 419                                 sc->ani.resetcal_timer = timestamp;
 420                 }
 421         }
 422
 423         /* Verify whether we must check ANI */
 424         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 425                 aniflag = true;
 426                 sc->ani.checkani_timer = timestamp;
 427         }
 428
 429         /* Skip all processing if there's nothing to do. */
 430         if (longcal || shortcal || aniflag) {
 431                 /* Call ANI routine if necessary */
 432                 if (aniflag)
 433                         ath9k_hw_ani_monitor(ah, ah->curchan);
 434
 435                 /* Perform calibration if necessary */
 436                 if (longcal || shortcal) {
 437                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 438                                                      sc->rx_chainmask, longcal);
 439
 440                         if (longcal)
 441                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 442                                                                      ah->curchan);
 443
 444                         DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 445                                 ah->curchan->channel, ah->curchan->channelFlags,
 446                                 sc->ani.noise_floor);
 447                 }
 448         }
 449
 450         ath9k_ps_restore(sc);
 451
 452 set_timer:
 453         spin_unlock(&sc->ani_lock);
 454         /*
 455         * Set timer interval based on previous results.
 456         * The interval must be the shortest necessary to satisfy ANI,
 457         * short calibration and long calibration.
 458         */
 459         cal_interval = ATH_LONG_CALINTERVAL;
 460         if (sc->sc_ah->config.enable_ani)
 461                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 462         if (!sc->ani.caldone)
 463                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 464
 465         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 466 }
 467
 468 static void ath_start_ani(struct ath_softc *sc)
 469 {
 470         unsigned long timestamp = jiffies_to_msecs(jiffies);
 471
 472         sc->ani.longcal_timer = timestamp;
 473         sc->ani.shortcal_timer = timestamp;
 474         sc->ani.checkani_timer = timestamp;
 475
 476         mod_timer(&sc->ani.timer,
 477                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 478 }
 479
 480 /*
 481  * Update tx/rx chainmask. For legacy association,
 482  * hard code chainmask to 1x1, for 11n association, use
 483  * the chainmask configuration, for bt coexistence, use
 484  * the chainmask configuration even in legacy mode.
 485  */
 486 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 487 {
 488         struct ath_hw *ah = sc->sc_ah;
 489
 490         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
 491             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 492                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 493                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 494         } else {
 495                 sc->tx_chainmask = 1;
 496                 sc->rx_chainmask = 1;
 497         }
 498
 499         DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 500                 sc->tx_chainmask, sc->rx_chainmask);
 501 }
 502
 503 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 504 {
 505         struct ath_node *an;
 506
 507         an = (struct ath_node *)sta->drv_priv;
 508
 509         if (sc->sc_flags & SC_OP_TXAGGR) {
 510                 ath_tx_node_init(sc, an);
 511                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 512                                      sta->ht_cap.ampdu_factor);
 513                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 514                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 515         }
 516 }
 517
 518 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 519 {
 520         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 521
 522         if (sc->sc_flags & SC_OP_TXAGGR)
 523                 ath_tx_node_cleanup(sc, an);
 524 }
 525
 526 static void ath9k_tasklet(unsigned long data)
 527 {
 528         struct ath_softc *sc = (struct ath_softc *)data;
 529         struct ath_hw *ah = sc->sc_ah;
 530
 531         u32 status = sc->intrstatus;
 532
 533         ath9k_ps_wakeup(sc);
 534
 535         if (status & ATH9K_INT_FATAL) {
 536                 ath_reset(sc, false);
 537                 ath9k_ps_restore(sc);
 538                 return;
 539         }
 540
 541         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 542                 spin_lock_bh(&sc->rx.rxflushlock);
 543                 ath_rx_tasklet(sc, 0);
 544                 spin_unlock_bh(&sc->rx.rxflushlock);
 545         }
 546
 547         if (status & ATH9K_INT_TX)
 548                 ath_tx_tasklet(sc);
 549
 550         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 551                 /*
 552                  * TSF sync does not look correct; remain awake to sync with
 553                  * the next Beacon.
 554                  */
 555                 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
 556                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 557         }
 558
 559         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 560                 if (status & ATH9K_INT_GENTIMER)
 561                         ath_gen_timer_isr(sc->sc_ah);
 562
 563         /* re-enable hardware interrupt */
 564         ath9k_hw_set_interrupts(ah, sc->imask);
 565         ath9k_ps_restore(sc);
 566 }
 567
 568 irqreturn_t ath_isr(int irq, void *dev)
 569 {
 570 #define SCHED_INTR (                            \
 571                 ATH9K_INT_FATAL |               \
 572                 ATH9K_INT_RXORN |               \
 573                 ATH9K_INT_RXEOL |               \
 574                 ATH9K_INT_RX |                  \
 575                 ATH9K_INT_TX |                  \
 576                 ATH9K_INT_BMISS |               \
 577                 ATH9K_INT_CST |                 \
 578                 ATH9K_INT_TSFOOR |              \
 579                 ATH9K_INT_GENTIMER)
 580
 581         struct ath_softc *sc = dev;
 582         struct ath_hw *ah = sc->sc_ah;
 583         enum ath9k_int status;
 584         bool sched = false;
 585
 586         /*
 587          * The hardware is not ready/present, don't
 588          * touch anything. Note this can happen early
 589          * on if the IRQ is shared.
 590          */
 591         if (sc->sc_flags & SC_OP_INVALID)
 592                 return IRQ_NONE;
 593
 594
 595         /* shared irq, not for us */
 596
 597         if (!ath9k_hw_intrpend(ah))
 598                 return IRQ_NONE;
 599
 600         /*
 601          * Figure out the reason(s) for the interrupt.  Note
 602          * that the hal returns a pseudo-ISR that may include
 603          * bits we haven't explicitly enabled so we mask the
 604          * value to insure we only process bits we requested.
 605          */
 606         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 607         status &= sc->imask;    /* discard unasked-for bits */
 608
 609         /*
 610          * If there are no status bits set, then this interrupt was not
 611          * for me (should have been caught above).
 612          */
 613         if (!status)
 614                 return IRQ_NONE;
 615
 616         /* Cache the status */
 617         sc->intrstatus = status;
 618
 619         if (status & SCHED_INTR)
 620                 sched = true;
 621
 622         /*
 623          * If a FATAL or RXORN interrupt is received, we have to reset the
 624          * chip immediately.
 625          */
 626         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 627                 goto chip_reset;
 628
 629         if (status & ATH9K_INT_SWBA)
 630                 tasklet_schedule(&sc->bcon_tasklet);
 631
 632         if (status & ATH9K_INT_TXURN)
 633                 ath9k_hw_updatetxtriglevel(ah, true);
 634
 635         if (status & ATH9K_INT_MIB) {
 636                 /*
 637                  * Disable interrupts until we service the MIB
 638                  * interrupt; otherwise it will continue to
 639                  * fire.
 640                  */
 641                 ath9k_hw_set_interrupts(ah, 0);
 642                 /*
 643                  * Let the hal handle the event. We assume
 644                  * it will clear whatever condition caused
 645                  * the interrupt.
 646                  */
 647                 ath9k_hw_procmibevent(ah);
 648                 ath9k_hw_set_interrupts(ah, sc->imask);
 649         }
 650
 651         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 652                 if (status & ATH9K_INT_TIM_TIMER) {
 653                         /* Clear RxAbort bit so that we can
 654                          * receive frames */
 655                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 656                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 657                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 658                 }
 659
 660 chip_reset:
 661
 662         ath_debug_stat_interrupt(sc, status);
 663
 664         if (sched) {
 665                 /* turn off every interrupt except SWBA */
 666                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 667                 tasklet_schedule(&sc->intr_tq);
 668         }
 669
 670         return IRQ_HANDLED;
 671
 672 #undef SCHED_INTR
 673 }
 674
 675 static u32 ath_get_extchanmode(struct ath_softc *sc,
 676                                struct ieee80211_channel *chan,
 677                                enum nl80211_channel_type channel_type)
 678 {
 679         u32 chanmode = 0;
 680
 681         switch (chan->band) {
 682         case IEEE80211_BAND_2GHZ:
 683                 switch(channel_type) {
 684                 case NL80211_CHAN_NO_HT:
 685                 case NL80211_CHAN_HT20:
 686                         chanmode = CHANNEL_G_HT20;
 687                         break;
 688                 case NL80211_CHAN_HT40PLUS:
 689                         chanmode = CHANNEL_G_HT40PLUS;
 690                         break;
 691                 case NL80211_CHAN_HT40MINUS:
 692                         chanmode = CHANNEL_G_HT40MINUS;
 693                         break;
 694                 }
 695                 break;
 696         case IEEE80211_BAND_5GHZ:
 697                 switch(channel_type) {
 698                 case NL80211_CHAN_NO_HT:
 699                 case NL80211_CHAN_HT20:
 700                         chanmode = CHANNEL_A_HT20;
 701                         break;
 702                 case NL80211_CHAN_HT40PLUS:
 703                         chanmode = CHANNEL_A_HT40PLUS;
 704                         break;
 705                 case NL80211_CHAN_HT40MINUS:
 706                         chanmode = CHANNEL_A_HT40MINUS;
 707                         break;
 708                 }
 709                 break;
 710         default:
 711                 break;
 712         }
 713
 714         return chanmode;
 715 }
 716
 717 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 718                            struct ath9k_keyval *hk, const u8 *addr,
 719                            bool authenticator)
 720 {
 721         const u8 *key_rxmic;
 722         const u8 *key_txmic;
 723
 724         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 725         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 726
 727         if (addr == NULL) {
 728                 /*
 729                  * Group key installation - only two key cache entries are used
 730                  * regardless of splitmic capability since group key is only
 731                  * used either for TX or RX.
 732                  */
 733                 if (authenticator) {
 734                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 735                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 736                 } else {
 737                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 738                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 739                 }
 740                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 741         }
 742         if (!sc->splitmic) {
 743                 /* TX and RX keys share the same key cache entry. */
 744                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 745                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 746                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 747         }
 748
 749         /* Separate key cache entries for TX and RX */
 750
 751         /* TX key goes at first index, RX key at +32. */
 752         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 753         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 754                 /* TX MIC entry failed. No need to proceed further */
 755                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 756                         "Setting TX MIC Key Failed\n");
 757                 return 0;
 758         }
 759
 760         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 761         /* XXX delete tx key on failure? */
 762         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 763 }
 764
 765 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 766 {
 767         int i;
 768
 769         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 770                 if (test_bit(i, sc->keymap) ||
 771                     test_bit(i + 64, sc->keymap))
 772                         continue; /* At least one part of TKIP key allocated */
 773                 if (sc->splitmic &&
 774                     (test_bit(i + 32, sc->keymap) ||
 775                      test_bit(i + 64 + 32, sc->keymap)))
 776                         continue; /* At least one part of TKIP key allocated */
 777
 778                 /* Found a free slot for a TKIP key */
 779                 return i;
 780         }
 781         return -1;
 782 }
 783
 784 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 785 {
 786         int i;
 787
 788         /* First, try to find slots that would not be available for TKIP. */
 789         if (sc->splitmic) {
 790                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 791                         if (!test_bit(i, sc->keymap) &&
 792                             (test_bit(i + 32, sc->keymap) ||
 793                              test_bit(i + 64, sc->keymap) ||
 794                              test_bit(i + 64 + 32, sc->keymap)))
 795                                 return i;
 796                         if (!test_bit(i + 32, sc->keymap) &&
 797                             (test_bit(i, sc->keymap) ||
 798                              test_bit(i + 64, sc->keymap) ||
 799                              test_bit(i + 64 + 32, sc->keymap)))
 800                                 return i + 32;
 801                         if (!test_bit(i + 64, sc->keymap) &&
 802                             (test_bit(i , sc->keymap) ||
 803                              test_bit(i + 32, sc->keymap) ||
 804                              test_bit(i + 64 + 32, sc->keymap)))
 805                                 return i + 64;
 806                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 807                             (test_bit(i, sc->keymap) ||
 808                              test_bit(i + 32, sc->keymap) ||
 809                              test_bit(i + 64, sc->keymap)))
 810                                 return i + 64 + 32;
 811                 }
 812         } else {
 813                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 814                         if (!test_bit(i, sc->keymap) &&
 815                             test_bit(i + 64, sc->keymap))
 816                                 return i;
 817                         if (test_bit(i, sc->keymap) &&
 818                             !test_bit(i + 64, sc->keymap))
 819                                 return i + 64;
 820                 }
 821         }
 822
 823         /* No partially used TKIP slots, pick any available slot */
 824         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 825                 /* Do not allow slots that could be needed for TKIP group keys
 826                  * to be used. This limitation could be removed if we know that
 827                  * TKIP will not be used. */
 828                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 829                         continue;
 830                 if (sc->splitmic) {
 831                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 832                                 continue;
 833                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 834                                 continue;
 835                 }
 836
 837                 if (!test_bit(i, sc->keymap))
 838                         return i; /* Found a free slot for a key */
 839         }
 840
 841         /* No free slot found */
 842         return -1;
 843 }
 844
 845 static int ath_key_config(struct ath_softc *sc,
 846                           struct ieee80211_vif *vif,
 847                           struct ieee80211_sta *sta,
 848                           struct ieee80211_key_conf *key)
 849 {
 850         struct ath9k_keyval hk;
 851         const u8 *mac = NULL;
 852         int ret = 0;
 853         int idx;
 854
 855         memset(&hk, 0, sizeof(hk));
 856
 857         switch (key->alg) {
 858         case ALG_WEP:
 859                 hk.kv_type = ATH9K_CIPHER_WEP;
 860                 break;
 861         case ALG_TKIP:
 862                 hk.kv_type = ATH9K_CIPHER_TKIP;
 863                 break;
 864         case ALG_CCMP:
 865                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 866                 break;
 867         default:
 868                 return -EOPNOTSUPP;
 869         }
 870
 871         hk.kv_len = key->keylen;
 872         memcpy(hk.kv_val, key->key, key->keylen);
 873
 874         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 875                 /* For now, use the default keys for broadcast keys. This may
 876                  * need to change with virtual interfaces. */
 877                 idx = key->keyidx;
 878         } else if (key->keyidx) {
 879                 if (WARN_ON(!sta))
 880                         return -EOPNOTSUPP;
 881                 mac = sta->addr;
 882
 883                 if (vif->type != NL80211_IFTYPE_AP) {
 884                         /* Only keyidx 0 should be used with unicast key, but
 885                          * allow this for client mode for now. */
 886                         idx = key->keyidx;
 887                 } else
 888                         return -EIO;
 889         } else {
 890                 if (WARN_ON(!sta))
 891                         return -EOPNOTSUPP;
 892                 mac = sta->addr;
 893
 894                 if (key->alg == ALG_TKIP)
 895                         idx = ath_reserve_key_cache_slot_tkip(sc);
 896                 else
 897                         idx = ath_reserve_key_cache_slot(sc);
 898                 if (idx < 0)
 899                         return -ENOSPC; /* no free key cache entries */
 900         }
 901
 902         if (key->alg == ALG_TKIP)
 903                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 904                                       vif->type == NL80211_IFTYPE_AP);
 905         else
 906                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 907
 908         if (!ret)
 909                 return -EIO;
 910
 911         set_bit(idx, sc->keymap);
 912         if (key->alg == ALG_TKIP) {
 913                 set_bit(idx + 64, sc->keymap);
 914                 if (sc->splitmic) {
 915                         set_bit(idx + 32, sc->keymap);
 916                         set_bit(idx + 64 + 32, sc->keymap);
 917                 }
 918         }
 919
 920         return idx;
 921 }
 922
 923 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 924 {
 925         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 926         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 927                 return;
 928
 929         clear_bit(key->hw_key_idx, sc->keymap);
 930         if (key->alg != ALG_TKIP)
 931                 return;
 932
 933         clear_bit(key->hw_key_idx + 64, sc->keymap);
 934         if (sc->splitmic) {
 935                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 936                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 937         }
 938 }
 939
 940 static void setup_ht_cap(struct ath_softc *sc,
 941                          struct ieee80211_sta_ht_cap *ht_info)
 942 {
 943         u8 tx_streams, rx_streams;
 944
 945         ht_info->ht_supported = true;
 946         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 947                        IEEE80211_HT_CAP_SM_PS |
 948                        IEEE80211_HT_CAP_SGI_40 |
 949                        IEEE80211_HT_CAP_DSSSCCK40;
 950
 951         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 952         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 953
 954         /* set up supported mcs set */
 955         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 956         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
 957         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
 958
 959         if (tx_streams != rx_streams) {
 960                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
 961                         tx_streams, rx_streams);
 962                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 963                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 964                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 965         }
 966
 967         ht_info->mcs.rx_mask[0] = 0xff;
 968         if (rx_streams >= 2)
 969                 ht_info->mcs.rx_mask[1] = 0xff;
 970
 971         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 972 }
 973
 974 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 975                                  struct ieee80211_vif *vif,
 976                                  struct ieee80211_bss_conf *bss_conf)
 977 {
 978         struct ath_hw *ah = sc->sc_ah;
 979         struct ath_common *common = ath9k_hw_common(ah);
 980
 981         if (bss_conf->assoc) {
 982                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 983                         bss_conf->aid, common->curbssid);
 984
 985                 /* New association, store aid */
 986                 common->curaid = bss_conf->aid;
 987                 ath9k_hw_write_associd(ah);
 988
 989                 /*
 990                  * Request a re-configuration of Beacon related timers
 991                  * on the receipt of the first Beacon frame (i.e.,
 992                  * after time sync with the AP).
 993                  */
 994                 sc->sc_flags |= SC_OP_BEACON_SYNC;
 995
 996                 /* Configure the beacon */
 997                 ath_beacon_config(sc, vif);
 998
 999                 /* Reset rssi stats */
1000                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1001
1002                 ath_start_ani(sc);
1003         } else {
1004                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1005                 common->curaid = 0;
1006                 /* Stop ANI */
1007                 del_timer_sync(&sc->ani.timer);
1008         }
1009 }
1010
1011 /********************************/
1012 /*       LED functions          */
1013 /********************************/
1014
1015 static void ath_led_blink_work(struct work_struct *work)
1016 {
1017         struct ath_softc *sc = container_of(work, struct ath_softc,
1018                                             ath_led_blink_work.work);
1019
1020         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1021                 return;
1022
1023         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1024             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1025                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1026         else
1027                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1028                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1029
1030         ieee80211_queue_delayed_work(sc->hw,
1031                                      &sc->ath_led_blink_work,
1032                                      (sc->sc_flags & SC_OP_LED_ON) ?
1033                                         msecs_to_jiffies(sc->led_off_duration) :
1034                                         msecs_to_jiffies(sc->led_on_duration));
1035
1036         sc->led_on_duration = sc->led_on_cnt ?
1037                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1038                         ATH_LED_ON_DURATION_IDLE;
1039         sc->led_off_duration = sc->led_off_cnt ?
1040                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1041                         ATH_LED_OFF_DURATION_IDLE;
1042         sc->led_on_cnt = sc->led_off_cnt = 0;
1043         if (sc->sc_flags & SC_OP_LED_ON)
1044                 sc->sc_flags &= ~SC_OP_LED_ON;
1045         else
1046                 sc->sc_flags |= SC_OP_LED_ON;
1047 }
1048
1049 static void ath_led_brightness(struct led_classdev *led_cdev,
1050                                enum led_brightness brightness)
1051 {
1052         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1053         struct ath_softc *sc = led->sc;
1054
1055         switch (brightness) {
1056         case LED_OFF:
1057                 if (led->led_type == ATH_LED_ASSOC ||
1058                     led->led_type == ATH_LED_RADIO) {
1059                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1060                                 (led->led_type == ATH_LED_RADIO));
1061                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062                         if (led->led_type == ATH_LED_RADIO)
1063                                 sc->sc_flags &= ~SC_OP_LED_ON;
1064                 } else {
1065                         sc->led_off_cnt++;
1066                 }
1067                 break;
1068         case LED_FULL:
1069                 if (led->led_type == ATH_LED_ASSOC) {
1070                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1071                         ieee80211_queue_delayed_work(sc->hw,
1072                                                      &sc->ath_led_blink_work, 0);
1073                 } else if (led->led_type == ATH_LED_RADIO) {
1074                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1075                         sc->sc_flags |= SC_OP_LED_ON;
1076                 } else {
1077                         sc->led_on_cnt++;
1078                 }
1079                 break;
1080         default:
1081                 break;
1082         }
1083 }
1084
1085 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1086                             char *trigger)
1087 {
1088         int ret;
1089
1090         led->sc = sc;
1091         led->led_cdev.name = led->name;
1092         led->led_cdev.default_trigger = trigger;
1093         led->led_cdev.brightness_set = ath_led_brightness;
1094
1095         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1096         if (ret)
1097                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1098                         "Failed to register led:%s", led->name);
1099         else
1100                 led->registered = 1;
1101         return ret;
1102 }
1103
1104 static void ath_unregister_led(struct ath_led *led)
1105 {
1106         if (led->registered) {
1107                 led_classdev_unregister(&led->led_cdev);
1108                 led->registered = 0;
1109         }
1110 }
1111
1112 static void ath_deinit_leds(struct ath_softc *sc)
1113 {
1114         ath_unregister_led(&sc->assoc_led);
1115         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1116         ath_unregister_led(&sc->tx_led);
1117         ath_unregister_led(&sc->rx_led);
1118         ath_unregister_led(&sc->radio_led);
1119         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1120 }
1121
1122 static void ath_init_leds(struct ath_softc *sc)
1123 {
1124         char *trigger;
1125         int ret;
1126
1127         if (AR_SREV_9287(sc->sc_ah))
1128                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1129         else
1130                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1131
1132         /* Configure gpio 1 for output */
1133         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1134                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1135         /* LED off, active low */
1136         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1137
1138         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1139
1140         trigger = ieee80211_get_radio_led_name(sc->hw);
1141         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1142                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1143         ret = ath_register_led(sc, &sc->radio_led, trigger);
1144         sc->radio_led.led_type = ATH_LED_RADIO;
1145         if (ret)
1146                 goto fail;
1147
1148         trigger = ieee80211_get_assoc_led_name(sc->hw);
1149         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1150                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1151         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1152         sc->assoc_led.led_type = ATH_LED_ASSOC;
1153         if (ret)
1154                 goto fail;
1155
1156         trigger = ieee80211_get_tx_led_name(sc->hw);
1157         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1158                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1159         ret = ath_register_led(sc, &sc->tx_led, trigger);
1160         sc->tx_led.led_type = ATH_LED_TX;
1161         if (ret)
1162                 goto fail;
1163
1164         trigger = ieee80211_get_rx_led_name(sc->hw);
1165         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1166                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1167         ret = ath_register_led(sc, &sc->rx_led, trigger);
1168         sc->rx_led.led_type = ATH_LED_RX;
1169         if (ret)
1170                 goto fail;
1171
1172         return;
1173
1174 fail:
1175         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1176         ath_deinit_leds(sc);
1177 }
1178
1179 void ath_radio_enable(struct ath_softc *sc)
1180 {
1181         struct ath_hw *ah = sc->sc_ah;
1182         struct ieee80211_channel *channel = sc->hw->conf.channel;
1183         int r;
1184
1185         ath9k_ps_wakeup(sc);
1186         ath9k_hw_configpcipowersave(ah, 0, 0);
1187
1188         if (!ah->curchan)
1189                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190
1191         spin_lock_bh(&sc->sc_resetlock);
1192         r = ath9k_hw_reset(ah, ah->curchan, false);
1193         if (r) {
1194                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1195                         "Unable to reset channel %u (%uMhz) ",
1196                         "reset status %d\n",
1197                         channel->center_freq, r);
1198         }
1199         spin_unlock_bh(&sc->sc_resetlock);
1200
1201         ath_update_txpow(sc);
1202         if (ath_startrecv(sc) != 0) {
1203                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1204                         "Unable to restart recv logic\n");
1205                 return;
1206         }
1207
1208         if (sc->sc_flags & SC_OP_BEACONS)
1209                 ath_beacon_config(sc, NULL);    /* restart beacons */
1210
1211         /* Re-Enable  interrupts */
1212         ath9k_hw_set_interrupts(ah, sc->imask);
1213
1214         /* Enable LED */
1215         ath9k_hw_cfg_output(ah, ah->led_pin,
1216                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1217         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1218
1219         ieee80211_wake_queues(sc->hw);
1220         ath9k_ps_restore(sc);
1221 }
1222
1223 void ath_radio_disable(struct ath_softc *sc)
1224 {
1225         struct ath_hw *ah = sc->sc_ah;
1226         struct ieee80211_channel *channel = sc->hw->conf.channel;
1227         int r;
1228
1229         ath9k_ps_wakeup(sc);
1230         ieee80211_stop_queues(sc->hw);
1231
1232         /* Disable LED */
1233         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1234         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1235
1236         /* Disable interrupts */
1237         ath9k_hw_set_interrupts(ah, 0);
1238
1239         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1240         ath_stoprecv(sc);               /* turn off frame recv */
1241         ath_flushrecv(sc);              /* flush recv queue */
1242
1243         if (!ah->curchan)
1244                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1245
1246         spin_lock_bh(&sc->sc_resetlock);
1247         r = ath9k_hw_reset(ah, ah->curchan, false);
1248         if (r) {
1249                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1250                         "Unable to reset channel %u (%uMhz) "
1251                         "reset status %d\n",
1252                         channel->center_freq, r);
1253         }
1254         spin_unlock_bh(&sc->sc_resetlock);
1255
1256         ath9k_hw_phy_disable(ah);
1257         ath9k_hw_configpcipowersave(ah, 1, 1);
1258         ath9k_ps_restore(sc);
1259         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1260 }
1261
1262 /*******************/
1263 /*      Rfkill     */
1264 /*******************/
1265
1266 static bool ath_is_rfkill_set(struct ath_softc *sc)
1267 {
1268         struct ath_hw *ah = sc->sc_ah;
1269
1270         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1271                                   ah->rfkill_polarity;
1272 }
1273
1274 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1275 {
1276         struct ath_wiphy *aphy = hw->priv;
1277         struct ath_softc *sc = aphy->sc;
1278         bool blocked = !!ath_is_rfkill_set(sc);
1279
1280         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1281 }
1282
1283 static void ath_start_rfkill_poll(struct ath_softc *sc)
1284 {
1285         struct ath_hw *ah = sc->sc_ah;
1286
1287         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1289 }
1290
1291 void ath_cleanup(struct ath_softc *sc)
1292 {
1293         ath_detach(sc);
1294         free_irq(sc->irq, sc);
1295         ath_bus_cleanup(sc);
1296         kfree(sc->sec_wiphy);
1297         ieee80211_free_hw(sc->hw);
1298 }
1299
1300 void ath_detach(struct ath_softc *sc)
1301 {
1302         struct ieee80211_hw *hw = sc->hw;
1303         struct ath_hw *ah = sc->sc_ah;
1304         int i = 0;
1305
1306         ath9k_ps_wakeup(sc);
1307
1308         dev_dbg(sc->dev, "Detach ATH hw\n");
1309
1310         ath_deinit_leds(sc);
1311         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1312
1313         for (i = 0; i < sc->num_sec_wiphy; i++) {
1314                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1315                 if (aphy == NULL)
1316                         continue;
1317                 sc->sec_wiphy[i] = NULL;
1318                 ieee80211_unregister_hw(aphy->hw);
1319                 ieee80211_free_hw(aphy->hw);
1320         }
1321         ieee80211_unregister_hw(hw);
1322         ath_rx_cleanup(sc);
1323         ath_tx_cleanup(sc);
1324
1325         tasklet_kill(&sc->intr_tq);
1326         tasklet_kill(&sc->bcon_tasklet);
1327
1328         if (!(sc->sc_flags & SC_OP_INVALID))
1329                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1330
1331         /* cleanup tx queues */
1332         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1333                 if (ATH_TXQ_SETUP(sc, i))
1334                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1335
1336         if ((sc->btcoex.no_stomp_timer) &&
1337             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1338                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1339
1340         ath9k_hw_detach(ah);
1341         ath9k_exit_debug(ah);
1342         sc->sc_ah = NULL;
1343 }
1344
1345 static int ath9k_reg_notifier(struct wiphy *wiphy,
1346                               struct regulatory_request *request)
1347 {
1348         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1349         struct ath_wiphy *aphy = hw->priv;
1350         struct ath_softc *sc = aphy->sc;
1351         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1352
1353         return ath_reg_notifier_apply(wiphy, request, reg);
1354 }
1355
1356 /*
1357  * Detects if there is any priority bt traffic
1358  */
1359 static void ath_detect_bt_priority(struct ath_softc *sc)
1360 {
1361         struct ath_btcoex *btcoex = &sc->btcoex;
1362         struct ath_hw *ah = sc->sc_ah;
1363
1364         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1365                 btcoex->bt_priority_cnt++;
1366
1367         if (time_after(jiffies, btcoex->bt_priority_time +
1368                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1369                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1370                         DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1371                                 "BT priority traffic detected");
1372                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1373                 } else {
1374                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1375                 }
1376
1377                 btcoex->bt_priority_cnt = 0;
1378                 btcoex->bt_priority_time = jiffies;
1379         }
1380 }
1381
1382 /*
1383  * Configures appropriate weight based on stomp type.
1384  */
1385 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1386                                   enum ath_stomp_type stomp_type)
1387 {
1388         struct ath_hw *ah = sc->sc_ah;
1389
1390         switch (stomp_type) {
1391         case ATH_BTCOEX_STOMP_ALL:
1392                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1393                                            AR_STOMP_ALL_WLAN_WGHT);
1394                 break;
1395         case ATH_BTCOEX_STOMP_LOW:
1396                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1397                                            AR_STOMP_LOW_WLAN_WGHT);
1398                 break;
1399         case ATH_BTCOEX_STOMP_NONE:
1400                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1401                                            AR_STOMP_NONE_WLAN_WGHT);
1402                 break;
1403         default:
1404                 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1405                 break;
1406         }
1407
1408         ath9k_hw_btcoex_enable(ah);
1409 }
1410
1411 /*
1412  * This is the master bt coex timer which runs for every
1413  * 45ms, bt traffic will be given priority during 55% of this
1414  * period while wlan gets remaining 45%
1415  */
1416 static void ath_btcoex_period_timer(unsigned long data)
1417 {
1418         struct ath_softc *sc = (struct ath_softc *) data;
1419         struct ath_hw *ah = sc->sc_ah;
1420         struct ath_btcoex *btcoex = &sc->btcoex;
1421
1422         ath_detect_bt_priority(sc);
1423
1424         spin_lock_bh(&btcoex->btcoex_lock);
1425
1426         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1427
1428         spin_unlock_bh(&btcoex->btcoex_lock);
1429
1430         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1431                 if (btcoex->hw_timer_enabled)
1432                         ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1433
1434                 ath_gen_timer_start(ah,
1435                         btcoex->no_stomp_timer,
1436                         (ath9k_hw_gettsf32(ah) +
1437                                 btcoex->btcoex_no_stomp),
1438                                 btcoex->btcoex_no_stomp * 10);
1439                 btcoex->hw_timer_enabled = true;
1440         }
1441
1442         mod_timer(&btcoex->period_timer, jiffies +
1443                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1444 }
1445
1446 /*
1447  * Generic tsf based hw timer which configures weight
1448  * registers to time slice between wlan and bt traffic
1449  */
1450 static void ath_btcoex_no_stomp_timer(void *arg)
1451 {
1452         struct ath_softc *sc = (struct ath_softc *)arg;
1453         struct ath_hw *ah = sc->sc_ah;
1454         struct ath_btcoex *btcoex = &sc->btcoex;
1455
1456         DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1457
1458         spin_lock_bh(&btcoex->btcoex_lock);
1459
1460         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1461                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1462          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1463                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1464
1465         spin_unlock_bh(&btcoex->btcoex_lock);
1466 }
1467
1468 static int ath_init_btcoex_timer(struct ath_softc *sc)
1469 {
1470         struct ath_btcoex *btcoex = &sc->btcoex;
1471
1472         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1473         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1474                 btcoex->btcoex_period / 100;
1475
1476         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1477                         (unsigned long) sc);
1478
1479         spin_lock_init(&btcoex->btcoex_lock);
1480
1481         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1482                         ath_btcoex_no_stomp_timer,
1483                         ath_btcoex_no_stomp_timer,
1484                         (void *) sc, AR_FIRST_NDP_TIMER);
1485
1486         if (!btcoex->no_stomp_timer)
1487                 return -ENOMEM;
1488
1489         return 0;
1490 }
1491
1492 /*
1493  * Read and write, they both share the same lock. We do this to serialize
1494  * reads and writes on Atheros 802.11n PCI devices only. This is required
1495  * as the FIFO on these devices can only accept sanely 2 requests. After
1496  * that the device goes bananas. Serializing the reads/writes prevents this
1497  * from happening.
1498  */
1499
1500 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1501 {
1502         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1503
1504         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1505                 unsigned long flags;
1506                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1507                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1508                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1509         } else
1510                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1511 }
1512
1513 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1514 {
1515         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1516         u32 val;
1517
1518         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1519                 unsigned long flags;
1520                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1521                 val = ioread32(ah->ah_sc->mem + reg_offset);
1522                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1523         } else
1524                 val = ioread32(ah->ah_sc->mem + reg_offset);
1525         return val;
1526 }
1527
1528 static struct ath_ops ath9k_common_ops = {
1529         .read = ath9k_ioread32,
1530         .write = ath9k_iowrite32,
1531 };
1532
1533 /*
1534  * Initialize and fill ath_softc, ath_sofct is the
1535  * "Software Carrier" struct. Historically it has existed
1536  * to allow the separation between hardware specific
1537  * variables (now in ath_hw) and driver specific variables.
1538  */
1539 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1540 {
1541         struct ath_hw *ah = NULL;
1542         struct ath_common *common;
1543         int r = 0, i;
1544         int csz = 0;
1545         int qnum;
1546
1547         /* XXX: hardware will not be ready until ath_open() being called */
1548         sc->sc_flags |= SC_OP_INVALID;
1549
1550         spin_lock_init(&sc->wiphy_lock);
1551         spin_lock_init(&sc->sc_resetlock);
1552         spin_lock_init(&sc->sc_serial_rw);
1553         spin_lock_init(&sc->ani_lock);
1554         spin_lock_init(&sc->sc_pm_lock);
1555         mutex_init(&sc->mutex);
1556         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1557         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1558                      (unsigned long)sc);
1559
1560         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1561         if (!ah) {
1562                 r = -ENOMEM;
1563                 goto bad_no_ah;
1564         }
1565
1566         ah->ah_sc = sc;
1567         ah->hw_version.devid = devid;
1568         ah->hw_version.subsysid = subsysid;
1569         sc->sc_ah = ah;
1570
1571         common = ath9k_hw_common(ah);
1572         common->ops = &ath9k_common_ops;
1573         common->ah = ah;
1574         common->hw = sc->hw;
1575
1576         /*
1577          * Cache line size is used to size and align various
1578          * structures used to communicate with the hardware.
1579          */
1580         ath_read_cachesize(sc, &csz);
1581         /* XXX assert csz is non-zero */
1582         common->cachelsz = csz << 2;    /* convert to bytes */
1583
1584         if (ath9k_init_debug(ah) < 0)
1585                 dev_err(sc->dev, "Unable to create debugfs files\n");
1586
1587         r = ath9k_hw_init(ah);
1588         if (r) {
1589                 DPRINTF(ah, ATH_DBG_FATAL,
1590                         "Unable to initialize hardware; "
1591                         "initialization status: %d\n", r);
1592                 goto bad;
1593         }
1594
1595         /* Get the hardware key cache size. */
1596         sc->keymax = ah->caps.keycache_size;
1597         if (sc->keymax > ATH_KEYMAX) {
1598                 DPRINTF(ah, ATH_DBG_ANY,
1599                         "Warning, using only %u entries in %u key cache\n",
1600                         ATH_KEYMAX, sc->keymax);
1601                 sc->keymax = ATH_KEYMAX;
1602         }
1603
1604         /*
1605          * Reset the key cache since some parts do not
1606          * reset the contents on initial power up.
1607          */
1608         for (i = 0; i < sc->keymax; i++)
1609                 ath9k_hw_keyreset(ah, (u16) i);
1610
1611         /* default to MONITOR mode */
1612         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1613
1614         /* Setup rate tables */
1615
1616         ath_rate_attach(sc);
1617         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1618         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1619
1620         /*
1621          * Allocate hardware transmit queues: one queue for
1622          * beacon frames and one data queue for each QoS
1623          * priority.  Note that the hal handles reseting
1624          * these queues at the needed time.
1625          */
1626         sc->beacon.beaconq = ath_beaconq_setup(ah);
1627         if (sc->beacon.beaconq == -1) {
1628                 DPRINTF(ah, ATH_DBG_FATAL,
1629                         "Unable to setup a beacon xmit queue\n");
1630                 r = -EIO;
1631                 goto bad2;
1632         }
1633         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1634         if (sc->beacon.cabq == NULL) {
1635                 DPRINTF(ah, ATH_DBG_FATAL,
1636                         "Unable to setup CAB xmit queue\n");
1637                 r = -EIO;
1638                 goto bad2;
1639         }
1640
1641         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1642         ath_cabq_update(sc);
1643
1644         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1645                 sc->tx.hwq_map[i] = -1;
1646
1647         /* Setup data queues */
1648         /* NB: ensure BK queue is the lowest priority h/w queue */
1649         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1650                 DPRINTF(ah, ATH_DBG_FATAL,
1651                         "Unable to setup xmit queue for BK traffic\n");
1652                 r = -EIO;
1653                 goto bad2;
1654         }
1655
1656         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1657                 DPRINTF(ah, ATH_DBG_FATAL,
1658                         "Unable to setup xmit queue for BE traffic\n");
1659                 r = -EIO;
1660                 goto bad2;
1661         }
1662         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1663                 DPRINTF(ah, ATH_DBG_FATAL,
1664                         "Unable to setup xmit queue for VI traffic\n");
1665                 r = -EIO;
1666                 goto bad2;
1667         }
1668         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1669                 DPRINTF(ah, ATH_DBG_FATAL,
1670                         "Unable to setup xmit queue for VO traffic\n");
1671                 r = -EIO;
1672                 goto bad2;
1673         }
1674
1675         /* Initializes the noise floor to a reasonable default value.
1676          * Later on this will be updated during ANI processing. */
1677
1678         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1679         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1680
1681         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1682                                    ATH9K_CIPHER_TKIP, NULL)) {
1683                 /*
1684                  * Whether we should enable h/w TKIP MIC.
1685                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1686                  * report WMM capable, so it's always safe to turn on
1687                  * TKIP MIC in this case.
1688                  */
1689                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1690                                        0, 1, NULL);
1691         }
1692
1693         /*
1694          * Check whether the separate key cache entries
1695          * are required to handle both tx+rx MIC keys.
1696          * With split mic keys the number of stations is limited
1697          * to 27 otherwise 59.
1698          */
1699         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1700                                    ATH9K_CIPHER_TKIP, NULL)
1701             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1702                                       ATH9K_CIPHER_MIC, NULL)
1703             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1704                                       0, NULL))
1705                 sc->splitmic = 1;
1706
1707         /* turn on mcast key search if possible */
1708         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1709                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1710                                              1, NULL);
1711
1712         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1713
1714         /* 11n Capabilities */
1715         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1716                 sc->sc_flags |= SC_OP_TXAGGR;
1717                 sc->sc_flags |= SC_OP_RXAGGR;
1718         }
1719
1720         sc->tx_chainmask = ah->caps.tx_chainmask;
1721         sc->rx_chainmask = ah->caps.rx_chainmask;
1722
1723         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1724         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1725
1726         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1727                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1728
1729         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1730
1731         /* initialize beacon slots */
1732         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1733                 sc->beacon.bslot[i] = NULL;
1734                 sc->beacon.bslot_aphy[i] = NULL;
1735         }
1736
1737         /* setup channels and rates */
1738
1739         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1740         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1741                 sc->rates[IEEE80211_BAND_2GHZ];
1742         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1743         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1744                 ARRAY_SIZE(ath9k_2ghz_chantable);
1745
1746         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1747                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1748                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1749                         sc->rates[IEEE80211_BAND_5GHZ];
1750                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1751                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1752                         ARRAY_SIZE(ath9k_5ghz_chantable);
1753         }
1754
1755         switch (ah->btcoex_hw.scheme) {
1756         case ATH_BTCOEX_CFG_NONE:
1757                 break;
1758         case ATH_BTCOEX_CFG_2WIRE:
1759                 ath9k_hw_btcoex_init_2wire(ah);
1760                 break;
1761         case ATH_BTCOEX_CFG_3WIRE:
1762                 ath9k_hw_btcoex_init_3wire(ah);
1763                 r = ath_init_btcoex_timer(sc);
1764                 if (r)
1765                         goto bad2;
1766                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1767                 ath9k_hw_init_btcoex_hw(ah, qnum);
1768                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1769                 break;
1770         default:
1771                 WARN_ON(1);
1772                 break;
1773         }
1774
1775         return 0;
1776 bad2:
1777         /* cleanup tx queues */
1778         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1779                 if (ATH_TXQ_SETUP(sc, i))
1780                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1781 bad:
1782         ath9k_hw_detach(ah);
1783 bad_no_ah:
1784         ath9k_exit_debug(sc->sc_ah);
1785         sc->sc_ah = NULL;
1786
1787         return r;
1788 }
1789
1790 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1791 {
1792         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1793                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1794                 IEEE80211_HW_SIGNAL_DBM |
1795                 IEEE80211_HW_AMPDU_AGGREGATION |
1796                 IEEE80211_HW_SUPPORTS_PS |
1797                 IEEE80211_HW_PS_NULLFUNC_STACK |
1798                 IEEE80211_HW_SPECTRUM_MGMT;
1799
1800         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1801                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1802
1803         hw->wiphy->interface_modes =
1804                 BIT(NL80211_IFTYPE_AP) |
1805                 BIT(NL80211_IFTYPE_STATION) |
1806                 BIT(NL80211_IFTYPE_ADHOC) |
1807                 BIT(NL80211_IFTYPE_MESH_POINT);
1808
1809         hw->queues = 4;
1810         hw->max_rates = 4;
1811         hw->channel_change_time = 5000;
1812         hw->max_listen_interval = 10;
1813         /* Hardware supports 10 but we use 4 */
1814         hw->max_rate_tries = 4;
1815         hw->sta_data_size = sizeof(struct ath_node);
1816         hw->vif_data_size = sizeof(struct ath_vif);
1817
1818         hw->rate_control_algorithm = "ath9k_rate_control";
1819
1820         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1821                 &sc->sbands[IEEE80211_BAND_2GHZ];
1822         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1823                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1824                         &sc->sbands[IEEE80211_BAND_5GHZ];
1825 }
1826
1827 /* Device driver core initialization */
1828 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1829 {
1830         struct ieee80211_hw *hw = sc->hw;
1831         struct ath_common *common;
1832         struct ath_hw *ah;
1833         int error = 0, i;
1834         struct ath_regulatory *reg;
1835
1836         dev_dbg(sc->dev, "Attach ATH hw\n");
1837
1838         error = ath_init_softc(devid, sc, subsysid);
1839         if (error != 0)
1840                 return error;
1841
1842         ah = sc->sc_ah;
1843         common = ath9k_hw_common(ah);
1844
1845         /* get mac address from hardware and set in mac80211 */
1846
1847         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1848
1849         ath_set_hw_capab(sc, hw);
1850
1851         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1852                               ath9k_reg_notifier);
1853         if (error)
1854                 return error;
1855
1856         reg = &common->regulatory;
1857
1858         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1859                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1860                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1861                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1862         }
1863
1864         /* initialize tx/rx engine */
1865         error = ath_tx_init(sc, ATH_TXBUF);
1866         if (error != 0)
1867                 goto error_attach;
1868
1869         error = ath_rx_init(sc, ATH_RXBUF);
1870         if (error != 0)
1871                 goto error_attach;
1872
1873         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1874         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1875         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1876
1877         error = ieee80211_register_hw(hw);
1878
1879         if (!ath_is_world_regd(reg)) {
1880                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1881                 if (error)
1882                         goto error_attach;
1883         }
1884
1885         /* Initialize LED control */
1886         ath_init_leds(sc);
1887
1888         ath_start_rfkill_poll(sc);
1889
1890         return 0;
1891
1892 error_attach:
1893         /* cleanup tx queues */
1894         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1895                 if (ATH_TXQ_SETUP(sc, i))
1896                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1897
1898         ath9k_hw_detach(ah);
1899         ath9k_exit_debug(ah);
1900         sc->sc_ah = NULL;
1901
1902         return error;
1903 }
1904
1905 int ath_reset(struct ath_softc *sc, bool retry_tx)
1906 {
1907         struct ath_hw *ah = sc->sc_ah;
1908         struct ieee80211_hw *hw = sc->hw;
1909         int r;
1910
1911         ath9k_hw_set_interrupts(ah, 0);
1912         ath_drain_all_txq(sc, retry_tx);
1913         ath_stoprecv(sc);
1914         ath_flushrecv(sc);
1915
1916         spin_lock_bh(&sc->sc_resetlock);
1917         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1918         if (r)
1919                 DPRINTF(ah, ATH_DBG_FATAL,
1920                         "Unable to reset hardware; reset status %d\n", r);
1921         spin_unlock_bh(&sc->sc_resetlock);
1922
1923         if (ath_startrecv(sc) != 0)
1924                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1925
1926         /*
1927          * We may be doing a reset in response to a request
1928          * that changes the channel so update any state that
1929          * might change as a result.
1930          */
1931         ath_cache_conf_rate(sc, &hw->conf);
1932
1933         ath_update_txpow(sc);
1934
1935         if (sc->sc_flags & SC_OP_BEACONS)
1936                 ath_beacon_config(sc, NULL);    /* restart beacons */
1937
1938         ath9k_hw_set_interrupts(ah, sc->imask);
1939
1940         if (retry_tx) {
1941                 int i;
1942                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1943                         if (ATH_TXQ_SETUP(sc, i)) {
1944                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1945                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1946                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1947                         }
1948                 }
1949         }
1950
1951         return r;
1952 }
1953
1954 /*
1955  *  This function will allocate both the DMA descriptor structure, and the
1956  *  buffers it contains.  These are used to contain the descriptors used
1957  *  by the system.
1958 */
1959 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1960                       struct list_head *head, const char *name,
1961                       int nbuf, int ndesc)
1962 {
1963 #define DS2PHYS(_dd, _ds)                                               \
1964         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1965 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1966 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1967
1968         struct ath_desc *ds;
1969         struct ath_buf *bf;
1970         int i, bsize, error;
1971
1972         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1973                 name, nbuf, ndesc);
1974
1975         INIT_LIST_HEAD(head);
1976         /* ath_desc must be a multiple of DWORDs */
1977         if ((sizeof(struct ath_desc) % 4) != 0) {
1978                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1979                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1980                 error = -ENOMEM;
1981                 goto fail;
1982         }
1983
1984         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1985
1986         /*
1987          * Need additional DMA memory because we can't use
1988          * descriptors that cross the 4K page boundary. Assume
1989          * one skipped descriptor per 4K page.
1990          */
1991         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1992                 u32 ndesc_skipped =
1993                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1994                 u32 dma_len;
1995
1996                 while (ndesc_skipped) {
1997                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1998                         dd->dd_desc_len += dma_len;
1999
2000                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2001                 };
2002         }
2003
2004         /* allocate descriptors */
2005         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2006                                          &dd->dd_desc_paddr, GFP_KERNEL);
2007         if (dd->dd_desc == NULL) {
2008                 error = -ENOMEM;
2009                 goto fail;
2010         }
2011         ds = dd->dd_desc;
2012         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2013                 name, ds, (u32) dd->dd_desc_len,
2014                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2015
2016         /* allocate buffers */
2017         bsize = sizeof(struct ath_buf) * nbuf;
2018         bf = kzalloc(bsize, GFP_KERNEL);
2019         if (bf == NULL) {
2020                 error = -ENOMEM;
2021                 goto fail2;
2022         }
2023         dd->dd_bufptr = bf;
2024
2025         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2026                 bf->bf_desc = ds;
2027                 bf->bf_daddr = DS2PHYS(dd, ds);
2028
2029                 if (!(sc->sc_ah->caps.hw_caps &
2030                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2031                         /*
2032                          * Skip descriptor addresses which can cause 4KB
2033                          * boundary crossing (addr + length) with a 32 dword
2034                          * descriptor fetch.
2035                          */
2036                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2037                                 ASSERT((caddr_t) bf->bf_desc <
2038                                        ((caddr_t) dd->dd_desc +
2039                                         dd->dd_desc_len));
2040
2041                                 ds += ndesc;
2042                                 bf->bf_desc = ds;
2043                                 bf->bf_daddr = DS2PHYS(dd, ds);
2044                         }
2045                 }
2046                 list_add_tail(&bf->list, head);
2047         }
2048         return 0;
2049 fail2:
2050         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2051                           dd->dd_desc_paddr);
2052 fail:
2053         memset(dd, 0, sizeof(*dd));
2054         return error;
2055 #undef ATH_DESC_4KB_BOUND_CHECK
2056 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2057 #undef DS2PHYS
2058 }
2059
2060 void ath_descdma_cleanup(struct ath_softc *sc,
2061                          struct ath_descdma *dd,
2062                          struct list_head *head)
2063 {
2064         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2065                           dd->dd_desc_paddr);
2066
2067         INIT_LIST_HEAD(head);
2068         kfree(dd->dd_bufptr);
2069         memset(dd, 0, sizeof(*dd));
2070 }
2071
2072 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2073 {
2074         int qnum;
2075
2076         switch (queue) {
2077         case 0:
2078                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2079                 break;
2080         case 1:
2081                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2082                 break;
2083         case 2:
2084                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2085                 break;
2086         case 3:
2087                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2088                 break;
2089         default:
2090                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2091                 break;
2092         }
2093
2094         return qnum;
2095 }
2096
2097 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2098 {
2099         int qnum;
2100
2101         switch (queue) {
2102         case ATH9K_WME_AC_VO:
2103                 qnum = 0;
2104                 break;
2105         case ATH9K_WME_AC_VI:
2106                 qnum = 1;
2107                 break;
2108         case ATH9K_WME_AC_BE:
2109                 qnum = 2;
2110                 break;
2111         case ATH9K_WME_AC_BK:
2112                 qnum = 3;
2113                 break;
2114         default:
2115                 qnum = -1;
2116                 break;
2117         }
2118
2119         return qnum;
2120 }
2121
2122 /* XXX: Remove me once we don't depend on ath9k_channel for all
2123  * this redundant data */
2124 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2125                            struct ath9k_channel *ichan)
2126 {
2127         struct ieee80211_channel *chan = hw->conf.channel;
2128         struct ieee80211_conf *conf = &hw->conf;
2129
2130         ichan->channel = chan->center_freq;
2131         ichan->chan = chan;
2132
2133         if (chan->band == IEEE80211_BAND_2GHZ) {
2134                 ichan->chanmode = CHANNEL_G;
2135                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2136         } else {
2137                 ichan->chanmode = CHANNEL_A;
2138                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2139         }
2140
2141         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2142
2143         if (conf_is_ht(conf)) {
2144                 if (conf_is_ht40(conf))
2145                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2146
2147                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2148                                             conf->channel_type);
2149         }
2150 }
2151
2152 /**********************/
2153 /* mac80211 callbacks */
2154 /**********************/
2155
2156 /*
2157  * (Re)start btcoex timers
2158  */
2159 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2160 {
2161         struct ath_btcoex *btcoex = &sc->btcoex;
2162         struct ath_hw *ah = sc->sc_ah;
2163
2164         DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2165
2166         /* make sure duty cycle timer is also stopped when resuming */
2167         if (btcoex->hw_timer_enabled)
2168                 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2169
2170         btcoex->bt_priority_cnt = 0;
2171         btcoex->bt_priority_time = jiffies;
2172         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2173
2174         mod_timer(&btcoex->period_timer, jiffies);
2175 }
2176
2177 static int ath9k_start(struct ieee80211_hw *hw)
2178 {
2179         struct ath_wiphy *aphy = hw->priv;
2180         struct ath_softc *sc = aphy->sc;
2181         struct ath_hw *ah = sc->sc_ah;
2182         struct ieee80211_channel *curchan = hw->conf.channel;
2183         struct ath9k_channel *init_channel;
2184         int r;
2185
2186         DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
2187                 "initial channel: %d MHz\n", curchan->center_freq);
2188
2189         mutex_lock(&sc->mutex);
2190
2191         if (ath9k_wiphy_started(sc)) {
2192                 if (sc->chan_idx == curchan->hw_value) {
2193                         /*
2194                          * Already on the operational channel, the new wiphy
2195                          * can be marked active.
2196                          */
2197                         aphy->state = ATH_WIPHY_ACTIVE;
2198                         ieee80211_wake_queues(hw);
2199                 } else {
2200                         /*
2201                          * Another wiphy is on another channel, start the new
2202                          * wiphy in paused state.
2203                          */
2204                         aphy->state = ATH_WIPHY_PAUSED;
2205                         ieee80211_stop_queues(hw);
2206                 }
2207                 mutex_unlock(&sc->mutex);
2208                 return 0;
2209         }
2210         aphy->state = ATH_WIPHY_ACTIVE;
2211
2212         /* setup initial channel */
2213
2214         sc->chan_idx = curchan->hw_value;
2215
2216         init_channel = ath_get_curchannel(sc, hw);
2217
2218         /* Reset SERDES registers */
2219         ath9k_hw_configpcipowersave(ah, 0, 0);
2220
2221         /*
2222          * The basic interface to setting the hardware in a good
2223          * state is ``reset''.  On return the hardware is known to
2224          * be powered up and with interrupts disabled.  This must
2225          * be followed by initialization of the appropriate bits
2226          * and then setup of the interrupt mask.
2227          */
2228         spin_lock_bh(&sc->sc_resetlock);
2229         r = ath9k_hw_reset(ah, init_channel, false);
2230         if (r) {
2231                 DPRINTF(ah, ATH_DBG_FATAL,
2232                         "Unable to reset hardware; reset status %d "
2233                         "(freq %u MHz)\n", r,
2234                         curchan->center_freq);
2235                 spin_unlock_bh(&sc->sc_resetlock);
2236                 goto mutex_unlock;
2237         }
2238         spin_unlock_bh(&sc->sc_resetlock);
2239
2240         /*
2241          * This is needed only to setup initial state
2242          * but it's best done after a reset.
2243          */
2244         ath_update_txpow(sc);
2245
2246         /*
2247          * Setup the hardware after reset:
2248          * The receive engine is set going.
2249          * Frame transmit is handled entirely
2250          * in the frame output path; there's nothing to do
2251          * here except setup the interrupt mask.
2252          */
2253         if (ath_startrecv(sc) != 0) {
2254                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
2255                 r = -EIO;
2256                 goto mutex_unlock;
2257         }
2258
2259         /* Setup our intr mask. */
2260         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2261                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2262                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2263
2264         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2265                 sc->imask |= ATH9K_INT_GTT;
2266
2267         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2268                 sc->imask |= ATH9K_INT_CST;
2269
2270         ath_cache_conf_rate(sc, &hw->conf);
2271
2272         sc->sc_flags &= ~SC_OP_INVALID;
2273
2274         /* Disable BMISS interrupt when we're not associated */
2275         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2276         ath9k_hw_set_interrupts(ah, sc->imask);
2277
2278         ieee80211_wake_queues(hw);
2279
2280         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2281
2282         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2283             !ah->btcoex_hw.enabled) {
2284                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2285                                            AR_STOMP_LOW_WLAN_WGHT);
2286                 ath9k_hw_btcoex_enable(ah);
2287
2288                 if (sc->bus_ops->bt_coex_prep)
2289                         sc->bus_ops->bt_coex_prep(sc);
2290                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2291                         ath9k_btcoex_timer_resume(sc);
2292         }
2293
2294 mutex_unlock:
2295         mutex_unlock(&sc->mutex);
2296
2297         return r;
2298 }
2299
2300 static int ath9k_tx(struct ieee80211_hw *hw,
2301                     struct sk_buff *skb)
2302 {
2303         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2304         struct ath_wiphy *aphy = hw->priv;
2305         struct ath_softc *sc = aphy->sc;
2306         struct ath_tx_control txctl;
2307         int hdrlen, padsize;
2308
2309         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2310                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2311                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2312                 goto exit;
2313         }
2314
2315         if (sc->ps_enabled) {
2316                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2317                 /*
2318                  * mac80211 does not set PM field for normal data frames, so we
2319                  * need to update that based on the current PS mode.
2320                  */
2321                 if (ieee80211_is_data(hdr->frame_control) &&
2322                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2323                     !ieee80211_has_pm(hdr->frame_control)) {
2324                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2325                                 "while in PS mode\n");
2326                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2327                 }
2328         }
2329
2330         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2331                 /*
2332                  * We are using PS-Poll and mac80211 can request TX while in
2333                  * power save mode. Need to wake up hardware for the TX to be
2334                  * completed and if needed, also for RX of buffered frames.
2335                  */
2336                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2337                 ath9k_ps_wakeup(sc);
2338                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2339                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2340                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2341                                 "buffered frame\n");
2342                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2343                 } else {
2344                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2345                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2346                 }
2347                 /*
2348                  * The actual restore operation will happen only after
2349                  * the sc_flags bit is cleared. We are just dropping
2350                  * the ps_usecount here.
2351                  */
2352                 ath9k_ps_restore(sc);
2353         }
2354
2355         memset(&txctl, 0, sizeof(struct ath_tx_control));
2356
2357         /*
2358          * As a temporary workaround, assign seq# here; this will likely need
2359          * to be cleaned up to work better with Beacon transmission and virtual
2360          * BSSes.
2361          */
2362         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2363                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2364                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2365                         sc->tx.seq_no += 0x10;
2366                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2367                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2368         }
2369
2370         /* Add the padding after the header if this is not already done */
2371         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2372         if (hdrlen & 3) {
2373                 padsize = hdrlen % 4;
2374                 if (skb_headroom(skb) < padsize)
2375                         return -1;
2376                 skb_push(skb, padsize);
2377                 memmove(skb->data, skb->data + padsize, hdrlen);
2378         }
2379
2380         /* Check if a tx queue is available */
2381
2382         txctl.txq = ath_test_get_txq(sc, skb);
2383         if (!txctl.txq)
2384                 goto exit;
2385
2386         DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2387
2388         if (ath_tx_start(hw, skb, &txctl) != 0) {
2389                 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2390                 goto exit;
2391         }
2392
2393         return 0;
2394 exit:
2395         dev_kfree_skb_any(skb);
2396         return 0;
2397 }
2398
2399 /*
2400  * Pause btcoex timer and bt duty cycle timer
2401  */
2402 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2403 {
2404         struct ath_btcoex *btcoex = &sc->btcoex;
2405         struct ath_hw *ah = sc->sc_ah;
2406
2407         del_timer_sync(&btcoex->period_timer);
2408
2409         if (btcoex->hw_timer_enabled)
2410                 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2411
2412         btcoex->hw_timer_enabled = false;
2413 }
2414
2415 static void ath9k_stop(struct ieee80211_hw *hw)
2416 {
2417         struct ath_wiphy *aphy = hw->priv;
2418         struct ath_softc *sc = aphy->sc;
2419         struct ath_hw *ah = sc->sc_ah;
2420
2421         mutex_lock(&sc->mutex);
2422
2423         aphy->state = ATH_WIPHY_INACTIVE;
2424
2425         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2426         cancel_delayed_work_sync(&sc->tx_complete_work);
2427
2428         if (!sc->num_sec_wiphy) {
2429                 cancel_delayed_work_sync(&sc->wiphy_work);
2430                 cancel_work_sync(&sc->chan_work);
2431         }
2432
2433         if (sc->sc_flags & SC_OP_INVALID) {
2434                 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
2435                 mutex_unlock(&sc->mutex);
2436                 return;
2437         }
2438
2439         if (ath9k_wiphy_started(sc)) {
2440                 mutex_unlock(&sc->mutex);
2441                 return; /* another wiphy still in use */
2442         }
2443
2444         if (ah->btcoex_hw.enabled) {
2445                 ath9k_hw_btcoex_disable(ah);
2446                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2447                         ath9k_btcoex_timer_pause(sc);
2448         }
2449
2450         /* make sure h/w will not generate any interrupt
2451          * before setting the invalid flag. */
2452         ath9k_hw_set_interrupts(ah, 0);
2453
2454         if (!(sc->sc_flags & SC_OP_INVALID)) {
2455                 ath_drain_all_txq(sc, false);
2456                 ath_stoprecv(sc);
2457                 ath9k_hw_phy_disable(ah);
2458         } else
2459                 sc->rx.rxlink = NULL;
2460
2461         /* disable HAL and put h/w to sleep */
2462         ath9k_hw_disable(ah);
2463         ath9k_hw_configpcipowersave(ah, 1, 1);
2464         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2465
2466         sc->sc_flags |= SC_OP_INVALID;
2467
2468         mutex_unlock(&sc->mutex);
2469
2470         DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
2471 }
2472
2473 static int ath9k_add_interface(struct ieee80211_hw *hw,
2474                                struct ieee80211_if_init_conf *conf)
2475 {
2476         struct ath_wiphy *aphy = hw->priv;
2477         struct ath_softc *sc = aphy->sc;
2478         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2479         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2480         int ret = 0;
2481
2482         mutex_lock(&sc->mutex);
2483
2484         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2485             sc->nvifs > 0) {
2486                 ret = -ENOBUFS;
2487                 goto out;
2488         }
2489
2490         switch (conf->type) {
2491         case NL80211_IFTYPE_STATION:
2492                 ic_opmode = NL80211_IFTYPE_STATION;
2493                 break;
2494         case NL80211_IFTYPE_ADHOC:
2495         case NL80211_IFTYPE_AP:
2496         case NL80211_IFTYPE_MESH_POINT:
2497                 if (sc->nbcnvifs >= ATH_BCBUF) {
2498                         ret = -ENOBUFS;
2499                         goto out;
2500                 }
2501                 ic_opmode = conf->type;
2502                 break;
2503         default:
2504                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2505                         "Interface type %d not yet supported\n", conf->type);
2506                 ret = -EOPNOTSUPP;
2507                 goto out;
2508         }
2509
2510         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2511
2512         /* Set the VIF opmode */
2513         avp->av_opmode = ic_opmode;
2514         avp->av_bslot = -1;
2515
2516         sc->nvifs++;
2517
2518         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2519                 ath9k_set_bssid_mask(hw);
2520
2521         if (sc->nvifs > 1)
2522                 goto out; /* skip global settings for secondary vif */
2523
2524         if (ic_opmode == NL80211_IFTYPE_AP) {
2525                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2526                 sc->sc_flags |= SC_OP_TSF_RESET;
2527         }
2528
2529         /* Set the device opmode */
2530         sc->sc_ah->opmode = ic_opmode;
2531
2532         /*
2533          * Enable MIB interrupts when there are hardware phy counters.
2534          * Note we only do this (at the moment) for station mode.
2535          */
2536         if ((conf->type == NL80211_IFTYPE_STATION) ||
2537             (conf->type == NL80211_IFTYPE_ADHOC) ||
2538             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2539                 sc->imask |= ATH9K_INT_MIB;
2540                 sc->imask |= ATH9K_INT_TSFOOR;
2541         }
2542
2543         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2544
2545         if (conf->type == NL80211_IFTYPE_AP    ||
2546             conf->type == NL80211_IFTYPE_ADHOC ||
2547             conf->type == NL80211_IFTYPE_MONITOR)
2548                 ath_start_ani(sc);
2549
2550 out:
2551         mutex_unlock(&sc->mutex);
2552         return ret;
2553 }
2554
2555 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2556                                    struct ieee80211_if_init_conf *conf)
2557 {
2558         struct ath_wiphy *aphy = hw->priv;
2559         struct ath_softc *sc = aphy->sc;
2560         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2561         int i;
2562
2563         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2564
2565         mutex_lock(&sc->mutex);
2566
2567         /* Stop ANI */
2568         del_timer_sync(&sc->ani.timer);
2569
2570         /* Reclaim beacon resources */
2571         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2572             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2573             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2574                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2575                 ath_beacon_return(sc, avp);
2576         }
2577
2578         sc->sc_flags &= ~SC_OP_BEACONS;
2579
2580         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2581                 if (sc->beacon.bslot[i] == conf->vif) {
2582                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2583                                "slot\n", __func__);
2584                         sc->beacon.bslot[i] = NULL;
2585                         sc->beacon.bslot_aphy[i] = NULL;
2586                 }
2587         }
2588
2589         sc->nvifs--;
2590
2591         mutex_unlock(&sc->mutex);
2592 }
2593
2594 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2595 {
2596         struct ath_wiphy *aphy = hw->priv;
2597         struct ath_softc *sc = aphy->sc;
2598         struct ieee80211_conf *conf = &hw->conf;
2599         struct ath_hw *ah = sc->sc_ah;
2600         bool all_wiphys_idle = false, disable_radio = false;
2601
2602         mutex_lock(&sc->mutex);
2603
2604         /* Leave this as the first check */
2605         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2606
2607                 spin_lock_bh(&sc->wiphy_lock);
2608                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2609                 spin_unlock_bh(&sc->wiphy_lock);
2610
2611                 if (conf->flags & IEEE80211_CONF_IDLE){
2612                         if (all_wiphys_idle)
2613                                 disable_radio = true;
2614                 }
2615                 else if (all_wiphys_idle) {
2616                         ath_radio_enable(sc);
2617                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2618                                 "not-idle: enabling radio\n");
2619                 }
2620         }
2621
2622         if (changed & IEEE80211_CONF_CHANGE_PS) {
2623                 if (conf->flags & IEEE80211_CONF_PS) {
2624                         if (!(ah->caps.hw_caps &
2625                               ATH9K_HW_CAP_AUTOSLEEP)) {
2626                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2627                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2628                                         ath9k_hw_set_interrupts(sc->sc_ah,
2629                                                         sc->imask);
2630                                 }
2631                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2632                         }
2633                         sc->ps_enabled = true;
2634                 } else {
2635                         sc->ps_enabled = false;
2636                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2637                         if (!(ah->caps.hw_caps &
2638                               ATH9K_HW_CAP_AUTOSLEEP)) {
2639                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2640                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2641                                                   SC_OP_WAIT_FOR_CAB |
2642                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2643                                                   SC_OP_WAIT_FOR_TX_ACK);
2644                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2645                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2646                                         ath9k_hw_set_interrupts(sc->sc_ah,
2647                                                         sc->imask);
2648                                 }
2649                         }
2650                 }
2651         }
2652
2653         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2654                 struct ieee80211_channel *curchan = hw->conf.channel;
2655                 int pos = curchan->hw_value;
2656
2657                 aphy->chan_idx = pos;
2658                 aphy->chan_is_ht = conf_is_ht(conf);
2659
2660                 if (aphy->state == ATH_WIPHY_SCAN ||
2661                     aphy->state == ATH_WIPHY_ACTIVE)
2662                         ath9k_wiphy_pause_all_forced(sc, aphy);
2663                 else {
2664                         /*
2665                          * Do not change operational channel based on a paused
2666                          * wiphy changes.
2667                          */
2668                         goto skip_chan_change;
2669                 }
2670
2671                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2672                         curchan->center_freq);
2673
2674                 /* XXX: remove me eventualy */
2675                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2676
2677                 ath_update_chainmask(sc, conf_is_ht(conf));
2678
2679                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2680                         DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2681                         mutex_unlock(&sc->mutex);
2682                         return -EINVAL;
2683                 }
2684         }
2685
2686 skip_chan_change:
2687         if (changed & IEEE80211_CONF_CHANGE_POWER)
2688                 sc->config.txpowlimit = 2 * conf->power_level;
2689
2690         if (disable_radio) {
2691                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2692                 ath_radio_disable(sc);
2693         }
2694
2695         mutex_unlock(&sc->mutex);
2696
2697         return 0;
2698 }
2699
2700 #define SUPPORTED_FILTERS                       \
2701         (FIF_PROMISC_IN_BSS |                   \
2702         FIF_ALLMULTI |                          \
2703         FIF_CONTROL |                           \
2704         FIF_PSPOLL |                            \
2705         FIF_OTHER_BSS |                         \
2706         FIF_BCN_PRBRESP_PROMISC |               \
2707         FIF_FCSFAIL)
2708
2709 /* FIXME: sc->sc_full_reset ? */
2710 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2711                                    unsigned int changed_flags,
2712                                    unsigned int *total_flags,
2713                                    u64 multicast)
2714 {
2715         struct ath_wiphy *aphy = hw->priv;
2716         struct ath_softc *sc = aphy->sc;
2717         u32 rfilt;
2718
2719         changed_flags &= SUPPORTED_FILTERS;
2720         *total_flags &= SUPPORTED_FILTERS;
2721
2722         sc->rx.rxfilter = *total_flags;
2723         ath9k_ps_wakeup(sc);
2724         rfilt = ath_calcrxfilter(sc);
2725         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2726         ath9k_ps_restore(sc);
2727
2728         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2729 }
2730
2731 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2732                              struct ieee80211_vif *vif,
2733                              enum sta_notify_cmd cmd,
2734                              struct ieee80211_sta *sta)
2735 {
2736         struct ath_wiphy *aphy = hw->priv;
2737         struct ath_softc *sc = aphy->sc;
2738
2739         switch (cmd) {
2740         case STA_NOTIFY_ADD:
2741                 ath_node_attach(sc, sta);
2742                 break;
2743         case STA_NOTIFY_REMOVE:
2744                 ath_node_detach(sc, sta);
2745                 break;
2746         default:
2747                 break;
2748         }
2749 }
2750
2751 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2752                          const struct ieee80211_tx_queue_params *params)
2753 {
2754         struct ath_wiphy *aphy = hw->priv;
2755         struct ath_softc *sc = aphy->sc;
2756         struct ath9k_tx_queue_info qi;
2757         int ret = 0, qnum;
2758
2759         if (queue >= WME_NUM_AC)
2760                 return 0;
2761
2762         mutex_lock(&sc->mutex);
2763
2764         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2765
2766         qi.tqi_aifs = params->aifs;
2767         qi.tqi_cwmin = params->cw_min;
2768         qi.tqi_cwmax = params->cw_max;
2769         qi.tqi_burstTime = params->txop;
2770         qnum = ath_get_hal_qnum(queue, sc);
2771
2772         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2773                 "Configure tx [queue/halq] [%d/%d],  "
2774                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2775                 queue, qnum, params->aifs, params->cw_min,
2776                 params->cw_max, params->txop);
2777
2778         ret = ath_txq_update(sc, qnum, &qi);
2779         if (ret)
2780                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2781
2782         mutex_unlock(&sc->mutex);
2783
2784         return ret;
2785 }
2786
2787 static int ath9k_set_key(struct ieee80211_hw *hw,
2788                          enum set_key_cmd cmd,
2789                          struct ieee80211_vif *vif,
2790                          struct ieee80211_sta *sta,
2791                          struct ieee80211_key_conf *key)
2792 {
2793         struct ath_wiphy *aphy = hw->priv;
2794         struct ath_softc *sc = aphy->sc;
2795         int ret = 0;
2796
2797         if (modparam_nohwcrypt)
2798                 return -ENOSPC;
2799
2800         mutex_lock(&sc->mutex);
2801         ath9k_ps_wakeup(sc);
2802         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2803
2804         switch (cmd) {
2805         case SET_KEY:
2806                 ret = ath_key_config(sc, vif, sta, key);
2807                 if (ret >= 0) {
2808                         key->hw_key_idx = ret;
2809                         /* push IV and Michael MIC generation to stack */
2810                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2811                         if (key->alg == ALG_TKIP)
2812                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2813                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2814                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2815                         ret = 0;
2816                 }
2817                 break;
2818         case DISABLE_KEY:
2819                 ath_key_delete(sc, key);
2820                 break;
2821         default:
2822                 ret = -EINVAL;
2823         }
2824
2825         ath9k_ps_restore(sc);
2826         mutex_unlock(&sc->mutex);
2827
2828         return ret;
2829 }
2830
2831 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2832                                    struct ieee80211_vif *vif,
2833                                    struct ieee80211_bss_conf *bss_conf,
2834                                    u32 changed)
2835 {
2836         struct ath_wiphy *aphy = hw->priv;
2837         struct ath_softc *sc = aphy->sc;
2838         struct ath_hw *ah = sc->sc_ah;
2839         struct ath_common *common = ath9k_hw_common(ah);
2840         struct ath_vif *avp = (void *)vif->drv_priv;
2841         u32 rfilt = 0;
2842         int error, i;
2843
2844         mutex_lock(&sc->mutex);
2845
2846         /*
2847          * TODO: Need to decide which hw opmode to use for
2848          *       multi-interface cases
2849          * XXX: This belongs into add_interface!
2850          */
2851         if (vif->type == NL80211_IFTYPE_AP &&
2852             ah->opmode != NL80211_IFTYPE_AP) {
2853                 ah->opmode = NL80211_IFTYPE_STATION;
2854                 ath9k_hw_setopmode(ah);
2855                 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2856                 common->curaid = 0;
2857                 ath9k_hw_write_associd(ah);
2858                 /* Request full reset to get hw opmode changed properly */
2859                 sc->sc_flags |= SC_OP_FULL_RESET;
2860         }
2861
2862         if ((changed & BSS_CHANGED_BSSID) &&
2863             !is_zero_ether_addr(bss_conf->bssid)) {
2864                 switch (vif->type) {
2865                 case NL80211_IFTYPE_STATION:
2866                 case NL80211_IFTYPE_ADHOC:
2867                 case NL80211_IFTYPE_MESH_POINT:
2868                         /* Set BSSID */
2869                         memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2870                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2871                         common->curaid = 0;
2872                         ath9k_hw_write_associd(ah);
2873
2874                         /* Set aggregation protection mode parameters */
2875                         sc->config.ath_aggr_prot = 0;
2876
2877                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2878                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2879                                 rfilt, common->curbssid, common->curaid);
2880
2881                         /* need to reconfigure the beacon */
2882                         sc->sc_flags &= ~SC_OP_BEACONS ;
2883
2884                         break;
2885                 default:
2886                         break;
2887                 }
2888         }
2889
2890         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2891             (vif->type == NL80211_IFTYPE_AP) ||
2892             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2893                 if ((changed & BSS_CHANGED_BEACON) ||
2894                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2895                      bss_conf->enable_beacon)) {
2896                         /*
2897                          * Allocate and setup the beacon frame.
2898                          *
2899                          * Stop any previous beacon DMA.  This may be
2900                          * necessary, for example, when an ibss merge
2901                          * causes reconfiguration; we may be called
2902                          * with beacon transmission active.
2903                          */
2904                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2905
2906                         error = ath_beacon_alloc(aphy, vif);
2907                         if (!error)
2908                                 ath_beacon_config(sc, vif);
2909                 }
2910         }
2911
2912         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2913         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2914                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2915                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2916                                 ath9k_hw_keysetmac(sc->sc_ah,
2917                                                    (u16)i,
2918                                                    common->curbssid);
2919         }
2920
2921         /* Only legacy IBSS for now */
2922         if (vif->type == NL80211_IFTYPE_ADHOC)
2923                 ath_update_chainmask(sc, 0);
2924
2925         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2926                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2927                         bss_conf->use_short_preamble);
2928                 if (bss_conf->use_short_preamble)
2929                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2930                 else
2931                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2932         }
2933
2934         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2935                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2936                         bss_conf->use_cts_prot);
2937                 if (bss_conf->use_cts_prot &&
2938                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2939                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2940                 else
2941                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2942         }
2943
2944         if (changed & BSS_CHANGED_ASSOC) {
2945                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2946                         bss_conf->assoc);
2947                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2948         }
2949
2950         /*
2951          * The HW TSF has to be reset when the beacon interval changes.
2952          * We set the flag here, and ath_beacon_config_ap() would take this
2953          * into account when it gets called through the subsequent
2954          * config_interface() call - with IFCC_BEACON in the changed field.
2955          */
2956
2957         if (changed & BSS_CHANGED_BEACON_INT) {
2958                 sc->sc_flags |= SC_OP_TSF_RESET;
2959                 sc->beacon_interval = bss_conf->beacon_int;
2960         }
2961
2962         mutex_unlock(&sc->mutex);
2963 }
2964
2965 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2966 {
2967         u64 tsf;
2968         struct ath_wiphy *aphy = hw->priv;
2969         struct ath_softc *sc = aphy->sc;
2970
2971         mutex_lock(&sc->mutex);
2972         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2973         mutex_unlock(&sc->mutex);
2974
2975         return tsf;
2976 }
2977
2978 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2979 {
2980         struct ath_wiphy *aphy = hw->priv;
2981         struct ath_softc *sc = aphy->sc;
2982
2983         mutex_lock(&sc->mutex);
2984         ath9k_hw_settsf64(sc->sc_ah, tsf);
2985         mutex_unlock(&sc->mutex);
2986 }
2987
2988 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2989 {
2990         struct ath_wiphy *aphy = hw->priv;
2991         struct ath_softc *sc = aphy->sc;
2992
2993         mutex_lock(&sc->mutex);
2994
2995         ath9k_ps_wakeup(sc);
2996         ath9k_hw_reset_tsf(sc->sc_ah);
2997         ath9k_ps_restore(sc);
2998
2999         mutex_unlock(&sc->mutex);
3000 }
3001
3002 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3003                               enum ieee80211_ampdu_mlme_action action,
3004                               struct ieee80211_sta *sta,
3005                               u16 tid, u16 *ssn)
3006 {
3007         struct ath_wiphy *aphy = hw->priv;
3008         struct ath_softc *sc = aphy->sc;
3009         int ret = 0;
3010
3011         switch (action) {
3012         case IEEE80211_AMPDU_RX_START:
3013                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3014                         ret = -ENOTSUPP;
3015                 break;
3016         case IEEE80211_AMPDU_RX_STOP:
3017                 break;
3018         case IEEE80211_AMPDU_TX_START:
3019                 ath_tx_aggr_start(sc, sta, tid, ssn);
3020                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3021                 break;
3022         case IEEE80211_AMPDU_TX_STOP:
3023                 ath_tx_aggr_stop(sc, sta, tid);
3024                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3025                 break;
3026         case IEEE80211_AMPDU_TX_OPERATIONAL:
3027                 ath_tx_aggr_resume(sc, sta, tid);
3028                 break;
3029         default:
3030                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
3031         }
3032
3033         return ret;
3034 }
3035
3036 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3037 {
3038         struct ath_wiphy *aphy = hw->priv;
3039         struct ath_softc *sc = aphy->sc;
3040
3041         mutex_lock(&sc->mutex);
3042         if (ath9k_wiphy_scanning(sc)) {
3043                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3044                        "same time\n");
3045                 /*
3046                  * Do not allow the concurrent scanning state for now. This
3047                  * could be improved with scanning control moved into ath9k.
3048                  */
3049                 mutex_unlock(&sc->mutex);
3050                 return;
3051         }
3052
3053         aphy->state = ATH_WIPHY_SCAN;
3054         ath9k_wiphy_pause_all_forced(sc, aphy);
3055
3056         spin_lock_bh(&sc->ani_lock);
3057         sc->sc_flags |= SC_OP_SCANNING;
3058         spin_unlock_bh(&sc->ani_lock);
3059         mutex_unlock(&sc->mutex);
3060 }
3061
3062 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3063 {
3064         struct ath_wiphy *aphy = hw->priv;
3065         struct ath_softc *sc = aphy->sc;
3066
3067         mutex_lock(&sc->mutex);
3068         spin_lock_bh(&sc->ani_lock);
3069         aphy->state = ATH_WIPHY_ACTIVE;
3070         sc->sc_flags &= ~SC_OP_SCANNING;
3071         sc->sc_flags |= SC_OP_FULL_RESET;
3072         spin_unlock_bh(&sc->ani_lock);
3073         ath_beacon_config(sc, NULL);
3074         mutex_unlock(&sc->mutex);
3075 }
3076
3077 struct ieee80211_ops ath9k_ops = {
3078         .tx                 = ath9k_tx,
3079         .start              = ath9k_start,
3080         .stop               = ath9k_stop,
3081         .add_interface      = ath9k_add_interface,
3082         .remove_interface   = ath9k_remove_interface,
3083         .config             = ath9k_config,
3084         .configure_filter   = ath9k_configure_filter,
3085         .sta_notify         = ath9k_sta_notify,
3086         .conf_tx            = ath9k_conf_tx,
3087         .bss_info_changed   = ath9k_bss_info_changed,
3088         .set_key            = ath9k_set_key,
3089         .get_tsf            = ath9k_get_tsf,
3090         .set_tsf            = ath9k_set_tsf,
3091         .reset_tsf          = ath9k_reset_tsf,
3092         .ampdu_action       = ath9k_ampdu_action,
3093         .sw_scan_start      = ath9k_sw_scan_start,
3094         .sw_scan_complete   = ath9k_sw_scan_complete,
3095         .rfkill_poll        = ath9k_rfkill_poll_state,
3096 };
3097
3098 static struct {
3099         u32 version;
3100         const char * name;
3101 } ath_mac_bb_names[] = {
3102         { AR_SREV_VERSION_5416_PCI,     "5416" },
3103         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3104         { AR_SREV_VERSION_9100,         "9100" },
3105         { AR_SREV_VERSION_9160,         "9160" },
3106         { AR_SREV_VERSION_9280,         "9280" },
3107         { AR_SREV_VERSION_9285,         "9285" },
3108         { AR_SREV_VERSION_9287,         "9287" }
3109 };
3110
3111 static struct {
3112         u16 version;
3113         const char * name;
3114 } ath_rf_names[] = {
3115         { 0,                            "5133" },
3116         { AR_RAD5133_SREV_MAJOR,        "5133" },
3117         { AR_RAD5122_SREV_MAJOR,        "5122" },
3118         { AR_RAD2133_SREV_MAJOR,        "2133" },
3119         { AR_RAD2122_SREV_MAJOR,        "2122" }
3120 };
3121
3122 /*
3123  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3124  */
3125 const char *
3126 ath_mac_bb_name(u32 mac_bb_version)
3127 {
3128         int i;
3129
3130         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3131                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3132                         return ath_mac_bb_names[i].name;
3133                 }
3134         }
3135
3136         return "????";
3137 }
3138
3139 /*
3140  * Return the RF name. "????" is returned if the RF is unknown.
3141  */
3142 const char *
3143 ath_rf_name(u16 rf_version)
3144 {
3145         int i;
3146
3147         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3148                 if (ath_rf_names[i].version == rf_version) {
3149                         return ath_rf_names[i].name;
3150                 }
3151         }
3152
3153         return "????";
3154 }
3155
3156 static int __init ath9k_init(void)
3157 {