ath9k: separate core driver and hw timer code
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19 #include "btcoex.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
32 /* We use the hw_value as an index into our private channel structure */
33
34 #define CHAN2G(_freq, _idx)  { \
35         .center_freq = (_freq), \
36         .hw_value = (_idx), \
37         .max_power = 20, \
38 }
39
40 #define CHAN5G(_freq, _idx) { \
41         .band = IEEE80211_BAND_5GHZ, \
42         .center_freq = (_freq), \
43         .hw_value = (_idx), \
44         .max_power = 20, \
45 }
46
47 /* Some 2 GHz radios are actually tunable on 2312-2732
48  * on 5 MHz steps, we support the channels which we know
49  * we have calibration data for all cards though to make
50  * this static */
51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52         CHAN2G(2412, 0), /* Channel 1 */
53         CHAN2G(2417, 1), /* Channel 2 */
54         CHAN2G(2422, 2), /* Channel 3 */
55         CHAN2G(2427, 3), /* Channel 4 */
56         CHAN2G(2432, 4), /* Channel 5 */
57         CHAN2G(2437, 5), /* Channel 6 */
58         CHAN2G(2442, 6), /* Channel 7 */
59         CHAN2G(2447, 7), /* Channel 8 */
60         CHAN2G(2452, 8), /* Channel 9 */
61         CHAN2G(2457, 9), /* Channel 10 */
62         CHAN2G(2462, 10), /* Channel 11 */
63         CHAN2G(2467, 11), /* Channel 12 */
64         CHAN2G(2472, 12), /* Channel 13 */
65         CHAN2G(2484, 13), /* Channel 14 */
66 };
67
68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
69  * on 5 MHz steps, we support the channels which we know
70  * we have calibration data for all cards though to make
71  * this static */
72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73         /* _We_ call this UNII 1 */
74         CHAN5G(5180, 14), /* Channel 36 */
75         CHAN5G(5200, 15), /* Channel 40 */
76         CHAN5G(5220, 16), /* Channel 44 */
77         CHAN5G(5240, 17), /* Channel 48 */
78         /* _We_ call this UNII 2 */
79         CHAN5G(5260, 18), /* Channel 52 */
80         CHAN5G(5280, 19), /* Channel 56 */
81         CHAN5G(5300, 20), /* Channel 60 */
82         CHAN5G(5320, 21), /* Channel 64 */
83         /* _We_ call this "Middle band" */
84         CHAN5G(5500, 22), /* Channel 100 */
85         CHAN5G(5520, 23), /* Channel 104 */
86         CHAN5G(5540, 24), /* Channel 108 */
87         CHAN5G(5560, 25), /* Channel 112 */
88         CHAN5G(5580, 26), /* Channel 116 */
89         CHAN5G(5600, 27), /* Channel 120 */
90         CHAN5G(5620, 28), /* Channel 124 */
91         CHAN5G(5640, 29), /* Channel 128 */
92         CHAN5G(5660, 30), /* Channel 132 */
93         CHAN5G(5680, 31), /* Channel 136 */
94         CHAN5G(5700, 32), /* Channel 140 */
95         /* _We_ call this UNII 3 */
96         CHAN5G(5745, 33), /* Channel 149 */
97         CHAN5G(5765, 34), /* Channel 153 */
98         CHAN5G(5785, 35), /* Channel 157 */
99         CHAN5G(5805, 36), /* Channel 161 */
100         CHAN5G(5825, 37), /* Channel 165 */
101 };
102
103 static void ath_cache_conf_rate(struct ath_softc *sc,
104                                 struct ieee80211_conf *conf)
105 {
106         switch (conf->channel->band) {
107         case IEEE80211_BAND_2GHZ:
108                 if (conf_is_ht20(conf))
109                         sc->cur_rate_table =
110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111                 else if (conf_is_ht40_minus(conf))
112                         sc->cur_rate_table =
113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114                 else if (conf_is_ht40_plus(conf))
115                         sc->cur_rate_table =
116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
117                 else
118                         sc->cur_rate_table =
119                           sc->hw_rate_table[ATH9K_MODE_11G];
120                 break;
121         case IEEE80211_BAND_5GHZ:
122                 if (conf_is_ht20(conf))
123                         sc->cur_rate_table =
124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125                 else if (conf_is_ht40_minus(conf))
126                         sc->cur_rate_table =
127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128                 else if (conf_is_ht40_plus(conf))
129                         sc->cur_rate_table =
130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131                 else
132                         sc->cur_rate_table =
133                           sc->hw_rate_table[ATH9K_MODE_11A];
134                 break;
135         default:
136                 BUG_ON(1);
137                 break;
138         }
139 }
140
141 static void ath_update_txpow(struct ath_softc *sc)
142 {
143         struct ath_hw *ah = sc->sc_ah;
144         u32 txpow;
145
146         if (sc->curtxpow != sc->config.txpowlimit) {
147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
148                 /* read back in case value is clamped */
149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
150                 sc->curtxpow = txpow;
151         }
152 }
153
154 static u8 parse_mpdudensity(u8 mpdudensity)
155 {
156         /*
157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158          *   0 for no restriction
159          *   1 for 1/4 us
160          *   2 for 1/2 us
161          *   3 for 1 us
162          *   4 for 2 us
163          *   5 for 4 us
164          *   6 for 8 us
165          *   7 for 16 us
166          */
167         switch (mpdudensity) {
168         case 0:
169                 return 0;
170         case 1:
171         case 2:
172         case 3:
173                 /* Our lower layer calculations limit our precision to
174                    1 microsecond */
175                 return 1;
176         case 4:
177                 return 2;
178         case 5:
179                 return 4;
180         case 6:
181                 return 8;
182         case 7:
183                 return 16;
184         default:
185                 return 0;
186         }
187 }
188
189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190 {
191         const struct ath_rate_table *rate_table = NULL;
192         struct ieee80211_supported_band *sband;
193         struct ieee80211_rate *rate;
194         int i, maxrates;
195
196         switch (band) {
197         case IEEE80211_BAND_2GHZ:
198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199                 break;
200         case IEEE80211_BAND_5GHZ:
201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202                 break;
203         default:
204                 break;
205         }
206
207         if (rate_table == NULL)
208                 return;
209
210         sband = &sc->sbands[band];
211         rate = sc->rates[band];
212
213         if (rate_table->rate_cnt > ATH_RATE_MAX)
214                 maxrates = ATH_RATE_MAX;
215         else
216                 maxrates = rate_table->rate_cnt;
217
218         for (i = 0; i < maxrates; i++) {
219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220                 rate[i].hw_value = rate_table->info[i].ratecode;
221                 if (rate_table->info[i].short_preamble) {
222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
223                                 rate_table->info[i].short_preamble;
224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225                 }
226                 sband->n_bitrates++;
227
228                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
229                         rate[i].bitrate / 10, rate[i].hw_value);
230         }
231 }
232
233 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234                                                 struct ieee80211_hw *hw)
235 {
236         struct ieee80211_channel *curchan = hw->conf.channel;
237         struct ath9k_channel *channel;
238         u8 chan_idx;
239
240         chan_idx = curchan->hw_value;
241         channel = &sc->sc_ah->channels[chan_idx];
242         ath9k_update_ichannel(sc, hw, channel);
243         return channel;
244 }
245
246 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
247 {
248         unsigned long flags;
249         bool ret;
250
251         spin_lock_irqsave(&sc->sc_pm_lock, flags);
252         ret = ath9k_hw_setpower(sc->sc_ah, mode);
253         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
254
255         return ret;
256 }
257
258 void ath9k_ps_wakeup(struct ath_softc *sc)
259 {
260         unsigned long flags;
261
262         spin_lock_irqsave(&sc->sc_pm_lock, flags);
263         if (++sc->ps_usecount != 1)
264                 goto unlock;
265
266         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
267
268  unlock:
269         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
270 }
271
272 void ath9k_ps_restore(struct ath_softc *sc)
273 {
274         unsigned long flags;
275
276         spin_lock_irqsave(&sc->sc_pm_lock, flags);
277         if (--sc->ps_usecount != 0)
278                 goto unlock;
279
280         if (sc->ps_enabled &&
281             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
282                               SC_OP_WAIT_FOR_CAB |
283                               SC_OP_WAIT_FOR_PSPOLL_DATA |
284                               SC_OP_WAIT_FOR_TX_ACK)))
285                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
286
287  unlock:
288         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
289 }
290
291 /*
292  * Set/change channels.  If the channel is really being changed, it's done
293  * by reseting the chip.  To accomplish this we must first cleanup any pending
294  * DMA, then restart stuff.
295 */
296 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
297                     struct ath9k_channel *hchan)
298 {
299         struct ath_hw *ah = sc->sc_ah;
300         bool fastcc = true, stopped;
301         struct ieee80211_channel *channel = hw->conf.channel;
302         int r;
303
304         if (sc->sc_flags & SC_OP_INVALID)
305                 return -EIO;
306
307         ath9k_ps_wakeup(sc);
308
309         /*
310          * This is only performed if the channel settings have
311          * actually changed.
312          *
313          * To switch channels clear any pending DMA operations;
314          * wait long enough for the RX fifo to drain, reset the
315          * hardware at the new frequency, and then re-enable
316          * the relevant bits of the h/w.
317          */
318         ath9k_hw_set_interrupts(ah, 0);
319         ath_drain_all_txq(sc, false);
320         stopped = ath_stoprecv(sc);
321
322         /* XXX: do not flush receive queue here. We don't want
323          * to flush data frames already in queue because of
324          * changing channel. */
325
326         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
327                 fastcc = false;
328
329         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
330                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
331                 sc->sc_ah->curchan->channel,
332                 channel->center_freq, sc->tx_chan_width);
333
334         spin_lock_bh(&sc->sc_resetlock);
335
336         r = ath9k_hw_reset(ah, hchan, fastcc);
337         if (r) {
338                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
339                         "Unable to reset channel (%u Mhz) "
340                         "reset status %d\n",
341                         channel->center_freq, r);
342                 spin_unlock_bh(&sc->sc_resetlock);
343                 goto ps_restore;
344         }
345         spin_unlock_bh(&sc->sc_resetlock);
346
347         sc->sc_flags &= ~SC_OP_FULL_RESET;
348
349         if (ath_startrecv(sc) != 0) {
350                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
351                         "Unable to restart recv logic\n");
352                 r = -EIO;
353                 goto ps_restore;
354         }
355
356         ath_cache_conf_rate(sc, &hw->conf);
357         ath_update_txpow(sc);
358         ath9k_hw_set_interrupts(ah, sc->imask);
359
360  ps_restore:
361         ath9k_ps_restore(sc);
362         return r;
363 }
364
365 /*
366  *  This routine performs the periodic noise floor calibration function
367  *  that is used to adjust and optimize the chip performance.  This
368  *  takes environmental changes (location, temperature) into account.
369  *  When the task is complete, it reschedules itself depending on the
370  *  appropriate interval that was calculated.
371  */
372 static void ath_ani_calibrate(unsigned long data)
373 {
374         struct ath_softc *sc = (struct ath_softc *)data;
375         struct ath_hw *ah = sc->sc_ah;
376         bool longcal = false;
377         bool shortcal = false;
378         bool aniflag = false;
379         unsigned int timestamp = jiffies_to_msecs(jiffies);
380         u32 cal_interval, short_cal_interval;
381
382         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
383                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
384
385         /*
386         * don't calibrate when we're scanning.
387         * we are most likely not on our home channel.
388         */
389         spin_lock(&sc->ani_lock);
390         if (sc->sc_flags & SC_OP_SCANNING)
391                 goto set_timer;
392
393         /* Only calibrate if awake */
394         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
395                 goto set_timer;
396
397         ath9k_ps_wakeup(sc);
398
399         /* Long calibration runs independently of short calibration. */
400         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
401                 longcal = true;
402                 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
403                 sc->ani.longcal_timer = timestamp;
404         }
405
406         /* Short calibration applies only while caldone is false */
407         if (!sc->ani.caldone) {
408                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
409                         shortcal = true;
410                         DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
411                         sc->ani.shortcal_timer = timestamp;
412                         sc->ani.resetcal_timer = timestamp;
413                 }
414         } else {
415                 if ((timestamp - sc->ani.resetcal_timer) >=
416                     ATH_RESTART_CALINTERVAL) {
417                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
418                         if (sc->ani.caldone)
419                                 sc->ani.resetcal_timer = timestamp;
420                 }
421         }
422
423         /* Verify whether we must check ANI */
424         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
425                 aniflag = true;
426                 sc->ani.checkani_timer = timestamp;
427         }
428
429         /* Skip all processing if there's nothing to do. */
430         if (longcal || shortcal || aniflag) {
431                 /* Call ANI routine if necessary */
432                 if (aniflag)
433                         ath9k_hw_ani_monitor(ah, ah->curchan);
434
435                 /* Perform calibration if necessary */
436                 if (longcal || shortcal) {
437                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
438                                                      sc->rx_chainmask, longcal);
439
440                         if (longcal)
441                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
442                                                                      ah->curchan);
443
444                         DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
445                                 ah->curchan->channel, ah->curchan->channelFlags,
446                                 sc->ani.noise_floor);
447                 }
448         }
449
450         ath9k_ps_restore(sc);
451
452 set_timer:
453         spin_unlock(&sc->ani_lock);
454         /*
455         * Set timer interval based on previous results.
456         * The interval must be the shortest necessary to satisfy ANI,
457         * short calibration and long calibration.
458         */
459         cal_interval = ATH_LONG_CALINTERVAL;
460         if (sc->sc_ah->config.enable_ani)
461                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
462         if (!sc->ani.caldone)
463                 cal_interval = min(cal_interval, (u32)short_cal_interval);
464
465         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
466 }
467
468 static void ath_start_ani(struct ath_softc *sc)
469 {
470         unsigned long timestamp = jiffies_to_msecs(jiffies);
471
472         sc->ani.longcal_timer = timestamp;
473         sc->ani.shortcal_timer = timestamp;
474         sc->ani.checkani_timer = timestamp;
475
476         mod_timer(&sc->ani.timer,
477                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
478 }
479
480 /*
481  * Update tx/rx chainmask. For legacy association,
482  * hard code chainmask to 1x1, for 11n association, use
483  * the chainmask configuration, for bt coexistence, use
484  * the chainmask configuration even in legacy mode.
485  */
486 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
487 {
488         struct ath_hw *ah = sc->sc_ah;
489
490         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
491             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
492                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
493                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
494         } else {
495                 sc->tx_chainmask = 1;
496                 sc->rx_chainmask = 1;
497         }
498
499         DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
500                 sc->tx_chainmask, sc->rx_chainmask);
501 }
502
503 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
504 {
505         struct ath_node *an;
506
507         an = (struct ath_node *)sta->drv_priv;
508
509         if (sc->sc_flags & SC_OP_TXAGGR) {
510                 ath_tx_node_init(sc, an);
511                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
512                                      sta->ht_cap.ampdu_factor);
513                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
514                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
515         }
516 }
517
518 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
519 {
520         struct ath_node *an = (struct ath_node *)sta->drv_priv;
521
522         if (sc->sc_flags & SC_OP_TXAGGR)
523                 ath_tx_node_cleanup(sc, an);
524 }
525
526 static void ath9k_tasklet(unsigned long data)
527 {
528         struct ath_softc *sc = (struct ath_softc *)data;
529         struct ath_hw *ah = sc->sc_ah;
530
531         u32 status = sc->intrstatus;
532
533         ath9k_ps_wakeup(sc);
534
535         if (status & ATH9K_INT_FATAL) {
536                 ath_reset(sc, false);
537                 ath9k_ps_restore(sc);
538                 return;
539         }
540
541         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
542                 spin_lock_bh(&sc->rx.rxflushlock);
543                 ath_rx_tasklet(sc, 0);
544                 spin_unlock_bh(&sc->rx.rxflushlock);
545         }
546
547         if (status & ATH9K_INT_TX)
548                 ath_tx_tasklet(sc);
549
550         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
551                 /*
552                  * TSF sync does not look correct; remain awake to sync with
553                  * the next Beacon.
554                  */
555                 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
556                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
557         }
558
559         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
560                 if (status & ATH9K_INT_GENTIMER)
561                         ath_gen_timer_isr(sc->sc_ah);
562
563         /* re-enable hardware interrupt */
564         ath9k_hw_set_interrupts(ah, sc->imask);
565         ath9k_ps_restore(sc);
566 }
567
568 irqreturn_t ath_isr(int irq, void *dev)
569 {
570 #define SCHED_INTR (                            \
571                 ATH9K_INT_FATAL |               \
572                 ATH9K_INT_RXORN |               \
573                 ATH9K_INT_RXEOL |               \
574                 ATH9K_INT_RX |                  \
575                 ATH9K_INT_TX |                  \
576                 ATH9K_INT_BMISS |               \
577                 ATH9K_INT_CST |                 \
578                 ATH9K_INT_TSFOOR |              \
579                 ATH9K_INT_GENTIMER)
580
581         struct ath_softc *sc = dev;
582         struct ath_hw *ah = sc->sc_ah;
583         enum ath9k_int status;
584         bool sched = false;
585
586         /*
587          * The hardware is not ready/present, don't
588          * touch anything. Note this can happen early
589          * on if the IRQ is shared.
590          */
591         if (sc->sc_flags & SC_OP_INVALID)
592                 return IRQ_NONE;
593
594
595         /* shared irq, not for us */
596
597         if (!ath9k_hw_intrpend(ah))
598                 return IRQ_NONE;
599
600         /*
601          * Figure out the reason(s) for the interrupt.  Note
602          * that the hal returns a pseudo-ISR that may include
603          * bits we haven't explicitly enabled so we mask the
604          * value to insure we only process bits we requested.
605          */
606         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
607         status &= sc->imask;    /* discard unasked-for bits */
608
609         /*
610          * If there are no status bits set, then this interrupt was not
611          * for me (should have been caught above).
612          */
613         if (!status)
614                 return IRQ_NONE;
615
616         /* Cache the status */
617         sc->intrstatus = status;
618
619         if (status & SCHED_INTR)
620                 sched = true;
621
622         /*
623          * If a FATAL or RXORN interrupt is received, we have to reset the
624          * chip immediately.
625          */
626         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
627                 goto chip_reset;
628
629         if (status & ATH9K_INT_SWBA)
630                 tasklet_schedule(&sc->bcon_tasklet);
631
632         if (status & ATH9K_INT_TXURN)
633                 ath9k_hw_updatetxtriglevel(ah, true);
634
635         if (status & ATH9K_INT_MIB) {
636                 /*
637                  * Disable interrupts until we service the MIB
638                  * interrupt; otherwise it will continue to
639                  * fire.
640                  */
641                 ath9k_hw_set_interrupts(ah, 0);
642                 /*
643                  * Let the hal handle the event. We assume
644                  * it will clear whatever condition caused
645                  * the interrupt.
646                  */
647                 ath9k_hw_procmibevent(ah);
648                 ath9k_hw_set_interrupts(ah, sc->imask);
649         }
650
651         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
652                 if (status & ATH9K_INT_TIM_TIMER) {
653                         /* Clear RxAbort bit so that we can
654                          * receive frames */
655                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
656                         ath9k_hw_setrxabort(sc->sc_ah, 0);
657                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
658                 }
659
660 chip_reset:
661
662         ath_debug_stat_interrupt(sc, status);
663
664         if (sched) {
665                 /* turn off every interrupt except SWBA */
666                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
667                 tasklet_schedule(&sc->intr_tq);
668         }
669
670         return IRQ_HANDLED;
671
672 #undef SCHED_INTR
673 }
674
675 static u32 ath_get_extchanmode(struct ath_softc *sc,
676                                struct ieee80211_channel *chan,
677                                enum nl80211_channel_type channel_type)
678 {
679         u32 chanmode = 0;
680
681         switch (chan->band) {
682         case IEEE80211_BAND_2GHZ:
683                 switch(channel_type) {
684                 case NL80211_CHAN_NO_HT:
685                 case NL80211_CHAN_HT20:
686                         chanmode = CHANNEL_G_HT20;
687                         break;
688                 case NL80211_CHAN_HT40PLUS:
689                         chanmode = CHANNEL_G_HT40PLUS;
690                         break;
691                 case NL80211_CHAN_HT40MINUS:
692                         chanmode = CHANNEL_G_HT40MINUS;
693                         break;
694                 }
695                 break;
696         case IEEE80211_BAND_5GHZ:
697                 switch(channel_type) {
698                 case NL80211_CHAN_NO_HT:
699                 case NL80211_CHAN_HT20:
700                         chanmode = CHANNEL_A_HT20;
701                         break;
702                 case NL80211_CHAN_HT40PLUS:
703                         chanmode = CHANNEL_A_HT40PLUS;
704                         break;
705                 case NL80211_CHAN_HT40MINUS:
706                         chanmode = CHANNEL_A_HT40MINUS;
707                         break;
708                 }
709                 break;
710         default:
711                 break;
712         }
713
714         return chanmode;
715 }
716
717 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
718                            struct ath9k_keyval *hk, const u8 *addr,
719                            bool authenticator)
720 {
721         const u8 *key_rxmic;
722         const u8 *key_txmic;
723
724         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
725         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
726
727         if (addr == NULL) {
728                 /*
729                  * Group key installation - only two key cache entries are used
730                  * regardless of splitmic capability since group key is only
731                  * used either for TX or RX.
732                  */
733                 if (authenticator) {
734                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
735                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
736                 } else {
737                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
738                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
739                 }
740                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
741         }
742         if (!sc->splitmic) {
743                 /* TX and RX keys share the same key cache entry. */
744                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
745                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
746                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
747         }
748
749         /* Separate key cache entries for TX and RX */
750
751         /* TX key goes at first index, RX key at +32. */
752         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
753         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
754                 /* TX MIC entry failed. No need to proceed further */
755                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
756                         "Setting TX MIC Key Failed\n");
757                 return 0;
758         }
759
760         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
761         /* XXX delete tx key on failure? */
762         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
763 }
764
765 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
766 {
767         int i;
768
769         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
770                 if (test_bit(i, sc->keymap) ||
771                     test_bit(i + 64, sc->keymap))
772                         continue; /* At least one part of TKIP key allocated */
773                 if (sc->splitmic &&
774                     (test_bit(i + 32, sc->keymap) ||
775                      test_bit(i + 64 + 32, sc->keymap)))
776                         continue; /* At least one part of TKIP key allocated */
777
778                 /* Found a free slot for a TKIP key */
779                 return i;
780         }
781         return -1;
782 }
783
784 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
785 {
786         int i;
787
788         /* First, try to find slots that would not be available for TKIP. */
789         if (sc->splitmic) {
790                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
791                         if (!test_bit(i, sc->keymap) &&
792                             (test_bit(i + 32, sc->keymap) ||
793                              test_bit(i + 64, sc->keymap) ||
794                              test_bit(i + 64 + 32, sc->keymap)))
795                                 return i;
796                         if (!test_bit(i + 32, sc->keymap) &&
797                             (test_bit(i, sc->keymap) ||
798                              test_bit(i + 64, sc->keymap) ||
799                              test_bit(i + 64 + 32, sc->keymap)))
800                                 return i + 32;
801                         if (!test_bit(i + 64, sc->keymap) &&
802                             (test_bit(i , sc->keymap) ||
803                              test_bit(i + 32, sc->keymap) ||
804                              test_bit(i + 64 + 32, sc->keymap)))
805                                 return i + 64;
806                         if (!test_bit(i + 64 + 32, sc->keymap) &&
807                             (test_bit(i, sc->keymap) ||
808                              test_bit(i + 32, sc->keymap) ||
809                              test_bit(i + 64, sc->keymap)))
810                                 return i + 64 + 32;
811                 }
812         } else {
813                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
814                         if (!test_bit(i, sc->keymap) &&
815                             test_bit(i + 64, sc->keymap))
816                                 return i;
817                         if (test_bit(i, sc->keymap) &&
818                             !test_bit(i + 64, sc->keymap))
819                                 return i + 64;
820                 }
821         }
822
823         /* No partially used TKIP slots, pick any available slot */
824         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
825                 /* Do not allow slots that could be needed for TKIP group keys
826                  * to be used. This limitation could be removed if we know that
827                  * TKIP will not be used. */
828                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
829                         continue;
830                 if (sc->splitmic) {
831                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
832                                 continue;
833                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
834                                 continue;
835                 }
836
837                 if (!test_bit(i, sc->keymap))
838                         return i; /* Found a free slot for a key */
839         }
840
841         /* No free slot found */
842         return -1;
843 }
844
845 static int ath_key_config(struct ath_softc *sc,
846                           struct ieee80211_vif *vif,
847                           struct ieee80211_sta *sta,
848                           struct ieee80211_key_conf *key)
849 {
850         struct ath9k_keyval hk;
851         const u8 *mac = NULL;
852         int ret = 0;
853         int idx;
854
855         memset(&hk, 0, sizeof(hk));
856
857         switch (key->alg) {
858         case ALG_WEP:
859                 hk.kv_type = ATH9K_CIPHER_WEP;
860                 break;
861         case ALG_TKIP:
862                 hk.kv_type = ATH9K_CIPHER_TKIP;
863                 break;
864         case ALG_CCMP:
865                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
866                 break;
867         default:
868                 return -EOPNOTSUPP;
869         }
870
871         hk.kv_len = key->keylen;
872         memcpy(hk.kv_val, key->key, key->keylen);
873
874         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
875                 /* For now, use the default keys for broadcast keys. This may
876                  * need to change with virtual interfaces. */
877                 idx = key->keyidx;
878         } else if (key->keyidx) {
879                 if (WARN_ON(!sta))
880                         return -EOPNOTSUPP;
881                 mac = sta->addr;
882
883                 if (vif->type != NL80211_IFTYPE_AP) {
884                         /* Only keyidx 0 should be used with unicast key, but
885                          * allow this for client mode for now. */
886                         idx = key->keyidx;
887                 } else
888                         return -EIO;
889         } else {
890                 if (WARN_ON(!sta))
891                         return -EOPNOTSUPP;
892                 mac = sta->addr;
893
894                 if (key->alg == ALG_TKIP)
895                         idx = ath_reserve_key_cache_slot_tkip(sc);
896                 else
897                         idx = ath_reserve_key_cache_slot(sc);
898                 if (idx < 0)
899                         return -ENOSPC; /* no free key cache entries */
900         }
901
902         if (key->alg == ALG_TKIP)
903                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
904                                       vif->type == NL80211_IFTYPE_AP);
905         else
906                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
907
908         if (!ret)
909                 return -EIO;
910
911         set_bit(idx, sc->keymap);
912         if (key->alg == ALG_TKIP) {
913                 set_bit(idx + 64, sc->keymap);
914                 if (sc->splitmic) {
915                         set_bit(idx + 32, sc->keymap);
916                         set_bit(idx + 64 + 32, sc->keymap);
917                 }
918         }
919
920         return idx;
921 }
922
923 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
924 {
925         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
926         if (key->hw_key_idx < IEEE80211_WEP_NKID)
927                 return;
928
929         clear_bit(key->hw_key_idx, sc->keymap);
930         if (key->alg != ALG_TKIP)
931                 return;
932
933         clear_bit(key->hw_key_idx + 64, sc->keymap);
934         if (sc->splitmic) {
935                 clear_bit(key->hw_key_idx + 32, sc->keymap);
936                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
937         }
938 }
939
940 static void setup_ht_cap(struct ath_softc *sc,
941                          struct ieee80211_sta_ht_cap *ht_info)
942 {
943         u8 tx_streams, rx_streams;
944
945         ht_info->ht_supported = true;
946         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
947                        IEEE80211_HT_CAP_SM_PS |
948                        IEEE80211_HT_CAP_SGI_40 |
949                        IEEE80211_HT_CAP_DSSSCCK40;
950
951         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
952         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
953
954         /* set up supported mcs set */
955         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
956         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
957         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
958
959         if (tx_streams != rx_streams) {
960                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
961                         tx_streams, rx_streams);
962                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
963                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
964                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
965         }
966
967         ht_info->mcs.rx_mask[0] = 0xff;
968         if (rx_streams >= 2)
969                 ht_info->mcs.rx_mask[1] = 0xff;
970
971         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
972 }
973
974 static void ath9k_bss_assoc_info(struct ath_softc *sc,
975                                  struct ieee80211_vif *vif,
976                                  struct ieee80211_bss_conf *bss_conf)
977 {
978         struct ath_hw *ah = sc->sc_ah;
979         struct ath_common *common = ath9k_hw_common(ah);
980
981         if (bss_conf->assoc) {
982                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
983                         bss_conf->aid, common->curbssid);
984
985                 /* New association, store aid */
986                 common->curaid = bss_conf->aid;
987                 ath9k_hw_write_associd(ah);
988
989                 /*
990                  * Request a re-configuration of Beacon related timers
991                  * on the receipt of the first Beacon frame (i.e.,
992                  * after time sync with the AP).
993                  */
994                 sc->sc_flags |= SC_OP_BEACON_SYNC;
995
996                 /* Configure the beacon */
997                 ath_beacon_config(sc, vif);
998
999                 /* Reset rssi stats */
1000                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1001
1002                 ath_start_ani(sc);
1003         } else {
1004                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1005                 common->curaid = 0;
1006                 /* Stop ANI */
1007                 del_timer_sync(&sc->ani.timer);
1008         }
1009 }
1010
1011 /********************************/
1012 /*       LED functions          */
1013 /********************************/
1014
1015 static void ath_led_blink_work(struct work_struct *work)
1016 {
1017         struct ath_softc *sc = container_of(work, struct ath_softc,
1018                                             ath_led_blink_work.work);
1019
1020         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1021                 return;
1022
1023         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1024             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1025                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1026         else
1027                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1028                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1029
1030         ieee80211_queue_delayed_work(sc->hw,
1031                                      &sc->ath_led_blink_work,
1032                                      (sc->sc_flags & SC_OP_LED_ON) ?
1033                                         msecs_to_jiffies(sc->led_off_duration) :
1034                                         msecs_to_jiffies(sc->led_on_duration));
1035
1036         sc->led_on_duration = sc->led_on_cnt ?
1037                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1038                         ATH_LED_ON_DURATION_IDLE;
1039         sc->led_off_duration = sc->led_off_cnt ?
1040                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1041                         ATH_LED_OFF_DURATION_IDLE;
1042         sc->led_on_cnt = sc->led_off_cnt = 0;
1043         if (sc->sc_flags & SC_OP_LED_ON)
1044                 sc->sc_flags &= ~SC_OP_LED_ON;
1045         else
1046                 sc->sc_flags |= SC_OP_LED_ON;
1047 }
1048
1049 static void ath_led_brightness(struct led_classdev *led_cdev,
1050                                enum led_brightness brightness)
1051 {
1052         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1053         struct ath_softc *sc = led->sc;
1054
1055         switch (brightness) {
1056         case LED_OFF:
1057                 if (led->led_type == ATH_LED_ASSOC ||
1058                     led->led_type == ATH_LED_RADIO) {
1059                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1060                                 (led->led_type == ATH_LED_RADIO));
1061                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062                         if (led->led_type == ATH_LED_RADIO)
1063                                 sc->sc_flags &= ~SC_OP_LED_ON;
1064                 } else {
1065                         sc->led_off_cnt++;
1066                 }
1067                 break;
1068         case LED_FULL:
1069                 if (led->led_type == ATH_LED_ASSOC) {
1070                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1071                         ieee80211_queue_delayed_work(sc->hw,
1072                                                      &sc->ath_led_blink_work, 0);
1073                 } else if (led->led_type == ATH_LED_RADIO) {
1074                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1075                         sc->sc_flags |= SC_OP_LED_ON;
1076                 } else {
1077                         sc->led_on_cnt++;
1078                 }
1079                 break;
1080         default:
1081                 break;
1082         }
1083 }
1084
1085 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1086                             char *trigger)
1087 {
1088         int ret;
1089
1090         led->sc = sc;
1091         led->led_cdev.name = led->name;
1092         led->led_cdev.default_trigger = trigger;
1093         led->led_cdev.brightness_set = ath_led_brightness;
1094
1095         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1096         if (ret)
1097                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1098                         "Failed to register led:%s", led->name);
1099         else
1100                 led->registered = 1;
1101         return ret;
1102 }
1103
1104 static void ath_unregister_led(struct ath_led *led)
1105 {
1106         if (led->registered) {
1107                 led_classdev_unregister(&led->led_cdev);
1108                 led->registered = 0;
1109         }
1110 }
1111
1112 static void ath_deinit_leds(struct ath_softc *sc)
1113 {
1114         ath_unregister_led(&sc->assoc_led);
1115         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1116         ath_unregister_led(&sc->tx_led);
1117         ath_unregister_led(&sc->rx_led);
1118         ath_unregister_led(&sc->radio_led);
1119         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1120 }
1121
1122 static void ath_init_leds(struct ath_softc *sc)
1123 {
1124         char *trigger;
1125         int ret;
1126
1127         if (AR_SREV_9287(sc->sc_ah))
1128                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1129         else
1130                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1131
1132         /* Configure gpio 1 for output */
1133         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1134                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1135         /* LED off, active low */
1136         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1137
1138         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1139
1140         trigger = ieee80211_get_radio_led_name(sc->hw);
1141         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1142                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1143         ret = ath_register_led(sc, &sc->radio_led, trigger);
1144         sc->radio_led.led_type = ATH_LED_RADIO;
1145         if (ret)
1146                 goto fail;
1147
1148         trigger = ieee80211_get_assoc_led_name(sc->hw);
1149         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1150                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1151         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1152         sc->assoc_led.led_type = ATH_LED_ASSOC;
1153         if (ret)
1154                 goto fail;
1155
1156         trigger = ieee80211_get_tx_led_name(sc->hw);
1157         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1158                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1159         ret = ath_register_led(sc, &sc->tx_led, trigger);
1160         sc->tx_led.led_type = ATH_LED_TX;
1161         if (ret)
1162                 goto fail;
1163
1164         trigger = ieee80211_get_rx_led_name(sc->hw);
1165         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1166                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1167         ret = ath_register_led(sc, &sc->rx_led, trigger);
1168         sc->rx_led.led_type = ATH_LED_RX;
1169         if (ret)
1170                 goto fail;
1171
1172         return;
1173
1174 fail:
1175         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1176         ath_deinit_leds(sc);
1177 }
1178
1179 void ath_radio_enable(struct ath_softc *sc)
1180 {
1181         struct ath_hw *ah = sc->sc_ah;
1182         struct ieee80211_channel *channel = sc->hw->conf.channel;
1183         int r;
1184
1185         ath9k_ps_wakeup(sc);
1186         ath9k_hw_configpcipowersave(ah, 0, 0);
1187
1188         if (!ah->curchan)
1189                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190
1191         spin_lock_bh(&sc->sc_resetlock);
1192         r = ath9k_hw_reset(ah, ah->curchan, false);
1193         if (r) {
1194                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1195                         "Unable to reset channel %u (%uMhz) ",
1196                         "reset status %d\n",
1197                         channel->center_freq, r);
1198         }
1199         spin_unlock_bh(&sc->sc_resetlock);
1200
1201         ath_update_txpow(sc);
1202         if (ath_startrecv(sc) != 0) {
1203                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1204                         "Unable to restart recv logic\n");
1205                 return;
1206         }
1207
1208         if (sc->sc_flags & SC_OP_BEACONS)
1209                 ath_beacon_config(sc, NULL);    /* restart beacons */
1210
1211         /* Re-Enable  interrupts */
1212         ath9k_hw_set_interrupts(ah, sc->imask);
1213
1214         /* Enable LED */
1215         ath9k_hw_cfg_output(ah, ah->led_pin,
1216                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1217         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1218
1219         ieee80211_wake_queues(sc->hw);
1220         ath9k_ps_restore(sc);
1221 }
1222
1223 void ath_radio_disable(struct ath_softc *sc)
1224 {
1225         struct ath_hw *ah = sc->sc_ah;
1226         struct ieee80211_channel *channel = sc->hw->conf.channel;
1227         int r;
1228
1229         ath9k_ps_wakeup(sc);
1230         ieee80211_stop_queues(sc->hw);
1231
1232         /* Disable LED */
1233         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1234         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1235
1236         /* Disable interrupts */
1237         ath9k_hw_set_interrupts(ah, 0);
1238
1239         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1240         ath_stoprecv(sc);               /* turn off frame recv */
1241         ath_flushrecv(sc);              /* flush recv queue */
1242
1243         if (!ah->curchan)
1244                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1245
1246         spin_lock_bh(&sc->sc_resetlock);
1247         r = ath9k_hw_reset(ah, ah->curchan, false);
1248         if (r) {
1249                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1250                         "Unable to reset channel %u (%uMhz) "
1251                         "reset status %d\n",
1252                         channel->center_freq, r);
1253         }
1254         spin_unlock_bh(&sc->sc_resetlock);
1255
1256         ath9k_hw_phy_disable(ah);
1257         ath9k_hw_configpcipowersave(ah, 1, 1);
1258         ath9k_ps_restore(sc);
1259         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1260 }
1261
1262 /*******************/
1263 /*      Rfkill     */
1264 /*******************/
1265
1266 static bool ath_is_rfkill_set(struct ath_softc *sc)
1267 {
1268         struct ath_hw *ah = sc->sc_ah;
1269
1270         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1271                                   ah->rfkill_polarity;
1272 }
1273
1274 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1275 {
1276         struct ath_wiphy *aphy = hw->priv;
1277         struct ath_softc *sc = aphy->sc;
1278         bool blocked = !!ath_is_rfkill_set(sc);
1279
1280         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1281 }
1282
1283 static void ath_start_rfkill_poll(struct ath_softc *sc)
1284 {
1285         struct ath_hw *ah = sc->sc_ah;
1286
1287         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1289 }
1290
1291 void ath_cleanup(struct ath_softc *sc)
1292 {
1293         ath_detach(sc);
1294         free_irq(sc->irq, sc);
1295         ath_bus_cleanup(sc);
1296         kfree(sc->sec_wiphy);
1297         ieee80211_free_hw(sc->hw);
1298 }
1299
1300 void ath_detach(struct ath_softc *sc)
1301 {
1302         struct ieee80211_hw *hw = sc->hw;
1303         struct ath_hw *ah = sc->sc_ah;
1304         int i = 0;
1305
1306         ath9k_ps_wakeup(sc);
1307
1308         dev_dbg(sc->dev, "Detach ATH hw\n");
1309
1310         ath_deinit_leds(sc);
1311         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1312
1313         for (i = 0; i < sc->num_sec_wiphy; i++) {
1314                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1315                 if (aphy == NULL)
1316                         continue;
1317                 sc->sec_wiphy[i] = NULL;
1318                 ieee80211_unregister_hw(aphy->hw);
1319                 ieee80211_free_hw(aphy->hw);
1320         }
1321         ieee80211_unregister_hw(hw);
1322         ath_rx_cleanup(sc);
1323         ath_tx_cleanup(sc);
1324
1325         tasklet_kill(&sc->intr_tq);
1326         tasklet_kill(&sc->bcon_tasklet);
1327
1328         if (!(sc->sc_flags & SC_OP_INVALID))
1329                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1330
1331         /* cleanup tx queues */
1332         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1333                 if (ATH_TXQ_SETUP(sc, i))
1334                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1335
1336         if ((sc->btcoex.no_stomp_timer) &&
1337             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1338                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1339
1340         ath9k_hw_detach(ah);
1341         ath9k_exit_debug(ah);
1342         sc->sc_ah = NULL;
1343 }
1344
1345 static int ath9k_reg_notifier(struct wiphy *wiphy,
1346                               struct regulatory_request *request)
1347 {
1348         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1349         struct ath_wiphy *aphy = hw->priv;
1350         struct ath_softc *sc = aphy->sc;
1351         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1352
1353         return ath_reg_notifier_apply(wiphy, request, reg);
1354 }
1355
1356 /*
1357  * Detects if there is any priority bt traffic
1358  */
1359 static void ath_detect_bt_priority(struct ath_softc *sc)
1360 {
1361         struct ath_btcoex *btcoex = &sc->btcoex;
1362         struct ath_hw *ah = sc->sc_ah;
1363
1364         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1365                 btcoex->bt_priority_cnt++;
1366
1367         if (time_after(jiffies, btcoex->bt_priority_time +
1368                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1369                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1370                         DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1371                                 "BT priority traffic detected");
1372                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1373                 } else {
1374                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1375                 }
1376
1377                 btcoex->bt_priority_cnt = 0;
1378                 btcoex->bt_priority_time = jiffies;
1379         }
1380 }
1381
1382 /*
1383  * Configures appropriate weight based on stomp type.
1384  */
1385 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1386                                   enum ath_stomp_type stomp_type)
1387 {
1388         struct ath_hw *ah = sc->sc_ah;
1389
1390         switch (stomp_type) {
1391         case ATH_BTCOEX_STOMP_ALL:
1392                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1393                                            AR_STOMP_ALL_WLAN_WGHT);
1394                 break;
1395         case ATH_BTCOEX_STOMP_LOW:
1396                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1397                                            AR_STOMP_LOW_WLAN_WGHT);
1398                 break;
1399         case ATH_BTCOEX_STOMP_NONE:
1400                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1401                                            AR_STOMP_NONE_WLAN_WGHT);
1402                 break;
1403         default:
1404                 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1405                 break;
1406         }
1407
1408         ath9k_hw_btcoex_enable(ah);
1409 }
1410
1411 static void ath9k_gen_timer_start(struct ath_hw *ah,
1412                                   struct ath_gen_timer *timer,
1413                                   u32 timer_next,
1414                                   u32 timer_period)
1415 {
1416         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1417
1418         if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
1419                 ath9k_hw_set_interrupts(ah, 0);
1420                 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
1421                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1422         }
1423 }
1424
1425 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1426 {
1427         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1428
1429         ath9k_hw_gen_timer_stop(ah, timer);
1430
1431         /* if no timer is enabled, turn off interrupt mask */
1432         if (timer_table->timer_mask.val == 0) {
1433                 ath9k_hw_set_interrupts(ah, 0);
1434                 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
1435                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1436         }
1437 }
1438
1439 /*
1440  * This is the master bt coex timer which runs for every
1441  * 45ms, bt traffic will be given priority during 55% of this
1442  * period while wlan gets remaining 45%
1443  */
1444 static void ath_btcoex_period_timer(unsigned long data)
1445 {
1446         struct ath_softc *sc = (struct ath_softc *) data;
1447         struct ath_hw *ah = sc->sc_ah;
1448         struct ath_btcoex *btcoex = &sc->btcoex;
1449
1450         ath_detect_bt_priority(sc);
1451
1452         spin_lock_bh(&btcoex->btcoex_lock);
1453
1454         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1455
1456         spin_unlock_bh(&btcoex->btcoex_lock);
1457
1458         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1459                 if (btcoex->hw_timer_enabled)
1460                         ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1461
1462                 ath9k_gen_timer_start(ah,
1463                                       btcoex->no_stomp_timer,
1464                                       (ath9k_hw_gettsf32(ah) +
1465                                        btcoex->btcoex_no_stomp),
1466                                        btcoex->btcoex_no_stomp * 10);
1467                 btcoex->hw_timer_enabled = true;
1468         }
1469
1470         mod_timer(&btcoex->period_timer, jiffies +
1471                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1472 }
1473
1474 /*
1475  * Generic tsf based hw timer which configures weight
1476  * registers to time slice between wlan and bt traffic
1477  */
1478 static void ath_btcoex_no_stomp_timer(void *arg)
1479 {
1480         struct ath_softc *sc = (struct ath_softc *)arg;
1481         struct ath_hw *ah = sc->sc_ah;
1482         struct ath_btcoex *btcoex = &sc->btcoex;
1483
1484         DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1485
1486         spin_lock_bh(&btcoex->btcoex_lock);
1487
1488         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1489                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1490          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1491                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1492
1493         spin_unlock_bh(&btcoex->btcoex_lock);
1494 }
1495
1496 static int ath_init_btcoex_timer(struct ath_softc *sc)
1497 {
1498         struct ath_btcoex *btcoex = &sc->btcoex;
1499
1500         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1501         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1502                 btcoex->btcoex_period / 100;
1503
1504         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1505                         (unsigned long) sc);
1506
1507         spin_lock_init(&btcoex->btcoex_lock);
1508
1509         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1510                         ath_btcoex_no_stomp_timer,
1511                         ath_btcoex_no_stomp_timer,
1512                         (void *) sc, AR_FIRST_NDP_TIMER);
1513
1514         if (!btcoex->no_stomp_timer)
1515                 return -ENOMEM;
1516
1517         return 0;
1518 }
1519
1520 /*
1521  * Read and write, they both share the same lock. We do this to serialize
1522  * reads and writes on Atheros 802.11n PCI devices only. This is required
1523  * as the FIFO on these devices can only accept sanely 2 requests. After
1524  * that the device goes bananas. Serializing the reads/writes prevents this
1525  * from happening.
1526  */
1527
1528 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1529 {
1530         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1531
1532         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1533                 unsigned long flags;
1534                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1535                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1536                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1537         } else
1538                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1539 }
1540
1541 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1542 {
1543         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1544         u32 val;
1545
1546         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1547                 unsigned long flags;
1548                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1549                 val = ioread32(ah->ah_sc->mem + reg_offset);
1550                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1551         } else
1552                 val = ioread32(ah->ah_sc->mem + reg_offset);
1553         return val;
1554 }
1555
1556 static struct ath_ops ath9k_common_ops = {
1557         .read = ath9k_ioread32,
1558         .write = ath9k_iowrite32,
1559 };
1560
1561 /*
1562  * Initialize and fill ath_softc, ath_sofct is the
1563  * "Software Carrier" struct. Historically it has existed
1564  * to allow the separation between hardware specific
1565  * variables (now in ath_hw) and driver specific variables.
1566  */
1567 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1568 {
1569         struct ath_hw *ah = NULL;
1570         struct ath_common *common;
1571         int r = 0, i;
1572         int csz = 0;
1573         int qnum;
1574
1575         /* XXX: hardware will not be ready until ath_open() being called */
1576         sc->sc_flags |= SC_OP_INVALID;
1577
1578         spin_lock_init(&sc->wiphy_lock);
1579         spin_lock_init(&sc->sc_resetlock);
1580         spin_lock_init(&sc->sc_serial_rw);
1581         spin_lock_init(&sc->ani_lock);
1582         spin_lock_init(&sc->sc_pm_lock);
1583         mutex_init(&sc->mutex);
1584         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1585         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1586                      (unsigned long)sc);
1587
1588         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1589         if (!ah) {
1590                 r = -ENOMEM;
1591                 goto bad_no_ah;
1592         }
1593
1594         ah->ah_sc = sc;
1595         ah->hw_version.devid = devid;
1596         ah->hw_version.subsysid = subsysid;
1597         sc->sc_ah = ah;
1598
1599         common = ath9k_hw_common(ah);
1600         common->ops = &ath9k_common_ops;
1601         common->ah = ah;
1602         common->hw = sc->hw;
1603
1604         /*
1605          * Cache line size is used to size and align various
1606          * structures used to communicate with the hardware.
1607          */
1608         ath_read_cachesize(sc, &csz);
1609         /* XXX assert csz is non-zero */
1610         common->cachelsz = csz << 2;    /* convert to bytes */
1611
1612         if (ath9k_init_debug(ah) < 0)
1613                 dev_err(sc->dev, "Unable to create debugfs files\n");
1614
1615         r = ath9k_hw_init(ah);
1616         if (r) {
1617                 DPRINTF(ah, ATH_DBG_FATAL,
1618                         "Unable to initialize hardware; "
1619                         "initialization status: %d\n", r);
1620                 goto bad;
1621         }
1622
1623         /* Get the hardware key cache size. */
1624         sc->keymax = ah->caps.keycache_size;
1625         if (sc->keymax > ATH_KEYMAX) {
1626                 DPRINTF(ah, ATH_DBG_ANY,
1627                         "Warning, using only %u entries in %u key cache\n",
1628                         ATH_KEYMAX, sc->keymax);
1629                 sc->keymax = ATH_KEYMAX;
1630         }
1631
1632         /*
1633          * Reset the key cache since some parts do not
1634          * reset the contents on initial power up.
1635          */
1636         for (i = 0; i < sc->keymax; i++)
1637                 ath9k_hw_keyreset(ah, (u16) i);
1638
1639         /* default to MONITOR mode */
1640         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1641
1642         /* Setup rate tables */
1643
1644         ath_rate_attach(sc);
1645         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1646         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1647
1648         /*
1649          * Allocate hardware transmit queues: one queue for
1650          * beacon frames and one data queue for each QoS
1651          * priority.  Note that the hal handles reseting
1652          * these queues at the needed time.
1653          */
1654         sc->beacon.beaconq = ath_beaconq_setup(ah);
1655         if (sc->beacon.beaconq == -1) {
1656                 DPRINTF(ah, ATH_DBG_FATAL,
1657                         "Unable to setup a beacon xmit queue\n");
1658                 r = -EIO;
1659                 goto bad2;
1660         }
1661         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1662         if (sc->beacon.cabq == NULL) {
1663                 DPRINTF(ah, ATH_DBG_FATAL,
1664                         "Unable to setup CAB xmit queue\n");
1665                 r = -EIO;
1666                 goto bad2;
1667         }
1668
1669         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1670         ath_cabq_update(sc);
1671
1672         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1673                 sc->tx.hwq_map[i] = -1;
1674
1675         /* Setup data queues */
1676         /* NB: ensure BK queue is the lowest priority h/w queue */
1677         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1678                 DPRINTF(ah, ATH_DBG_FATAL,
1679                         "Unable to setup xmit queue for BK traffic\n");
1680                 r = -EIO;
1681                 goto bad2;
1682         }
1683
1684         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1685                 DPRINTF(ah, ATH_DBG_FATAL,
1686                         "Unable to setup xmit queue for BE traffic\n");
1687                 r = -EIO;
1688                 goto bad2;
1689         }
1690         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1691                 DPRINTF(ah, ATH_DBG_FATAL,
1692                         "Unable to setup xmit queue for VI traffic\n");
1693                 r = -EIO;
1694                 goto bad2;
1695         }
1696         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1697                 DPRINTF(ah, ATH_DBG_FATAL,
1698                         "Unable to setup xmit queue for VO traffic\n");
1699                 r = -EIO;
1700                 goto bad2;
1701         }
1702
1703         /* Initializes the noise floor to a reasonable default value.
1704          * Later on this will be updated during ANI processing. */
1705
1706         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1707         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1708
1709         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1710                                    ATH9K_CIPHER_TKIP, NULL)) {
1711                 /*
1712                  * Whether we should enable h/w TKIP MIC.
1713                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1714                  * report WMM capable, so it's always safe to turn on
1715                  * TKIP MIC in this case.
1716                  */
1717                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1718                                        0, 1, NULL);
1719         }
1720
1721         /*
1722          * Check whether the separate key cache entries
1723          * are required to handle both tx+rx MIC keys.
1724          * With split mic keys the number of stations is limited
1725          * to 27 otherwise 59.
1726          */
1727         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1728                                    ATH9K_CIPHER_TKIP, NULL)
1729             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1730                                       ATH9K_CIPHER_MIC, NULL)
1731             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1732                                       0, NULL))
1733                 sc->splitmic = 1;
1734
1735         /* turn on mcast key search if possible */
1736         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1737                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1738                                              1, NULL);
1739
1740         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1741
1742         /* 11n Capabilities */
1743         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1744                 sc->sc_flags |= SC_OP_TXAGGR;
1745                 sc->sc_flags |= SC_OP_RXAGGR;
1746         }
1747
1748         sc->tx_chainmask = ah->caps.tx_chainmask;
1749         sc->rx_chainmask = ah->caps.rx_chainmask;
1750
1751         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1752         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1753
1754         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1755                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1756
1757         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1758
1759         /* initialize beacon slots */
1760         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1761                 sc->beacon.bslot[i] = NULL;
1762                 sc->beacon.bslot_aphy[i] = NULL;
1763         }
1764
1765         /* setup channels and rates */
1766
1767         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1768         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1769                 sc->rates[IEEE80211_BAND_2GHZ];
1770         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1771         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1772                 ARRAY_SIZE(ath9k_2ghz_chantable);
1773
1774         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1775                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1776                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1777                         sc->rates[IEEE80211_BAND_5GHZ];
1778                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1779                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1780                         ARRAY_SIZE(ath9k_5ghz_chantable);
1781         }
1782
1783         switch (ah->btcoex_hw.scheme) {
1784         case ATH_BTCOEX_CFG_NONE:
1785                 break;
1786         case ATH_BTCOEX_CFG_2WIRE:
1787                 ath9k_hw_btcoex_init_2wire(ah);
1788                 break;
1789         case ATH_BTCOEX_CFG_3WIRE:
1790                 ath9k_hw_btcoex_init_3wire(ah);
1791                 r = ath_init_btcoex_timer(sc);
1792                 if (r)
1793                         goto bad2;
1794                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1795                 ath9k_hw_init_btcoex_hw(ah, qnum);
1796                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1797                 break;
1798         default:
1799                 WARN_ON(1);
1800                 break;
1801         }
1802
1803         return 0;
1804 bad2:
1805         /* cleanup tx queues */
1806         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1807                 if (ATH_TXQ_SETUP(sc, i))
1808                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1809 bad:
1810         ath9k_hw_detach(ah);
1811 bad_no_ah:
1812         ath9k_exit_debug(sc->sc_ah);
1813         sc->sc_ah = NULL;
1814
1815         return r;
1816 }
1817
1818 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1819 {
1820         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1821                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1822                 IEEE80211_HW_SIGNAL_DBM |
1823                 IEEE80211_HW_AMPDU_AGGREGATION |
1824                 IEEE80211_HW_SUPPORTS_PS |
1825                 IEEE80211_HW_PS_NULLFUNC_STACK |
1826                 IEEE80211_HW_SPECTRUM_MGMT;
1827
1828         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1829                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1830
1831         hw->wiphy->interface_modes =
1832                 BIT(NL80211_IFTYPE_AP) |
1833                 BIT(NL80211_IFTYPE_STATION) |
1834                 BIT(NL80211_IFTYPE_ADHOC) |
1835                 BIT(NL80211_IFTYPE_MESH_POINT);
1836
1837         hw->queues = 4;
1838         hw->max_rates = 4;
1839         hw->channel_change_time = 5000;
1840         hw->max_listen_interval = 10;
1841         /* Hardware supports 10 but we use 4 */
1842         hw->max_rate_tries = 4;
1843         hw->sta_data_size = sizeof(struct ath_node);
1844         hw->vif_data_size = sizeof(struct ath_vif);
1845
1846         hw->rate_control_algorithm = "ath9k_rate_control";
1847
1848         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1849                 &sc->sbands[IEEE80211_BAND_2GHZ];
1850         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1851                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1852                         &sc->sbands[IEEE80211_BAND_5GHZ];
1853 }
1854
1855 /* Device driver core initialization */
1856 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1857 {
1858         struct ieee80211_hw *hw = sc->hw;
1859         struct ath_common *common;
1860         struct ath_hw *ah;
1861         int error = 0, i;
1862         struct ath_regulatory *reg;
1863
1864         dev_dbg(sc->dev, "Attach ATH hw\n");
1865
1866         error = ath_init_softc(devid, sc, subsysid);
1867         if (error != 0)
1868                 return error;
1869
1870         ah = sc->sc_ah;
1871         common = ath9k_hw_common(ah);
1872
1873         /* get mac address from hardware and set in mac80211 */
1874
1875         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1876
1877         ath_set_hw_capab(sc, hw);
1878
1879         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1880                               ath9k_reg_notifier);
1881         if (error)
1882                 return error;
1883
1884         reg = &common->regulatory;
1885
1886         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1887                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1888                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1889                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1890         }
1891
1892         /* initialize tx/rx engine */
1893         error = ath_tx_init(sc, ATH_TXBUF);
1894         if (error != 0)
1895                 goto error_attach;
1896
1897         error = ath_rx_init(sc, ATH_RXBUF);
1898         if (error != 0)
1899                 goto error_attach;
1900
1901         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1902         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1903         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1904
1905         error = ieee80211_register_hw(hw);
1906
1907         if (!ath_is_world_regd(reg)) {
1908                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1909                 if (error)
1910                         goto error_attach;
1911         }
1912
1913         /* Initialize LED control */
1914         ath_init_leds(sc);
1915
1916         ath_start_rfkill_poll(sc);
1917
1918         return 0;
1919
1920 error_attach:
1921         /* cleanup tx queues */
1922         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1923                 if (ATH_TXQ_SETUP(sc, i))
1924                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1925
1926         ath9k_hw_detach(ah);
1927         ath9k_exit_debug(ah);
1928         sc->sc_ah = NULL;
1929
1930         return error;
1931 }
1932
1933 int ath_reset(struct ath_softc *sc, bool retry_tx)
1934 {
1935         struct ath_hw *ah = sc->sc_ah;
1936         struct ieee80211_hw *hw = sc->hw;
1937         int r;
1938
1939         ath9k_hw_set_interrupts(ah, 0);
1940         ath_drain_all_txq(sc, retry_tx);
1941         ath_stoprecv(sc);
1942         ath_flushrecv(sc);
1943
1944         spin_lock_bh(&sc->sc_resetlock);
1945         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1946         if (r)
1947                 DPRINTF(ah, ATH_DBG_FATAL,
1948                         "Unable to reset hardware; reset status %d\n", r);
1949         spin_unlock_bh(&sc->sc_resetlock);
1950
1951         if (ath_startrecv(sc) != 0)
1952                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1953
1954         /*
1955          * We may be doing a reset in response to a request
1956          * that changes the channel so update any state that
1957          * might change as a result.
1958          */
1959         ath_cache_conf_rate(sc, &hw->conf);
1960
1961         ath_update_txpow(sc);
1962
1963         if (sc->sc_flags & SC_OP_BEACONS)
1964                 ath_beacon_config(sc, NULL);    /* restart beacons */
1965
1966         ath9k_hw_set_interrupts(ah, sc->imask);
1967
1968         if (retry_tx) {
1969                 int i;
1970                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1971                         if (ATH_TXQ_SETUP(sc, i)) {
1972                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1973                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1974                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1975                         }
1976                 }
1977         }
1978
1979         return r;
1980 }
1981
1982 /*
1983  *  This function will allocate both the DMA descriptor structure, and the
1984  *  buffers it contains.  These are used to contain the descriptors used
1985  *  by the system.
1986 */
1987 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1988                       struct list_head *head, const char *name,
1989                       int nbuf, int ndesc)
1990 {
1991 #define DS2PHYS(_dd, _ds)                                               \
1992         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1993 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1994 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1995
1996         struct ath_desc *ds;
1997         struct ath_buf *bf;
1998         int i, bsize, error;
1999
2000         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2001                 name, nbuf, ndesc);
2002
2003         INIT_LIST_HEAD(head);
2004         /* ath_desc must be a multiple of DWORDs */
2005         if ((sizeof(struct ath_desc) % 4) != 0) {
2006                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
2007                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
2008                 error = -ENOMEM;
2009                 goto fail;
2010         }
2011
2012         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2013
2014         /*
2015          * Need additional DMA memory because we can't use
2016          * descriptors that cross the 4K page boundary. Assume
2017          * one skipped descriptor per 4K page.
2018          */
2019         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2020                 u32 ndesc_skipped =
2021                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2022                 u32 dma_len;
2023
2024                 while (ndesc_skipped) {
2025                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
2026                         dd->dd_desc_len += dma_len;
2027
2028                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2029                 };
2030         }
2031
2032         /* allocate descriptors */
2033         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2034                                          &dd->dd_desc_paddr, GFP_KERNEL);
2035         if (dd->dd_desc == NULL) {
2036                 error = -ENOMEM;
2037                 goto fail;
2038         }
2039         ds = dd->dd_desc;
2040         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2041                 name, ds, (u32) dd->dd_desc_len,
2042                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2043
2044         /* allocate buffers */
2045         bsize = sizeof(struct ath_buf) * nbuf;
2046         bf = kzalloc(bsize, GFP_KERNEL);
2047         if (bf == NULL) {
2048                 error = -ENOMEM;
2049                 goto fail2;
2050         }
2051         dd->dd_bufptr = bf;
2052
2053         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2054                 bf->bf_desc = ds;
2055                 bf->bf_daddr = DS2PHYS(dd, ds);
2056
2057                 if (!(sc->sc_ah->caps.hw_caps &
2058                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2059                         /*
2060                          * Skip descriptor addresses which can cause 4KB
2061                          * boundary crossing (addr + length) with a 32 dword
2062                          * descriptor fetch.
2063                          */
2064                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2065                                 ASSERT((caddr_t) bf->bf_desc <
2066                                        ((caddr_t) dd->dd_desc +
2067                                         dd->dd_desc_len));
2068
2069                                 ds += ndesc;
2070                                 bf->bf_desc = ds;
2071                                 bf->bf_daddr = DS2PHYS(dd, ds);
2072                         }
2073                 }
2074                 list_add_tail(&bf->list, head);
2075         }
2076         return 0;
2077 fail2:
2078         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2079                           dd->dd_desc_paddr);
2080 fail:
2081         memset(dd, 0, sizeof(*dd));
2082         return error;
2083 #undef ATH_DESC_4KB_BOUND_CHECK
2084 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2085 #undef DS2PHYS
2086 }
2087
2088 void ath_descdma_cleanup(struct ath_softc *sc,
2089                          struct ath_descdma *dd,
2090                          struct list_head *head)
2091 {
2092         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2093                           dd->dd_desc_paddr);
2094
2095         INIT_LIST_HEAD(head);
2096         kfree(dd->dd_bufptr);
2097         memset(dd, 0, sizeof(*dd));
2098 }
2099
2100 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2101 {
2102         int qnum;
2103
2104         switch (queue) {
2105         case 0:
2106                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2107                 break;
2108         case 1:
2109                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2110                 break;
2111         case 2:
2112                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2113                 break;
2114         case 3:
2115                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2116                 break;
2117         default:
2118                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2119                 break;
2120         }
2121
2122         return qnum;
2123 }
2124
2125 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2126 {
2127         int qnum;
2128
2129         switch (queue) {
2130         case ATH9K_WME_AC_VO:
2131                 qnum = 0;
2132                 break;
2133         case ATH9K_WME_AC_VI:
2134                 qnum = 1;
2135                 break;
2136         case ATH9K_WME_AC_BE:
2137                 qnum = 2;
2138                 break;
2139         case ATH9K_WME_AC_BK:
2140                 qnum = 3;
2141                 break;
2142         default:
2143                 qnum = -1;
2144                 break;
2145         }
2146
2147         return qnum;
2148 }
2149
2150 /* XXX: Remove me once we don't depend on ath9k_channel for all
2151  * this redundant data */
2152 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2153                            struct ath9k_channel *ichan)
2154 {
2155         struct ieee80211_channel *chan = hw->conf.channel;
2156         struct ieee80211_conf *conf = &hw->conf;
2157
2158         ichan->channel = chan->center_freq;
2159         ichan->chan = chan;
2160
2161         if (chan->band == IEEE80211_BAND_2GHZ) {
2162                 ichan->chanmode = CHANNEL_G;
2163                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2164         } else {
2165                 ichan->chanmode = CHANNEL_A;
2166                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2167         }
2168
2169         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2170
2171         if (conf_is_ht(conf)) {
2172                 if (conf_is_ht40(conf))
2173                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2174
2175                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2176                                             conf->channel_type);
2177         }
2178 }
2179
2180 /**********************/
2181 /* mac80211 callbacks */
2182 /**********************/
2183
2184 /*
2185  * (Re)start btcoex timers
2186  */
2187 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2188 {
2189         struct ath_btcoex *btcoex = &sc->btcoex;
2190         struct ath_hw *ah = sc->sc_ah;
2191
2192         DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2193
2194         /* make sure duty cycle timer is also stopped when resuming */
2195         if (btcoex->hw_timer_enabled)
2196                 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2197
2198         btcoex->bt_priority_cnt = 0;
2199         btcoex->bt_priority_time = jiffies;
2200         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2201
2202         mod_timer(&btcoex->period_timer, jiffies);
2203 }
2204
2205 static int ath9k_start(struct ieee80211_hw *hw)
2206 {
2207         struct ath_wiphy *aphy = hw->priv;
2208         struct ath_softc *sc = aphy->sc;
2209         struct ath_hw *ah = sc->sc_ah;
2210         struct ieee80211_channel *curchan = hw->conf.channel;
2211         struct ath9k_channel *init_channel;
2212         int r;
2213
2214         DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
2215                 "initial channel: %d MHz\n", curchan->center_freq);
2216
2217         mutex_lock(&sc->mutex);
2218
2219         if (ath9k_wiphy_started(sc)) {
2220                 if (sc->chan_idx == curchan->hw_value) {
2221                         /*
2222                          * Already on the operational channel, the new wiphy
2223                          * can be marked active.
2224                          */
2225                         aphy->state = ATH_WIPHY_ACTIVE;
2226                         ieee80211_wake_queues(hw);
2227                 } else {
2228                         /*
2229                          * Another wiphy is on another channel, start the new
2230                          * wiphy in paused state.
2231                          */
2232                         aphy->state = ATH_WIPHY_PAUSED;
2233                         ieee80211_stop_queues(hw);
2234                 }
2235                 mutex_unlock(&sc->mutex);
2236                 return 0;
2237         }
2238         aphy->state = ATH_WIPHY_ACTIVE;
2239
2240         /* setup initial channel */
2241
2242         sc->chan_idx = curchan->hw_value;
2243
2244         init_channel = ath_get_curchannel(sc, hw);
2245
2246         /* Reset SERDES registers */
2247         ath9k_hw_configpcipowersave(ah, 0, 0);
2248
2249         /*
2250          * The basic interface to setting the hardware in a good
2251          * state is ``reset''.  On return the hardware is known to
2252          * be powered up and with interrupts disabled.  This must
2253          * be followed by initialization of the appropriate bits
2254          * and then setup of the interrupt mask.
2255          */
2256         spin_lock_bh(&sc->sc_resetlock);
2257         r = ath9k_hw_reset(ah, init_channel, false);
2258         if (r) {
2259                 DPRINTF(ah, ATH_DBG_FATAL,
2260                         "Unable to reset hardware; reset status %d "
2261                         "(freq %u MHz)\n", r,
2262                         curchan->center_freq);
2263                 spin_unlock_bh(&sc->sc_resetlock);
2264                 goto mutex_unlock;
2265         }
2266         spin_unlock_bh(&sc->sc_resetlock);
2267
2268         /*
2269          * This is needed only to setup initial state
2270          * but it's best done after a reset.
2271          */
2272         ath_update_txpow(sc);
2273
2274         /*
2275          * Setup the hardware after reset:
2276          * The receive engine is set going.
2277          * Frame transmit is handled entirely
2278          * in the frame output path; there's nothing to do
2279          * here except setup the interrupt mask.
2280          */
2281         if (ath_startrecv(sc) != 0) {
2282                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
2283                 r = -EIO;
2284                 goto mutex_unlock;
2285         }
2286
2287         /* Setup our intr mask. */
2288         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2289                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2290                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2291
2292         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2293                 sc->imask |= ATH9K_INT_GTT;
2294
2295         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2296                 sc->imask |= ATH9K_INT_CST;
2297
2298         ath_cache_conf_rate(sc, &hw->conf);
2299
2300         sc->sc_flags &= ~SC_OP_INVALID;
2301
2302         /* Disable BMISS interrupt when we're not associated */
2303         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2304         ath9k_hw_set_interrupts(ah, sc->imask);
2305
2306         ieee80211_wake_queues(hw);
2307
2308         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2309
2310         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2311             !ah->btcoex_hw.enabled) {
2312                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2313                                            AR_STOMP_LOW_WLAN_WGHT);
2314                 ath9k_hw_btcoex_enable(ah);
2315
2316                 if (sc->bus_ops->bt_coex_prep)
2317                         sc->bus_ops->bt_coex_prep(sc);
2318                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2319                         ath9k_btcoex_timer_resume(sc);
2320         }
2321
2322 mutex_unlock:
2323         mutex_unlock(&sc->mutex);
2324
2325         return r;
2326 }
2327
2328 static int ath9k_tx(struct ieee80211_hw *hw,
2329                     struct sk_buff *skb)
2330 {
2331         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2332         struct ath_wiphy *aphy = hw->priv;
2333         struct ath_softc *sc = aphy->sc;
2334         struct ath_tx_control txctl;
2335         int hdrlen, padsize;
2336
2337         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2338                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2339                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2340                 goto exit;
2341         }
2342
2343         if (sc->ps_enabled) {
2344                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2345                 /*
2346                  * mac80211 does not set PM field for normal data frames, so we
2347                  * need to update that based on the current PS mode.
2348                  */
2349                 if (ieee80211_is_data(hdr->frame_control) &&
2350                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2351                     !ieee80211_has_pm(hdr->frame_control)) {
2352                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2353                                 "while in PS mode\n");
2354                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2355                 }
2356         }
2357
2358         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2359                 /*
2360                  * We are using PS-Poll and mac80211 can request TX while in
2361                  * power save mode. Need to wake up hardware for the TX to be
2362                  * completed and if needed, also for RX of buffered frames.
2363                  */
2364                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2365                 ath9k_ps_wakeup(sc);
2366                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2367                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2368                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2369                                 "buffered frame\n");
2370                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2371                 } else {
2372                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2373                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2374                 }
2375                 /*
2376                  * The actual restore operation will happen only after
2377                  * the sc_flags bit is cleared. We are just dropping
2378                  * the ps_usecount here.
2379                  */
2380                 ath9k_ps_restore(sc);
2381         }
2382
2383         memset(&txctl, 0, sizeof(struct ath_tx_control));
2384
2385         /*
2386          * As a temporary workaround, assign seq# here; this will likely need
2387          * to be cleaned up to work better with Beacon transmission and virtual
2388          * BSSes.
2389          */
2390         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2391                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2392                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2393                         sc->tx.seq_no += 0x10;
2394                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2395                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2396         }
2397
2398         /* Add the padding after the header if this is not already done */
2399         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2400         if (hdrlen & 3) {
2401                 padsize = hdrlen % 4;
2402                 if (skb_headroom(skb) < padsize)
2403                         return -1;
2404                 skb_push(skb, padsize);
2405                 memmove(skb->data, skb->data + padsize, hdrlen);
2406         }
2407
2408         /* Check if a tx queue is available */
2409
2410         txctl.txq = ath_test_get_txq(sc, skb);
2411         if (!txctl.txq)
2412                 goto exit;
2413
2414         DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2415
2416         if (ath_tx_start(hw, skb, &txctl) != 0) {
2417                 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2418                 goto exit;
2419         }
2420
2421         return 0;
2422 exit:
2423         dev_kfree_skb_any(skb);
2424         return 0;
2425 }
2426
2427 /*
2428  * Pause btcoex timer and bt duty cycle timer
2429  */
2430 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2431 {
2432         struct ath_btcoex *btcoex = &sc->btcoex;
2433         struct ath_hw *ah = sc->sc_ah;
2434
2435         del_timer_sync(&btcoex->period_timer);
2436
2437         if (btcoex->hw_timer_enabled)
2438                 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2439
2440         btcoex->hw_timer_enabled = false;
2441 }
2442
2443 static void ath9k_stop(struct ieee80211_hw *hw)
2444 {
2445         struct ath_wiphy *aphy = hw->priv;
2446         struct ath_softc *sc = aphy->sc;
2447         struct ath_hw *ah = sc->sc_ah;
2448
2449         mutex_lock(&sc->mutex);
2450
2451         aphy->state = ATH_WIPHY_INACTIVE;
2452
2453         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2454         cancel_delayed_work_sync(&sc->tx_complete_work);
2455
2456         if (!sc->num_sec_wiphy) {
2457                 cancel_delayed_work_sync(&sc->wiphy_work);
2458                 cancel_work_sync(&sc->chan_work);
2459         }
2460
2461         if (sc->sc_flags & SC_OP_INVALID) {
2462                 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
2463                 mutex_unlock(&sc->mutex);
2464                 return;
2465         }
2466
2467         if (ath9k_wiphy_started(sc)) {
2468                 mutex_unlock(&sc->mutex);
2469                 return; /* another wiphy still in use */
2470         }
2471
2472         if (ah->btcoex_hw.enabled) {
2473                 ath9k_hw_btcoex_disable(ah);
2474                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2475                         ath9k_btcoex_timer_pause(sc);
2476         }
2477
2478         /* make sure h/w will not generate any interrupt
2479          * before setting the invalid flag. */
2480         ath9k_hw_set_interrupts(ah, 0);
2481
2482         if (!(sc->sc_flags & SC_OP_INVALID)) {
2483                 ath_drain_all_txq(sc, false);
2484                 ath_stoprecv(sc);
2485                 ath9k_hw_phy_disable(ah);
2486         } else
2487                 sc->rx.rxlink = NULL;
2488
2489         /* disable HAL and put h/w to sleep */
2490         ath9k_hw_disable(ah);
2491         ath9k_hw_configpcipowersave(ah, 1, 1);
2492         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2493
2494         sc->sc_flags |= SC_OP_INVALID;
2495
2496         mutex_unlock(&sc->mutex);
2497
2498         DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
2499 }
2500
2501 static int ath9k_add_interface(struct ieee80211_hw *hw,
2502                                struct ieee80211_if_init_conf *conf)
2503 {
2504         struct ath_wiphy *aphy = hw->priv;
2505         struct ath_softc *sc = aphy->sc;
2506         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2507         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2508         int ret = 0;
2509
2510         mutex_lock(&sc->mutex);
2511
2512         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2513             sc->nvifs > 0) {
2514                 ret = -ENOBUFS;
2515                 goto out;
2516         }
2517
2518         switch (conf->type) {
2519         case NL80211_IFTYPE_STATION:
2520                 ic_opmode = NL80211_IFTYPE_STATION;
2521                 break;
2522         case NL80211_IFTYPE_ADHOC:
2523         case NL80211_IFTYPE_AP:
2524         case NL80211_IFTYPE_MESH_POINT:
2525                 if (sc->nbcnvifs >= ATH_BCBUF) {
2526                         ret = -ENOBUFS;
2527                         goto out;
2528                 }
2529                 ic_opmode = conf->type;
2530                 break;
2531         default:
2532                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2533                         "Interface type %d not yet supported\n", conf->type);
2534                 ret = -EOPNOTSUPP;
2535                 goto out;
2536         }
2537
2538         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2539
2540         /* Set the VIF opmode */
2541         avp->av_opmode = ic_opmode;
2542         avp->av_bslot = -1;
2543
2544         sc->nvifs++;
2545
2546         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2547                 ath9k_set_bssid_mask(hw);
2548
2549         if (sc->nvifs > 1)
2550                 goto out; /* skip global settings for secondary vif */
2551
2552         if (ic_opmode == NL80211_IFTYPE_AP) {
2553                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2554                 sc->sc_flags |= SC_OP_TSF_RESET;
2555         }
2556
2557         /* Set the device opmode */
2558         sc->sc_ah->opmode = ic_opmode;
2559
2560         /*
2561          * Enable MIB interrupts when there are hardware phy counters.
2562          * Note we only do this (at the moment) for station mode.
2563          */
2564         if ((conf->type == NL80211_IFTYPE_STATION) ||
2565             (conf->type == NL80211_IFTYPE_ADHOC) ||
2566             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2567                 sc->imask |= ATH9K_INT_MIB;
2568                 sc->imask |= ATH9K_INT_TSFOOR;
2569         }
2570
2571         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2572
2573         if (conf->type == NL80211_IFTYPE_AP    ||
2574             conf->type == NL80211_IFTYPE_ADHOC ||
2575             conf->type == NL80211_IFTYPE_MONITOR)
2576                 ath_start_ani(sc);
2577
2578 out:
2579         mutex_unlock(&sc->mutex);
2580         return ret;
2581 }
2582
2583 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2584                                    struct ieee80211_if_init_conf *conf)
2585 {
2586         struct ath_wiphy *aphy = hw->priv;
2587         struct ath_softc *sc = aphy->sc;
2588         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2589         int i;
2590
2591         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2592
2593         mutex_lock(&sc->mutex);
2594
2595         /* Stop ANI */
2596         del_timer_sync(&sc->ani.timer);
2597
2598         /* Reclaim beacon resources */
2599         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2600             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2601             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2602                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2603                 ath_beacon_return(sc, avp);
2604         }
2605
2606         sc->sc_flags &= ~SC_OP_BEACONS;
2607
2608         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2609                 if (sc->beacon.bslot[i] == conf->vif) {
2610                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2611                                "slot\n", __func__);
2612                         sc->beacon.bslot[i] = NULL;
2613                         sc->beacon.bslot_aphy[i] = NULL;
2614                 }
2615         }
2616
2617         sc->nvifs--;
2618
2619         mutex_unlock(&sc->mutex);
2620 }
2621
2622 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2623 {
2624         struct ath_wiphy *aphy = hw->priv;
2625         struct ath_softc *sc = aphy->sc;
2626         struct ieee80211_conf *conf = &hw->conf;
2627         struct ath_hw *ah = sc->sc_ah;
2628         bool all_wiphys_idle = false, disable_radio = false;
2629
2630         mutex_lock(&sc->mutex);
2631
2632         /* Leave this as the first check */
2633         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2634
2635                 spin_lock_bh(&sc->wiphy_lock);
2636                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2637                 spin_unlock_bh(&sc->wiphy_lock);
2638
2639                 if (conf->flags & IEEE80211_CONF_IDLE){
2640                         if (all_wiphys_idle)
2641                                 disable_radio = true;
2642                 }
2643                 else if (all_wiphys_idle) {
2644                         ath_radio_enable(sc);
2645                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2646                                 "not-idle: enabling radio\n");
2647                 }
2648         }
2649
2650         if (changed & IEEE80211_CONF_CHANGE_PS) {
2651                 if (conf->flags & IEEE80211_CONF_PS) {
2652                         if (!(ah->caps.hw_caps &
2653                               ATH9K_HW_CAP_AUTOSLEEP)) {
2654                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2655                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2656                                         ath9k_hw_set_interrupts(sc->sc_ah,
2657                                                         sc->imask);
2658                                 }
2659                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2660                         }
2661                         sc->ps_enabled = true;
2662                 } else {
2663                         sc->ps_enabled = false;
2664                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2665                         if (!(ah->caps.hw_caps &
2666                               ATH9K_HW_CAP_AUTOSLEEP)) {
2667                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2668                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2669                                                   SC_OP_WAIT_FOR_CAB |
2670                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2671                                                   SC_OP_WAIT_FOR_TX_ACK);
2672                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2673                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2674                                         ath9k_hw_set_interrupts(sc->sc_ah,
2675                                                         sc->imask);
2676                                 }
2677                         }
2678                 }
2679         }
2680
2681         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2682                 struct ieee80211_channel *curchan = hw->conf.channel;
2683                 int pos = curchan->hw_value;
2684
2685                 aphy->chan_idx = pos;
2686                 aphy->chan_is_ht = conf_is_ht(conf);
2687
2688                 if (aphy->state == ATH_WIPHY_SCAN ||
2689                     aphy->state == ATH_WIPHY_ACTIVE)
2690                         ath9k_wiphy_pause_all_forced(sc, aphy);
2691                 else {
2692                         /*
2693                          * Do not change operational channel based on a paused
2694                          * wiphy changes.
2695                          */
2696                         goto skip_chan_change;
2697                 }
2698
2699                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2700                         curchan->center_freq);
2701
2702                 /* XXX: remove me eventualy */
2703                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2704
2705                 ath_update_chainmask(sc, conf_is_ht(conf));
2706
2707                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2708                         DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2709                         mutex_unlock(&sc->mutex);
2710                         return -EINVAL;
2711                 }
2712         }
2713
2714 skip_chan_change:
2715         if (changed & IEEE80211_CONF_CHANGE_POWER)
2716                 sc->config.txpowlimit = 2 * conf->power_level;
2717
2718         if (disable_radio) {
2719                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2720                 ath_radio_disable(sc);
2721         }
2722
2723         mutex_unlock(&sc->mutex);
2724
2725         return 0;
2726 }
2727
2728 #define SUPPORTED_FILTERS                       \
2729         (FIF_PROMISC_IN_BSS |                   \
2730         FIF_ALLMULTI |                          \
2731         FIF_CONTROL |                           \
2732         FIF_PSPOLL |                            \
2733         FIF_OTHER_BSS |                         \
2734         FIF_BCN_PRBRESP_PROMISC |               \
2735         FIF_FCSFAIL)
2736
2737 /* FIXME: sc->sc_full_reset ? */
2738 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2739                                    unsigned int changed_flags,
2740                                    unsigned int *total_flags,
2741                                    u64 multicast)
2742 {
2743         struct ath_wiphy *aphy = hw->priv;
2744         struct ath_softc *sc = aphy->sc;
2745         u32 rfilt;
2746
2747         changed_flags &= SUPPORTED_FILTERS;
2748         *total_flags &= SUPPORTED_FILTERS;
2749
2750         sc->rx.rxfilter = *total_flags;
2751         ath9k_ps_wakeup(sc);
2752         rfilt = ath_calcrxfilter(sc);
2753         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2754         ath9k_ps_restore(sc);
2755
2756         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2757 }
2758
2759 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2760                              struct ieee80211_vif *vif,
2761                              enum sta_notify_cmd cmd,
2762                              struct ieee80211_sta *sta)
2763 {
2764         struct ath_wiphy *aphy = hw->priv;
2765         struct ath_softc *sc = aphy->sc;
2766
2767         switch (cmd) {
2768         case STA_NOTIFY_ADD:
2769                 ath_node_attach(sc, sta);
2770                 break;
2771         case STA_NOTIFY_REMOVE:
2772                 ath_node_detach(sc, sta);
2773                 break;
2774         default:
2775                 break;
2776         }
2777 }
2778
2779 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2780                          const struct ieee80211_tx_queue_params *params)
2781 {
2782         struct ath_wiphy *aphy = hw->priv;
2783         struct ath_softc *sc = aphy->sc;
2784         struct ath9k_tx_queue_info qi;
2785         int ret = 0, qnum;
2786
2787         if (queue >= WME_NUM_AC)
2788                 return 0;
2789
2790         mutex_lock(&sc->mutex);
2791
2792         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2793
2794         qi.tqi_aifs = params->aifs;
2795         qi.tqi_cwmin = params->cw_min;
2796         qi.tqi_cwmax = params->cw_max;
2797         qi.tqi_burstTime = params->txop;
2798         qnum = ath_get_hal_qnum(queue, sc);
2799
2800         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2801                 "Configure tx [queue/halq] [%d/%d],  "
2802                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2803                 queue, qnum, params->aifs, params->cw_min,
2804                 params->cw_max, params->txop);
2805
2806         ret = ath_txq_update(sc, qnum, &qi);
2807         if (ret)
2808                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2809
2810         mutex_unlock(&sc->mutex);
2811
2812         return ret;
2813 }
2814
2815 static int ath9k_set_key(struct ieee80211_hw *hw,
2816                          enum set_key_cmd cmd,
2817                          struct ieee80211_vif *vif,
2818                          struct ieee80211_sta *sta,
2819                          struct ieee80211_key_conf *key)
2820 {
2821         struct ath_wiphy *aphy = hw->priv;
2822         struct ath_softc *sc = aphy->sc;
2823         int ret = 0;
2824
2825         if (modparam_nohwcrypt)
2826                 return -ENOSPC;
2827
2828         mutex_lock(&sc->mutex);
2829         ath9k_ps_wakeup(sc);
2830         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2831
2832         switch (cmd) {
2833         case SET_KEY:
2834                 ret = ath_key_config(sc, vif, sta, key);
2835                 if (ret >= 0) {
2836                         key->hw_key_idx = ret;
2837                         /* push IV and Michael MIC generation to stack */
2838                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2839                         if (key->alg == ALG_TKIP)
2840                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2841                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2842                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2843                         ret = 0;
2844                 }
2845                 break;
2846         case DISABLE_KEY:
2847                 ath_key_delete(sc, key);
2848                 break;
2849         default:
2850                 ret = -EINVAL;
2851         }
2852
2853         ath9k_ps_restore(sc);
2854         mutex_unlock(&sc->mutex);
2855
2856         return ret;
2857 }
2858
2859 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2860                                    struct ieee80211_vif *vif,
2861                                    struct ieee80211_bss_conf *bss_conf,
2862                                    u32 changed)
2863 {
2864         struct ath_wiphy *aphy = hw->priv;
2865         struct ath_softc *sc = aphy->sc;
2866         struct ath_hw *ah = sc->sc_ah;
2867         struct ath_common *common = ath9k_hw_common(ah);
2868         struct ath_vif *avp = (void *)vif->drv_priv;
2869         u32 rfilt = 0;
2870         int error, i;
2871
2872         mutex_lock(&sc->mutex);
2873
2874         /*
2875          * TODO: Need to decide which hw opmode to use for
2876          *       multi-interface cases
2877          * XXX: This belongs into add_interface!
2878          */
2879         if (vif->type == NL80211_IFTYPE_AP &&
2880             ah->opmode != NL80211_IFTYPE_AP) {
2881                 ah->opmode = NL80211_IFTYPE_STATION;
2882                 ath9k_hw_setopmode(ah);
2883                 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2884                 common->curaid = 0;
2885                 ath9k_hw_write_associd(ah);
2886                 /* Request full reset to get hw opmode changed properly */
2887                 sc->sc_flags |= SC_OP_FULL_RESET;
2888         }
2889
2890         if ((changed & BSS_CHANGED_BSSID) &&
2891             !is_zero_ether_addr(bss_conf->bssid)) {
2892                 switch (vif->type) {
2893                 case NL80211_IFTYPE_STATION:
2894                 case NL80211_IFTYPE_ADHOC:
2895                 case NL80211_IFTYPE_MESH_POINT:
2896                         /* Set BSSID */
2897                         memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2898                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2899                         common->curaid = 0;
2900                         ath9k_hw_write_associd(ah);
2901
2902                         /* Set aggregation protection mode parameters */
2903                         sc->config.ath_aggr_prot = 0;
2904
2905                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2906                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2907                                 rfilt, common->curbssid, common->curaid);
2908
2909                         /* need to reconfigure the beacon */
2910                         sc->sc_flags &= ~SC_OP_BEACONS ;
2911
2912                         break;
2913                 default:
2914                         break;
2915                 }
2916         }
2917
2918         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2919             (vif->type == NL80211_IFTYPE_AP) ||
2920             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2921                 if ((changed & BSS_CHANGED_BEACON) ||
2922                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2923                      bss_conf->enable_beacon)) {
2924                         /*
2925                          * Allocate and setup the beacon frame.
2926                          *
2927                          * Stop any previous beacon DMA.  This may be
2928                          * necessary, for example, when an ibss merge
2929                          * causes reconfiguration; we may be called
2930                          * with beacon transmission active.
2931                          */
2932                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2933
2934                         error = ath_beacon_alloc(aphy, vif);
2935                         if (!error)
2936                                 ath_beacon_config(sc, vif);
2937                 }
2938         }
2939
2940         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2941         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2942                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2943                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2944                                 ath9k_hw_keysetmac(sc->sc_ah,
2945                                                    (u16)i,
2946                                                    common->curbssid);
2947         }
2948
2949         /* Only legacy IBSS for now */
2950         if (vif->type == NL80211_IFTYPE_ADHOC)
2951                 ath_update_chainmask(sc, 0);
2952
2953         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2954                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2955                         bss_conf->use_short_preamble);
2956                 if (bss_conf->use_short_preamble)
2957                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2958                 else
2959                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2960         }
2961
2962         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2963                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2964                         bss_conf->use_cts_prot);
2965                 if (bss_conf->use_cts_prot &&
2966                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2967                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2968                 else
2969                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2970         }
2971
2972         if (changed & BSS_CHANGED_ASSOC) {
2973                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2974                         bss_conf->assoc);
2975                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2976         }
2977
2978         /*
2979          * The HW TSF has to be reset when the beacon interval changes.
2980          * We set the flag here, and ath_beacon_config_ap() would take this
2981          * into account when it gets called through the subsequent
2982          * config_interface() call - with IFCC_BEACON in the changed field.
2983          */
2984
2985         if (changed & BSS_CHANGED_BEACON_INT) {
2986                 sc->sc_flags |= SC_OP_TSF_RESET;
2987                 sc->beacon_interval = bss_conf->beacon_int;
2988         }
2989
2990         mutex_unlock(&sc->mutex);
2991 }
2992
2993 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2994 {
2995         u64 tsf;
2996         struct ath_wiphy *aphy = hw->priv;
2997         struct ath_softc *sc = aphy->sc;
2998
2999         mutex_lock(&sc->mutex);
3000         tsf = ath9k_hw_gettsf64(sc->sc_ah);
3001         mutex_unlock(&sc->mutex);
3002
3003         return tsf;
3004 }
3005
3006 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3007 {
3008         struct ath_wiphy *aphy = hw->priv;
3009         struct ath_softc *sc = aphy->sc;
3010
3011         mutex_lock(&sc->mutex);
3012         ath9k_hw_settsf64(sc->sc_ah, tsf);
3013         mutex_unlock(&sc->mutex);
3014 }
3015
3016 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3017 {
3018         struct ath_wiphy *aphy = hw->priv;
3019         struct ath_softc *sc = aphy->sc;
3020
3021         mutex_lock(&sc->mutex);
3022
3023         ath9k_ps_wakeup(sc);
3024         ath9k_hw_reset_tsf(sc->sc_ah);
3025         ath9k_ps_restore(sc);
3026
3027         mutex_unlock(&sc->mutex);
3028 }
3029
3030 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3031                               enum ieee80211_ampdu_mlme_action action,
3032                               struct ieee80211_sta *sta,
3033                               u16 tid, u16 *ssn)
3034 {
3035         struct ath_wiphy *aphy = hw->priv;
3036         struct ath_softc *sc = aphy->sc;
3037         int ret = 0;
3038
3039         switch (action) {
3040         case IEEE80211_AMPDU_RX_START:
3041                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3042                         ret = -ENOTSUPP;
3043                 break;
3044         case IEEE80211_AMPDU_RX_STOP:
3045                 break;
3046         case IEEE80211_AMPDU_TX_START:
3047                 ath_tx_aggr_start(sc, sta, tid, ssn);
3048                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3049                 break;
3050         case IEEE80211_AMPDU_TX_STOP:
3051                 ath_tx_aggr_stop(sc, sta, tid);
3052                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3053                 break;
3054         case IEEE80211_AMPDU_TX_OPERATIONAL:
3055                 ath_tx_aggr_resume(sc, sta, tid);
3056                 break;
3057         default:
3058                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
3059         }
3060
3061         return ret;
3062 }
3063
3064 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3065 {
3066         struct ath_wiphy *aphy = hw->priv;
3067         struct ath_softc *sc = aphy->sc;
3068
3069         mutex_lock(&sc->mutex);
3070         if (ath9k_wiphy_scanning(sc)) {
3071                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3072                        "same time\n");
3073                 /*
3074                  * Do not allow the concurrent scanning state for now. This
3075                  * could be improved with scanning control moved into ath9k.
3076                  */
3077                 mutex_unlock(&sc->mutex);
3078                 return;
3079         }
3080
3081         aphy->state = ATH_WIPHY_SCAN;
3082         ath9k_wiphy_pause_all_forced(sc, aphy);
3083
3084         spin_lock_bh(&sc->ani_lock);
3085         sc->sc_flags |= SC_OP_SCANNING;
3086         spin_unlock_bh(&sc->ani_lock);
3087         mutex_unlock(&sc->mutex);
3088 }
3089
3090 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3091 {
3092         struct ath_wiphy *aphy = hw->priv;
3093         struct ath_softc *sc = aphy->sc;
3094
3095         mutex_lock(&sc->mutex);
3096         spin_lock_bh(&sc->ani_lock);
3097         aphy->state = ATH_WIPHY_ACTIVE;
3098         sc->sc_flags &= ~SC_OP_SCANNING;
3099         sc->sc_flags |= SC_OP_FULL_RESET;
3100         spin_unlock_bh(&sc->ani_lock);
3101         ath_beacon_config(sc, NULL);
3102         mutex_unlock(&sc->mutex);
3103 }
3104
3105 struct ieee80211_ops ath9k_ops = {
3106         .tx                 = ath9k_tx,
3107         .start              = ath9k_start,
3108         .stop               = ath9k_stop,
3109         .add_interface      = ath9k_add_interface,
3110         .remove_interface   = ath9k_remove_interface,
3111         .config             = ath9k_config,
3112         .configure_filter   = ath9k_configure_filter,
3113         .sta_notify         = ath9k_sta_notify,
3114         .conf_tx            = ath9k_conf_tx,
3115         .bss_info_changed   = ath9k_bss_info_changed,
3116         .set_key            = ath9k_set_key,
3117         .get_tsf            = ath9k_get_tsf,
3118         .set_tsf            = ath9k_set_tsf,
3119         .reset_tsf          = ath9k_reset_tsf,
3120         .ampdu_action       = ath9k_ampdu_action,
3121         .sw_scan_start      = ath9k_sw_scan_start,
3122         .sw_scan_complete   = ath9k_sw_scan_complete,
3123         .rfkill_poll        = ath9k_rfkill_poll_state,
3124 };
3125
3126 static struct {
3127         u32 version;
3128         const char * name;
3129 } ath_mac_bb_names[] = {
3130         { AR_SREV_VERSION_5416_PCI,     "5416" },
3131         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3132         { AR_SREV_VERSION_9100,         "9100" },
3133         { AR_SREV_VERSION_9160,         "9160" },
3134         { AR_SREV_VERSION_9280,         "9280" },
3135         { AR_SREV_VERSION_9285,         "9285" },
3136         { AR_SREV_VERSION_9287,         "9287" }
3137 };
3138
3139 static struct {
3140         u16 version;
3141         const char * name;
3142 } ath_rf_names[] = {
3143         { 0,                            "5133" },
3144         { AR_RAD5133_SREV_MAJOR,        "5133" },
3145         { AR_RAD5122_SREV_MAJOR,        "5122" },
3146         { AR_RAD2133_SREV_MAJOR,        "2133" },
3147         { AR_RAD2122_SREV_MAJOR,        "2122" }
3148 };
3149
3150 /*
3151  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3152  */