drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static char *dev_info = "ath9k";
  22
  23 MODULE_AUTHOR("Atheros Communications");
  24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  26 MODULE_LICENSE("Dual BSD/GPL");
  27
  28 static int modparam_nohwcrypt;
  29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  31
  32 /* We use the hw_value as an index into our private channel structure */
  33
  34 #define CHAN2G(_freq, _idx)  { \
  35         .center_freq = (_freq), \
  36         .hw_value = (_idx), \
  37         .max_power = 20, \
  38 }
  39
  40 #define CHAN5G(_freq, _idx) { \
  41         .band = IEEE80211_BAND_5GHZ, \
  42         .center_freq = (_freq), \
  43         .hw_value = (_idx), \
  44         .max_power = 20, \
  45 }
  46
  47 /* Some 2 GHz radios are actually tunable on 2312-2732
  48  * on 5 MHz steps, we support the channels which we know
  49  * we have calibration data for all cards though to make
  50  * this static */
  51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  52         CHAN2G(2412, 0), /* Channel 1 */
  53         CHAN2G(2417, 1), /* Channel 2 */
  54         CHAN2G(2422, 2), /* Channel 3 */
  55         CHAN2G(2427, 3), /* Channel 4 */
  56         CHAN2G(2432, 4), /* Channel 5 */
  57         CHAN2G(2437, 5), /* Channel 6 */
  58         CHAN2G(2442, 6), /* Channel 7 */
  59         CHAN2G(2447, 7), /* Channel 8 */
  60         CHAN2G(2452, 8), /* Channel 9 */
  61         CHAN2G(2457, 9), /* Channel 10 */
  62         CHAN2G(2462, 10), /* Channel 11 */
  63         CHAN2G(2467, 11), /* Channel 12 */
  64         CHAN2G(2472, 12), /* Channel 13 */
  65         CHAN2G(2484, 13), /* Channel 14 */
  66 };
  67
  68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  69  * on 5 MHz steps, we support the channels which we know
  70  * we have calibration data for all cards though to make
  71  * this static */
  72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  73         /* _We_ call this UNII 1 */
  74         CHAN5G(5180, 14), /* Channel 36 */
  75         CHAN5G(5200, 15), /* Channel 40 */
  76         CHAN5G(5220, 16), /* Channel 44 */
  77         CHAN5G(5240, 17), /* Channel 48 */
  78         /* _We_ call this UNII 2 */
  79         CHAN5G(5260, 18), /* Channel 52 */
  80         CHAN5G(5280, 19), /* Channel 56 */
  81         CHAN5G(5300, 20), /* Channel 60 */
  82         CHAN5G(5320, 21), /* Channel 64 */
  83         /* _We_ call this "Middle band" */
  84         CHAN5G(5500, 22), /* Channel 100 */
  85         CHAN5G(5520, 23), /* Channel 104 */
  86         CHAN5G(5540, 24), /* Channel 108 */
  87         CHAN5G(5560, 25), /* Channel 112 */
  88         CHAN5G(5580, 26), /* Channel 116 */
  89         CHAN5G(5600, 27), /* Channel 120 */
  90         CHAN5G(5620, 28), /* Channel 124 */
  91         CHAN5G(5640, 29), /* Channel 128 */
  92         CHAN5G(5660, 30), /* Channel 132 */
  93         CHAN5G(5680, 31), /* Channel 136 */
  94         CHAN5G(5700, 32), /* Channel 140 */
  95         /* _We_ call this UNII 3 */
  96         CHAN5G(5745, 33), /* Channel 149 */
  97         CHAN5G(5765, 34), /* Channel 153 */
  98         CHAN5G(5785, 35), /* Channel 157 */
  99         CHAN5G(5805, 36), /* Channel 161 */
 100         CHAN5G(5825, 37), /* Channel 165 */
 101 };
 102
 103 static void ath_cache_conf_rate(struct ath_softc *sc,
 104                                 struct ieee80211_conf *conf)
 105 {
 106         switch (conf->channel->band) {
 107         case IEEE80211_BAND_2GHZ:
 108                 if (conf_is_ht20(conf))
 109                         sc->cur_rate_table =
 110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 111                 else if (conf_is_ht40_minus(conf))
 112                         sc->cur_rate_table =
 113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 114                 else if (conf_is_ht40_plus(conf))
 115                         sc->cur_rate_table =
 116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 117                 else
 118                         sc->cur_rate_table =
 119                           sc->hw_rate_table[ATH9K_MODE_11G];
 120                 break;
 121         case IEEE80211_BAND_5GHZ:
 122                 if (conf_is_ht20(conf))
 123                         sc->cur_rate_table =
 124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 125                 else if (conf_is_ht40_minus(conf))
 126                         sc->cur_rate_table =
 127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 128                 else if (conf_is_ht40_plus(conf))
 129                         sc->cur_rate_table =
 130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 131                 else
 132                         sc->cur_rate_table =
 133                           sc->hw_rate_table[ATH9K_MODE_11A];
 134                 break;
 135         default:
 136                 BUG_ON(1);
 137                 break;
 138         }
 139 }
 140
 141 static void ath_update_txpow(struct ath_softc *sc)
 142 {
 143         struct ath_hw *ah = sc->sc_ah;
 144         u32 txpow;
 145
 146         if (sc->curtxpow != sc->config.txpowlimit) {
 147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 148                 /* read back in case value is clamped */
 149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 150                 sc->curtxpow = txpow;
 151         }
 152 }
 153
 154 static u8 parse_mpdudensity(u8 mpdudensity)
 155 {
 156         /*
 157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 158          *   0 for no restriction
 159          *   1 for 1/4 us
 160          *   2 for 1/2 us
 161          *   3 for 1 us
 162          *   4 for 2 us
 163          *   5 for 4 us
 164          *   6 for 8 us
 165          *   7 for 16 us
 166          */
 167         switch (mpdudensity) {
 168         case 0:
 169                 return 0;
 170         case 1:
 171         case 2:
 172         case 3:
 173                 /* Our lower layer calculations limit our precision to
 174                    1 microsecond */
 175                 return 1;
 176         case 4:
 177                 return 2;
 178         case 5:
 179                 return 4;
 180         case 6:
 181                 return 8;
 182         case 7:
 183                 return 16;
 184         default:
 185                 return 0;
 186         }
 187 }
 188
 189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 190 {
 191         const struct ath_rate_table *rate_table = NULL;
 192         struct ieee80211_supported_band *sband;
 193         struct ieee80211_rate *rate;
 194         int i, maxrates;
 195
 196         switch (band) {
 197         case IEEE80211_BAND_2GHZ:
 198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 199                 break;
 200         case IEEE80211_BAND_5GHZ:
 201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 202                 break;
 203         default:
 204                 break;
 205         }
 206
 207         if (rate_table == NULL)
 208                 return;
 209
 210         sband = &sc->sbands[band];
 211         rate = sc->rates[band];
 212
 213         if (rate_table->rate_cnt > ATH_RATE_MAX)
 214                 maxrates = ATH_RATE_MAX;
 215         else
 216                 maxrates = rate_table->rate_cnt;
 217
 218         for (i = 0; i < maxrates; i++) {
 219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 220                 rate[i].hw_value = rate_table->info[i].ratecode;
 221                 if (rate_table->info[i].short_preamble) {
 222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 223                                 rate_table->info[i].short_preamble;
 224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 225                 }
 226                 sband->n_bitrates++;
 227
 228                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
 229                           "Rate: %2dMbps, ratecode: %2d\n",
 230                           rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 235                                                 struct ieee80211_hw *hw)
 236 {
 237         struct ieee80211_channel *curchan = hw->conf.channel;
 238         struct ath9k_channel *channel;
 239         u8 chan_idx;
 240
 241         chan_idx = curchan->hw_value;
 242         channel = &sc->sc_ah->channels[chan_idx];
 243         ath9k_update_ichannel(sc, hw, channel);
 244         return channel;
 245 }
 246
 247 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 248 {
 249         unsigned long flags;
 250         bool ret;
 251
 252         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 253         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 254         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 255
 256         return ret;
 257 }
 258
 259 void ath9k_ps_wakeup(struct ath_softc *sc)
 260 {
 261         unsigned long flags;
 262
 263         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 264         if (++sc->ps_usecount != 1)
 265                 goto unlock;
 266
 267         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 268
 269  unlock:
 270         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 271 }
 272
 273 void ath9k_ps_restore(struct ath_softc *sc)
 274 {
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 278         if (--sc->ps_usecount != 0)
 279                 goto unlock;
 280
 281         if (sc->ps_enabled &&
 282             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 283                               SC_OP_WAIT_FOR_CAB |
 284                               SC_OP_WAIT_FOR_PSPOLL_DATA |
 285                               SC_OP_WAIT_FOR_TX_ACK)))
 286                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 287
 288  unlock:
 289         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 290 }
 291
 292 /*
 293  * Set/change channels.  If the channel is really being changed, it's done
 294  * by reseting the chip.  To accomplish this we must first cleanup any pending
 295  * DMA, then restart stuff.
 296 */
 297 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 298                     struct ath9k_channel *hchan)
 299 {
 300         struct ath_hw *ah = sc->sc_ah;
 301         struct ath_common *common = ath9k_hw_common(ah);
 302         struct ieee80211_conf *conf = &common->hw->conf;
 303         bool fastcc = true, stopped;
 304         struct ieee80211_channel *channel = hw->conf.channel;
 305         int r;
 306
 307         if (sc->sc_flags & SC_OP_INVALID)
 308                 return -EIO;
 309
 310         ath9k_ps_wakeup(sc);
 311
 312         /*
 313          * This is only performed if the channel settings have
 314          * actually changed.
 315          *
 316          * To switch channels clear any pending DMA operations;
 317          * wait long enough for the RX fifo to drain, reset the
 318          * hardware at the new frequency, and then re-enable
 319          * the relevant bits of the h/w.
 320          */
 321         ath9k_hw_set_interrupts(ah, 0);
 322         ath_drain_all_txq(sc, false);
 323         stopped = ath_stoprecv(sc);
 324
 325         /* XXX: do not flush receive queue here. We don't want
 326          * to flush data frames already in queue because of
 327          * changing channel. */
 328
 329         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 330                 fastcc = false;
 331
 332         ath_print(common, ATH_DBG_CONFIG,
 333                   "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
 334                   sc->sc_ah->curchan->channel,
 335                   channel->center_freq, conf_is_ht40(conf));
 336
 337         spin_lock_bh(&sc->sc_resetlock);
 338
 339         r = ath9k_hw_reset(ah, hchan, fastcc);
 340         if (r) {
 341                 ath_print(common, ATH_DBG_FATAL,
 342                           "Unable to reset channel (%u Mhz) "
 343                           "reset status %d\n",
 344                           channel->center_freq, r);
 345                 spin_unlock_bh(&sc->sc_resetlock);
 346                 goto ps_restore;
 347         }
 348         spin_unlock_bh(&sc->sc_resetlock);
 349
 350         sc->sc_flags &= ~SC_OP_FULL_RESET;
 351
 352         if (ath_startrecv(sc) != 0) {
 353                 ath_print(common, ATH_DBG_FATAL,
 354                           "Unable to restart recv logic\n");
 355                 r = -EIO;
 356                 goto ps_restore;
 357         }
 358
 359         ath_cache_conf_rate(sc, &hw->conf);
 360         ath_update_txpow(sc);
 361         ath9k_hw_set_interrupts(ah, sc->imask);
 362
 363  ps_restore:
 364         ath9k_ps_restore(sc);
 365         return r;
 366 }
 367
 368 /*
 369  *  This routine performs the periodic noise floor calibration function
 370  *  that is used to adjust and optimize the chip performance.  This
 371  *  takes environmental changes (location, temperature) into account.
 372  *  When the task is complete, it reschedules itself depending on the
 373  *  appropriate interval that was calculated.
 374  */
 375 static void ath_ani_calibrate(unsigned long data)
 376 {
 377         struct ath_softc *sc = (struct ath_softc *)data;
 378         struct ath_hw *ah = sc->sc_ah;
 379         struct ath_common *common = ath9k_hw_common(ah);
 380         bool longcal = false;
 381         bool shortcal = false;
 382         bool aniflag = false;
 383         unsigned int timestamp = jiffies_to_msecs(jiffies);
 384         u32 cal_interval, short_cal_interval;
 385
 386         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 387                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 388
 389         /*
 390         * don't calibrate when we're scanning.
 391         * we are most likely not on our home channel.
 392         */
 393         spin_lock(&sc->ani_lock);
 394         if (sc->sc_flags & SC_OP_SCANNING)
 395                 goto set_timer;
 396
 397         /* Only calibrate if awake */
 398         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 399                 goto set_timer;
 400
 401         ath9k_ps_wakeup(sc);
 402
 403         /* Long calibration runs independently of short calibration. */
 404         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 405                 longcal = true;
 406                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 407                 sc->ani.longcal_timer = timestamp;
 408         }
 409
 410         /* Short calibration applies only while caldone is false */
 411         if (!sc->ani.caldone) {
 412                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 413                         shortcal = true;
 414                         ath_print(common, ATH_DBG_ANI,
 415                                   "shortcal @%lu\n", jiffies);
 416                         sc->ani.shortcal_timer = timestamp;
 417                         sc->ani.resetcal_timer = timestamp;
 418                 }
 419         } else {
 420                 if ((timestamp - sc->ani.resetcal_timer) >=
 421                     ATH_RESTART_CALINTERVAL) {
 422                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 423                         if (sc->ani.caldone)
 424                                 sc->ani.resetcal_timer = timestamp;
 425                 }
 426         }
 427
 428         /* Verify whether we must check ANI */
 429         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 430                 aniflag = true;
 431                 sc->ani.checkani_timer = timestamp;
 432         }
 433
 434         /* Skip all processing if there's nothing to do. */
 435         if (longcal || shortcal || aniflag) {
 436                 /* Call ANI routine if necessary */
 437                 if (aniflag)
 438                         ath9k_hw_ani_monitor(ah, ah->curchan);
 439
 440                 /* Perform calibration if necessary */
 441                 if (longcal || shortcal) {
 442                         sc->ani.caldone =
 443                                 ath9k_hw_calibrate(ah,
 444                                                    ah->curchan,
 445                                                    common->rx_chainmask,
 446                                                    longcal);
 447
 448                         if (longcal)
 449                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 450                                                                      ah->curchan);
 451
 452                         ath_print(common, ATH_DBG_ANI,
 453                                   " calibrate chan %u/%x nf: %d\n",
 454                                   ah->curchan->channel,
 455                                   ah->curchan->channelFlags,
 456                                   sc->ani.noise_floor);
 457                 }
 458         }
 459
 460         ath9k_ps_restore(sc);
 461
 462 set_timer:
 463         spin_unlock(&sc->ani_lock);
 464         /*
 465         * Set timer interval based on previous results.
 466         * The interval must be the shortest necessary to satisfy ANI,
 467         * short calibration and long calibration.
 468         */
 469         cal_interval = ATH_LONG_CALINTERVAL;
 470         if (sc->sc_ah->config.enable_ani)
 471                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 472         if (!sc->ani.caldone)
 473                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 474
 475         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 476 }
 477
 478 static void ath_start_ani(struct ath_softc *sc)
 479 {
 480         unsigned long timestamp = jiffies_to_msecs(jiffies);
 481
 482         sc->ani.longcal_timer = timestamp;
 483         sc->ani.shortcal_timer = timestamp;
 484         sc->ani.checkani_timer = timestamp;
 485
 486         mod_timer(&sc->ani.timer,
 487                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 488 }
 489
 490 /*
 491  * Update tx/rx chainmask. For legacy association,
 492  * hard code chainmask to 1x1, for 11n association, use
 493  * the chainmask configuration, for bt coexistence, use
 494  * the chainmask configuration even in legacy mode.
 495  */
 496 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 497 {
 498         struct ath_hw *ah = sc->sc_ah;
 499         struct ath_common *common = ath9k_hw_common(ah);
 500
 501         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
 502             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 503                 common->tx_chainmask = ah->caps.tx_chainmask;
 504                 common->rx_chainmask = ah->caps.rx_chainmask;
 505         } else {
 506                 common->tx_chainmask = 1;
 507                 common->rx_chainmask = 1;
 508         }
 509
 510         ath_print(common, ATH_DBG_CONFIG,
 511                   "tx chmask: %d, rx chmask: %d\n",
 512                   common->tx_chainmask,
 513                   common->rx_chainmask);
 514 }
 515
 516 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 517 {
 518         struct ath_node *an;
 519
 520         an = (struct ath_node *)sta->drv_priv;
 521
 522         if (sc->sc_flags & SC_OP_TXAGGR) {
 523                 ath_tx_node_init(sc, an);
 524                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 525                                      sta->ht_cap.ampdu_factor);
 526                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 527                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 528         }
 529 }
 530
 531 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 532 {
 533         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 534
 535         if (sc->sc_flags & SC_OP_TXAGGR)
 536                 ath_tx_node_cleanup(sc, an);
 537 }
 538
 539 static void ath9k_tasklet(unsigned long data)
 540 {
 541         struct ath_softc *sc = (struct ath_softc *)data;
 542         struct ath_hw *ah = sc->sc_ah;
 543         struct ath_common *common = ath9k_hw_common(ah);
 544
 545         u32 status = sc->intrstatus;
 546
 547         ath9k_ps_wakeup(sc);
 548
 549         if (status & ATH9K_INT_FATAL) {
 550                 ath_reset(sc, false);
 551                 ath9k_ps_restore(sc);
 552                 return;
 553         }
 554
 555         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 556                 spin_lock_bh(&sc->rx.rxflushlock);
 557                 ath_rx_tasklet(sc, 0);
 558                 spin_unlock_bh(&sc->rx.rxflushlock);
 559         }
 560
 561         if (status & ATH9K_INT_TX)
 562                 ath_tx_tasklet(sc);
 563
 564         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 565                 /*
 566                  * TSF sync does not look correct; remain awake to sync with
 567                  * the next Beacon.
 568                  */
 569                 ath_print(common, ATH_DBG_PS,
 570                           "TSFOOR - Sync with next Beacon\n");
 571                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 572         }
 573
 574         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 575                 if (status & ATH9K_INT_GENTIMER)
 576                         ath_gen_timer_isr(sc->sc_ah);
 577
 578         /* re-enable hardware interrupt */
 579         ath9k_hw_set_interrupts(ah, sc->imask);
 580         ath9k_ps_restore(sc);
 581 }
 582
 583 irqreturn_t ath_isr(int irq, void *dev)
 584 {
 585 #define SCHED_INTR (                            \
 586                 ATH9K_INT_FATAL |               \
 587                 ATH9K_INT_RXORN |               \
 588                 ATH9K_INT_RXEOL |               \
 589                 ATH9K_INT_RX |                  \
 590                 ATH9K_INT_TX |                  \
 591                 ATH9K_INT_BMISS |               \
 592                 ATH9K_INT_CST |                 \
 593                 ATH9K_INT_TSFOOR |              \
 594                 ATH9K_INT_GENTIMER)
 595
 596         struct ath_softc *sc = dev;
 597         struct ath_hw *ah = sc->sc_ah;
 598         enum ath9k_int status;
 599         bool sched = false;
 600
 601         /*
 602          * The hardware is not ready/present, don't
 603          * touch anything. Note this can happen early
 604          * on if the IRQ is shared.
 605          */
 606         if (sc->sc_flags & SC_OP_INVALID)
 607                 return IRQ_NONE;
 608
 609
 610         /* shared irq, not for us */
 611
 612         if (!ath9k_hw_intrpend(ah))
 613                 return IRQ_NONE;
 614
 615         /*
 616          * Figure out the reason(s) for the interrupt.  Note
 617          * that the hal returns a pseudo-ISR that may include
 618          * bits we haven't explicitly enabled so we mask the
 619          * value to insure we only process bits we requested.
 620          */
 621         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 622         status &= sc->imask;    /* discard unasked-for bits */
 623
 624         /*
 625          * If there are no status bits set, then this interrupt was not
 626          * for me (should have been caught above).
 627          */
 628         if (!status)
 629                 return IRQ_NONE;
 630
 631         /* Cache the status */
 632         sc->intrstatus = status;
 633
 634         if (status & SCHED_INTR)
 635                 sched = true;
 636
 637         /*
 638          * If a FATAL or RXORN interrupt is received, we have to reset the
 639          * chip immediately.
 640          */
 641         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 642                 goto chip_reset;
 643
 644         if (status & ATH9K_INT_SWBA)
 645                 tasklet_schedule(&sc->bcon_tasklet);
 646
 647         if (status & ATH9K_INT_TXURN)
 648                 ath9k_hw_updatetxtriglevel(ah, true);
 649
 650         if (status & ATH9K_INT_MIB) {
 651                 /*
 652                  * Disable interrupts until we service the MIB
 653                  * interrupt; otherwise it will continue to
 654                  * fire.
 655                  */
 656                 ath9k_hw_set_interrupts(ah, 0);
 657                 /*
 658                  * Let the hal handle the event. We assume
 659                  * it will clear whatever condition caused
 660                  * the interrupt.
 661                  */
 662                 ath9k_hw_procmibevent(ah);
 663                 ath9k_hw_set_interrupts(ah, sc->imask);
 664         }
 665
 666         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 667                 if (status & ATH9K_INT_TIM_TIMER) {
 668                         /* Clear RxAbort bit so that we can
 669                          * receive frames */
 670                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 671                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 672                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 673                 }
 674
 675 chip_reset:
 676
 677         ath_debug_stat_interrupt(sc, status);
 678
 679         if (sched) {
 680                 /* turn off every interrupt except SWBA */
 681                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 682                 tasklet_schedule(&sc->intr_tq);
 683         }
 684
 685         return IRQ_HANDLED;
 686
 687 #undef SCHED_INTR
 688 }
 689
 690 static u32 ath_get_extchanmode(struct ath_softc *sc,
 691                                struct ieee80211_channel *chan,
 692                                enum nl80211_channel_type channel_type)
 693 {
 694         u32 chanmode = 0;
 695
 696         switch (chan->band) {
 697         case IEEE80211_BAND_2GHZ:
 698                 switch(channel_type) {
 699                 case NL80211_CHAN_NO_HT:
 700                 case NL80211_CHAN_HT20:
 701                         chanmode = CHANNEL_G_HT20;
 702                         break;
 703                 case NL80211_CHAN_HT40PLUS:
 704                         chanmode = CHANNEL_G_HT40PLUS;
 705                         break;
 706                 case NL80211_CHAN_HT40MINUS:
 707                         chanmode = CHANNEL_G_HT40MINUS;
 708                         break;
 709                 }
 710                 break;
 711         case IEEE80211_BAND_5GHZ:
 712                 switch(channel_type) {
 713                 case NL80211_CHAN_NO_HT:
 714                 case NL80211_CHAN_HT20:
 715                         chanmode = CHANNEL_A_HT20;
 716                         break;
 717                 case NL80211_CHAN_HT40PLUS:
 718                         chanmode = CHANNEL_A_HT40PLUS;
 719                         break;
 720                 case NL80211_CHAN_HT40MINUS:
 721                         chanmode = CHANNEL_A_HT40MINUS;
 722                         break;
 723                 }
 724                 break;
 725         default:
 726                 break;
 727         }
 728
 729         return chanmode;
 730 }
 731
 732 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 733                            struct ath9k_keyval *hk, const u8 *addr,
 734                            bool authenticator)
 735 {
 736         const u8 *key_rxmic;
 737         const u8 *key_txmic;
 738
 739         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 740         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 741
 742         if (addr == NULL) {
 743                 /*
 744                  * Group key installation - only two key cache entries are used
 745                  * regardless of splitmic capability since group key is only
 746                  * used either for TX or RX.
 747                  */
 748                 if (authenticator) {
 749                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 750                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 751                 } else {
 752                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 753                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 754                 }
 755                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 756         }
 757         if (!sc->splitmic) {
 758                 /* TX and RX keys share the same key cache entry. */
 759                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 760                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 761                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 762         }
 763
 764         /* Separate key cache entries for TX and RX */
 765
 766         /* TX key goes at first index, RX key at +32. */
 767         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 768         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 769                 /* TX MIC entry failed. No need to proceed further */
 770                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
 771                           "Setting TX MIC Key Failed\n");
 772                 return 0;
 773         }
 774
 775         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 776         /* XXX delete tx key on failure? */
 777         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 778 }
 779
 780 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 781 {
 782         int i;
 783
 784         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 785                 if (test_bit(i, sc->keymap) ||
 786                     test_bit(i + 64, sc->keymap))
 787                         continue; /* At least one part of TKIP key allocated */
 788                 if (sc->splitmic &&
 789                     (test_bit(i + 32, sc->keymap) ||
 790                      test_bit(i + 64 + 32, sc->keymap)))
 791                         continue; /* At least one part of TKIP key allocated */
 792
 793                 /* Found a free slot for a TKIP key */
 794                 return i;
 795         }
 796         return -1;
 797 }
 798
 799 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 800 {
 801         int i;
 802
 803         /* First, try to find slots that would not be available for TKIP. */
 804         if (sc->splitmic) {
 805                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 806                         if (!test_bit(i, sc->keymap) &&
 807                             (test_bit(i + 32, sc->keymap) ||
 808                              test_bit(i + 64, sc->keymap) ||
 809                              test_bit(i + 64 + 32, sc->keymap)))
 810                                 return i;
 811                         if (!test_bit(i + 32, sc->keymap) &&
 812                             (test_bit(i, sc->keymap) ||
 813                              test_bit(i + 64, sc->keymap) ||
 814                              test_bit(i + 64 + 32, sc->keymap)))
 815                                 return i + 32;
 816                         if (!test_bit(i + 64, sc->keymap) &&
 817                             (test_bit(i , sc->keymap) ||
 818                              test_bit(i + 32, sc->keymap) ||
 819                              test_bit(i + 64 + 32, sc->keymap)))
 820                                 return i + 64;
 821                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 822                             (test_bit(i, sc->keymap) ||
 823                              test_bit(i + 32, sc->keymap) ||
 824                              test_bit(i + 64, sc->keymap)))
 825                                 return i + 64 + 32;
 826                 }
 827         } else {
 828                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 829                         if (!test_bit(i, sc->keymap) &&
 830                             test_bit(i + 64, sc->keymap))
 831                                 return i;
 832                         if (test_bit(i, sc->keymap) &&
 833                             !test_bit(i + 64, sc->keymap))
 834                                 return i + 64;
 835                 }
 836         }
 837
 838         /* No partially used TKIP slots, pick any available slot */
 839         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 840                 /* Do not allow slots that could be needed for TKIP group keys
 841                  * to be used. This limitation could be removed if we know that
 842                  * TKIP will not be used. */
 843                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 844                         continue;
 845                 if (sc->splitmic) {
 846                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 847                                 continue;
 848                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 849                                 continue;
 850                 }
 851
 852                 if (!test_bit(i, sc->keymap))
 853                         return i; /* Found a free slot for a key */
 854         }
 855
 856         /* No free slot found */
 857         return -1;
 858 }
 859
 860 static int ath_key_config(struct ath_softc *sc,
 861                           struct ieee80211_vif *vif,
 862                           struct ieee80211_sta *sta,
 863                           struct ieee80211_key_conf *key)
 864 {
 865         struct ath9k_keyval hk;
 866         const u8 *mac = NULL;
 867         int ret = 0;
 868         int idx;
 869
 870         memset(&hk, 0, sizeof(hk));
 871
 872         switch (key->alg) {
 873         case ALG_WEP:
 874                 hk.kv_type = ATH9K_CIPHER_WEP;
 875                 break;
 876         case ALG_TKIP:
 877                 hk.kv_type = ATH9K_CIPHER_TKIP;
 878                 break;
 879         case ALG_CCMP:
 880                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 881                 break;
 882         default:
 883                 return -EOPNOTSUPP;
 884         }
 885
 886         hk.kv_len = key->keylen;
 887         memcpy(hk.kv_val, key->key, key->keylen);
 888
 889         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 890                 /* For now, use the default keys for broadcast keys. This may
 891                  * need to change with virtual interfaces. */
 892                 idx = key->keyidx;
 893         } else if (key->keyidx) {
 894                 if (WARN_ON(!sta))
 895                         return -EOPNOTSUPP;
 896                 mac = sta->addr;
 897
 898                 if (vif->type != NL80211_IFTYPE_AP) {
 899                         /* Only keyidx 0 should be used with unicast key, but
 900                          * allow this for client mode for now. */
 901                         idx = key->keyidx;
 902                 } else
 903                         return -EIO;
 904         } else {
 905                 if (WARN_ON(!sta))
 906                         return -EOPNOTSUPP;
 907                 mac = sta->addr;
 908
 909                 if (key->alg == ALG_TKIP)
 910                         idx = ath_reserve_key_cache_slot_tkip(sc);
 911                 else
 912                         idx = ath_reserve_key_cache_slot(sc);
 913                 if (idx < 0)
 914                         return -ENOSPC; /* no free key cache entries */
 915         }
 916
 917         if (key->alg == ALG_TKIP)
 918                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 919                                       vif->type == NL80211_IFTYPE_AP);
 920         else
 921                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 922
 923         if (!ret)
 924                 return -EIO;
 925
 926         set_bit(idx, sc->keymap);
 927         if (key->alg == ALG_TKIP) {
 928                 set_bit(idx + 64, sc->keymap);
 929                 if (sc->splitmic) {
 930                         set_bit(idx + 32, sc->keymap);
 931                         set_bit(idx + 64 + 32, sc->keymap);
 932                 }
 933         }
 934
 935         return idx;
 936 }
 937
 938 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 939 {
 940         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 941         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 942                 return;
 943
 944         clear_bit(key->hw_key_idx, sc->keymap);
 945         if (key->alg != ALG_TKIP)
 946                 return;
 947
 948         clear_bit(key->hw_key_idx + 64, sc->keymap);
 949         if (sc->splitmic) {
 950                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 951                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 952         }
 953 }
 954
 955 static void setup_ht_cap(struct ath_softc *sc,
 956                          struct ieee80211_sta_ht_cap *ht_info)
 957 {
 958         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 959         u8 tx_streams, rx_streams;
 960
 961         ht_info->ht_supported = true;
 962         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 963                        IEEE80211_HT_CAP_SM_PS |
 964                        IEEE80211_HT_CAP_SGI_40 |
 965                        IEEE80211_HT_CAP_DSSSCCK40;
 966
 967         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 968         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 969
 970         /* set up supported mcs set */
 971         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 972         tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
 973                      1 : 2;
 974         rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
 975                      1 : 2;
 976
 977         if (tx_streams != rx_streams) {
 978                 ath_print(common, ATH_DBG_CONFIG,
 979                           "TX streams %d, RX streams: %d\n",
 980                           tx_streams, rx_streams);
 981                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 982                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 983                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 984         }
 985
 986         ht_info->mcs.rx_mask[0] = 0xff;
 987         if (rx_streams >= 2)
 988                 ht_info->mcs.rx_mask[1] = 0xff;
 989
 990         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 991 }
 992
 993 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 994                                  struct ieee80211_vif *vif,
 995                                  struct ieee80211_bss_conf *bss_conf)
 996 {
 997         struct ath_hw *ah = sc->sc_ah;
 998         struct ath_common *common = ath9k_hw_common(ah);
 999
1000         if (bss_conf->assoc) {
1001                 ath_print(common, ATH_DBG_CONFIG,
1002                           "Bss Info ASSOC %d, bssid: %pM\n",
1003                            bss_conf->aid, common->curbssid);
1004
1005                 /* New association, store aid */
1006                 common->curaid = bss_conf->aid;
1007                 ath9k_hw_write_associd(ah);
1008
1009                 /*
1010                  * Request a re-configuration of Beacon related timers
1011                  * on the receipt of the first Beacon frame (i.e.,
1012                  * after time sync with the AP).
1013                  */
1014                 sc->sc_flags |= SC_OP_BEACON_SYNC;
1015
1016                 /* Configure the beacon */
1017                 ath_beacon_config(sc, vif);
1018
1019                 /* Reset rssi stats */
1020                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1021
1022                 ath_start_ani(sc);
1023         } else {
1024                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1025                 common->curaid = 0;
1026                 /* Stop ANI */
1027                 del_timer_sync(&sc->ani.timer);
1028         }
1029 }
1030
1031 /********************************/
1032 /*       LED functions          */
1033 /********************************/
1034
1035 static void ath_led_blink_work(struct work_struct *work)
1036 {
1037         struct ath_softc *sc = container_of(work, struct ath_softc,
1038                                             ath_led_blink_work.work);
1039
1040         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1041                 return;
1042
1043         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1044             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1045                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1046         else
1047                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1048                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1049
1050         ieee80211_queue_delayed_work(sc->hw,
1051                                      &sc->ath_led_blink_work,
1052                                      (sc->sc_flags & SC_OP_LED_ON) ?
1053                                         msecs_to_jiffies(sc->led_off_duration) :
1054                                         msecs_to_jiffies(sc->led_on_duration));
1055
1056         sc->led_on_duration = sc->led_on_cnt ?
1057                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1058                         ATH_LED_ON_DURATION_IDLE;
1059         sc->led_off_duration = sc->led_off_cnt ?
1060                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1061                         ATH_LED_OFF_DURATION_IDLE;
1062         sc->led_on_cnt = sc->led_off_cnt = 0;
1063         if (sc->sc_flags & SC_OP_LED_ON)
1064                 sc->sc_flags &= ~SC_OP_LED_ON;
1065         else
1066                 sc->sc_flags |= SC_OP_LED_ON;
1067 }
1068
1069 static void ath_led_brightness(struct led_classdev *led_cdev,
1070                                enum led_brightness brightness)
1071 {
1072         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1073         struct ath_softc *sc = led->sc;
1074
1075         switch (brightness) {
1076         case LED_OFF:
1077                 if (led->led_type == ATH_LED_ASSOC ||
1078                     led->led_type == ATH_LED_RADIO) {
1079                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1080                                 (led->led_type == ATH_LED_RADIO));
1081                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1082                         if (led->led_type == ATH_LED_RADIO)
1083                                 sc->sc_flags &= ~SC_OP_LED_ON;
1084                 } else {
1085                         sc->led_off_cnt++;
1086                 }
1087                 break;
1088         case LED_FULL:
1089                 if (led->led_type == ATH_LED_ASSOC) {
1090                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1091                         ieee80211_queue_delayed_work(sc->hw,
1092                                                      &sc->ath_led_blink_work, 0);
1093                 } else if (led->led_type == ATH_LED_RADIO) {
1094                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1095                         sc->sc_flags |= SC_OP_LED_ON;
1096                 } else {
1097                         sc->led_on_cnt++;
1098                 }
1099                 break;
1100         default:
1101                 break;
1102         }
1103 }
1104
1105 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1106                             char *trigger)
1107 {
1108         int ret;
1109
1110         led->sc = sc;
1111         led->led_cdev.name = led->name;
1112         led->led_cdev.default_trigger = trigger;
1113         led->led_cdev.brightness_set = ath_led_brightness;
1114
1115         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1116         if (ret)
1117                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1118                           "Failed to register led:%s", led->name);
1119         else
1120                 led->registered = 1;
1121         return ret;
1122 }
1123
1124 static void ath_unregister_led(struct ath_led *led)
1125 {
1126         if (led->registered) {
1127                 led_classdev_unregister(&led->led_cdev);
1128                 led->registered = 0;
1129         }
1130 }
1131
1132 static void ath_deinit_leds(struct ath_softc *sc)
1133 {
1134         ath_unregister_led(&sc->assoc_led);
1135         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1136         ath_unregister_led(&sc->tx_led);
1137         ath_unregister_led(&sc->rx_led);
1138         ath_unregister_led(&sc->radio_led);
1139         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1140 }
1141
1142 static void ath_init_leds(struct ath_softc *sc)
1143 {
1144         char *trigger;
1145         int ret;
1146
1147         if (AR_SREV_9287(sc->sc_ah))
1148                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1149         else
1150                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1151
1152         /* Configure gpio 1 for output */
1153         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1154                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1155         /* LED off, active low */
1156         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1157
1158         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1159
1160         trigger = ieee80211_get_radio_led_name(sc->hw);
1161         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1162                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1163         ret = ath_register_led(sc, &sc->radio_led, trigger);
1164         sc->radio_led.led_type = ATH_LED_RADIO;
1165         if (ret)
1166                 goto fail;
1167
1168         trigger = ieee80211_get_assoc_led_name(sc->hw);
1169         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1170                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1171         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1172         sc->assoc_led.led_type = ATH_LED_ASSOC;
1173         if (ret)
1174                 goto fail;
1175
1176         trigger = ieee80211_get_tx_led_name(sc->hw);
1177         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1178                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1179         ret = ath_register_led(sc, &sc->tx_led, trigger);
1180         sc->tx_led.led_type = ATH_LED_TX;
1181         if (ret)
1182                 goto fail;
1183
1184         trigger = ieee80211_get_rx_led_name(sc->hw);
1185         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1186                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1187         ret = ath_register_led(sc, &sc->rx_led, trigger);
1188         sc->rx_led.led_type = ATH_LED_RX;
1189         if (ret)
1190                 goto fail;
1191
1192         return;
1193
1194 fail:
1195         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1196         ath_deinit_leds(sc);
1197 }
1198
1199 void ath_radio_enable(struct ath_softc *sc)
1200 {
1201         struct ath_hw *ah = sc->sc_ah;
1202         struct ath_common *common = ath9k_hw_common(ah);
1203         struct ieee80211_channel *channel = sc->hw->conf.channel;
1204         int r;
1205
1206         ath9k_ps_wakeup(sc);
1207         ath9k_hw_configpcipowersave(ah, 0, 0);
1208
1209         if (!ah->curchan)
1210                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1211
1212         spin_lock_bh(&sc->sc_resetlock);
1213         r = ath9k_hw_reset(ah, ah->curchan, false);
1214         if (r) {
1215                 ath_print(common, ATH_DBG_FATAL,
1216                           "Unable to reset channel %u (%uMhz) ",
1217                           "reset status %d\n",
1218                           channel->center_freq, r);
1219         }
1220         spin_unlock_bh(&sc->sc_resetlock);
1221
1222         ath_update_txpow(sc);
1223         if (ath_startrecv(sc) != 0) {
1224                 ath_print(common, ATH_DBG_FATAL,
1225                           "Unable to restart recv logic\n");
1226                 return;
1227         }
1228
1229         if (sc->sc_flags & SC_OP_BEACONS)
1230                 ath_beacon_config(sc, NULL);    /* restart beacons */
1231
1232         /* Re-Enable  interrupts */
1233         ath9k_hw_set_interrupts(ah, sc->imask);
1234
1235         /* Enable LED */
1236         ath9k_hw_cfg_output(ah, ah->led_pin,
1237                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1238         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1239
1240         ieee80211_wake_queues(sc->hw);
1241         ath9k_ps_restore(sc);
1242 }
1243
1244 void ath_radio_disable(struct ath_softc *sc)
1245 {
1246         struct ath_hw *ah = sc->sc_ah;
1247         struct ieee80211_channel *channel = sc->hw->conf.channel;
1248         int r;
1249
1250         ath9k_ps_wakeup(sc);
1251         ieee80211_stop_queues(sc->hw);
1252
1253         /* Disable LED */
1254         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1255         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1256
1257         /* Disable interrupts */
1258         ath9k_hw_set_interrupts(ah, 0);
1259
1260         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1261         ath_stoprecv(sc);               /* turn off frame recv */
1262         ath_flushrecv(sc);              /* flush recv queue */
1263
1264         if (!ah->curchan)
1265                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1266
1267         spin_lock_bh(&sc->sc_resetlock);
1268         r = ath9k_hw_reset(ah, ah->curchan, false);
1269         if (r) {
1270                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1271                           "Unable to reset channel %u (%uMhz) "
1272                           "reset status %d\n",
1273                           channel->center_freq, r);
1274         }
1275         spin_unlock_bh(&sc->sc_resetlock);
1276
1277         ath9k_hw_phy_disable(ah);
1278         ath9k_hw_configpcipowersave(ah, 1, 1);
1279         ath9k_ps_restore(sc);
1280         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1281 }
1282
1283 /*******************/
1284 /*      Rfkill     */
1285 /*******************/
1286
1287 static bool ath_is_rfkill_set(struct ath_softc *sc)
1288 {
1289         struct ath_hw *ah = sc->sc_ah;
1290
1291         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1292                                   ah->rfkill_polarity;
1293 }
1294
1295 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1296 {
1297         struct ath_wiphy *aphy = hw->priv;
1298         struct ath_softc *sc = aphy->sc;
1299         bool blocked = !!ath_is_rfkill_set(sc);
1300
1301         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1302 }
1303
1304 static void ath_start_rfkill_poll(struct ath_softc *sc)
1305 {
1306         struct ath_hw *ah = sc->sc_ah;
1307
1308         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1309                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1310 }
1311
1312 void ath_cleanup(struct ath_softc *sc)
1313 {
1314         ath_detach(sc);
1315         free_irq(sc->irq, sc);
1316         ath_bus_cleanup(sc);
1317         kfree(sc->sec_wiphy);
1318         ieee80211_free_hw(sc->hw);
1319 }
1320
1321 void ath_detach(struct ath_softc *sc)
1322 {
1323         struct ieee80211_hw *hw = sc->hw;
1324         struct ath_hw *ah = sc->sc_ah;
1325         int i = 0;
1326
1327         ath9k_ps_wakeup(sc);
1328
1329         dev_dbg(sc->dev, "Detach ATH hw\n");
1330
1331         ath_deinit_leds(sc);
1332         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1333
1334         for (i = 0; i < sc->num_sec_wiphy; i++) {
1335                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1336                 if (aphy == NULL)
1337                         continue;
1338                 sc->sec_wiphy[i] = NULL;
1339                 ieee80211_unregister_hw(aphy->hw);
1340                 ieee80211_free_hw(aphy->hw);
1341         }
1342         ieee80211_unregister_hw(hw);
1343         ath_rx_cleanup(sc);
1344         ath_tx_cleanup(sc);
1345
1346         tasklet_kill(&sc->intr_tq);
1347         tasklet_kill(&sc->bcon_tasklet);
1348
1349         if (!(sc->sc_flags & SC_OP_INVALID))
1350                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1351
1352         /* cleanup tx queues */
1353         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1354                 if (ATH_TXQ_SETUP(sc, i))
1355                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1356
1357         if ((sc->btcoex.no_stomp_timer) &&
1358             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1359                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1360
1361         ath9k_hw_detach(ah);
1362         ath9k_exit_debug(ah);
1363         sc->sc_ah = NULL;
1364 }
1365
1366 static int ath9k_reg_notifier(struct wiphy *wiphy,
1367                               struct regulatory_request *request)
1368 {
1369         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1370         struct ath_wiphy *aphy = hw->priv;
1371         struct ath_softc *sc = aphy->sc;
1372         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1373
1374         return ath_reg_notifier_apply(wiphy, request, reg);
1375 }
1376
1377 /*
1378  * Detects if there is any priority bt traffic
1379  */
1380 static void ath_detect_bt_priority(struct ath_softc *sc)
1381 {
1382         struct ath_btcoex *btcoex = &sc->btcoex;
1383         struct ath_hw *ah = sc->sc_ah;
1384
1385         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1386                 btcoex->bt_priority_cnt++;
1387
1388         if (time_after(jiffies, btcoex->bt_priority_time +
1389                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1390                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1391                         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1392                                   "BT priority traffic detected");
1393                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1394                 } else {
1395                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1396                 }
1397
1398                 btcoex->bt_priority_cnt = 0;
1399                 btcoex->bt_priority_time = jiffies;
1400         }
1401 }
1402
1403 /*
1404  * Configures appropriate weight based on stomp type.
1405  */
1406 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1407                                   enum ath_stomp_type stomp_type)
1408 {
1409         struct ath_hw *ah = sc->sc_ah;
1410
1411         switch (stomp_type) {
1412         case ATH_BTCOEX_STOMP_ALL:
1413                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1414                                            AR_STOMP_ALL_WLAN_WGHT);
1415                 break;
1416         case ATH_BTCOEX_STOMP_LOW:
1417                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1418                                            AR_STOMP_LOW_WLAN_WGHT);
1419                 break;
1420         case ATH_BTCOEX_STOMP_NONE:
1421                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1422                                            AR_STOMP_NONE_WLAN_WGHT);
1423                 break;
1424         default:
1425                 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1426                           "Invalid Stomptype\n");
1427                 break;
1428         }
1429
1430         ath9k_hw_btcoex_enable(ah);
1431 }
1432
1433 static void ath9k_gen_timer_start(struct ath_hw *ah,
1434                                   struct ath_gen_timer *timer,
1435                                   u32 timer_next,
1436                                   u32 timer_period)
1437 {
1438         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1439
1440         if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
1441                 ath9k_hw_set_interrupts(ah, 0);
1442                 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
1443                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1444         }
1445 }
1446
1447 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1448 {
1449         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1450
1451         ath9k_hw_gen_timer_stop(ah, timer);
1452
1453         /* if no timer is enabled, turn off interrupt mask */
1454         if (timer_table->timer_mask.val == 0) {
1455                 ath9k_hw_set_interrupts(ah, 0);
1456                 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
1457                 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
1458         }
1459 }
1460
1461 /*
1462  * This is the master bt coex timer which runs for every
1463  * 45ms, bt traffic will be given priority during 55% of this
1464  * period while wlan gets remaining 45%
1465  */
1466 static void ath_btcoex_period_timer(unsigned long data)
1467 {
1468         struct ath_softc *sc = (struct ath_softc *) data;
1469         struct ath_hw *ah = sc->sc_ah;
1470         struct ath_btcoex *btcoex = &sc->btcoex;
1471
1472         ath_detect_bt_priority(sc);
1473
1474         spin_lock_bh(&btcoex->btcoex_lock);
1475
1476         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1477
1478         spin_unlock_bh(&btcoex->btcoex_lock);
1479
1480         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1481                 if (btcoex->hw_timer_enabled)
1482                         ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1483
1484                 ath9k_gen_timer_start(ah,
1485                                       btcoex->no_stomp_timer,
1486                                       (ath9k_hw_gettsf32(ah) +
1487                                        btcoex->btcoex_no_stomp),
1488                                        btcoex->btcoex_no_stomp * 10);
1489                 btcoex->hw_timer_enabled = true;
1490         }
1491
1492         mod_timer(&btcoex->period_timer, jiffies +
1493                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1494 }
1495
1496 /*
1497  * Generic tsf based hw timer which configures weight
1498  * registers to time slice between wlan and bt traffic
1499  */
1500 static void ath_btcoex_no_stomp_timer(void *arg)
1501 {
1502         struct ath_softc *sc = (struct ath_softc *)arg;
1503         struct ath_hw *ah = sc->sc_ah;
1504         struct ath_btcoex *btcoex = &sc->btcoex;
1505
1506         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1507                   "no stomp timer running \n");
1508
1509         spin_lock_bh(&btcoex->btcoex_lock);
1510
1511         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1512                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1513          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1514                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1515
1516         spin_unlock_bh(&btcoex->btcoex_lock);
1517 }
1518
1519 static int ath_init_btcoex_timer(struct ath_softc *sc)
1520 {
1521         struct ath_btcoex *btcoex = &sc->btcoex;
1522
1523         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1524         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1525                 btcoex->btcoex_period / 100;
1526
1527         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1528                         (unsigned long) sc);
1529
1530         spin_lock_init(&btcoex->btcoex_lock);
1531
1532         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1533                         ath_btcoex_no_stomp_timer,
1534                         ath_btcoex_no_stomp_timer,
1535                         (void *) sc, AR_FIRST_NDP_TIMER);
1536
1537         if (!btcoex->no_stomp_timer)
1538                 return -ENOMEM;
1539
1540         return 0;
1541 }
1542
1543 /*
1544  * Read and write, they both share the same lock. We do this to serialize
1545  * reads and writes on Atheros 802.11n PCI devices only. This is required
1546  * as the FIFO on these devices can only accept sanely 2 requests. After
1547  * that the device goes bananas. Serializing the reads/writes prevents this
1548  * from happening.
1549  */
1550
1551 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1552 {
1553         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1554
1555         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1556                 unsigned long flags;
1557                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1558                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1559                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1560         } else
1561                 iowrite32(val, ah->ah_sc->mem + reg_offset);
1562 }
1563
1564 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1565 {
1566         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1567         u32 val;
1568
1569         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1570                 unsigned long flags;
1571                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
1572                 val = ioread32(ah->ah_sc->mem + reg_offset);
1573                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
1574         } else
1575                 val = ioread32(ah->ah_sc->mem + reg_offset);
1576         return val;
1577 }
1578
1579 static struct ath_ops ath9k_common_ops = {
1580         .read = ath9k_ioread32,
1581         .write = ath9k_iowrite32,
1582 };
1583
1584 /*
1585  * Initialize and fill ath_softc, ath_sofct is the
1586  * "Software Carrier" struct. Historically it has existed
1587  * to allow the separation between hardware specific
1588  * variables (now in ath_hw) and driver specific variables.
1589  */
1590 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1591 {
1592         struct ath_hw *ah = NULL;
1593         struct ath_common *common;
1594         int r = 0, i;
1595         int csz = 0;
1596         int qnum;
1597
1598         /* XXX: hardware will not be ready until ath_open() being called */
1599         sc->sc_flags |= SC_OP_INVALID;
1600
1601         spin_lock_init(&sc->wiphy_lock);
1602         spin_lock_init(&sc->sc_resetlock);
1603         spin_lock_init(&sc->sc_serial_rw);
1604         spin_lock_init(&sc->ani_lock);
1605         spin_lock_init(&sc->sc_pm_lock);
1606         mutex_init(&sc->mutex);
1607         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1608         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1609                      (unsigned long)sc);
1610
1611         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1612         if (!ah) {
1613                 r = -ENOMEM;
1614                 goto bad_no_ah;
1615         }
1616
1617         ah->ah_sc = sc;
1618         ah->hw_version.devid = devid;
1619         ah->hw_version.subsysid = subsysid;
1620         sc->sc_ah = ah;
1621
1622         common = ath9k_hw_common(ah);
1623         common->ops = &ath9k_common_ops;
1624         common->ah = ah;
1625         common->hw = sc->hw;
1626
1627         /*
1628          * Cache line size is used to size and align various
1629          * structures used to communicate with the hardware.
1630          */
1631         ath_read_cachesize(sc, &csz);
1632         /* XXX assert csz is non-zero */
1633         common->cachelsz = csz << 2;    /* convert to bytes */
1634
1635         if (ath9k_init_debug(ah) < 0)
1636                 dev_err(sc->dev, "Unable to create debugfs files\n");
1637
1638         r = ath9k_hw_init(ah);
1639         if (r) {
1640                 ath_print(common, ATH_DBG_FATAL,
1641                           "Unable to initialize hardware; "
1642                           "initialization status: %d\n", r);
1643                 goto bad;
1644         }
1645
1646         /* Get the hardware key cache size. */
1647         sc->keymax = ah->caps.keycache_size;
1648         if (sc->keymax > ATH_KEYMAX) {
1649                 ath_print(common, ATH_DBG_ANY,
1650                           "Warning, using only %u entries in %u key cache\n",
1651                           ATH_KEYMAX, sc->keymax);
1652                 sc->keymax = ATH_KEYMAX;
1653         }
1654
1655         /*
1656          * Reset the key cache since some parts do not
1657          * reset the contents on initial power up.
1658          */
1659         for (i = 0; i < sc->keymax; i++)
1660                 ath9k_hw_keyreset(ah, (u16) i);
1661
1662         /* default to MONITOR mode */
1663         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1664
1665         /* Setup rate tables */
1666
1667         ath_rate_attach(sc);
1668         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1669         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1670
1671         /*
1672          * Allocate hardware transmit queues: one queue for
1673          * beacon frames and one data queue for each QoS
1674          * priority.  Note that the hal handles reseting
1675          * these queues at the needed time.
1676          */
1677         sc->beacon.beaconq = ath_beaconq_setup(ah);
1678         if (sc->beacon.beaconq == -1) {
1679                 ath_print(common, ATH_DBG_FATAL,
1680                           "Unable to setup a beacon xmit queue\n");
1681                 r = -EIO;
1682                 goto bad2;
1683         }
1684         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1685         if (sc->beacon.cabq == NULL) {
1686                 ath_print(common, ATH_DBG_FATAL,
1687                           "Unable to setup CAB xmit queue\n");
1688                 r = -EIO;
1689                 goto bad2;
1690         }
1691
1692         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1693         ath_cabq_update(sc);
1694
1695         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1696                 sc->tx.hwq_map[i] = -1;
1697
1698         /* Setup data queues */
1699         /* NB: ensure BK queue is the lowest priority h/w queue */
1700         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1701                 ath_print(common, ATH_DBG_FATAL,
1702                           "Unable to setup xmit queue for BK traffic\n");
1703                 r = -EIO;
1704                 goto bad2;
1705         }
1706
1707         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1708                 ath_print(common, ATH_DBG_FATAL,
1709                           "Unable to setup xmit queue for BE traffic\n");
1710                 r = -EIO;
1711                 goto bad2;
1712         }
1713         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1714                 ath_print(common, ATH_DBG_FATAL,
1715                           "Unable to setup xmit queue for VI traffic\n");
1716                 r = -EIO;
1717                 goto bad2;
1718         }
1719         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1720                 ath_print(common, ATH_DBG_FATAL,
1721                           "Unable to setup xmit queue for VO traffic\n");
1722                 r = -EIO;
1723                 goto bad2;
1724         }
1725
1726         /* Initializes the noise floor to a reasonable default value.
1727          * Later on this will be updated during ANI processing. */
1728
1729         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1730         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1731
1732         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1733                                    ATH9K_CIPHER_TKIP, NULL)) {
1734                 /*
1735                  * Whether we should enable h/w TKIP MIC.
1736                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1737                  * report WMM capable, so it's always safe to turn on
1738                  * TKIP MIC in this case.
1739                  */
1740                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1741                                        0, 1, NULL);
1742         }
1743
1744         /*
1745          * Check whether the separate key cache entries
1746          * are required to handle both tx+rx MIC keys.
1747          * With split mic keys the number of stations is limited
1748          * to 27 otherwise 59.
1749          */
1750         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1751                                    ATH9K_CIPHER_TKIP, NULL)
1752             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1753                                       ATH9K_CIPHER_MIC, NULL)
1754             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1755                                       0, NULL))
1756                 sc->splitmic = 1;
1757
1758         /* turn on mcast key search if possible */
1759         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1760                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1761                                              1, NULL);
1762
1763         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1764
1765         /* 11n Capabilities */
1766         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1767                 sc->sc_flags |= SC_OP_TXAGGR;
1768                 sc->sc_flags |= SC_OP_RXAGGR;
1769         }
1770
1771         common->tx_chainmask = ah->caps.tx_chainmask;
1772         common->rx_chainmask = ah->caps.rx_chainmask;
1773
1774         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1775         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1776
1777         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1778                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1779
1780         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1781
1782         /* initialize beacon slots */
1783         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1784                 sc->beacon.bslot[i] = NULL;
1785                 sc->beacon.bslot_aphy[i] = NULL;
1786         }
1787
1788         /* setup channels and rates */
1789
1790         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1791         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1792                 sc->rates[IEEE80211_BAND_2GHZ];
1793         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1794         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1795                 ARRAY_SIZE(ath9k_2ghz_chantable);
1796
1797         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1798                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1799                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1800                         sc->rates[IEEE80211_BAND_5GHZ];
1801                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1802                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1803                         ARRAY_SIZE(ath9k_5ghz_chantable);
1804         }
1805
1806         switch (ah->btcoex_hw.scheme) {
1807         case ATH_BTCOEX_CFG_NONE:
1808                 break;
1809         case ATH_BTCOEX_CFG_2WIRE:
1810                 ath9k_hw_btcoex_init_2wire(ah);
1811                 break;
1812         case ATH_BTCOEX_CFG_3WIRE:
1813                 ath9k_hw_btcoex_init_3wire(ah);
1814                 r = ath_init_btcoex_timer(sc);
1815                 if (r)
1816                         goto bad2;
1817                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1818                 ath9k_hw_init_btcoex_hw(ah, qnum);
1819                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1820                 break;
1821         default:
1822                 WARN_ON(1);
1823                 break;
1824         }
1825
1826         return 0;
1827 bad2:
1828         /* cleanup tx queues */
1829         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1830                 if (ATH_TXQ_SETUP(sc, i))
1831                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1832 bad:
1833         ath9k_hw_detach(ah);
1834 bad_no_ah:
1835         ath9k_exit_debug(sc->sc_ah);
1836         sc->sc_ah = NULL;
1837
1838         return r;
1839 }
1840
1841 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1842 {
1843         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1844                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1845                 IEEE80211_HW_SIGNAL_DBM |
1846                 IEEE80211_HW_AMPDU_AGGREGATION |
1847                 IEEE80211_HW_SUPPORTS_PS |
1848                 IEEE80211_HW_PS_NULLFUNC_STACK |
1849                 IEEE80211_HW_SPECTRUM_MGMT;
1850
1851         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1852                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1853
1854         hw->wiphy->interface_modes =
1855                 BIT(NL80211_IFTYPE_AP) |
1856                 BIT(NL80211_IFTYPE_STATION) |
1857                 BIT(NL80211_IFTYPE_ADHOC) |
1858                 BIT(NL80211_IFTYPE_MESH_POINT);
1859
1860         hw->queues = 4;
1861         hw->max_rates = 4;
1862         hw->channel_change_time = 5000;
1863         hw->max_listen_interval = 10;
1864         /* Hardware supports 10 but we use 4 */
1865         hw->max_rate_tries = 4;
1866         hw->sta_data_size = sizeof(struct ath_node);
1867         hw->vif_data_size = sizeof(struct ath_vif);
1868
1869         hw->rate_control_algorithm = "ath9k_rate_control";
1870
1871         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1872                 &sc->sbands[IEEE80211_BAND_2GHZ];
1873         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1874                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1875                         &sc->sbands[IEEE80211_BAND_5GHZ];
1876 }
1877
1878 /* Device driver core initialization */
1879 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1880 {
1881         struct ieee80211_hw *hw = sc->hw;
1882         struct ath_common *common;
1883         struct ath_hw *ah;
1884         int error = 0, i;
1885         struct ath_regulatory *reg;
1886
1887         dev_dbg(sc->dev, "Attach ATH hw\n");
1888
1889         error = ath_init_softc(devid, sc, subsysid);
1890         if (error != 0)
1891                 return error;
1892
1893         ah = sc->sc_ah;
1894         common = ath9k_hw_common(ah);
1895
1896         /* get mac address from hardware and set in mac80211 */
1897
1898         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1899
1900         ath_set_hw_capab(sc, hw);
1901
1902         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1903                               ath9k_reg_notifier);
1904         if (error)
1905                 return error;
1906
1907         reg = &common->regulatory;
1908
1909         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1910                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1911                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1912                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1913         }
1914
1915         /* initialize tx/rx engine */
1916         error = ath_tx_init(sc, ATH_TXBUF);
1917         if (error != 0)
1918                 goto error_attach;
1919
1920         error = ath_rx_init(sc, ATH_RXBUF);
1921         if (error != 0)
1922                 goto error_attach;
1923
1924         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1925         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1926         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1927
1928         error = ieee80211_register_hw(hw);
1929
1930         if (!ath_is_world_regd(reg)) {
1931                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1932                 if (error)
1933                         goto error_attach;
1934         }
1935
1936         /* Initialize LED control */
1937         ath_init_leds(sc);
1938
1939         ath_start_rfkill_poll(sc);
1940
1941         return 0;
1942
1943 error_attach:
1944         /* cleanup tx queues */
1945         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1946                 if (ATH_TXQ_SETUP(sc, i))
1947                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1948
1949         ath9k_hw_detach(ah);
1950         ath9k_exit_debug(ah);
1951         sc->sc_ah = NULL;
1952
1953         return error;
1954 }
1955
1956 int ath_reset(struct ath_softc *sc, bool retry_tx)
1957 {
1958         struct ath_hw *ah = sc->sc_ah;
1959         struct ath_common *common = ath9k_hw_common(ah);
1960         struct ieee80211_hw *hw = sc->hw;
1961         int r;
1962
1963         ath9k_hw_set_interrupts(ah, 0);
1964         ath_drain_all_txq(sc, retry_tx);
1965         ath_stoprecv(sc);
1966         ath_flushrecv(sc);
1967
1968         spin_lock_bh(&sc->sc_resetlock);
1969         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1970         if (r)
1971                 ath_print(common, ATH_DBG_FATAL,
1972                           "Unable to reset hardware; reset status %d\n", r);
1973         spin_unlock_bh(&sc->sc_resetlock);
1974
1975         if (ath_startrecv(sc) != 0)
1976                 ath_print(common, ATH_DBG_FATAL,
1977                           "Unable to start recv logic\n");
1978
1979         /*
1980          * We may be doing a reset in response to a request
1981          * that changes the channel so update any state that
1982          * might change as a result.
1983          */
1984         ath_cache_conf_rate(sc, &hw->conf);
1985
1986         ath_update_txpow(sc);
1987
1988         if (sc->sc_flags & SC_OP_BEACONS)
1989                 ath_beacon_config(sc, NULL);    /* restart beacons */
1990
1991         ath9k_hw_set_interrupts(ah, sc->imask);
1992
1993         if (retry_tx) {
1994                 int i;
1995                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1996                         if (ATH_TXQ_SETUP(sc, i)) {
1997                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1998                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1999                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2000                         }
2001                 }
2002         }
2003
2004         return r;
2005 }
2006
2007 /*
2008  *  This function will allocate both the DMA descriptor structure, and the
2009  *  buffers it contains.  These are used to contain the descriptors used
2010  *  by the system.
2011 */
2012 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2013                       struct list_head *head, const char *name,
2014                       int nbuf, int ndesc)
2015 {
2016 #define DS2PHYS(_dd, _ds)                                               \
2017         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2018 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2019 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2020         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2021         struct ath_desc *ds;
2022         struct ath_buf *bf;
2023         int i, bsize, error;
2024
2025         ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2026                   name, nbuf, ndesc);
2027
2028         INIT_LIST_HEAD(head);
2029         /* ath_desc must be a multiple of DWORDs */
2030         if ((sizeof(struct ath_desc) % 4) != 0) {
2031                 ath_print(common, ATH_DBG_FATAL,
2032                           "ath_desc not DWORD aligned\n");
2033                 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2034                 error = -ENOMEM;
2035                 goto fail;
2036         }
2037
2038         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2039
2040         /*
2041          * Need additional DMA memory because we can't use
2042          * descriptors that cross the 4K page boundary. Assume
2043          * one skipped descriptor per 4K page.
2044          */
2045         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2046                 u32 ndesc_skipped =
2047                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2048                 u32 dma_len;
2049
2050                 while (ndesc_skipped) {
2051                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
2052                         dd->dd_desc_len += dma_len;
2053
2054                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2055                 };
2056         }
2057
2058         /* allocate descriptors */
2059         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2060                                          &dd->dd_desc_paddr, GFP_KERNEL);
2061         if (dd->dd_desc == NULL) {
2062                 error = -ENOMEM;
2063                 goto fail;
2064         }
2065         ds = dd->dd_desc;
2066         ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2067                   name, ds, (u32) dd->dd_desc_len,
2068                   ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2069
2070         /* allocate buffers */
2071         bsize = sizeof(struct ath_buf) * nbuf;
2072         bf = kzalloc(bsize, GFP_KERNEL);
2073         if (bf == NULL) {
2074                 error = -ENOMEM;
2075                 goto fail2;
2076         }
2077         dd->dd_bufptr = bf;
2078
2079         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2080                 bf->bf_desc = ds;
2081                 bf->bf_daddr = DS2PHYS(dd, ds);
2082
2083                 if (!(sc->sc_ah->caps.hw_caps &
2084                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2085                         /*
2086                          * Skip descriptor addresses which can cause 4KB
2087                          * boundary crossing (addr + length) with a 32 dword
2088                          * descriptor fetch.
2089                          */
2090                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2091                                 BUG_ON((caddr_t) bf->bf_desc >=
2092                                        ((caddr_t) dd->dd_desc +
2093                                         dd->dd_desc_len));
2094
2095                                 ds += ndesc;
2096                                 bf->bf_desc = ds;
2097                                 bf->bf_daddr = DS2PHYS(dd, ds);
2098                         }
2099                 }
2100                 list_add_tail(&bf->list, head);
2101         }
2102         return 0;
2103 fail2:
2104         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2105                           dd->dd_desc_paddr);
2106 fail:
2107         memset(dd, 0, sizeof(*dd));
2108         return error;
2109 #undef ATH_DESC_4KB_BOUND_CHECK
2110 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2111 #undef DS2PHYS
2112 }
2113
2114 void ath_descdma_cleanup(struct ath_softc *sc,
2115                          struct ath_descdma *dd,
2116                          struct list_head *head)
2117 {
2118         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2119                           dd->dd_desc_paddr);
2120
2121         INIT_LIST_HEAD(head);
2122         kfree(dd->dd_bufptr);
2123         memset(dd, 0, sizeof(*dd));
2124 }
2125
2126 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2127 {
2128         int qnum;
2129
2130         switch (queue) {
2131         case 0:
2132                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2133                 break;
2134         case 1:
2135                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2136                 break;
2137         case 2:
2138                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2139                 break;
2140         case 3:
2141                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2142                 break;
2143         default:
2144                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2145                 break;
2146         }
2147
2148         return qnum;
2149 }
2150
2151 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2152 {
2153         int qnum;
2154
2155         switch (queue) {
2156         case ATH9K_WME_AC_VO:
2157                 qnum = 0;
2158                 break;
2159         case ATH9K_WME_AC_VI:
2160                 qnum = 1;
2161                 break;
2162         case ATH9K_WME_AC_BE:
2163                 qnum = 2;
2164                 break;
2165         case ATH9K_WME_AC_BK:
2166                 qnum = 3;
2167                 break;
2168         default:
2169                 qnum = -1;
2170                 break;
2171         }
2172
2173         return qnum;
2174 }
2175
2176 /* XXX: Remove me once we don't depend on ath9k_channel for all
2177  * this redundant data */
2178 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2179                            struct ath9k_channel *ichan)
2180 {
2181         struct ieee80211_channel *chan = hw->conf.channel;
2182         struct ieee80211_conf *conf = &hw->conf;
2183
2184         ichan->channel = chan->center_freq;
2185         ichan->chan = chan;
2186
2187         if (chan->band == IEEE80211_BAND_2GHZ) {
2188                 ichan->chanmode = CHANNEL_G;
2189                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2190         } else {
2191                 ichan->chanmode = CHANNEL_A;
2192                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2193         }
2194
2195         if (conf_is_ht(conf))
2196                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2197                                             conf->channel_type);
2198 }
2199
2200 /**********************/
2201 /* mac80211 callbacks */
2202 /**********************/
2203
2204 /*
2205  * (Re)start btcoex timers
2206  */
2207 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2208 {
2209         struct ath_btcoex *btcoex = &sc->btcoex;
2210         struct ath_hw *ah = sc->sc_ah;
2211
2212         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2213                   "Starting btcoex timers");
2214
2215         /* make sure duty cycle timer is also stopped when resuming */
2216         if (btcoex->hw_timer_enabled)
2217                 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2218
2219         btcoex->bt_priority_cnt = 0;
2220         btcoex->bt_priority_time = jiffies;
2221         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2222
2223         mod_timer(&btcoex->period_timer, jiffies);
2224 }
2225
2226 static int ath9k_start(struct ieee80211_hw *hw)
2227 {
2228         struct ath_wiphy *aphy = hw->priv;
2229         struct ath_softc *sc = aphy->sc;
2230         struct ath_hw *ah = sc->sc_ah;
2231         struct ath_common *common = ath9k_hw_common(ah);
2232         struct ieee80211_channel *curchan = hw->conf.channel;
2233         struct ath9k_channel *init_channel;
2234         int r;
2235
2236         ath_print(common, ATH_DBG_CONFIG,
2237                   "Starting driver with initial channel: %d MHz\n",
2238                   curchan->center_freq);
2239
2240         mutex_lock(&sc->mutex);
2241
2242         if (ath9k_wiphy_started(sc)) {
2243                 if (sc->chan_idx == curchan->hw_value) {
2244                         /*
2245                          * Already on the operational channel, the new wiphy
2246                          * can be marked active.
2247                          */
2248                         aphy->state = ATH_WIPHY_ACTIVE;
2249                         ieee80211_wake_queues(hw);
2250                 } else {
2251                         /*
2252                          * Another wiphy is on another channel, start the new
2253                          * wiphy in paused state.
2254                          */
2255                         aphy->state = ATH_WIPHY_PAUSED;
2256                         ieee80211_stop_queues(hw);
2257                 }
2258                 mutex_unlock(&sc->mutex);
2259                 return 0;
2260         }
2261         aphy->state = ATH_WIPHY_ACTIVE;
2262
2263         /* setup initial channel */
2264
2265         sc->chan_idx = curchan->hw_value;
2266
2267         init_channel = ath_get_curchannel(sc, hw);
2268
2269         /* Reset SERDES registers */
2270         ath9k_hw_configpcipowersave(ah, 0, 0);
2271
2272         /*
2273          * The basic interface to setting the hardware in a good
2274          * state is ``reset''.  On return the hardware is known to
2275          * be powered up and with interrupts disabled.  This must
2276          * be followed by initialization of the appropriate bits
2277          * and then setup of the interrupt mask.
2278          */
2279         spin_lock_bh(&sc->sc_resetlock);
2280         r = ath9k_hw_reset(ah, init_channel, false);
2281         if (r) {
2282                 ath_print(common, ATH_DBG_FATAL,
2283                           "Unable to reset hardware; reset status %d "
2284                           "(freq %u MHz)\n", r,
2285                           curchan->center_freq);
2286                 spin_unlock_bh(&sc->sc_resetlock);
2287                 goto mutex_unlock;
2288         }
2289         spin_unlock_bh(&sc->sc_resetlock);
2290
2291         /*
2292          * This is needed only to setup initial state
2293          * but it's best done after a reset.
2294          */
2295         ath_update_txpow(sc);
2296
2297         /*
2298          * Setup the hardware after reset:
2299          * The receive engine is set going.
2300          * Frame transmit is handled entirely
2301          * in the frame output path; there's nothing to do
2302          * here except setup the interrupt mask.
2303          */
2304         if (ath_startrecv(sc) != 0) {
2305                 ath_print(common, ATH_DBG_FATAL,
2306                           "Unable to start recv logic\n");
2307                 r = -EIO;
2308                 goto mutex_unlock;
2309         }
2310
2311         /* Setup our intr mask. */
2312         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2313                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2314                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2315
2316         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2317                 sc->imask |= ATH9K_INT_GTT;
2318
2319         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2320                 sc->imask |= ATH9K_INT_CST;
2321
2322         ath_cache_conf_rate(sc, &hw->conf);
2323
2324         sc->sc_flags &= ~SC_OP_INVALID;
2325
2326         /* Disable BMISS interrupt when we're not associated */
2327         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2328         ath9k_hw_set_interrupts(ah, sc->imask);
2329
2330         ieee80211_wake_queues(hw);
2331
2332         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2333
2334         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2335             !ah->btcoex_hw.enabled) {
2336                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2337                                            AR_STOMP_LOW_WLAN_WGHT);
2338                 ath9k_hw_btcoex_enable(ah);
2339
2340                 if (sc->bus_ops->bt_coex_prep)
2341                         sc->bus_ops->bt_coex_prep(sc);
2342                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2343                         ath9k_btcoex_timer_resume(sc);
2344         }
2345
2346 mutex_unlock:
2347         mutex_unlock(&sc->mutex);
2348
2349         return r;
2350 }
2351
2352 static int ath9k_tx(struct ieee80211_hw *hw,
2353                     struct sk_buff *skb)
2354 {
2355         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2356         struct ath_wiphy *aphy = hw->priv;
2357         struct ath_softc *sc = aphy->sc;
2358         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2359         struct ath_tx_control txctl;
2360         int hdrlen, padsize;
2361
2362         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2363                 ath_print(common, ATH_DBG_XMIT,
2364                           "ath9k: %s: TX in unexpected wiphy state "
2365                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
2366                 goto exit;
2367         }
2368
2369         if (sc->ps_enabled) {
2370                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2371                 /*
2372                  * mac80211 does not set PM field for normal data frames, so we
2373                  * need to update that based on the current PS mode.
2374                  */
2375                 if (ieee80211_is_data(hdr->frame_control) &&
2376                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2377                     !ieee80211_has_pm(hdr->frame_control)) {
2378                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2379                                   "while in PS mode\n");
2380                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2381                 }
2382         }
2383
2384         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2385                 /*
2386                  * We are using PS-Poll and mac80211 can request TX while in
2387                  * power save mode. Need to wake up hardware for the TX to be
2388                  * completed and if needed, also for RX of buffered frames.
2389                  */
2390                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2391                 ath9k_ps_wakeup(sc);
2392                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2393                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2394                         ath_print(common, ATH_DBG_PS,
2395                                   "Sending PS-Poll to pick a buffered frame\n");
2396                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2397                 } else {
2398                         ath_print(common, ATH_DBG_PS,
2399                                   "Wake up to complete TX\n");
2400                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2401                 }
2402                 /*
2403                  * The actual restore operation will happen only after
2404                  * the sc_flags bit is cleared. We are just dropping
2405                  * the ps_usecount here.
2406                  */
2407                 ath9k_ps_restore(sc);
2408         }
2409
2410         memset(&txctl, 0, sizeof(struct ath_tx_control));
2411
2412         /*
2413          * As a temporary workaround, assign seq# here; this will likely need
2414          * to be cleaned up to work better with Beacon transmission and virtual
2415          * BSSes.
2416          */
2417         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2418                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2419                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2420                         sc->tx.seq_no += 0x10;
2421                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2422                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2423         }
2424
2425         /* Add the padding after the header if this is not already done */
2426         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2427         if (hdrlen & 3) {
2428                 padsize = hdrlen % 4;
2429                 if (skb_headroom(skb) < padsize)
2430                         return -1;
2431                 skb_push(skb, padsize);
2432                 memmove(skb->data, skb->data + padsize, hdrlen);
2433         }
2434
2435         /* Check if a tx queue is available */
2436
2437         txctl.txq = ath_test_get_txq(sc, skb);
2438         if (!txctl.txq)
2439                 goto exit;
2440
2441         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2442
2443         if (ath_tx_start(hw, skb, &txctl) != 0) {
2444                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2445                 goto exit;
2446         }
2447
2448         return 0;
2449 exit:
2450         dev_kfree_skb_any(skb);
2451         return 0;
2452 }
2453
2454 /*
2455  * Pause btcoex timer and bt duty cycle timer
2456  */
2457 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2458 {
2459         struct ath_btcoex *btcoex = &sc->btcoex;
2460         struct ath_hw *ah = sc->sc_ah;
2461
2462         del_timer_sync(&btcoex->period_timer);
2463
2464         if (btcoex->hw_timer_enabled)
2465                 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2466
2467         btcoex->hw_timer_enabled = false;
2468 }
2469
2470 static void ath9k_stop(struct ieee80211_hw *hw)
2471 {
2472         struct ath_wiphy *aphy = hw->priv;
2473         struct ath_softc *sc = aphy->sc;
2474         struct ath_hw *ah = sc->sc_ah;
2475         struct ath_common *common = ath9k_hw_common(ah);
2476
2477         mutex_lock(&sc->mutex);
2478
2479         aphy->state = ATH_WIPHY_INACTIVE;
2480
2481         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2482         cancel_delayed_work_sync(&sc->tx_complete_work);
2483
2484         if (!sc->num_sec_wiphy) {
2485                 cancel_delayed_work_sync(&sc->wiphy_work);
2486                 cancel_work_sync(&sc->chan_work);
2487         }
2488
2489         if (sc->sc_flags & SC_OP_INVALID) {
2490                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2491                 mutex_unlock(&sc->mutex);
2492                 return;
2493         }
2494
2495         if (ath9k_wiphy_started(sc)) {
2496                 mutex_unlock(&sc->mutex);
2497                 return; /* another wiphy still in use */
2498         }
2499
2500         if (ah->btcoex_hw.enabled) {
2501                 ath9k_hw_btcoex_disable(ah);
2502                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2503                         ath9k_btcoex_timer_pause(sc);
2504         }
2505
2506         /* make sure h/w will not generate any interrupt
2507          * before setting the invalid flag. */
2508         ath9k_hw_set_interrupts(ah, 0);
2509
2510         if (!(sc->sc_flags & SC_OP_INVALID)) {
2511                 ath_drain_all_txq(sc, false);
2512                 ath_stoprecv(sc);
2513                 ath9k_hw_phy_disable(ah);
2514         } else
2515                 sc->rx.rxlink = NULL;
2516
2517         /* disable HAL and put h/w to sleep */
2518         ath9k_hw_disable(ah);
2519         ath9k_hw_configpcipowersave(ah, 1, 1);
2520         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2521
2522         sc->sc_flags |= SC_OP_INVALID;
2523
2524         mutex_unlock(&sc->mutex);
2525
2526         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2527 }
2528
2529 static int ath9k_add_interface(struct ieee80211_hw *hw,
2530                                struct ieee80211_if_init_conf *conf)
2531 {
2532         struct ath_wiphy *aphy = hw->priv;
2533         struct ath_softc *sc = aphy->sc;
2534         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2535         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2536         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2537         int ret = 0;
2538
2539         mutex_lock(&sc->mutex);
2540
2541         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2542             sc->nvifs > 0) {
2543                 ret = -ENOBUFS;
2544                 goto out;
2545         }
2546
2547         switch (conf->type) {
2548         case NL80211_IFTYPE_STATION:
2549                 ic_opmode = NL80211_IFTYPE_STATION;
2550                 break;
2551         case NL80211_IFTYPE_ADHOC:
2552         case NL80211_IFTYPE_AP:
2553         case NL80211_IFTYPE_MESH_POINT:
2554                 if (sc->nbcnvifs >= ATH_BCBUF) {
2555                         ret = -ENOBUFS;
2556                         goto out;
2557                 }
2558                 ic_opmode = conf->type;
2559                 break;
2560         default:
2561                 ath_print(common, ATH_DBG_FATAL,
2562                         "Interface type %d not yet supported\n", conf->type);
2563                 ret = -EOPNOTSUPP;
2564                 goto out;
2565         }
2566
2567         ath_print(common, ATH_DBG_CONFIG,
2568                   "Attach a VIF of type: %d\n", ic_opmode);
2569
2570         /* Set the VIF opmode */
2571         avp->av_opmode = ic_opmode;
2572         avp->av_bslot = -1;
2573
2574         sc->nvifs++;
2575
2576         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2577                 ath9k_set_bssid_mask(hw);
2578
2579         if (sc->nvifs > 1)
2580                 goto out; /* skip global settings for secondary vif */
2581
2582         if (ic_opmode == NL80211_IFTYPE_AP) {
2583                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2584                 sc->sc_flags |= SC_OP_TSF_RESET;
2585         }
2586
2587         /* Set the device opmode */
2588         sc->sc_ah->opmode = ic_opmode;
2589
2590         /*
2591          * Enable MIB interrupts when there are hardware phy counters.
2592          * Note we only do this (at the moment) for station mode.
2593          */
2594         if ((conf->type == NL80211_IFTYPE_STATION) ||
2595             (conf->type == NL80211_IFTYPE_ADHOC) ||
2596             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2597                 sc->imask |= ATH9K_INT_MIB;
2598                 sc->imask |= ATH9K_INT_TSFOOR;
2599         }
2600
2601         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2602
2603         if (conf->type == NL80211_IFTYPE_AP    ||
2604             conf->type == NL80211_IFTYPE_ADHOC ||
2605             conf->type == NL80211_IFTYPE_MONITOR)
2606                 ath_start_ani(sc);
2607
2608 out:
2609         mutex_unlock(&sc->mutex);
2610         return ret;
2611 }
2612
2613 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2614                                    struct ieee80211_if_init_conf *conf)
2615 {
2616         struct ath_wiphy *aphy = hw->priv;
2617         struct ath_softc *sc = aphy->sc;
2618         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2619         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2620         int i;
2621
2622         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2623
2624         mutex_lock(&sc->mutex);
2625
2626         /* Stop ANI */
2627         del_timer_sync(&sc->ani.timer);
2628
2629         /* Reclaim beacon resources */
2630         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2631             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2632             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2633                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2634                 ath_beacon_return(sc, avp);
2635         }
2636
2637         sc->sc_flags &= ~SC_OP_BEACONS;
2638
2639         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2640                 if (sc->beacon.bslot[i] == conf->vif) {
2641                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2642                                "slot\n", __func__);
2643                         sc->beacon.bslot[i] = NULL;
2644                         sc->beacon.bslot_aphy[i] = NULL;
2645                 }
2646         }
2647
2648         sc->nvifs--;
2649
2650         mutex_unlock(&sc->mutex);
2651 }
2652
2653 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2654 {
2655         struct ath_wiphy *aphy = hw->priv;
2656         struct ath_softc *sc = aphy->sc;
2657         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2658         struct ieee80211_conf *conf = &hw->conf;
2659         struct ath_hw *ah = sc->sc_ah;
2660         bool all_wiphys_idle = false, disable_radio = false;
2661
2662         mutex_lock(&sc->mutex);
2663
2664         /* Leave this as the first check */
2665         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2666
2667                 spin_lock_bh(&sc->wiphy_lock);
2668                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2669                 spin_unlock_bh(&sc->wiphy_lock);
2670
2671                 if (conf->flags & IEEE80211_CONF_IDLE){
2672                         if (all_wiphys_idle)
2673                                 disable_radio = true;
2674                 }
2675                 else if (all_wiphys_idle) {
2676                         ath_radio_enable(sc);
2677                         ath_print(common, ATH_DBG_CONFIG,
2678                                   "not-idle: enabling radio\n");
2679                 }
2680         }
2681
2682         if (changed & IEEE80211_CONF_CHANGE_PS) {
2683                 if (conf->flags & IEEE80211_CONF_PS) {
2684                         if (!(ah->caps.hw_caps &
2685                               ATH9K_HW_CAP_AUTOSLEEP)) {
2686                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2687                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2688                                         ath9k_hw_set_interrupts(sc->sc_ah,
2689                                                         sc->imask);
2690                                 }
2691                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2692                         }
2693                         sc->ps_enabled = true;
2694                 } else {
2695                         sc->ps_enabled = false;
2696                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2697                         if (!(ah->caps.hw_caps &
2698                               ATH9K_HW_CAP_AUTOSLEEP)) {
2699                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2700                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2701                                                   SC_OP_WAIT_FOR_CAB |
2702                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2703                                                   SC_OP_WAIT_FOR_TX_ACK);
2704                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2705                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2706                                         ath9k_hw_set_interrupts(sc->sc_ah,
2707                                                         sc->imask);
2708                                 }
2709                         }
2710                 }
2711         }
2712
2713         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2714                 struct ieee80211_channel *curchan = hw->conf.channel;
2715                 int pos = curchan->hw_value;
2716
2717                 aphy->chan_idx = pos;
2718                 aphy->chan_is_ht = conf_is_ht(conf);
2719
2720                 if (aphy->state == ATH_WIPHY_SCAN ||
2721                     aphy->state == ATH_WIPHY_ACTIVE)
2722                         ath9k_wiphy_pause_all_forced(sc, aphy);
2723                 else {
2724                         /*
2725                          * Do not change operational channel based on a paused
2726                          * wiphy changes.
2727                          */
2728                         goto skip_chan_change;
2729                 }
2730
2731                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2732                           curchan->center_freq);
2733
2734                 /* XXX: remove me eventualy */
2735                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2736
2737                 ath_update_chainmask(sc, conf_is_ht(conf));
2738
2739                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2740                         ath_print(common, ATH_DBG_FATAL,
2741                                   "Unable to set channel\n");
2742                         mutex_unlock(&sc->mutex);
2743                         return -EINVAL;
2744                 }
2745         }
2746
2747 skip_chan_change:
2748         if (changed & IEEE80211_CONF_CHANGE_POWER)
2749                 sc->config.txpowlimit = 2 * conf->power_level;
2750
2751         if (disable_radio) {
2752                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2753                 ath_radio_disable(sc);
2754         }
2755
2756         mutex_unlock(&sc->mutex);
2757
2758         return 0;
2759 }
2760
2761 #define SUPPORTED_FILTERS                       \
2762         (FIF_PROMISC_IN_BSS |                   \
2763         FIF_ALLMULTI |                          \
2764         FIF_CONTROL |                           \
2765         FIF_PSPOLL |                            \
2766         FIF_OTHER_BSS |                         \
2767         FIF_BCN_PRBRESP_PROMISC |               \
2768         FIF_FCSFAIL)
2769
2770 /* FIXME: sc->sc_full_reset ? */
2771 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2772                                    unsigned int changed_flags,
2773                                    unsigned int *total_flags,
2774                                    u64 multicast)
2775 {
2776         struct ath_wiphy *aphy = hw->priv;
2777         struct ath_softc *sc = aphy->sc;
2778         u32 rfilt;
2779
2780         changed_flags &= SUPPORTED_FILTERS;
2781         *total_flags &= SUPPORTED_FILTERS;
2782
2783         sc->rx.rxfilter = *total_flags;
2784         ath9k_ps_wakeup(sc);
2785         rfilt = ath_calcrxfilter(sc);
2786         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2787         ath9k_ps_restore(sc);
2788
2789         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2790                   "Set HW RX filter: 0x%x\n", rfilt);
2791 }
2792
2793 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2794                              struct ieee80211_vif *vif,
2795                              enum sta_notify_cmd cmd,
2796                              struct ieee80211_sta *sta)
2797 {
2798         struct ath_wiphy *aphy = hw->priv;
2799         struct ath_softc *sc = aphy->sc;
2800
2801         switch (cmd) {
2802         case STA_NOTIFY_ADD:
2803                 ath_node_attach(sc, sta);
2804                 break;
2805         case STA_NOTIFY_REMOVE:
2806                 ath_node_detach(sc, sta);
2807                 break;
2808         default:
2809                 break;
2810         }
2811 }
2812
2813 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2814                          const struct ieee80211_tx_queue_params *params)
2815 {
2816         struct ath_wiphy *aphy = hw->priv;
2817         struct ath_softc *sc = aphy->sc;
2818         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2819         struct ath9k_tx_queue_info qi;
2820         int ret = 0, qnum;
2821
2822         if (queue >= WME_NUM_AC)
2823                 return 0;
2824
2825         mutex_lock(&sc->mutex);
2826
2827         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2828
2829         qi.tqi_aifs = params->aifs;
2830         qi.tqi_cwmin = params->cw_min;
2831         qi.tqi_cwmax = params->cw_max;
2832         qi.tqi_burstTime = params->txop;
2833         qnum = ath_get_hal_qnum(queue, sc);
2834
2835         ath_print(common, ATH_DBG_CONFIG,
2836                   "Configure tx [queue/halq] [%d/%d],  "
2837                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2838                   queue, qnum, params->aifs, params->cw_min,
2839                   params->cw_max, params->txop);
2840
2841         ret = ath_txq_update(sc, qnum, &qi);
2842         if (ret)
2843                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2844
2845         mutex_unlock(&sc->mutex);
2846
2847         return ret;
2848 }
2849
2850 static int ath9k_set_key(struct ieee80211_hw *hw,
2851                          enum set_key_cmd cmd,
2852                          struct ieee80211_vif *vif,
2853                          struct ieee80211_sta *sta,
2854                          struct ieee80211_key_conf *key)
2855 {
2856         struct ath_wiphy *aphy = hw->priv;
2857         struct ath_softc *sc = aphy->sc;
2858         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2859         int ret = 0;
2860
2861         if (modparam_nohwcrypt)
2862                 return -ENOSPC;
2863
2864         mutex_lock(&sc->mutex);
2865         ath9k_ps_wakeup(sc);
2866         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2867
2868         switch (cmd) {
2869         case SET_KEY:
2870                 ret = ath_key_config(sc, vif, sta, key);
2871                 if (ret >= 0) {
2872                         key->hw_key_idx = ret;
2873                         /* push IV and Michael MIC generation to stack */
2874                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2875                         if (key->alg == ALG_TKIP)
2876                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2877                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2878                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2879                         ret = 0;
2880                 }
2881                 break;
2882         case DISABLE_KEY:
2883                 ath_key_delete(sc, key);
2884                 break;
2885         default:
2886                 ret = -EINVAL;
2887         }
2888
2889         ath9k_ps_restore(sc);
2890         mutex_unlock(&sc->mutex);
2891
2892         return ret;
2893 }
2894
2895 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2896                                    struct ieee80211_vif *vif,
2897                                    struct ieee80211_bss_conf *bss_conf,
2898                                    u32 changed)
2899 {
2900         struct ath_wiphy *aphy = hw->priv;
2901         struct ath_softc *sc = aphy->sc;
2902         struct ath_hw *ah = sc->sc_ah;
2903         struct ath_common *common = ath9k_hw_common(ah);
2904         struct ath_vif *avp = (void *)vif->drv_priv;
2905         u32 rfilt = 0;
2906         int error, i;
2907
2908         mutex_lock(&sc->mutex);
2909
2910         /*
2911          * TODO: Need to decide which hw opmode to use for
2912          *       multi-interface cases
2913          * XXX: This belongs into add_interface!
2914          */
2915         if (vif->type == NL80211_IFTYPE_AP &&
2916             ah->opmode != NL80211_IFTYPE_AP) {
2917                 ah->opmode = NL80211_IFTYPE_STATION;
2918                 ath9k_hw_setopmode(ah);
2919                 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2920                 common->curaid = 0;
2921                 ath9k_hw_write_associd(ah);
2922                 /* Request full reset to get hw opmode changed properly */
2923                 sc->sc_flags |= SC_OP_FULL_RESET;
2924         }
2925
2926         if ((changed & BSS_CHANGED_BSSID) &&
2927             !is_zero_ether_addr(bss_conf->bssid)) {
2928                 switch (vif->type) {
2929                 case NL80211_IFTYPE_STATION:
2930                 case NL80211_IFTYPE_ADHOC:
2931                 case NL80211_IFTYPE_MESH_POINT:
2932                         /* Set BSSID */
2933                         memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2934                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2935                         common->curaid = 0;
2936                         ath9k_hw_write_associd(ah);
2937
2938                         /* Set aggregation protection mode parameters */
2939                         sc->config.ath_aggr_prot = 0;
2940
2941                         ath_print(common, ATH_DBG_CONFIG,
2942                                   "RX filter 0x%x bssid %pM aid 0x%x\n",
2943                                   rfilt, common->curbssid, common->curaid);
2944
2945                         /* need to reconfigure the beacon */
2946                         sc->sc_flags &= ~SC_OP_BEACONS ;
2947
2948                         break;
2949                 default:
2950                         break;
2951                 }
2952         }
2953
2954         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2955             (vif->type == NL80211_IFTYPE_AP) ||
2956             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2957                 if ((changed & BSS_CHANGED_BEACON) ||
2958                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2959                      bss_conf->enable_beacon)) {
2960                         /*
2961                          * Allocate and setup the beacon frame.
2962                          *
2963                          * Stop any previous beacon DMA.  This may be
2964                          * necessary, for example, when an ibss merge
2965                          * causes reconfiguration; we may be called
2966                          * with beacon transmission active.
2967                          */
2968                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2969
2970                         error = ath_beacon_alloc(aphy, vif);
2971                         if (!error)
2972                                 ath_beacon_config(sc, vif);
2973                 }
2974         }
2975
2976         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2977         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2978                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2979                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2980                                 ath9k_hw_keysetmac(sc->sc_ah,
2981                                                    (u16)i,
2982                                                    common->curbssid);
2983         }
2984
2985         /* Only legacy IBSS for now */
2986         if (vif->type == NL80211_IFTYPE_ADHOC)
2987                 ath_update_chainmask(sc, 0);
2988
2989         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2990                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2991                           bss_conf->use_short_preamble);
2992                 if (bss_conf->use_short_preamble)
2993                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2994                 else
2995                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2996         }
2997
2998         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2999                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3000                           bss_conf->use_cts_prot);
3001                 if (bss_conf->use_cts_prot &&
3002                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3003                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3004                 else
3005                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3006         }
3007
3008         if (changed & BSS_CHANGED_ASSOC) {
3009                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3010                         bss_conf->assoc);
3011                 ath9k_bss_assoc_info(sc, vif, bss_conf);
3012         }
3013
3014         /*
3015          * The HW TSF has to be reset when the beacon interval changes.
3016          * We set the flag here, and ath_beacon_config_ap() would take this
3017          * into account when it gets called through the subsequent
3018          * config_interface() call - with IFCC_BEACON in the changed field.
3019          */
3020
3021         if (changed & BSS_CHANGED_BEACON_INT) {
3022                 sc->sc_flags |= SC_OP_TSF_RESET;
3023                 sc->beacon_interval = bss_conf->beacon_int;
3024         }
3025
3026         mutex_unlock(&sc->mutex);
3027 }
3028
3029 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3030 {
3031         u64 tsf;
3032         struct ath_wiphy *aphy = hw->priv;
3033         struct ath_softc *sc = aphy->sc;
3034
3035         mutex_lock(&sc->mutex);
3036         tsf = ath9k_hw_gettsf64(sc->sc_ah);
3037         mutex_unlock(&sc->mutex);
3038
3039         return tsf;
3040 }
3041
3042 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3043 {
3044         struct ath_wiphy *aphy = hw->priv;
3045         struct ath_softc *sc = aphy->sc;
3046
3047         mutex_lock(&sc->mutex);
3048         ath9k_hw_settsf64(sc->sc_ah, tsf);
3049         mutex_unlock(&sc->mutex);
3050 }
3051
3052 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3053 {
3054         struct ath_wiphy *aphy = hw->priv;
3055         struct ath_softc *sc = aphy->sc;
3056
3057         mutex_lock(&sc->mutex);
3058
3059         ath9k_ps_wakeup(sc);
3060         ath9k_hw_reset_tsf(sc->sc_ah);
3061         ath9k_ps_restore(sc);
3062
3063         mutex_unlock(&sc->mutex);
3064 }
3065
3066 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3067                               enum ieee80211_ampdu_mlme_action action,
3068                               struct ieee80211_sta *sta,
3069                               u16 tid, u16 *ssn)
3070 {
3071         struct ath_wiphy *aphy = hw->priv;
3072         struct ath_softc *sc = aphy->sc;
3073         int ret = 0;
3074
3075         switch (action) {
3076         case IEEE80211_AMPDU_RX_START:
3077                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3078                         ret = -ENOTSUPP;
3079                 break;
3080         case IEEE80211_AMPDU_RX_STOP:
3081                 break;
3082         case IEEE80211_AMPDU_TX_START:
3083                 ath_tx_aggr_start(sc, sta, tid, ssn);
3084                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3085                 break;
3086         case IEEE80211_AMPDU_TX_STOP:
3087                 ath_tx_aggr_stop(sc, sta, tid);
3088                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3089                 break;
3090         case IEEE80211_AMPDU_TX_OPERATIONAL:
3091                 ath_tx_aggr_resume(sc, sta, tid);
3092                 break;
3093         default:
3094                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3095                           "Unknown AMPDU action\n");
3096         }
3097
3098         return ret;
3099 }
3100
3101 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3102 {
3103         struct ath_wiphy *aphy = hw->priv;
3104         struct ath_softc *sc = aphy->sc;
3105
3106         mutex_lock(&sc->mutex);
3107         if (ath9k_wiphy_scanning(sc)) {
3108                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3109                        "same time\n");
3110                 /*
3111                  * Do not allow the concurrent scanning state for now. This
3112                  * could be improved with scanning control moved into ath9k.
3113                  */
3114                 mutex_unlock(&sc->mutex);
3115                 return;
3116         }
3117
3118         aphy->state = ATH_WIPHY_SCAN;
3119         ath9k_wiphy_pause_all_forced(sc, aphy);
3120
3121         spin_lock_bh(&sc->ani_lock);
3122         sc->sc_flags |= SC_OP_SCANNING;
3123         spin_unlock_bh(&sc->ani_lock);
3124         mutex_unlock(&sc->mutex);
3125 }
3126
3127 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3128 {
3129         struct ath_wiphy *aphy = hw->priv;
3130         struct ath_softc *sc = aphy->sc;
3131
3132         mutex_lock(&sc->mutex);
3133         spin_lock_bh(&sc->ani_lock);
3134         aphy->state = ATH_WIPHY_ACTIVE;
3135         sc->sc_flags &= ~SC_OP_SCANNING;
3136         sc->sc_flags |= SC_OP_FULL_RESET;
3137         spin_unlock_bh(&sc->ani_lock);
3138         ath_beacon_config(sc, NULL);
3139         mutex_unlock(&sc->mutex);
3140 }
3141
3142 struct ieee80211_ops ath9k_ops = {
3143         .tx                 = ath9k_tx,
3144         .start              = ath9k_start,