8f04b644e2e66cffc230ef57eaeb309153757719
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18
19 static void ath9k_get_txgain_index(struct ath_hw *ah,
20                 struct ath9k_channel *chan,
21                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
22                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
23 {
24         u8 pcdac, i = 0;
25         u16 idxL = 0, idxR = 0, numPiers;
26         bool match;
27         struct chan_centers centers;
28
29         ath9k_hw_get_channel_centers(ah, chan, &centers);
30
31         for (numPiers = 0; numPiers < availPiers; numPiers++)
32                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
33                         break;
34
35         match = ath9k_hw_get_lower_upper_index(
36                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
37                         calChans, numPiers, &idxL, &idxR);
38         if (match) {
39                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
40                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
41         } else {
42                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
43                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
44                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
45         }
46
47         while (pcdac > ah->originalGain[i] &&
48                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
49                 i++;
50
51         *pcdacIdx = i;
52         return;
53 }
54
55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
56                                 u32 initTxGain,
57                                 int txPower,
58                                 u8 *pPDADCValues)
59 {
60         u32 i;
61         u32 offset;
62
63         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
67
68         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
70
71         offset = txPower;
72         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
73                 if (i < offset)
74                         pPDADCValues[i] = 0x0;
75                 else
76                         pPDADCValues[i] = 0xFF;
77 }
78
79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
80 {
81         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
82 }
83
84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
85 {
86         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
87 }
88
89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90 {
91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92         struct ath_common *common = ath9k_hw_common(ah);
93         u16 *eep_data = (u16 *)&ah->eeprom.def;
94         int addr, ar5416_eep_start_loc = 0x100;
95
96         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
97                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
98                                          eep_data)) {
99                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
100                                   "Unable to read eeprom region\n");
101                         return false;
102                 }
103                 eep_data++;
104         }
105         return true;
106 #undef SIZE_EEPROM_DEF
107 }
108
109 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
110 {
111         struct ar5416_eeprom_def *eep =
112                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
113         struct ath_common *common = ath9k_hw_common(ah);
114         u16 *eepdata, temp, magic, magic2;
115         u32 sum = 0, el;
116         bool need_swap = false;
117         int i, addr, size;
118
119         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
120                 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
121                 return false;
122         }
123
124         if (!ath9k_hw_use_flash(ah)) {
125                 ath_print(common, ATH_DBG_EEPROM,
126                           "Read Magic = 0x%04X\n", magic);
127
128                 if (magic != AR5416_EEPROM_MAGIC) {
129                         magic2 = swab16(magic);
130
131                         if (magic2 == AR5416_EEPROM_MAGIC) {
132                                 size = sizeof(struct ar5416_eeprom_def);
133                                 need_swap = true;
134                                 eepdata = (u16 *) (&ah->eeprom);
135
136                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
137                                         temp = swab16(*eepdata);
138                                         *eepdata = temp;
139                                         eepdata++;
140                                 }
141                         } else {
142                                 ath_print(common, ATH_DBG_FATAL,
143                                           "Invalid EEPROM Magic. "
144                                           "Endianness mismatch.\n");
145                                 return -EINVAL;
146                         }
147                 }
148         }
149
150         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
151                   need_swap ? "True" : "False");
152
153         if (need_swap)
154                 el = swab16(ah->eeprom.def.baseEepHeader.length);
155         else
156                 el = ah->eeprom.def.baseEepHeader.length;
157
158         if (el > sizeof(struct ar5416_eeprom_def))
159                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
160         else
161                 el = el / sizeof(u16);
162
163         eepdata = (u16 *)(&ah->eeprom);
164
165         for (i = 0; i < el; i++)
166                 sum ^= *eepdata++;
167
168         if (need_swap) {
169                 u32 integer, j;
170                 u16 word;
171
172                 ath_print(common, ATH_DBG_EEPROM,
173                           "EEPROM Endianness is not native.. Changing.\n");
174
175                 word = swab16(eep->baseEepHeader.length);
176                 eep->baseEepHeader.length = word;
177
178                 word = swab16(eep->baseEepHeader.checksum);
179                 eep->baseEepHeader.checksum = word;
180
181                 word = swab16(eep->baseEepHeader.version);
182                 eep->baseEepHeader.version = word;
183
184                 word = swab16(eep->baseEepHeader.regDmn[0]);
185                 eep->baseEepHeader.regDmn[0] = word;
186
187                 word = swab16(eep->baseEepHeader.regDmn[1]);
188                 eep->baseEepHeader.regDmn[1] = word;
189
190                 word = swab16(eep->baseEepHeader.rfSilent);
191                 eep->baseEepHeader.rfSilent = word;
192
193                 word = swab16(eep->baseEepHeader.blueToothOptions);
194                 eep->baseEepHeader.blueToothOptions = word;
195
196                 word = swab16(eep->baseEepHeader.deviceCap);
197                 eep->baseEepHeader.deviceCap = word;
198
199                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
200                         struct modal_eep_header *pModal =
201                                 &eep->modalHeader[j];
202                         integer = swab32(pModal->antCtrlCommon);
203                         pModal->antCtrlCommon = integer;
204
205                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
206                                 integer = swab32(pModal->antCtrlChain[i]);
207                                 pModal->antCtrlChain[i] = integer;
208                         }
209
210                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
211                                 word = swab16(pModal->spurChans[i].spurChan);
212                                 pModal->spurChans[i].spurChan = word;
213                         }
214                 }
215         }
216
217         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
218             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
219                 ath_print(common, ATH_DBG_FATAL,
220                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
221                         sum, ah->eep_ops->get_eeprom_ver(ah));
222                 return -EINVAL;
223         }
224
225         return 0;
226 }
227
228 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
229                                    enum eeprom_param param)
230 {
231         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
232         struct modal_eep_header *pModal = eep->modalHeader;
233         struct base_eep_header *pBase = &eep->baseEepHeader;
234
235         switch (param) {
236         case EEP_NFTHRESH_5:
237                 return pModal[0].noiseFloorThreshCh[0];
238         case EEP_NFTHRESH_2:
239                 return pModal[1].noiseFloorThreshCh[0];
240         case AR_EEPROM_MAC(0):
241                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
242         case AR_EEPROM_MAC(1):
243                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
244         case AR_EEPROM_MAC(2):
245                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
246         case EEP_REG_0:
247                 return pBase->regDmn[0];
248         case EEP_REG_1:
249                 return pBase->regDmn[1];
250         case EEP_OP_CAP:
251                 return pBase->deviceCap;
252         case EEP_OP_MODE:
253                 return pBase->opCapFlags;
254         case EEP_RF_SILENT:
255                 return pBase->rfSilent;
256         case EEP_OB_5:
257                 return pModal[0].ob;
258         case EEP_DB_5:
259                 return pModal[0].db;
260         case EEP_OB_2:
261                 return pModal[1].ob;
262         case EEP_DB_2:
263                 return pModal[1].db;
264         case EEP_MINOR_REV:
265                 return AR5416_VER_MASK;
266         case EEP_TX_MASK:
267                 return pBase->txMask;
268         case EEP_RX_MASK:
269                 return pBase->rxMask;
270         case EEP_RXGAIN_TYPE:
271                 return pBase->rxGainType;
272         case EEP_TXGAIN_TYPE:
273                 return pBase->txGainType;
274         case EEP_OL_PWRCTRL:
275                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
276                         return pBase->openLoopPwrCntl ? true : false;
277                 else
278                         return false;
279         case EEP_RC_CHAIN_MASK:
280                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
281                         return pBase->rcChainMask;
282                 else
283                         return 0;
284         case EEP_DAC_HPWR_5G:
285                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
286                         return pBase->dacHiPwrMode_5G;
287                 else
288                         return 0;
289         case EEP_FRAC_N_5G:
290                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
291                         return pBase->frac_n_5g;
292                 else
293                         return 0;
294         default:
295                 return 0;
296         }
297 }
298
299 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
300                                   struct modal_eep_header *pModal,
301                                   struct ar5416_eeprom_def *eep,
302                                   u8 txRxAttenLocal, int regChainOffset, int i)
303 {
304         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
305                 txRxAttenLocal = pModal->txRxAttenCh[i];
306
307                 if (AR_SREV_9280_10_OR_LATER(ah)) {
308                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
309                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
310                               pModal->bswMargin[i]);
311                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
312                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
313                               pModal->bswAtten[i]);
314                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
315                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
316                               pModal->xatten2Margin[i]);
317                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
318                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
319                               pModal->xatten2Db[i]);
320                 } else {
321                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
322                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
323                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
324                           | SM(pModal-> bswMargin[i],
325                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
326                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
327                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
328                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
329                           | SM(pModal->bswAtten[i],
330                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
331                 }
332         }
333
334         if (AR_SREV_9280_10_OR_LATER(ah)) {
335                 REG_RMW_FIELD(ah,
336                       AR_PHY_RXGAIN + regChainOffset,
337                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
338                 REG_RMW_FIELD(ah,
339                       AR_PHY_RXGAIN + regChainOffset,
340                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
341         } else {
342                 REG_WRITE(ah,
343                           AR_PHY_RXGAIN + regChainOffset,
344                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
345                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
346                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
347                 REG_WRITE(ah,
348                           AR_PHY_GAIN_2GHZ + regChainOffset,
349                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
350                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
351                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
352         }
353 }
354
355 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
356                                           struct ath9k_channel *chan)
357 {
358         struct modal_eep_header *pModal;
359         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
360         int i, regChainOffset;
361         u8 txRxAttenLocal;
362
363         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
364         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
365
366         REG_WRITE(ah, AR_PHY_SWITCH_COM,
367                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
368
369         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
370                 if (AR_SREV_9280(ah)) {
371                         if (i >= 2)
372                                 break;
373                 }
374
375                 if (AR_SREV_5416_20_OR_LATER(ah) &&
376                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
377                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
378                 else
379                         regChainOffset = i * 0x1000;
380
381                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
382                           pModal->antCtrlChain[i]);
383
384                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
385                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
386                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
387                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
388                           SM(pModal->iqCalICh[i],
389                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
390                           SM(pModal->iqCalQCh[i],
391                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
392
393                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
394                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
395                                               regChainOffset, i);
396         }
397
398         if (AR_SREV_9280_10_OR_LATER(ah)) {
399                 if (IS_CHAN_2GHZ(chan)) {
400                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
401                                                   AR_AN_RF2G1_CH0_OB,
402                                                   AR_AN_RF2G1_CH0_OB_S,
403                                                   pModal->ob);
404                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
405                                                   AR_AN_RF2G1_CH0_DB,
406                                                   AR_AN_RF2G1_CH0_DB_S,
407                                                   pModal->db);
408                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
409                                                   AR_AN_RF2G1_CH1_OB,
410                                                   AR_AN_RF2G1_CH1_OB_S,
411                                                   pModal->ob_ch1);
412                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
413                                                   AR_AN_RF2G1_CH1_DB,
414                                                   AR_AN_RF2G1_CH1_DB_S,
415                                                   pModal->db_ch1);
416                 } else {
417                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
418                                                   AR_AN_RF5G1_CH0_OB5,
419                                                   AR_AN_RF5G1_CH0_OB5_S,
420                                                   pModal->ob);
421                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
422                                                   AR_AN_RF5G1_CH0_DB5,
423                                                   AR_AN_RF5G1_CH0_DB5_S,
424                                                   pModal->db);
425                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
426                                                   AR_AN_RF5G1_CH1_OB5,
427                                                   AR_AN_RF5G1_CH1_OB5_S,
428                                                   pModal->ob_ch1);
429                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
430                                                   AR_AN_RF5G1_CH1_DB5,
431                                                   AR_AN_RF5G1_CH1_DB5_S,
432                                                   pModal->db_ch1);
433                 }
434                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
435                                           AR_AN_TOP2_XPABIAS_LVL,
436                                           AR_AN_TOP2_XPABIAS_LVL_S,
437                                           pModal->xpaBiasLvl);
438                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
439                                           AR_AN_TOP2_LOCALBIAS,
440                                           AR_AN_TOP2_LOCALBIAS_S,
441                                           pModal->local_bias);
442                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
443                               pModal->force_xpaon);
444         }
445
446         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
447                       pModal->switchSettling);
448         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
449                       pModal->adcDesiredSize);
450
451         if (!AR_SREV_9280_10_OR_LATER(ah))
452                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
453                               AR_PHY_DESIRED_SZ_PGA,
454                               pModal->pgaDesiredSize);
455
456         REG_WRITE(ah, AR_PHY_RF_CTL4,
457                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
458                   | SM(pModal->txEndToXpaOff,
459                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
460                   | SM(pModal->txFrameToXpaOn,
461                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
462                   | SM(pModal->txFrameToXpaOn,
463                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
464
465         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
466                       pModal->txEndToRxOn);
467
468         if (AR_SREV_9280_10_OR_LATER(ah)) {
469                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
470                               pModal->thresh62);
471                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
472                               AR_PHY_EXT_CCA0_THRESH62,
473                               pModal->thresh62);
474         } else {
475                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
476                               pModal->thresh62);
477                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
478                               AR_PHY_EXT_CCA_THRESH62,
479                               pModal->thresh62);
480         }
481
482         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
483                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
484                               AR_PHY_TX_END_DATA_START,
485                               pModal->txFrameToDataStart);
486                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
487                               pModal->txFrameToPaOn);
488         }
489
490         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
491                 if (IS_CHAN_HT40(chan))
492                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
493                                       AR_PHY_SETTLING_SWITCH,
494                                       pModal->swSettleHt40);
495         }
496
497         if (AR_SREV_9280_20_OR_LATER(ah) &&
498             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
499                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
500                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
501                               pModal->miscBits);
502
503
504         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
505                 if (IS_CHAN_2GHZ(chan))
506                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
507                                         eep->baseEepHeader.dacLpMode);
508                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
509                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
510                 else
511                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
512                                       eep->baseEepHeader.dacLpMode);
513
514                 udelay(100);
515
516                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
517                               pModal->miscBits >> 2);
518
519                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
520                               AR_PHY_TX_DESIRED_SCALE_CCK,
521                               eep->baseEepHeader.desiredScaleCCK);
522         }
523 }
524
525 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
526                                    struct ath9k_channel *chan)
527 {
528 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
529         struct modal_eep_header *pModal;
530         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
531         u8 biaslevel;
532
533         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
534                 return;
535
536         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
537                 return;
538
539         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
540
541         if (pModal->xpaBiasLvl != 0xff) {
542                 biaslevel = pModal->xpaBiasLvl;
543         } else {
544                 u16 resetFreqBin, freqBin, freqCount = 0;
545                 struct chan_centers centers;
546
547                 ath9k_hw_get_channel_centers(ah, chan, &centers);
548
549                 resetFreqBin = FREQ2FBIN(centers.synth_center,
550                                          IS_CHAN_2GHZ(chan));
551                 freqBin = XPA_LVL_FREQ(0) & 0xff;
552                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
553
554                 freqCount++;
555
556                 while (freqCount < 3) {
557                         if (XPA_LVL_FREQ(freqCount) == 0x0)
558                                 break;
559
560                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
561                         if (resetFreqBin >= freqBin)
562                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
563                         else
564                                 break;
565                         freqCount++;
566                 }
567         }
568
569         if (IS_CHAN_2GHZ(chan)) {
570                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
571                                         7, 1) & (~0x18)) | biaslevel << 3;
572         } else {
573                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
574                                         6, 1) & (~0xc0)) | biaslevel << 6;
575         }
576 #undef XPA_LVL_FREQ
577 }
578
579 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
580                                 struct ath9k_channel *chan,
581                                 struct cal_data_per_freq *pRawDataSet,
582                                 u8 *bChans, u16 availPiers,
583                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
584                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
585                                 u16 numXpdGains)
586 {
587         int i, j, k;
588         int16_t ss;
589         u16 idxL = 0, idxR = 0, numPiers;
590         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
591                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
592         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
593                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
594         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
595                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
596
597         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
598         u8 minPwrT4[AR5416_NUM_PD_GAINS];
599         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
600         int16_t vpdStep;
601         int16_t tmpVal;
602         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
603         bool match;
604         int16_t minDelta = 0;
605         struct chan_centers centers;
606
607         ath9k_hw_get_channel_centers(ah, chan, &centers);
608
609         for (numPiers = 0; numPiers < availPiers; numPiers++) {
610                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
611                         break;
612         }
613
614         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
615                                                              IS_CHAN_2GHZ(chan)),
616                                                bChans, numPiers, &idxL, &idxR);
617
618         if (match) {
619                 for (i = 0; i < numXpdGains; i++) {
620                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
621                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
622                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
623                                         pRawDataSet[idxL].pwrPdg[i],
624                                         pRawDataSet[idxL].vpdPdg[i],
625                                         AR5416_PD_GAIN_ICEPTS,
626                                         vpdTableI[i]);
627                 }
628         } else {
629                 for (i = 0; i < numXpdGains; i++) {
630                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
631                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
632                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
633                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
634
635                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
636
637                         maxPwrT4[i] =
638                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
639                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
640
641
642                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
643                                                 pPwrL, pVpdL,
644                                                 AR5416_PD_GAIN_ICEPTS,
645                                                 vpdTableL[i]);
646                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
647                                                 pPwrR, pVpdR,
648                                                 AR5416_PD_GAIN_ICEPTS,
649                                                 vpdTableR[i]);
650
651                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
652                                 vpdTableI[i][j] =
653                                         (u8)(ath9k_hw_interpolate((u16)
654                                              FREQ2FBIN(centers.
655                                                        synth_center,
656                                                        IS_CHAN_2GHZ
657                                                        (chan)),
658                                              bChans[idxL], bChans[idxR],
659                                              vpdTableL[i][j], vpdTableR[i][j]));
660                         }
661                 }
662         }
663
664         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
665
666         k = 0;
667
668         for (i = 0; i < numXpdGains; i++) {
669                 if (i == (numXpdGains - 1))
670                         pPdGainBoundaries[i] =
671                                 (u16)(maxPwrT4[i] / 2);
672                 else
673                         pPdGainBoundaries[i] =
674                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
675
676                 pPdGainBoundaries[i] =
677                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
678
679                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
680                         minDelta = pPdGainBoundaries[0] - 23;
681                         pPdGainBoundaries[0] = 23;
682                 } else {
683                         minDelta = 0;
684                 }
685
686                 if (i == 0) {
687                         if (AR_SREV_9280_10_OR_LATER(ah))
688                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
689                         else
690                                 ss = 0;
691                 } else {
692                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
693                                         (minPwrT4[i] / 2)) -
694                                        tPdGainOverlap + 1 + minDelta);
695                 }
696                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
697                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
698
699                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
700                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
701                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
702                         ss++;
703                 }
704
705                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
706                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
707                                 (minPwrT4[i] / 2));
708                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
709                         tgtIndex : sizeCurrVpdTable;
710
711                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
712                         pPDADCValues[k++] = vpdTableI[i][ss++];
713                 }
714
715                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
716                                     vpdTableI[i][sizeCurrVpdTable - 2]);
717                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
718
719                 if (tgtIndex > maxIndex) {
720                         while ((ss <= tgtIndex) &&
721                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
722                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
723                                                     (ss - maxIndex + 1) * vpdStep));
724                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
725                                                          255 : tmpVal);
726                                 ss++;
727                         }
728                 }
729         }
730
731         while (i < AR5416_PD_GAINS_IN_MASK) {
732                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
733                 i++;
734         }
735
736         while (k < AR5416_NUM_PDADC_VALUES) {
737                 pPDADCValues[k] = pPDADCValues[k - 1];
738                 k++;
739         }
740
741         return;
742 }
743
744 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
745                                   struct ath9k_channel *chan,
746                                   int16_t *pTxPowerIndexOffset)
747 {
748 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
749 #define SM_PDGAIN_B(x, y) \
750                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
751         struct ath_common *common = ath9k_hw_common(ah);
752         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
753         struct cal_data_per_freq *pRawDataset;
754         u8 *pCalBChans = NULL;
755         u16 pdGainOverlap_t2;
756         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
757         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
758         u16 numPiers, i, j;
759         int16_t tMinCalPower;
760         u16 numXpdGain, xpdMask;
761         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
762         u32 reg32, regOffset, regChainOffset;
763         int16_t modalIdx;
764
765         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
766         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
767
768         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
769             AR5416_EEP_MINOR_VER_2) {
770                 pdGainOverlap_t2 =
771                         pEepData->modalHeader[modalIdx].pdGainOverlap;
772         } else {
773                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
774                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
775         }
776
777         if (IS_CHAN_2GHZ(chan)) {
778                 pCalBChans = pEepData->calFreqPier2G;
779                 numPiers = AR5416_NUM_2G_CAL_PIERS;
780         } else {
781                 pCalBChans = pEepData->calFreqPier5G;
782                 numPiers = AR5416_NUM_5G_CAL_PIERS;
783         }
784
785         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
786                 pRawDataset = pEepData->calPierData2G[0];
787                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
788                                  pRawDataset)->vpdPdg[0][0];
789         }
790
791         numXpdGain = 0;
792
793         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
794                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
795                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
796                                 break;
797                         xpdGainValues[numXpdGain] =
798                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
799                         numXpdGain++;
800                 }
801         }
802
803         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
804                       (numXpdGain - 1) & 0x3);
805         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
806                       xpdGainValues[0]);
807         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
808                       xpdGainValues[1]);
809         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
810                       xpdGainValues[2]);
811
812         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
813                 if (AR_SREV_5416_20_OR_LATER(ah) &&
814                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
815                     (i != 0)) {
816                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
817                 } else
818                         regChainOffset = i * 0x1000;
819
820                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
821                         if (IS_CHAN_2GHZ(chan))
822                                 pRawDataset = pEepData->calPierData2G[i];
823                         else
824                                 pRawDataset = pEepData->calPierData5G[i];
825
826
827                         if (OLC_FOR_AR9280_20_LATER) {
828                                 u8 pcdacIdx;
829                                 u8 txPower;
830
831                                 ath9k_get_txgain_index(ah, chan,
832                                 (struct calDataPerFreqOpLoop *)pRawDataset,
833                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
834                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
835                                                      txPower/2, pdadcValues);
836                         } else {
837                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
838                                                         chan, pRawDataset,
839                                                         pCalBChans, numPiers,
840                                                         pdGainOverlap_t2,
841                                                         &tMinCalPower,
842                                                         gainBoundaries,
843                                                         pdadcValues,
844                                                         numXpdGain);
845                         }
846
847                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
848                                 if (OLC_FOR_AR9280_20_LATER) {
849                                         REG_WRITE(ah,
850                                                 AR_PHY_TPCRG5 + regChainOffset,
851                                                 SM(0x6,
852                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
853                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
854                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
855                                 } else {
856                                         REG_WRITE(ah,
857                                                 AR_PHY_TPCRG5 + regChainOffset,
858                                                 SM(pdGainOverlap_t2,
859                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
860                                                 SM_PDGAIN_B(0, 1) |
861                                                 SM_PDGAIN_B(1, 2) |
862                                                 SM_PDGAIN_B(2, 3) |
863                                                 SM_PDGAIN_B(3, 4));
864                                 }
865                         }
866
867                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
868                         for (j = 0; j < 32; j++) {
869                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
870                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
871                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
872                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
873                                 REG_WRITE(ah, regOffset, reg32);
874
875                                 ath_print(common, ATH_DBG_EEPROM,
876                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
877                                           i, regChainOffset, regOffset,
878                                           reg32);
879                                 ath_print(common, ATH_DBG_EEPROM,
880                                           "PDADC: Chain %d | PDADC %3d "
881                                           "Value %3d | PDADC %3d Value %3d | "
882                                           "PDADC %3d Value %3d | PDADC %3d "
883                                           "Value %3d |\n",
884                                           i, 4 * j, pdadcValues[4 * j],
885                                           4 * j + 1, pdadcValues[4 * j + 1],
886                                           4 * j + 2, pdadcValues[4 * j + 2],
887                                           4 * j + 3,
888                                           pdadcValues[4 * j + 3]);
889
890                                 regOffset += 4;
891                         }
892                 }
893         }
894
895         *pTxPowerIndexOffset = 0;
896 #undef SM_PD_GAIN
897 #undef SM_PDGAIN_B
898 }
899
900 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
901                                                   struct ath9k_channel *chan,
902                                                   int16_t *ratesArray,
903                                                   u16 cfgCtl,
904                                                   u16 AntennaReduction,
905                                                   u16 twiceMaxRegulatoryPower,
906                                                   u16 powerLimit)
907 {
908 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
909 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
910
911         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
912         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
913         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
914         static const u16 tpScaleReductionTable[5] =
915                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
916
917         int i;
918         int16_t twiceLargestAntenna;
919         struct cal_ctl_data *rep;
920         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
921                 0, { 0, 0, 0, 0}
922         };
923         struct cal_target_power_leg targetPowerOfdmExt = {
924                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
925                 0, { 0, 0, 0, 0 }
926         };
927         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
928                 0, {0, 0, 0, 0}
929         };
930         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
931         u16 ctlModesFor11a[] =
932                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
933         u16 ctlModesFor11g[] =
934                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
935                   CTL_2GHT40
936                 };
937         u16 numCtlModes, *pCtlMode, ctlMode, freq;
938         struct chan_centers centers;
939         int tx_chainmask;
940         u16 twiceMinEdgePower;
941
942         tx_chainmask = ah->txchainmask;
943
944         ath9k_hw_get_channel_centers(ah, chan, &centers);
945
946         twiceLargestAntenna = max(
947                 pEepData->modalHeader
948                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
949                 pEepData->modalHeader
950                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
951
952         twiceLargestAntenna = max((u8)twiceLargestAntenna,
953                                   pEepData->modalHeader
954                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
955
956         twiceLargestAntenna = (int16_t)min(AntennaReduction -
957                                            twiceLargestAntenna, 0);
958
959         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
960
961         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
962                 maxRegAllowedPower -=
963                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
964         }
965
966         scaledPower = min(powerLimit, maxRegAllowedPower);
967
968         switch (ar5416_get_ntxchains(tx_chainmask)) {
969         case 1:
970                 break;
971         case 2:
972                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
973                 break;
974         case 3:
975                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
976                 break;
977         }
978
979         scaledPower = max((u16)0, scaledPower);
980
981         if (IS_CHAN_2GHZ(chan)) {
982                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
983                         SUB_NUM_CTL_MODES_AT_2G_40;
984                 pCtlMode = ctlModesFor11g;
985
986                 ath9k_hw_get_legacy_target_powers(ah, chan,
987                         pEepData->calTargetPowerCck,
988                         AR5416_NUM_2G_CCK_TARGET_POWERS,
989                         &targetPowerCck, 4, false);
990                 ath9k_hw_get_legacy_target_powers(ah, chan,
991                         pEepData->calTargetPower2G,
992                         AR5416_NUM_2G_20_TARGET_POWERS,
993                         &targetPowerOfdm, 4, false);
994                 ath9k_hw_get_target_powers(ah, chan,
995                         pEepData->calTargetPower2GHT20,
996                         AR5416_NUM_2G_20_TARGET_POWERS,
997                         &targetPowerHt20, 8, false);
998
999                 if (IS_CHAN_HT40(chan)) {
1000                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1001                         ath9k_hw_get_target_powers(ah, chan,
1002                                 pEepData->calTargetPower2GHT40,
1003                                 AR5416_NUM_2G_40_TARGET_POWERS,
1004                                 &targetPowerHt40, 8, true);
1005                         ath9k_hw_get_legacy_target_powers(ah, chan,
1006                                 pEepData->calTargetPowerCck,
1007                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
1008                                 &targetPowerCckExt, 4, true);
1009                         ath9k_hw_get_legacy_target_powers(ah, chan,
1010                                 pEepData->calTargetPower2G,
1011                                 AR5416_NUM_2G_20_TARGET_POWERS,
1012                                 &targetPowerOfdmExt, 4, true);
1013                 }
1014         } else {
1015                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1016                         SUB_NUM_CTL_MODES_AT_5G_40;
1017                 pCtlMode = ctlModesFor11a;
1018
1019                 ath9k_hw_get_legacy_target_powers(ah, chan,
1020                         pEepData->calTargetPower5G,
1021                         AR5416_NUM_5G_20_TARGET_POWERS,
1022                         &targetPowerOfdm, 4, false);
1023                 ath9k_hw_get_target_powers(ah, chan,
1024                         pEepData->calTargetPower5GHT20,
1025                         AR5416_NUM_5G_20_TARGET_POWERS,
1026                         &targetPowerHt20, 8, false);
1027
1028                 if (IS_CHAN_HT40(chan)) {
1029                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1030                         ath9k_hw_get_target_powers(ah, chan,
1031                                 pEepData->calTargetPower5GHT40,
1032                                 AR5416_NUM_5G_40_TARGET_POWERS,
1033                                 &targetPowerHt40, 8, true);
1034                         ath9k_hw_get_legacy_target_powers(ah, chan,
1035                                 pEepData->calTargetPower5G,
1036                                 AR5416_NUM_5G_20_TARGET_POWERS,
1037                                 &targetPowerOfdmExt, 4, true);
1038                 }
1039         }
1040
1041         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1042                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1043                         (pCtlMode[ctlMode] == CTL_2GHT40);
1044                 if (isHt40CtlMode)
1045                         freq = centers.synth_center;
1046                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1047                         freq = centers.ext_center;
1048                 else
1049                         freq = centers.ctl_center;
1050
1051                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1052                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
1053                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1054
1055                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1056                         if ((((cfgCtl & ~CTL_MODE_M) |
1057                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1058                              pEepData->ctlIndex[i]) ||
1059                             (((cfgCtl & ~CTL_MODE_M) |
1060                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1061                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1062                                 rep = &(pEepData->ctlData[i]);
1063
1064                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1065                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1066                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1067
1068                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1069                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1070                                                                 twiceMinEdgePower);
1071                                 } else {
1072                                         twiceMaxEdgePower = twiceMinEdgePower;
1073                                         break;
1074                                 }
1075                         }
1076                 }
1077
1078                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1079
1080                 switch (pCtlMode[ctlMode]) {
1081                 case CTL_11B:
1082                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1083                                 targetPowerCck.tPow2x[i] =
1084                                         min((u16)targetPowerCck.tPow2x[i],
1085                                             minCtlPower);
1086                         }
1087                         break;
1088                 case CTL_11A:
1089                 case CTL_11G:
1090                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1091                                 targetPowerOfdm.tPow2x[i] =
1092                                         min((u16)targetPowerOfdm.tPow2x[i],
1093                                             minCtlPower);
1094                         }
1095                         break;
1096                 case CTL_5GHT20:
1097                 case CTL_2GHT20:
1098                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1099                                 targetPowerHt20.tPow2x[i] =
1100                                         min((u16)targetPowerHt20.tPow2x[i],
1101                                             minCtlPower);
1102                         }
1103                         break;
1104                 case CTL_11B_EXT:
1105                         targetPowerCckExt.tPow2x[0] = min((u16)
1106                                         targetPowerCckExt.tPow2x[0],
1107                                         minCtlPower);
1108                         break;
1109                 case CTL_11A_EXT:
1110                 case CTL_11G_EXT:
1111                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1112                                         targetPowerOfdmExt.tPow2x[0],
1113                                         minCtlPower);
1114                         break;
1115                 case CTL_5GHT40:
1116                 case CTL_2GHT40:
1117                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1118                                 targetPowerHt40.tPow2x[i] =
1119                                         min((u16)targetPowerHt40.tPow2x[i],
1120                                             minCtlPower);
1121                         }
1122                         break;
1123                 default:
1124                         break;
1125                 }
1126         }
1127
1128         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1129                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1130                 targetPowerOfdm.tPow2x[0];
1131         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1132         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1133         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1134         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1135
1136         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1137                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1138
1139         if (IS_CHAN_2GHZ(chan)) {
1140                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1141                 ratesArray[rate2s] = ratesArray[rate2l] =
1142                         targetPowerCck.tPow2x[1];
1143                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1144                         targetPowerCck.tPow2x[2];
1145                 ratesArray[rate11s] = ratesArray[rate11l] =
1146                         targetPowerCck.tPow2x[3];
1147         }
1148         if (IS_CHAN_HT40(chan)) {
1149                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1150                         ratesArray[rateHt40_0 + i] =
1151                                 targetPowerHt40.tPow2x[i];
1152                 }
1153                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1154                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1155                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1156                 if (IS_CHAN_2GHZ(chan)) {
1157                         ratesArray[rateExtCck] =
1158                                 targetPowerCckExt.tPow2x[0];
1159                 }
1160         }
1161 }
1162
1163 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1164                                     struct ath9k_channel *chan,
1165                                     u16 cfgCtl,
1166                                     u8 twiceAntennaReduction,
1167                                     u8 twiceMaxRegulatoryPower,
1168                                     u8 powerLimit)
1169 {
1170 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1171         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1172         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1173         struct modal_eep_header *pModal =
1174                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1175         int16_t ratesArray[Ar5416RateSize];
1176         int16_t txPowerIndexOffset = 0;
1177         u8 ht40PowerIncForPdadc = 2;
1178         int i, cck_ofdm_delta = 0;
1179
1180         memset(ratesArray, 0, sizeof(ratesArray));
1181
1182         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1183             AR5416_EEP_MINOR_VER_2) {
1184                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1185         }
1186
1187         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1188                                                &ratesArray[0], cfgCtl,
1189                                                twiceAntennaReduction,
1190                                                twiceMaxRegulatoryPower,
1191                                                powerLimit);
1192
1193         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1194
1195         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1196                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1197                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1198                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1199         }
1200
1201         if (AR_SREV_9280_10_OR_LATER(ah)) {
1202                 for (i = 0; i < Ar5416RateSize; i++)
1203                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1204         }
1205
1206         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1207                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1208                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1209                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1210                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1211         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1212                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1213                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1214                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1215                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1216
1217         if (IS_CHAN_2GHZ(chan)) {
1218                 if (OLC_FOR_AR9280_20_LATER) {
1219                         cck_ofdm_delta = 2;
1220                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1221                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1222                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1223                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1224                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1225                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1226                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1227                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1228                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1229                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1230                 } else {
1231                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1232                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1233                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1234                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1235                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1236                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1237                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1238                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1239                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1240                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1241                 }
1242         }
1243
1244         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1245                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1246                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1247                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1248                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1249         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1250                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1251                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1252                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1253                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1254
1255         if (IS_CHAN_HT40(chan)) {
1256                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1257                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1258                                        ht40PowerIncForPdadc, 24)
1259                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1260                                          ht40PowerIncForPdadc, 16)
1261                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1262                                          ht40PowerIncForPdadc, 8)
1263                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1264                                          ht40PowerIncForPdadc, 0));
1265                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1266                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1267                                        ht40PowerIncForPdadc, 24)
1268                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1269                                          ht40PowerIncForPdadc, 16)
1270                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1271                                          ht40PowerIncForPdadc, 8)
1272                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1273                                          ht40PowerIncForPdadc, 0));
1274                 if (OLC_FOR_AR9280_20_LATER) {
1275                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1276                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1277                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1278                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1279                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1280                 } else {
1281                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1282                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1283                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1284                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1285                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1286                 }
1287         }
1288
1289         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1290                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1291                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1292
1293         i = rate6mb;
1294
1295         if (IS_CHAN_HT40(chan))
1296                 i = rateHt40_0;
1297         else if (IS_CHAN_HT20(chan))
1298                 i = rateHt20_0;
1299
1300         if (AR_SREV_9280_10_OR_LATER(ah))
1301                 regulatory->max_power_level =
1302                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1303         else
1304                 regulatory->max_power_level = ratesArray[i];
1305
1306         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1307         case 1:
1308                 break;
1309         case 2:
1310                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1311                 break;
1312         case 3:
1313                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1314                 break;
1315         default:
1316                 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1317                           "Invalid chainmask configuration\n");
1318                 break;
1319         }
1320 }
1321
1322 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1323                                           enum ieee80211_band freq_band)
1324 {
1325         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1326         struct modal_eep_header *pModal =
1327                 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1328         struct base_eep_header *pBase = &eep->baseEepHeader;
1329         u8 num_ant_config;
1330
1331         num_ant_config = 1;
1332
1333         if (pBase->version >= 0x0E0D)
1334                 if (pModal->useAnt1)
1335                         num_ant_config += 1;
1336
1337         return num_ant_config;
1338 }
1339
1340 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1341                                                struct ath9k_channel *chan)
1342 {
1343         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1344         struct modal_eep_header *pModal =
1345                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1346
1347         return pModal->antCtrlCommon & 0xFFFF;
1348 }
1349
1350 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1351 {
1352 #define EEP_DEF_SPURCHAN \
1353         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1354         struct ath_common *common = ath9k_hw_common(ah);
1355
1356         u16 spur_val = AR_NO_SPUR;
1357
1358         ath_print(common, ATH_DBG_ANI,
1359                   "Getting spur idx %d is2Ghz. %d val %x\n",
1360                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1361
1362         switch (ah->config.spurmode) {
1363         case SPUR_DISABLE:
1364                 break;
1365         case SPUR_ENABLE_IOCTL:
1366                 spur_val = ah->config.spurchans[i][is2GHz];
1367                 ath_print(common, ATH_DBG_ANI,
1368                           "Getting spur val from new loc. %d\n", spur_val);
1369                 break;
1370         case SPUR_ENABLE_EEPROM:
1371                 spur_val = EEP_DEF_SPURCHAN;
1372                 break;
1373         }
1374
1375         return spur_val;
1376
1377 #undef EEP_DEF_SPURCHAN
1378 }
1379
1380 const struct eeprom_ops eep_def_ops = {
1381         .check_eeprom           = ath9k_hw_def_check_eeprom,
1382         .get_eeprom             = ath9k_hw_def_get_eeprom,
1383         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1384         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1385         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1386         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1387         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1388         .set_board_values       = ath9k_hw_def_set_board_values,
1389         .set_addac              = ath9k_hw_def_set_addac,
1390         .set_txpower            = ath9k_hw_def_set_txpower,
1391         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1392 };