ath9k: clarify what hw code is and remove ath9k.h from a few files
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_4k.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18
19 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20 {
21         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
22 }
23
24 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
25 {
26         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
27 }
28
29 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30 {
31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
32         struct ath_common *common = ath9k_hw_common(ah);
33         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
34         int addr, eep_start_loc = 0;
35
36         eep_start_loc = 64;
37
38         if (!ath9k_hw_use_flash(ah)) {
39                 ath_print(common, ATH_DBG_EEPROM,
40                           "Reading from EEPROM, not flash\n");
41         }
42
43         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
44                 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
45                         ath_print(common, ATH_DBG_EEPROM,
46                                   "Unable to read eeprom region \n");
47                         return false;
48                 }
49                 eep_data++;
50         }
51
52         return true;
53 #undef SIZE_EEPROM_4K
54 }
55
56 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
57 {
58 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
59         struct ath_common *common = ath9k_hw_common(ah);
60         struct ar5416_eeprom_4k *eep =
61                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
62         u16 *eepdata, temp, magic, magic2;
63         u32 sum = 0, el;
64         bool need_swap = false;
65         int i, addr;
66
67
68         if (!ath9k_hw_use_flash(ah)) {
69                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
70                                          &magic)) {
71                         ath_print(common, ATH_DBG_FATAL,
72                                   "Reading Magic # failed\n");
73                         return false;
74                 }
75
76                 ath_print(common, ATH_DBG_EEPROM,
77                           "Read Magic = 0x%04X\n", magic);
78
79                 if (magic != AR5416_EEPROM_MAGIC) {
80                         magic2 = swab16(magic);
81
82                         if (magic2 == AR5416_EEPROM_MAGIC) {
83                                 need_swap = true;
84                                 eepdata = (u16 *) (&ah->eeprom);
85
86                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
87                                         temp = swab16(*eepdata);
88                                         *eepdata = temp;
89                                         eepdata++;
90                                 }
91                         } else {
92                                 ath_print(common, ATH_DBG_FATAL,
93                                           "Invalid EEPROM Magic. "
94                                           "endianness mismatch.\n");
95                                 return -EINVAL;
96                         }
97                 }
98         }
99
100         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
101                   need_swap ? "True" : "False");
102
103         if (need_swap)
104                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
105         else
106                 el = ah->eeprom.map4k.baseEepHeader.length;
107
108         if (el > sizeof(struct ar5416_eeprom_4k))
109                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
110         else
111                 el = el / sizeof(u16);
112
113         eepdata = (u16 *)(&ah->eeprom);
114
115         for (i = 0; i < el; i++)
116                 sum ^= *eepdata++;
117
118         if (need_swap) {
119                 u32 integer;
120                 u16 word;
121
122                 ath_print(common, ATH_DBG_EEPROM,
123                           "EEPROM Endianness is not native.. Changing\n");
124
125                 word = swab16(eep->baseEepHeader.length);
126                 eep->baseEepHeader.length = word;
127
128                 word = swab16(eep->baseEepHeader.checksum);
129                 eep->baseEepHeader.checksum = word;
130
131                 word = swab16(eep->baseEepHeader.version);
132                 eep->baseEepHeader.version = word;
133
134                 word = swab16(eep->baseEepHeader.regDmn[0]);
135                 eep->baseEepHeader.regDmn[0] = word;
136
137                 word = swab16(eep->baseEepHeader.regDmn[1]);
138                 eep->baseEepHeader.regDmn[1] = word;
139
140                 word = swab16(eep->baseEepHeader.rfSilent);
141                 eep->baseEepHeader.rfSilent = word;
142
143                 word = swab16(eep->baseEepHeader.blueToothOptions);
144                 eep->baseEepHeader.blueToothOptions = word;
145
146                 word = swab16(eep->baseEepHeader.deviceCap);
147                 eep->baseEepHeader.deviceCap = word;
148
149                 integer = swab32(eep->modalHeader.antCtrlCommon);
150                 eep->modalHeader.antCtrlCommon = integer;
151
152                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
153                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
154                         eep->modalHeader.antCtrlChain[i] = integer;
155                 }
156
157                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
158                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
159                         eep->modalHeader.spurChans[i].spurChan = word;
160                 }
161         }
162
163         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
164             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
165                 ath_print(common, ATH_DBG_FATAL,
166                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
167                           sum, ah->eep_ops->get_eeprom_ver(ah));
168                 return -EINVAL;
169         }
170
171         return 0;
172 #undef EEPROM_4K_SIZE
173 }
174
175 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
176                                   enum eeprom_param param)
177 {
178         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
179         struct modal_eep_4k_header *pModal = &eep->modalHeader;
180         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
181
182         switch (param) {
183         case EEP_NFTHRESH_2:
184                 return pModal->noiseFloorThreshCh[0];
185         case AR_EEPROM_MAC(0):
186                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
187         case AR_EEPROM_MAC(1):
188                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
189         case AR_EEPROM_MAC(2):
190                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
191         case EEP_REG_0:
192                 return pBase->regDmn[0];
193         case EEP_REG_1:
194                 return pBase->regDmn[1];
195         case EEP_OP_CAP:
196                 return pBase->deviceCap;
197         case EEP_OP_MODE:
198                 return pBase->opCapFlags;
199         case EEP_RF_SILENT:
200                 return pBase->rfSilent;
201         case EEP_OB_2:
202                 return pModal->ob_0;
203         case EEP_DB_2:
204                 return pModal->db1_1;
205         case EEP_MINOR_REV:
206                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
207         case EEP_TX_MASK:
208                 return pBase->txMask;
209         case EEP_RX_MASK:
210                 return pBase->rxMask;
211         case EEP_FRAC_N_5G:
212                 return 0;
213         default:
214                 return 0;
215         }
216 }
217
218 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
219                                 struct ath9k_channel *chan,
220                                 struct cal_data_per_freq_4k *pRawDataSet,
221                                 u8 *bChans, u16 availPiers,
222                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
223                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
224                                 u16 numXpdGains)
225 {
226 #define TMP_VAL_VPD_TABLE \
227         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
228         int i, j, k;
229         int16_t ss;
230         u16 idxL = 0, idxR = 0, numPiers;
231         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
232                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
233         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
234                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
235         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
236                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
237
238         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
239         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
240         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
241         int16_t vpdStep;
242         int16_t tmpVal;
243         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
244         bool match;
245         int16_t minDelta = 0;
246         struct chan_centers centers;
247 #define PD_GAIN_BOUNDARY_DEFAULT 58;
248
249         ath9k_hw_get_channel_centers(ah, chan, &centers);
250
251         for (numPiers = 0; numPiers < availPiers; numPiers++) {
252                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
253                         break;
254         }
255
256         match = ath9k_hw_get_lower_upper_index(
257                                         (u8)FREQ2FBIN(centers.synth_center,
258                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
259                                         &idxL, &idxR);
260
261         if (match) {
262                 for (i = 0; i < numXpdGains; i++) {
263                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
264                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
265                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
266                                         pRawDataSet[idxL].pwrPdg[i],
267                                         pRawDataSet[idxL].vpdPdg[i],
268                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
269                                         vpdTableI[i]);
270                 }
271         } else {
272                 for (i = 0; i < numXpdGains; i++) {
273                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
274                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
275                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
276                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
277
278                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
279
280                         maxPwrT4[i] =
281                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
282                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
283
284
285                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
286                                                 pPwrL, pVpdL,
287                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
288                                                 vpdTableL[i]);
289                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
290                                                 pPwrR, pVpdR,
291                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
292                                                 vpdTableR[i]);
293
294                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
295                                 vpdTableI[i][j] =
296                                         (u8)(ath9k_hw_interpolate((u16)
297                                              FREQ2FBIN(centers.
298                                                        synth_center,
299                                                        IS_CHAN_2GHZ
300                                                        (chan)),
301                                              bChans[idxL], bChans[idxR],
302                                              vpdTableL[i][j], vpdTableR[i][j]));
303                         }
304                 }
305         }
306
307         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
308
309         k = 0;
310
311         for (i = 0; i < numXpdGains; i++) {
312                 if (i == (numXpdGains - 1))
313                         pPdGainBoundaries[i] =
314                                 (u16)(maxPwrT4[i] / 2);
315                 else
316                         pPdGainBoundaries[i] =
317                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
318
319                 pPdGainBoundaries[i] =
320                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
321
322                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
323                         minDelta = pPdGainBoundaries[0] - 23;
324                         pPdGainBoundaries[0] = 23;
325                 } else {
326                         minDelta = 0;
327                 }
328
329                 if (i == 0) {
330                         if (AR_SREV_9280_10_OR_LATER(ah))
331                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
332                         else
333                                 ss = 0;
334                 } else {
335                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
336                                         (minPwrT4[i] / 2)) -
337                                        tPdGainOverlap + 1 + minDelta);
338                 }
339                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
340                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
341
342                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
343                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
344                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
345                         ss++;
346                 }
347
348                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
349                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
350                                 (minPwrT4[i] / 2));
351                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
352                         tgtIndex : sizeCurrVpdTable;
353
354                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
355                         pPDADCValues[k++] = vpdTableI[i][ss++];
356
357                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
358                                     vpdTableI[i][sizeCurrVpdTable - 2]);
359                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
360
361                 if (tgtIndex >= maxIndex) {
362                         while ((ss <= tgtIndex) &&
363                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
364                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
365                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
366                                                          255 : tmpVal);
367                                 ss++;
368                         }
369                 }
370         }
371
372         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
373                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
374                 i++;
375         }
376
377         while (k < AR5416_NUM_PDADC_VALUES) {
378                 pPDADCValues[k] = pPDADCValues[k - 1];
379                 k++;
380         }
381
382         return;
383 #undef TMP_VAL_VPD_TABLE
384 }
385
386 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
387                                   struct ath9k_channel *chan,
388                                   int16_t *pTxPowerIndexOffset)
389 {
390         struct ath_common *common = ath9k_hw_common(ah);
391         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
392         struct cal_data_per_freq_4k *pRawDataset;
393         u8 *pCalBChans = NULL;
394         u16 pdGainOverlap_t2;
395         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
396         u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
397         u16 numPiers, i, j;
398         int16_t tMinCalPower;
399         u16 numXpdGain, xpdMask;
400         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
401         u32 reg32, regOffset, regChainOffset;
402
403         xpdMask = pEepData->modalHeader.xpdGain;
404
405         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
406             AR5416_EEP_MINOR_VER_2) {
407                 pdGainOverlap_t2 =
408                         pEepData->modalHeader.pdGainOverlap;
409         } else {
410                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
411                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
412         }
413
414         pCalBChans = pEepData->calFreqPier2G;
415         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
416
417         numXpdGain = 0;
418
419         for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
420                 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
421                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
422                                 break;
423                         xpdGainValues[numXpdGain] =
424                                 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
425                         numXpdGain++;
426                 }
427         }
428
429         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
430                       (numXpdGain - 1) & 0x3);
431         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
432                       xpdGainValues[0]);
433         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
434                       xpdGainValues[1]);
435         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
436
437         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
438                 if (AR_SREV_5416_20_OR_LATER(ah) &&
439                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
440                     (i != 0)) {
441                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
442                 } else
443                         regChainOffset = i * 0x1000;
444
445                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
446                         pRawDataset = pEepData->calPierData2G[i];
447
448                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
449                                             pRawDataset, pCalBChans,
450                                             numPiers, pdGainOverlap_t2,
451                                             &tMinCalPower, gainBoundaries,
452                                             pdadcValues, numXpdGain);
453
454                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
455                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
456                                           SM(pdGainOverlap_t2,
457                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
458                                           | SM(gainBoundaries[0],
459                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
460                                           | SM(gainBoundaries[1],
461                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
462                                           | SM(gainBoundaries[2],
463                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
464                                           | SM(gainBoundaries[3],
465                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
466                         }
467
468                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
469                         for (j = 0; j < 32; j++) {
470                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
471                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
472                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
473                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
474                                 REG_WRITE(ah, regOffset, reg32);
475
476                                 ath_print(common, ATH_DBG_EEPROM,
477                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
478                                           i, regChainOffset, regOffset,
479                                           reg32);
480                                 ath_print(common, ATH_DBG_EEPROM,
481                                           "PDADC: Chain %d | "
482                                           "PDADC %3d Value %3d | "
483                                           "PDADC %3d Value %3d | "
484                                           "PDADC %3d Value %3d | "
485                                           "PDADC %3d Value %3d |\n",
486                                           i, 4 * j, pdadcValues[4 * j],
487                                           4 * j + 1, pdadcValues[4 * j + 1],
488                                           4 * j + 2, pdadcValues[4 * j + 2],
489                                           4 * j + 3,
490                                           pdadcValues[4 * j + 3]);
491
492                                 regOffset += 4;
493                         }
494                 }
495         }
496
497         *pTxPowerIndexOffset = 0;
498 }
499
500 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
501                                                  struct ath9k_channel *chan,
502                                                  int16_t *ratesArray,
503                                                  u16 cfgCtl,
504                                                  u16 AntennaReduction,
505                                                  u16 twiceMaxRegulatoryPower,
506                                                  u16 powerLimit)
507 {
508 #define CMP_TEST_GRP \
509         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
510          pEepData->ctlIndex[i])                                         \
511         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
512             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
513
514         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
515         int i;
516         int16_t twiceLargestAntenna;
517         u16 twiceMinEdgePower;
518         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
519         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
520         u16 numCtlModes, *pCtlMode, ctlMode, freq;
521         struct chan_centers centers;
522         struct cal_ctl_data_4k *rep;
523         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
524         static const u16 tpScaleReductionTable[5] =
525                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
526         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
527                 0, { 0, 0, 0, 0}
528         };
529         struct cal_target_power_leg targetPowerOfdmExt = {
530                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
531                 0, { 0, 0, 0, 0 }
532         };
533         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
534                 0, {0, 0, 0, 0}
535         };
536         u16 ctlModesFor11g[] =
537                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
538                   CTL_2GHT40
539                 };
540
541         ath9k_hw_get_channel_centers(ah, chan, &centers);
542
543         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
544         twiceLargestAntenna = (int16_t)min(AntennaReduction -
545                                            twiceLargestAntenna, 0);
546
547         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
548         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
549                 maxRegAllowedPower -=
550                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
551         }
552
553         scaledPower = min(powerLimit, maxRegAllowedPower);
554         scaledPower = max((u16)0, scaledPower);
555
556         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
557         pCtlMode = ctlModesFor11g;
558
559         ath9k_hw_get_legacy_target_powers(ah, chan,
560                         pEepData->calTargetPowerCck,
561                         AR5416_NUM_2G_CCK_TARGET_POWERS,
562                         &targetPowerCck, 4, false);
563         ath9k_hw_get_legacy_target_powers(ah, chan,
564                         pEepData->calTargetPower2G,
565                         AR5416_NUM_2G_20_TARGET_POWERS,
566                         &targetPowerOfdm, 4, false);
567         ath9k_hw_get_target_powers(ah, chan,
568                         pEepData->calTargetPower2GHT20,
569                         AR5416_NUM_2G_20_TARGET_POWERS,
570                         &targetPowerHt20, 8, false);
571
572         if (IS_CHAN_HT40(chan)) {
573                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
574                 ath9k_hw_get_target_powers(ah, chan,
575                                 pEepData->calTargetPower2GHT40,
576                                 AR5416_NUM_2G_40_TARGET_POWERS,
577                                 &targetPowerHt40, 8, true);
578                 ath9k_hw_get_legacy_target_powers(ah, chan,
579                                 pEepData->calTargetPowerCck,
580                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
581                                 &targetPowerCckExt, 4, true);
582                 ath9k_hw_get_legacy_target_powers(ah, chan,
583                                 pEepData->calTargetPower2G,
584                                 AR5416_NUM_2G_20_TARGET_POWERS,
585                                 &targetPowerOfdmExt, 4, true);
586         }
587
588         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
589                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
590                         (pCtlMode[ctlMode] == CTL_2GHT40);
591
592                 if (isHt40CtlMode)
593                         freq = centers.synth_center;
594                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
595                         freq = centers.ext_center;
596                 else
597                         freq = centers.ctl_center;
598
599                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
600                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
601                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
602
603                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
604                              pEepData->ctlIndex[i]; i++) {
605
606                         if (CMP_TEST_GRP) {
607                                 rep = &(pEepData->ctlData[i]);
608
609                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
610                                         freq,
611                                         rep->ctlEdges[
612                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
613                                         IS_CHAN_2GHZ(chan),
614                                         AR5416_EEP4K_NUM_BAND_EDGES);
615
616                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
617                                         twiceMaxEdgePower =
618                                                 min(twiceMaxEdgePower,
619                                                     twiceMinEdgePower);
620                                 } else {
621                                         twiceMaxEdgePower = twiceMinEdgePower;
622                                         break;
623                                 }
624                         }
625                 }
626
627                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
628
629                 switch (pCtlMode[ctlMode]) {
630                 case CTL_11B:
631                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
632                                 targetPowerCck.tPow2x[i] =
633                                         min((u16)targetPowerCck.tPow2x[i],
634                                             minCtlPower);
635                         }
636                         break;
637                 case CTL_11G:
638                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
639                                 targetPowerOfdm.tPow2x[i] =
640                                         min((u16)targetPowerOfdm.tPow2x[i],
641                                             minCtlPower);
642                         }
643                         break;
644                 case CTL_2GHT20:
645                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
646                                 targetPowerHt20.tPow2x[i] =
647                                         min((u16)targetPowerHt20.tPow2x[i],
648                                             minCtlPower);
649                         }
650                         break;
651                 case CTL_11B_EXT:
652                         targetPowerCckExt.tPow2x[0] =
653                                 min((u16)targetPowerCckExt.tPow2x[0],
654                                     minCtlPower);
655                         break;
656                 case CTL_11G_EXT:
657                         targetPowerOfdmExt.tPow2x[0] =
658                                 min((u16)targetPowerOfdmExt.tPow2x[0],
659                                     minCtlPower);
660                         break;
661                 case CTL_2GHT40:
662                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
663                                 targetPowerHt40.tPow2x[i] =
664                                         min((u16)targetPowerHt40.tPow2x[i],
665                                             minCtlPower);
666                         }
667                         break;
668                 default:
669                         break;
670                 }
671         }
672
673         ratesArray[rate6mb] =
674         ratesArray[rate9mb] =
675         ratesArray[rate12mb] =
676         ratesArray[rate18mb] =
677         ratesArray[rate24mb] =
678         targetPowerOfdm.tPow2x[0];
679
680         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
681         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
682         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
683         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
684
685         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
686                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
687
688         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
689         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
690         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
691         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
692
693         if (IS_CHAN_HT40(chan)) {
694                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
695                         ratesArray[rateHt40_0 + i] =
696                                 targetPowerHt40.tPow2x[i];
697                 }
698                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
699                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
700                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
701                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
702         }
703
704 #undef CMP_TEST_GRP
705 }
706
707 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
708                                     struct ath9k_channel *chan,
709                                     u16 cfgCtl,
710                                     u8 twiceAntennaReduction,
711                                     u8 twiceMaxRegulatoryPower,
712                                     u8 powerLimit)
713 {
714         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
715         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
716         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
717         int16_t ratesArray[Ar5416RateSize];
718         int16_t txPowerIndexOffset = 0;
719         u8 ht40PowerIncForPdadc = 2;
720         int i;
721
722         memset(ratesArray, 0, sizeof(ratesArray));
723
724         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
725             AR5416_EEP_MINOR_VER_2) {
726                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
727         }
728
729         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
730                                              &ratesArray[0], cfgCtl,
731                                              twiceAntennaReduction,
732                                              twiceMaxRegulatoryPower,
733                                              powerLimit);
734
735         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
736
737         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
738                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
739                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
740                         ratesArray[i] = AR5416_MAX_RATE_POWER;
741         }
742
743
744         /* Update regulatory */
745
746         i = rate6mb;
747         if (IS_CHAN_HT40(chan))
748                 i = rateHt40_0;
749         else if (IS_CHAN_HT20(chan))
750                 i = rateHt20_0;
751
752         regulatory->max_power_level = ratesArray[i];
753
754         if (AR_SREV_9280_10_OR_LATER(ah)) {
755                 for (i = 0; i < Ar5416RateSize; i++)
756                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
757         }
758
759         /* OFDM power per rate */
760         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
761                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
762                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
763                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
764                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
765         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
766                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
767                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
768                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
769                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
770
771         /* CCK power per rate */
772         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
773                   ATH9K_POW_SM(ratesArray[rate2s], 24)
774                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
775                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
776                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
777         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
778                   ATH9K_POW_SM(ratesArray[rate11s], 24)
779                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
780                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
781                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
782
783         /* HT20 power per rate */
784         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
785                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
786                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
787                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
788                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
789         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
790                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
791                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
792                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
793                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
794
795         /* HT40 power per rate */
796         if (IS_CHAN_HT40(chan)) {
797                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
798                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
799                                        ht40PowerIncForPdadc, 24)
800                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
801                                          ht40PowerIncForPdadc, 16)
802                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
803                                          ht40PowerIncForPdadc, 8)
804                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
805                                          ht40PowerIncForPdadc, 0));
806                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
807                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
808                                        ht40PowerIncForPdadc, 24)
809                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
810                                          ht40PowerIncForPdadc, 16)
811                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
812                                          ht40PowerIncForPdadc, 8)
813                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
814                                          ht40PowerIncForPdadc, 0));
815                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
816                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
817                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
818                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
819                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
820         }
821 }
822
823 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
824                                   struct ath9k_channel *chan)
825 {
826         struct modal_eep_4k_header *pModal;
827         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
828         u8 biaslevel;
829
830         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
831                 return;
832
833         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
834                 return;
835
836         pModal = &eep->modalHeader;
837
838         if (pModal->xpaBiasLvl != 0xff) {
839                 biaslevel = pModal->xpaBiasLvl;
840                 INI_RA(&ah->iniAddac, 7, 1) =
841                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
842         }
843 }
844
845 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
846                                  struct modal_eep_4k_header *pModal,
847                                  struct ar5416_eeprom_4k *eep,
848                                  u8 txRxAttenLocal)
849 {
850         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
851                   pModal->antCtrlChain[0]);
852
853         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
854                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
855                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
856                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
857                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
858                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
859
860         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
861             AR5416_EEP_MINOR_VER_3) {
862                 txRxAttenLocal = pModal->txRxAttenCh[0];
863
864                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
865                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
866                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
867                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
868                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
869                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
870                               pModal->xatten2Margin[0]);
871                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
872                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
873
874                 /* Set the block 1 value to block 0 value */
875                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
876                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
877                               pModal->bswMargin[0]);
878                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
879                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
880                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
881                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
882                               pModal->xatten2Margin[0]);
883                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
884                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
885                               pModal->xatten2Db[0]);
886         }
887
888         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
889                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
890         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
891                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
892
893         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
894                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
895         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
896                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
897
898         if (AR_SREV_9285_11(ah))
899                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
900 }
901
902 /*
903  * Read EEPROM header info and program the device for correct operation
904  * given the channel value.
905  */
906 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
907                                          struct ath9k_channel *chan)
908 {
909         struct modal_eep_4k_header *pModal;
910         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
911         u8 txRxAttenLocal;
912         u8 ob[5], db1[5], db2[5];
913         u8 ant_div_control1, ant_div_control2;
914         u32 regVal;
915
916         pModal = &eep->modalHeader;
917         txRxAttenLocal = 23;
918
919         REG_WRITE(ah, AR_PHY_SWITCH_COM,
920                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
921
922         /* Single chain for 4K EEPROM*/
923         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
924
925         /* Initialize Ant Diversity settings from EEPROM */
926         if (pModal->version >= 3) {
927                 ant_div_control1 = pModal->antdiv_ctl1;
928                 ant_div_control2 = pModal->antdiv_ctl2;
929
930                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
931                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
932
933                 regVal |= SM(ant_div_control1,
934                              AR_PHY_9285_ANT_DIV_CTL);
935                 regVal |= SM(ant_div_control2,
936                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
937                 regVal |= SM((ant_div_control2 >> 2),
938                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
939                 regVal |= SM((ant_div_control1 >> 1),
940                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
941                 regVal |= SM((ant_div_control1 >> 2),
942                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
943
944
945                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
946                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
947                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
948                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
949                 regVal |= SM((ant_div_control1 >> 3),
950                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
951
952                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
953                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
954         }
955
956         if (pModal->version >= 2) {
957                 ob[0] = pModal->ob_0;
958                 ob[1] = pModal->ob_1;
959                 ob[2] = pModal->ob_2;
960                 ob[3] = pModal->ob_3;
961                 ob[4] = pModal->ob_4;
962
963                 db1[0] = pModal->db1_0;
964                 db1[1] = pModal->db1_1;
965                 db1[2] = pModal->db1_2;
966                 db1[3] = pModal->db1_3;
967                 db1[4] = pModal->db1_4;
968
969                 db2[0] = pModal->db2_0;
970                 db2[1] = pModal->db2_1;
971                 db2[2] = pModal->db2_2;
972                 db2[3] = pModal->db2_3;
973                 db2[4] = pModal->db2_4;
974         } else if (pModal->version == 1) {
975                 ob[0] = pModal->ob_0;
976                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
977                 db1[0] = pModal->db1_0;
978                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
979                 db2[0] = pModal->db2_0;
980                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
981         } else {
982                 int i;
983
984                 for (i = 0; i < 5; i++) {
985                         ob[i] = pModal->ob_0;
986                         db1[i] = pModal->db1_0;
987                         db2[i] = pModal->db1_0;
988                 }
989         }
990
991         if (AR_SREV_9271(ah)) {
992                 ath9k_hw_analog_shift_rmw(ah,
993                                           AR9285_AN_RF2G3,
994                                           AR9271_AN_RF2G3_OB_cck,
995                                           AR9271_AN_RF2G3_OB_cck_S,
996                                           ob[0]);
997                 ath9k_hw_analog_shift_rmw(ah,
998                                           AR9285_AN_RF2G3,
999                                           AR9271_AN_RF2G3_OB_psk,
1000                                           AR9271_AN_RF2G3_OB_psk_S,
1001                                           ob[1]);
1002                 ath9k_hw_analog_shift_rmw(ah,
1003                                           AR9285_AN_RF2G3,
1004                                           AR9271_AN_RF2G3_OB_qam,
1005                                           AR9271_AN_RF2G3_OB_qam_S,
1006                                           ob[2]);
1007                 ath9k_hw_analog_shift_rmw(ah,
1008                                           AR9285_AN_RF2G3,
1009                                           AR9271_AN_RF2G3_DB_1,
1010                                           AR9271_AN_RF2G3_DB_1_S,
1011                                           db1[0]);
1012                 ath9k_hw_analog_shift_rmw(ah,
1013                                           AR9285_AN_RF2G4,
1014                                           AR9271_AN_RF2G4_DB_2,
1015                                           AR9271_AN_RF2G4_DB_2_S,
1016                                           db2[0]);
1017         } else {
1018                 ath9k_hw_analog_shift_rmw(ah,
1019                                           AR9285_AN_RF2G3,
1020                                           AR9285_AN_RF2G3_OB_0,
1021                                           AR9285_AN_RF2G3_OB_0_S,
1022                                           ob[0]);
1023                 ath9k_hw_analog_shift_rmw(ah,
1024                                           AR9285_AN_RF2G3,
1025                                           AR9285_AN_RF2G3_OB_1,
1026                                           AR9285_AN_RF2G3_OB_1_S,
1027                                           ob[1]);
1028                 ath9k_hw_analog_shift_rmw(ah,
1029                                           AR9285_AN_RF2G3,
1030                                           AR9285_AN_RF2G3_OB_2,
1031                                           AR9285_AN_RF2G3_OB_2_S,
1032                                           ob[2]);
1033                 ath9k_hw_analog_shift_rmw(ah,
1034                                           AR9285_AN_RF2G3,
1035                                           AR9285_AN_RF2G3_OB_3,
1036                                           AR9285_AN_RF2G3_OB_3_S,
1037                                           ob[3]);
1038                 ath9k_hw_analog_shift_rmw(ah,
1039                                           AR9285_AN_RF2G3,
1040                                           AR9285_AN_RF2G3_OB_4,
1041                                           AR9285_AN_RF2G3_OB_4_S,
1042                                           ob[4]);
1043
1044                 ath9k_hw_analog_shift_rmw(ah,
1045                                           AR9285_AN_RF2G3,
1046                                           AR9285_AN_RF2G3_DB1_0,
1047                                           AR9285_AN_RF2G3_DB1_0_S,
1048                                           db1[0]);
1049                 ath9k_hw_analog_shift_rmw(ah,
1050                                           AR9285_AN_RF2G3,
1051                                           AR9285_AN_RF2G3_DB1_1,
1052                                           AR9285_AN_RF2G3_DB1_1_S,
1053                                           db1[1]);
1054                 ath9k_hw_analog_shift_rmw(ah,
1055                                           AR9285_AN_RF2G3,
1056                                           AR9285_AN_RF2G3_DB1_2,
1057                                           AR9285_AN_RF2G3_DB1_2_S,
1058                                           db1[2]);
1059                 ath9k_hw_analog_shift_rmw(ah,
1060                                           AR9285_AN_RF2G4,
1061                                           AR9285_AN_RF2G4_DB1_3,
1062                                           AR9285_AN_RF2G4_DB1_3_S,
1063                                           db1[3]);
1064                 ath9k_hw_analog_shift_rmw(ah,
1065                                           AR9285_AN_RF2G4,
1066                                           AR9285_AN_RF2G4_DB1_4,
1067                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1068
1069                 ath9k_hw_analog_shift_rmw(ah,
1070                                           AR9285_AN_RF2G4,
1071                                           AR9285_AN_RF2G4_DB2_0,
1072                                           AR9285_AN_RF2G4_DB2_0_S,
1073                                           db2[0]);
1074                 ath9k_hw_analog_shift_rmw(ah,
1075                                           AR9285_AN_RF2G4,
1076                                           AR9285_AN_RF2G4_DB2_1,
1077                                           AR9285_AN_RF2G4_DB2_1_S,
1078                                           db2[1]);
1079                 ath9k_hw_analog_shift_rmw(ah,
1080                                           AR9285_AN_RF2G4,
1081                                           AR9285_AN_RF2G4_DB2_2,
1082                                           AR9285_AN_RF2G4_DB2_2_S,
1083                                           db2[2]);
1084                 ath9k_hw_analog_shift_rmw(ah,
1085                                           AR9285_AN_RF2G4,
1086                                           AR9285_AN_RF2G4_DB2_3,
1087                                           AR9285_AN_RF2G4_DB2_3_S,
1088                                           db2[3]);
1089                 ath9k_hw_analog_shift_rmw(ah,
1090                                           AR9285_AN_RF2G4,
1091                                           AR9285_AN_RF2G4_DB2_4,
1092                                           AR9285_AN_RF2G4_DB2_4_S,
1093                                           db2[4]);
1094         }
1095
1096
1097         if (AR_SREV_9285_11(ah))
1098                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1099
1100         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1101                       pModal->switchSettling);
1102         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1103                       pModal->adcDesiredSize);
1104
1105         REG_WRITE(ah, AR_PHY_RF_CTL4,
1106                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1107                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1108                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1109                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1110
1111         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1112                       pModal->txEndToRxOn);
1113         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1114                       pModal->thresh62);
1115         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1116                       pModal->thresh62);
1117
1118         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1119                                                 AR5416_EEP_MINOR_VER_2) {
1120                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1121                               pModal->txFrameToDataStart);
1122                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1123                               pModal->txFrameToPaOn);
1124         }
1125
1126         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1127                                                 AR5416_EEP_MINOR_VER_3) {
1128                 if (IS_CHAN_HT40(chan))
1129                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1130                                       AR_PHY_SETTLING_SWITCH,
1131                                       pModal->swSettleHt40);
1132         }
1133 }
1134
1135 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1136                                               struct ath9k_channel *chan)
1137 {
1138         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1139         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1140
1141         return pModal->antCtrlCommon & 0xFFFF;
1142 }
1143
1144 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1145                                          enum ieee80211_band freq_band)
1146 {
1147         return 1;
1148 }
1149
1150 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1151 {
1152 #define EEP_MAP4K_SPURCHAN \
1153         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1154         struct ath_common *common = ath9k_hw_common(ah);
1155
1156         u16 spur_val = AR_NO_SPUR;
1157
1158         ath_print(common, ATH_DBG_ANI,
1159                   "Getting spur idx %d is2Ghz. %d val %x\n",
1160                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1161
1162         switch (ah->config.spurmode) {
1163         case SPUR_DISABLE:
1164                 break;
1165         case SPUR_ENABLE_IOCTL:
1166                 spur_val = ah->config.spurchans[i][is2GHz];
1167                 ath_print(common, ATH_DBG_ANI,
1168                           "Getting spur val from new loc. %d\n", spur_val);
1169                 break;
1170         case SPUR_ENABLE_EEPROM:
1171                 spur_val = EEP_MAP4K_SPURCHAN;
1172                 break;
1173         }
1174
1175         return spur_val;
1176
1177 #undef EEP_MAP4K_SPURCHAN
1178 }
1179
1180 const struct eeprom_ops eep_4k_ops = {
1181         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1182         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1183         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1184         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1185         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1186         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1187         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1188         .set_board_values       = ath9k_hw_4k_set_board_values,
1189         .set_addac              = ath9k_hw_4k_set_addac,
1190         .set_txpower            = ath9k_hw_4k_set_txpower,
1191         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1192 };