079dd201a2d8b537d441e13e436fcc3ada86a12f
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_4k.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "ath9k.h"
18 #include "hw.h"
19
20 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
21 {
22         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
23 }
24
25 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
26 {
27         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
28 }
29
30 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
31 {
32 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
33         struct ath_common *common = ath9k_hw_common(ah);
34         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
35         int addr, eep_start_loc = 0;
36
37         eep_start_loc = 64;
38
39         if (!ath9k_hw_use_flash(ah)) {
40                 ath_print(common, ATH_DBG_EEPROM,
41                           "Reading from EEPROM, not flash\n");
42         }
43
44         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
45                 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
46                         ath_print(common, ATH_DBG_EEPROM,
47                                   "Unable to read eeprom region \n");
48                         return false;
49                 }
50                 eep_data++;
51         }
52
53         return true;
54 #undef SIZE_EEPROM_4K
55 }
56
57 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
58 {
59 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
60         struct ath_common *common = ath9k_hw_common(ah);
61         struct ar5416_eeprom_4k *eep =
62                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
63         u16 *eepdata, temp, magic, magic2;
64         u32 sum = 0, el;
65         bool need_swap = false;
66         int i, addr;
67
68
69         if (!ath9k_hw_use_flash(ah)) {
70                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
71                                          &magic)) {
72                         ath_print(common, ATH_DBG_FATAL,
73                                   "Reading Magic # failed\n");
74                         return false;
75                 }
76
77                 ath_print(common, ATH_DBG_EEPROM,
78                           "Read Magic = 0x%04X\n", magic);
79
80                 if (magic != AR5416_EEPROM_MAGIC) {
81                         magic2 = swab16(magic);
82
83                         if (magic2 == AR5416_EEPROM_MAGIC) {
84                                 need_swap = true;
85                                 eepdata = (u16 *) (&ah->eeprom);
86
87                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
88                                         temp = swab16(*eepdata);
89                                         *eepdata = temp;
90                                         eepdata++;
91                                 }
92                         } else {
93                                 ath_print(common, ATH_DBG_FATAL,
94                                           "Invalid EEPROM Magic. "
95                                           "endianness mismatch.\n");
96                                 return -EINVAL;
97                         }
98                 }
99         }
100
101         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
102                   need_swap ? "True" : "False");
103
104         if (need_swap)
105                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
106         else
107                 el = ah->eeprom.map4k.baseEepHeader.length;
108
109         if (el > sizeof(struct ar5416_eeprom_4k))
110                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
111         else
112                 el = el / sizeof(u16);
113
114         eepdata = (u16 *)(&ah->eeprom);
115
116         for (i = 0; i < el; i++)
117                 sum ^= *eepdata++;
118
119         if (need_swap) {
120                 u32 integer;
121                 u16 word;
122
123                 ath_print(common, ATH_DBG_EEPROM,
124                           "EEPROM Endianness is not native.. Changing\n");
125
126                 word = swab16(eep->baseEepHeader.length);
127                 eep->baseEepHeader.length = word;
128
129                 word = swab16(eep->baseEepHeader.checksum);
130                 eep->baseEepHeader.checksum = word;
131
132                 word = swab16(eep->baseEepHeader.version);
133                 eep->baseEepHeader.version = word;
134
135                 word = swab16(eep->baseEepHeader.regDmn[0]);
136                 eep->baseEepHeader.regDmn[0] = word;
137
138                 word = swab16(eep->baseEepHeader.regDmn[1]);
139                 eep->baseEepHeader.regDmn[1] = word;
140
141                 word = swab16(eep->baseEepHeader.rfSilent);
142                 eep->baseEepHeader.rfSilent = word;
143
144                 word = swab16(eep->baseEepHeader.blueToothOptions);
145                 eep->baseEepHeader.blueToothOptions = word;
146
147                 word = swab16(eep->baseEepHeader.deviceCap);
148                 eep->baseEepHeader.deviceCap = word;
149
150                 integer = swab32(eep->modalHeader.antCtrlCommon);
151                 eep->modalHeader.antCtrlCommon = integer;
152
153                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
154                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
155                         eep->modalHeader.antCtrlChain[i] = integer;
156                 }
157
158                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
159                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
160                         eep->modalHeader.spurChans[i].spurChan = word;
161                 }
162         }
163
164         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
165             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
166                 ath_print(common, ATH_DBG_FATAL,
167                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
168                           sum, ah->eep_ops->get_eeprom_ver(ah));
169                 return -EINVAL;
170         }
171
172         return 0;
173 #undef EEPROM_4K_SIZE
174 }
175
176 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
177                                   enum eeprom_param param)
178 {
179         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
180         struct modal_eep_4k_header *pModal = &eep->modalHeader;
181         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
182
183         switch (param) {
184         case EEP_NFTHRESH_2:
185                 return pModal->noiseFloorThreshCh[0];
186         case AR_EEPROM_MAC(0):
187                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
188         case AR_EEPROM_MAC(1):
189                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
190         case AR_EEPROM_MAC(2):
191                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
192         case EEP_REG_0:
193                 return pBase->regDmn[0];
194         case EEP_REG_1:
195                 return pBase->regDmn[1];
196         case EEP_OP_CAP:
197                 return pBase->deviceCap;
198         case EEP_OP_MODE:
199                 return pBase->opCapFlags;
200         case EEP_RF_SILENT:
201                 return pBase->rfSilent;
202         case EEP_OB_2:
203                 return pModal->ob_0;
204         case EEP_DB_2:
205                 return pModal->db1_1;
206         case EEP_MINOR_REV:
207                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
208         case EEP_TX_MASK:
209                 return pBase->txMask;
210         case EEP_RX_MASK:
211                 return pBase->rxMask;
212         case EEP_FRAC_N_5G:
213                 return 0;
214         default:
215                 return 0;
216         }
217 }
218
219 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
220                                 struct ath9k_channel *chan,
221                                 struct cal_data_per_freq_4k *pRawDataSet,
222                                 u8 *bChans, u16 availPiers,
223                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
224                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
225                                 u16 numXpdGains)
226 {
227 #define TMP_VAL_VPD_TABLE \
228         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
229         int i, j, k;
230         int16_t ss;
231         u16 idxL = 0, idxR = 0, numPiers;
232         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
233                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
234         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
235                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
236         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
237                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
238
239         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
240         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
241         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
242         int16_t vpdStep;
243         int16_t tmpVal;
244         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
245         bool match;
246         int16_t minDelta = 0;
247         struct chan_centers centers;
248 #define PD_GAIN_BOUNDARY_DEFAULT 58;
249
250         ath9k_hw_get_channel_centers(ah, chan, &centers);
251
252         for (numPiers = 0; numPiers < availPiers; numPiers++) {
253                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
254                         break;
255         }
256
257         match = ath9k_hw_get_lower_upper_index(
258                                         (u8)FREQ2FBIN(centers.synth_center,
259                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
260                                         &idxL, &idxR);
261
262         if (match) {
263                 for (i = 0; i < numXpdGains; i++) {
264                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
265                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
266                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
267                                         pRawDataSet[idxL].pwrPdg[i],
268                                         pRawDataSet[idxL].vpdPdg[i],
269                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
270                                         vpdTableI[i]);
271                 }
272         } else {
273                 for (i = 0; i < numXpdGains; i++) {
274                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
275                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
276                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
277                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
278
279                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
280
281                         maxPwrT4[i] =
282                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
283                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
284
285
286                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
287                                                 pPwrL, pVpdL,
288                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
289                                                 vpdTableL[i]);
290                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
291                                                 pPwrR, pVpdR,
292                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
293                                                 vpdTableR[i]);
294
295                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
296                                 vpdTableI[i][j] =
297                                         (u8)(ath9k_hw_interpolate((u16)
298                                              FREQ2FBIN(centers.
299                                                        synth_center,
300                                                        IS_CHAN_2GHZ
301                                                        (chan)),
302                                              bChans[idxL], bChans[idxR],
303                                              vpdTableL[i][j], vpdTableR[i][j]));
304                         }
305                 }
306         }
307
308         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
309
310         k = 0;
311
312         for (i = 0; i < numXpdGains; i++) {
313                 if (i == (numXpdGains - 1))
314                         pPdGainBoundaries[i] =
315                                 (u16)(maxPwrT4[i] / 2);
316                 else
317                         pPdGainBoundaries[i] =
318                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
319
320                 pPdGainBoundaries[i] =
321                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
322
323                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
324                         minDelta = pPdGainBoundaries[0] - 23;
325                         pPdGainBoundaries[0] = 23;
326                 } else {
327                         minDelta = 0;
328                 }
329
330                 if (i == 0) {
331                         if (AR_SREV_9280_10_OR_LATER(ah))
332                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
333                         else
334                                 ss = 0;
335                 } else {
336                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
337                                         (minPwrT4[i] / 2)) -
338                                        tPdGainOverlap + 1 + minDelta);
339                 }
340                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
341                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
342
343                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
344                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
345                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
346                         ss++;
347                 }
348
349                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
350                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
351                                 (minPwrT4[i] / 2));
352                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
353                         tgtIndex : sizeCurrVpdTable;
354
355                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
356                         pPDADCValues[k++] = vpdTableI[i][ss++];
357
358                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
359                                     vpdTableI[i][sizeCurrVpdTable - 2]);
360                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
361
362                 if (tgtIndex >= maxIndex) {
363                         while ((ss <= tgtIndex) &&
364                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
365                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
366                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
367                                                          255 : tmpVal);
368                                 ss++;
369                         }
370                 }
371         }
372
373         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
374                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
375                 i++;
376         }
377
378         while (k < AR5416_NUM_PDADC_VALUES) {
379                 pPDADCValues[k] = pPDADCValues[k - 1];
380                 k++;
381         }
382
383         return;
384 #undef TMP_VAL_VPD_TABLE
385 }
386
387 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
388                                   struct ath9k_channel *chan,
389                                   int16_t *pTxPowerIndexOffset)
390 {
391         struct ath_common *common = ath9k_hw_common(ah);
392         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
393         struct cal_data_per_freq_4k *pRawDataset;
394         u8 *pCalBChans = NULL;
395         u16 pdGainOverlap_t2;
396         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
397         u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
398         u16 numPiers, i, j;
399         int16_t tMinCalPower;
400         u16 numXpdGain, xpdMask;
401         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
402         u32 reg32, regOffset, regChainOffset;
403
404         xpdMask = pEepData->modalHeader.xpdGain;
405
406         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
407             AR5416_EEP_MINOR_VER_2) {
408                 pdGainOverlap_t2 =
409                         pEepData->modalHeader.pdGainOverlap;
410         } else {
411                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
412                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
413         }
414
415         pCalBChans = pEepData->calFreqPier2G;
416         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
417
418         numXpdGain = 0;
419
420         for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
421                 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
422                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
423                                 break;
424                         xpdGainValues[numXpdGain] =
425                                 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
426                         numXpdGain++;
427                 }
428         }
429
430         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
431                       (numXpdGain - 1) & 0x3);
432         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
433                       xpdGainValues[0]);
434         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
435                       xpdGainValues[1]);
436         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
437
438         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
439                 if (AR_SREV_5416_20_OR_LATER(ah) &&
440                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
441                     (i != 0)) {
442                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
443                 } else
444                         regChainOffset = i * 0x1000;
445
446                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
447                         pRawDataset = pEepData->calPierData2G[i];
448
449                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
450                                             pRawDataset, pCalBChans,
451                                             numPiers, pdGainOverlap_t2,
452                                             &tMinCalPower, gainBoundaries,
453                                             pdadcValues, numXpdGain);
454
455                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
456                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
457                                           SM(pdGainOverlap_t2,
458                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
459                                           | SM(gainBoundaries[0],
460                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
461                                           | SM(gainBoundaries[1],
462                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
463                                           | SM(gainBoundaries[2],
464                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
465                                           | SM(gainBoundaries[3],
466                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
467                         }
468
469                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
470                         for (j = 0; j < 32; j++) {
471                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
472                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
473                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
474                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
475                                 REG_WRITE(ah, regOffset, reg32);
476
477                                 ath_print(common, ATH_DBG_EEPROM,
478                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
479                                           i, regChainOffset, regOffset,
480                                           reg32);
481                                 ath_print(common, ATH_DBG_EEPROM,
482                                           "PDADC: Chain %d | "
483                                           "PDADC %3d Value %3d | "
484                                           "PDADC %3d Value %3d | "
485                                           "PDADC %3d Value %3d | "
486                                           "PDADC %3d Value %3d |\n",
487                                           i, 4 * j, pdadcValues[4 * j],
488                                           4 * j + 1, pdadcValues[4 * j + 1],
489                                           4 * j + 2, pdadcValues[4 * j + 2],
490                                           4 * j + 3,
491                                           pdadcValues[4 * j + 3]);
492
493                                 regOffset += 4;
494                         }
495                 }
496         }
497
498         *pTxPowerIndexOffset = 0;
499 }
500
501 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
502                                                  struct ath9k_channel *chan,
503                                                  int16_t *ratesArray,
504                                                  u16 cfgCtl,
505                                                  u16 AntennaReduction,
506                                                  u16 twiceMaxRegulatoryPower,
507                                                  u16 powerLimit)
508 {
509 #define CMP_TEST_GRP \
510         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
511          pEepData->ctlIndex[i])                                         \
512         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
513             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
514
515         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
516         int i;
517         int16_t twiceLargestAntenna;
518         u16 twiceMinEdgePower;
519         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
520         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
521         u16 numCtlModes, *pCtlMode, ctlMode, freq;
522         struct chan_centers centers;
523         struct cal_ctl_data_4k *rep;
524         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
525         static const u16 tpScaleReductionTable[5] =
526                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
527         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
528                 0, { 0, 0, 0, 0}
529         };
530         struct cal_target_power_leg targetPowerOfdmExt = {
531                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
532                 0, { 0, 0, 0, 0 }
533         };
534         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
535                 0, {0, 0, 0, 0}
536         };
537         u16 ctlModesFor11g[] =
538                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
539                   CTL_2GHT40
540                 };
541
542         ath9k_hw_get_channel_centers(ah, chan, &centers);
543
544         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
545         twiceLargestAntenna = (int16_t)min(AntennaReduction -
546                                            twiceLargestAntenna, 0);
547
548         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
549         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
550                 maxRegAllowedPower -=
551                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
552         }
553
554         scaledPower = min(powerLimit, maxRegAllowedPower);
555         scaledPower = max((u16)0, scaledPower);
556
557         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
558         pCtlMode = ctlModesFor11g;
559
560         ath9k_hw_get_legacy_target_powers(ah, chan,
561                         pEepData->calTargetPowerCck,
562                         AR5416_NUM_2G_CCK_TARGET_POWERS,
563                         &targetPowerCck, 4, false);
564         ath9k_hw_get_legacy_target_powers(ah, chan,
565                         pEepData->calTargetPower2G,
566                         AR5416_NUM_2G_20_TARGET_POWERS,
567                         &targetPowerOfdm, 4, false);
568         ath9k_hw_get_target_powers(ah, chan,
569                         pEepData->calTargetPower2GHT20,
570                         AR5416_NUM_2G_20_TARGET_POWERS,
571                         &targetPowerHt20, 8, false);
572
573         if (IS_CHAN_HT40(chan)) {
574                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
575                 ath9k_hw_get_target_powers(ah, chan,
576                                 pEepData->calTargetPower2GHT40,
577                                 AR5416_NUM_2G_40_TARGET_POWERS,
578                                 &targetPowerHt40, 8, true);
579                 ath9k_hw_get_legacy_target_powers(ah, chan,
580                                 pEepData->calTargetPowerCck,
581                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
582                                 &targetPowerCckExt, 4, true);
583                 ath9k_hw_get_legacy_target_powers(ah, chan,
584                                 pEepData->calTargetPower2G,
585                                 AR5416_NUM_2G_20_TARGET_POWERS,
586                                 &targetPowerOfdmExt, 4, true);
587         }
588
589         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
590                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
591                         (pCtlMode[ctlMode] == CTL_2GHT40);
592
593                 if (isHt40CtlMode)
594                         freq = centers.synth_center;
595                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
596                         freq = centers.ext_center;
597                 else
598                         freq = centers.ctl_center;
599
600                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
601                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
602                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
603
604                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
605                              pEepData->ctlIndex[i]; i++) {
606
607                         if (CMP_TEST_GRP) {
608                                 rep = &(pEepData->ctlData[i]);
609
610                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
611                                         freq,
612                                         rep->ctlEdges[
613                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
614                                         IS_CHAN_2GHZ(chan),
615                                         AR5416_EEP4K_NUM_BAND_EDGES);
616
617                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
618                                         twiceMaxEdgePower =
619                                                 min(twiceMaxEdgePower,
620                                                     twiceMinEdgePower);
621                                 } else {
622                                         twiceMaxEdgePower = twiceMinEdgePower;
623                                         break;
624                                 }
625                         }
626                 }
627
628                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
629
630                 switch (pCtlMode[ctlMode]) {
631                 case CTL_11B:
632                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
633                                 targetPowerCck.tPow2x[i] =
634                                         min((u16)targetPowerCck.tPow2x[i],
635                                             minCtlPower);
636                         }
637                         break;
638                 case CTL_11G:
639                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
640                                 targetPowerOfdm.tPow2x[i] =
641                                         min((u16)targetPowerOfdm.tPow2x[i],
642                                             minCtlPower);
643                         }
644                         break;
645                 case CTL_2GHT20:
646                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
647                                 targetPowerHt20.tPow2x[i] =
648                                         min((u16)targetPowerHt20.tPow2x[i],
649                                             minCtlPower);
650                         }
651                         break;
652                 case CTL_11B_EXT:
653                         targetPowerCckExt.tPow2x[0] =
654                                 min((u16)targetPowerCckExt.tPow2x[0],
655                                     minCtlPower);
656                         break;
657                 case CTL_11G_EXT:
658                         targetPowerOfdmExt.tPow2x[0] =
659                                 min((u16)targetPowerOfdmExt.tPow2x[0],
660                                     minCtlPower);
661                         break;
662                 case CTL_2GHT40:
663                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
664                                 targetPowerHt40.tPow2x[i] =
665                                         min((u16)targetPowerHt40.tPow2x[i],
666                                             minCtlPower);
667                         }
668                         break;
669                 default:
670                         break;
671                 }
672         }
673
674         ratesArray[rate6mb] =
675         ratesArray[rate9mb] =
676         ratesArray[rate12mb] =
677         ratesArray[rate18mb] =
678         ratesArray[rate24mb] =
679         targetPowerOfdm.tPow2x[0];
680
681         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
682         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
683         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
684         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
685
686         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
687                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
688
689         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
690         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
691         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
692         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
693
694         if (IS_CHAN_HT40(chan)) {
695                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
696                         ratesArray[rateHt40_0 + i] =
697                                 targetPowerHt40.tPow2x[i];
698                 }
699                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
700                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
701                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
702                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
703         }
704
705 #undef CMP_TEST_GRP
706 }
707
708 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
709                                     struct ath9k_channel *chan,
710                                     u16 cfgCtl,
711                                     u8 twiceAntennaReduction,
712                                     u8 twiceMaxRegulatoryPower,
713                                     u8 powerLimit)
714 {
715         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
716         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
717         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
718         int16_t ratesArray[Ar5416RateSize];
719         int16_t txPowerIndexOffset = 0;
720         u8 ht40PowerIncForPdadc = 2;
721         int i;
722
723         memset(ratesArray, 0, sizeof(ratesArray));
724
725         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
726             AR5416_EEP_MINOR_VER_2) {
727                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
728         }
729
730         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
731                                              &ratesArray[0], cfgCtl,
732                                              twiceAntennaReduction,
733                                              twiceMaxRegulatoryPower,
734                                              powerLimit);
735
736         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
737
738         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
739                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
740                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
741                         ratesArray[i] = AR5416_MAX_RATE_POWER;
742         }
743
744
745         /* Update regulatory */
746
747         i = rate6mb;
748         if (IS_CHAN_HT40(chan))
749                 i = rateHt40_0;
750         else if (IS_CHAN_HT20(chan))
751                 i = rateHt20_0;
752
753         regulatory->max_power_level = ratesArray[i];
754
755         if (AR_SREV_9280_10_OR_LATER(ah)) {
756                 for (i = 0; i < Ar5416RateSize; i++)
757                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
758         }
759
760         /* OFDM power per rate */
761         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
762                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
763                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
764                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
765                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
766         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
767                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
768                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
769                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
770                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
771
772         /* CCK power per rate */
773         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
774                   ATH9K_POW_SM(ratesArray[rate2s], 24)
775                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
776                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
777                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
778         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
779                   ATH9K_POW_SM(ratesArray[rate11s], 24)
780                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
781                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
782                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
783
784         /* HT20 power per rate */
785         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
786                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
787                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
788                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
789                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
790         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
791                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
792                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
793                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
794                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
795
796         /* HT40 power per rate */
797         if (IS_CHAN_HT40(chan)) {
798                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
799                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
800                                        ht40PowerIncForPdadc, 24)
801                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
802                                          ht40PowerIncForPdadc, 16)
803                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
804                                          ht40PowerIncForPdadc, 8)
805                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
806                                          ht40PowerIncForPdadc, 0));
807                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
808                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
809                                        ht40PowerIncForPdadc, 24)
810                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
811                                          ht40PowerIncForPdadc, 16)
812                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
813                                          ht40PowerIncForPdadc, 8)
814                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
815                                          ht40PowerIncForPdadc, 0));
816                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
817                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
818                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
819                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
820                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
821         }
822 }
823
824 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
825                                   struct ath9k_channel *chan)
826 {
827         struct modal_eep_4k_header *pModal;
828         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
829         u8 biaslevel;
830
831         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
832                 return;
833
834         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
835                 return;
836
837         pModal = &eep->modalHeader;
838
839         if (pModal->xpaBiasLvl != 0xff) {
840                 biaslevel = pModal->xpaBiasLvl;
841                 INI_RA(&ah->iniAddac, 7, 1) =
842                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
843         }
844 }
845
846 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
847                                  struct modal_eep_4k_header *pModal,
848                                  struct ar5416_eeprom_4k *eep,
849                                  u8 txRxAttenLocal)
850 {
851         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
852                   pModal->antCtrlChain[0]);
853
854         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
855                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
856                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
857                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
858                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
859                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
860
861         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
862             AR5416_EEP_MINOR_VER_3) {
863                 txRxAttenLocal = pModal->txRxAttenCh[0];
864
865                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
866                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
867                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
868                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
869                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
870                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
871                               pModal->xatten2Margin[0]);
872                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
873                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
874
875                 /* Set the block 1 value to block 0 value */
876                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
877                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
878                               pModal->bswMargin[0]);
879                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
880                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
881                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
882                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
883                               pModal->xatten2Margin[0]);
884                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
885                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
886                               pModal->xatten2Db[0]);
887         }
888
889         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
890                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
891         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
892                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
893
894         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
895                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
896         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
897                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
898
899         if (AR_SREV_9285_11(ah))
900                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
901 }
902
903 /*
904  * Read EEPROM header info and program the device for correct operation
905  * given the channel value.
906  */
907 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
908                                          struct ath9k_channel *chan)
909 {
910         struct modal_eep_4k_header *pModal;
911         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
912         u8 txRxAttenLocal;
913         u8 ob[5], db1[5], db2[5];
914         u8 ant_div_control1, ant_div_control2;
915         u32 regVal;
916
917         pModal = &eep->modalHeader;
918         txRxAttenLocal = 23;
919
920         REG_WRITE(ah, AR_PHY_SWITCH_COM,
921                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
922
923         /* Single chain for 4K EEPROM*/
924         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
925
926         /* Initialize Ant Diversity settings from EEPROM */
927         if (pModal->version >= 3) {
928                 ant_div_control1 = pModal->antdiv_ctl1;
929                 ant_div_control2 = pModal->antdiv_ctl2;
930
931                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
932                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
933
934                 regVal |= SM(ant_div_control1,
935                              AR_PHY_9285_ANT_DIV_CTL);
936                 regVal |= SM(ant_div_control2,
937                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
938                 regVal |= SM((ant_div_control2 >> 2),
939                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
940                 regVal |= SM((ant_div_control1 >> 1),
941                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
942                 regVal |= SM((ant_div_control1 >> 2),
943                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
944
945
946                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
947                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
948                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
949                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
950                 regVal |= SM((ant_div_control1 >> 3),
951                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
952
953                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
954                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
955         }
956
957         if (pModal->version >= 2) {
958                 ob[0] = pModal->ob_0;
959                 ob[1] = pModal->ob_1;
960                 ob[2] = pModal->ob_2;
961                 ob[3] = pModal->ob_3;
962                 ob[4] = pModal->ob_4;
963
964                 db1[0] = pModal->db1_0;
965                 db1[1] = pModal->db1_1;
966                 db1[2] = pModal->db1_2;
967                 db1[3] = pModal->db1_3;
968                 db1[4] = pModal->db1_4;
969
970                 db2[0] = pModal->db2_0;
971                 db2[1] = pModal->db2_1;
972                 db2[2] = pModal->db2_2;
973                 db2[3] = pModal->db2_3;
974                 db2[4] = pModal->db2_4;
975         } else if (pModal->version == 1) {
976                 ob[0] = pModal->ob_0;
977                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
978                 db1[0] = pModal->db1_0;
979                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
980                 db2[0] = pModal->db2_0;
981                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
982         } else {
983                 int i;
984
985                 for (i = 0; i < 5; i++) {
986                         ob[i] = pModal->ob_0;
987                         db1[i] = pModal->db1_0;
988                         db2[i] = pModal->db1_0;
989                 }
990         }
991
992         if (AR_SREV_9271(ah)) {
993                 ath9k_hw_analog_shift_rmw(ah,
994                                           AR9285_AN_RF2G3,
995                                           AR9271_AN_RF2G3_OB_cck,
996                                           AR9271_AN_RF2G3_OB_cck_S,
997                                           ob[0]);
998                 ath9k_hw_analog_shift_rmw(ah,
999                                           AR9285_AN_RF2G3,
1000                                           AR9271_AN_RF2G3_OB_psk,
1001                                           AR9271_AN_RF2G3_OB_psk_S,
1002                                           ob[1]);
1003                 ath9k_hw_analog_shift_rmw(ah,
1004                                           AR9285_AN_RF2G3,
1005                                           AR9271_AN_RF2G3_OB_qam,
1006                                           AR9271_AN_RF2G3_OB_qam_S,
1007                                           ob[2]);
1008                 ath9k_hw_analog_shift_rmw(ah,
1009                                           AR9285_AN_RF2G3,
1010                                           AR9271_AN_RF2G3_DB_1,
1011                                           AR9271_AN_RF2G3_DB_1_S,
1012                                           db1[0]);
1013                 ath9k_hw_analog_shift_rmw(ah,
1014                                           AR9285_AN_RF2G4,
1015                                           AR9271_AN_RF2G4_DB_2,
1016                                           AR9271_AN_RF2G4_DB_2_S,
1017                                           db2[0]);
1018         } else {
1019                 ath9k_hw_analog_shift_rmw(ah,
1020                                           AR9285_AN_RF2G3,
1021                                           AR9285_AN_RF2G3_OB_0,
1022                                           AR9285_AN_RF2G3_OB_0_S,
1023                                           ob[0]);
1024                 ath9k_hw_analog_shift_rmw(ah,
1025                                           AR9285_AN_RF2G3,
1026                                           AR9285_AN_RF2G3_OB_1,
1027                                           AR9285_AN_RF2G3_OB_1_S,
1028                                           ob[1]);
1029                 ath9k_hw_analog_shift_rmw(ah,
1030                                           AR9285_AN_RF2G3,
1031                                           AR9285_AN_RF2G3_OB_2,
1032                                           AR9285_AN_RF2G3_OB_2_S,
1033                                           ob[2]);
1034                 ath9k_hw_analog_shift_rmw(ah,
1035                                           AR9285_AN_RF2G3,
1036                                           AR9285_AN_RF2G3_OB_3,
1037                                           AR9285_AN_RF2G3_OB_3_S,
1038                                           ob[3]);
1039                 ath9k_hw_analog_shift_rmw(ah,
1040                                           AR9285_AN_RF2G3,
1041                                           AR9285_AN_RF2G3_OB_4,
1042                                           AR9285_AN_RF2G3_OB_4_S,
1043                                           ob[4]);
1044
1045                 ath9k_hw_analog_shift_rmw(ah,
1046                                           AR9285_AN_RF2G3,
1047                                           AR9285_AN_RF2G3_DB1_0,
1048                                           AR9285_AN_RF2G3_DB1_0_S,
1049                                           db1[0]);
1050                 ath9k_hw_analog_shift_rmw(ah,
1051                                           AR9285_AN_RF2G3,
1052                                           AR9285_AN_RF2G3_DB1_1,
1053                                           AR9285_AN_RF2G3_DB1_1_S,
1054                                           db1[1]);
1055                 ath9k_hw_analog_shift_rmw(ah,
1056                                           AR9285_AN_RF2G3,
1057                                           AR9285_AN_RF2G3_DB1_2,
1058                                           AR9285_AN_RF2G3_DB1_2_S,
1059                                           db1[2]);
1060                 ath9k_hw_analog_shift_rmw(ah,
1061                                           AR9285_AN_RF2G4,
1062                                           AR9285_AN_RF2G4_DB1_3,
1063                                           AR9285_AN_RF2G4_DB1_3_S,
1064                                           db1[3]);
1065                 ath9k_hw_analog_shift_rmw(ah,
1066                                           AR9285_AN_RF2G4,
1067                                           AR9285_AN_RF2G4_DB1_4,
1068                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1069
1070                 ath9k_hw_analog_shift_rmw(ah,
1071                                           AR9285_AN_RF2G4,
1072                                           AR9285_AN_RF2G4_DB2_0,
1073                                           AR9285_AN_RF2G4_DB2_0_S,
1074                                           db2[0]);
1075                 ath9k_hw_analog_shift_rmw(ah,
1076                                           AR9285_AN_RF2G4,
1077                                           AR9285_AN_RF2G4_DB2_1,
1078                                           AR9285_AN_RF2G4_DB2_1_S,
1079                                           db2[1]);
1080                 ath9k_hw_analog_shift_rmw(ah,
1081                                           AR9285_AN_RF2G4,
1082                                           AR9285_AN_RF2G4_DB2_2,
1083                                           AR9285_AN_RF2G4_DB2_2_S,
1084                                           db2[2]);
1085                 ath9k_hw_analog_shift_rmw(ah,
1086                                           AR9285_AN_RF2G4,
1087                                           AR9285_AN_RF2G4_DB2_3,
1088                                           AR9285_AN_RF2G4_DB2_3_S,
1089                                           db2[3]);
1090                 ath9k_hw_analog_shift_rmw(ah,
1091                                           AR9285_AN_RF2G4,
1092                                           AR9285_AN_RF2G4_DB2_4,
1093                                           AR9285_AN_RF2G4_DB2_4_S,
1094                                           db2[4]);
1095         }
1096
1097
1098         if (AR_SREV_9285_11(ah))
1099                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1100
1101         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1102                       pModal->switchSettling);
1103         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1104                       pModal->adcDesiredSize);
1105
1106         REG_WRITE(ah, AR_PHY_RF_CTL4,
1107                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1108                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1109                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1110                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1111
1112         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1113                       pModal->txEndToRxOn);
1114         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1115                       pModal->thresh62);
1116         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1117                       pModal->thresh62);
1118
1119         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1120                                                 AR5416_EEP_MINOR_VER_2) {
1121                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1122                               pModal->txFrameToDataStart);
1123                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1124                               pModal->txFrameToPaOn);
1125         }
1126
1127         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1128                                                 AR5416_EEP_MINOR_VER_3) {
1129                 if (IS_CHAN_HT40(chan))
1130                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1131                                       AR_PHY_SETTLING_SWITCH,
1132                                       pModal->swSettleHt40);
1133         }
1134 }
1135
1136 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1137                                               struct ath9k_channel *chan)
1138 {
1139         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1140         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1141
1142         return pModal->antCtrlCommon & 0xFFFF;
1143 }
1144
1145 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1146                                          enum ieee80211_band freq_band)
1147 {
1148         return 1;
1149 }
1150
1151 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1152 {
1153 #define EEP_MAP4K_SPURCHAN \
1154         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1155         struct ath_common *common = ath9k_hw_common(ah);
1156
1157         u16 spur_val = AR_NO_SPUR;
1158
1159         ath_print(common, ATH_DBG_ANI,
1160                   "Getting spur idx %d is2Ghz. %d val %x\n",
1161                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1162
1163         switch (ah->config.spurmode) {
1164         case SPUR_DISABLE:
1165                 break;
1166         case SPUR_ENABLE_IOCTL:
1167                 spur_val = ah->config.spurchans[i][is2GHz];
1168                 ath_print(common, ATH_DBG_ANI,
1169                           "Getting spur val from new loc. %d\n", spur_val);
1170                 break;
1171         case SPUR_ENABLE_EEPROM:
1172                 spur_val = EEP_MAP4K_SPURCHAN;
1173                 break;
1174         }
1175
1176         return spur_val;
1177
1178 #undef EEP_MAP4K_SPURCHAN
1179 }
1180
1181 const struct eeprom_ops eep_4k_ops = {
1182         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1183         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1184         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1185         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1186         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1187         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1188         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1189         .set_board_values       = ath9k_hw_4k_set_board_values,
1190         .set_addac              = ath9k_hw_4k_set_addac,
1191         .set_txpower            = ath9k_hw_4k_set_txpower,
1192         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1193 };