drivers/net/wireless/ath/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #include <net/cfg80211.h>
  21
  22 #define AH_USE_EEPROM   0x1
  23
  24 #ifdef __BIG_ENDIAN
  25 #define AR5416_EEPROM_MAGIC 0x5aa5
  26 #else
  27 #define AR5416_EEPROM_MAGIC 0xa55a
  28 #endif
  29
  30 #define CTRY_DEBUG   0x1ff
  31 #define CTRY_DEFAULT 0
  32
  33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  34 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  36 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  37 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  38 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  40 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  41 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  42
  43 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  44 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  45 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  46 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  47 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  48 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  49
  50 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  51 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  52
  53 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  54 #define AR5416_EEPROM_S             2
  55 #define AR5416_EEPROM_OFFSET        0x2000
  56 #define AR5416_EEPROM_MAX           0xae0
  57
  58 #define AR5416_EEPROM_START_ADDR \
  59         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  60
  61 #define SD_NO_CTL               0xE0
  62 #define NO_CTL                  0xff
  63 #define CTL_MODE_M              7
  64 #define CTL_11A                 0
  65 #define CTL_11B                 1
  66 #define CTL_11G                 2
  67 #define CTL_2GHT20              5
  68 #define CTL_5GHT20              6
  69 #define CTL_2GHT40              7
  70 #define CTL_5GHT40              8
  71
  72 #define EXT_ADDITIVE (0x8000)
  73 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  74 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  75 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  76
  77 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  78 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  79
  80 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  81 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  82
  83 /*
  84  * For AR9285 and later chipsets, the following bits are not being programmed
  85  * in EEPROM and so need to be enabled always.
  86  *
  87  * Bit 0: en_fcc_mid
  88  * Bit 1: en_jap_mid
  89  * Bit 2: en_fcc_dfs_ht40
  90  * Bit 3: en_jap_ht40
  91  * Bit 4: en_jap_dfs_ht40
  92  */
  93 #define AR9285_RDEXT_DEFAULT    0x1F
  94
  95 #define AR_EEPROM_MAC(i)        (0x1d+(i))
  96 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  97 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  98 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
  99
 100 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 101 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
 102                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 103
 104 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 105 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 106 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 107 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 108
 109 #define EEP_RFSILENT_ENABLED        0x0001
 110 #define EEP_RFSILENT_ENABLED_S      0
 111 #define EEP_RFSILENT_POLARITY       0x0002
 112 #define EEP_RFSILENT_POLARITY_S     1
 113 #define EEP_RFSILENT_GPIO_SEL       0x001c
 114 #define EEP_RFSILENT_GPIO_SEL_S     2
 115
 116 #define AR5416_OPFLAGS_11A           0x01
 117 #define AR5416_OPFLAGS_11G           0x02
 118 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 119 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 120 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 121 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 122
 123 #define AR5416_EEP_NO_BACK_VER       0x1
 124 #define AR5416_EEP_VER               0xE
 125 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 126 #define AR5416_EEP_MINOR_VER_2       0x2
 127 #define AR5416_EEP_MINOR_VER_3       0x3
 128 #define AR5416_EEP_MINOR_VER_7       0x7
 129 #define AR5416_EEP_MINOR_VER_9       0x9
 130 #define AR5416_EEP_MINOR_VER_16      0x10
 131 #define AR5416_EEP_MINOR_VER_17      0x11
 132 #define AR5416_EEP_MINOR_VER_19      0x13
 133 #define AR5416_EEP_MINOR_VER_20      0x14
 134 #define AR5416_EEP_MINOR_VER_22      0x16
 135
 136 #define AR5416_NUM_5G_CAL_PIERS         8
 137 #define AR5416_NUM_2G_CAL_PIERS         4
 138 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 139 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 140 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 141 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 142 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 143 #define AR5416_NUM_CTLS                 24
 144 #define AR5416_NUM_BAND_EDGES           8
 145 #define AR5416_NUM_PD_GAINS             4
 146 #define AR5416_PD_GAINS_IN_MASK         4
 147 #define AR5416_PD_GAIN_ICEPTS           5
 148 #define AR5416_EEPROM_MODAL_SPURS       5
 149 #define AR5416_MAX_RATE_POWER           63
 150 #define AR5416_NUM_PDADC_VALUES         128
 151 #define AR5416_BCHAN_UNUSED             0xFF
 152 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 153 #define AR5416_MAX_CHAINS               3
 154 #define AR5416_PWR_TABLE_OFFSET         -5
 155
 156 /* Rx gain type values */
 157 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 158 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 159 #define AR5416_EEP_RXGAIN_ORIG             2
 160
 161 /* Tx gain type values */
 162 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 163 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 164
 165 #define AR5416_EEP4K_START_LOC                64
 166 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 167 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 168 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 169 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 170 #define AR5416_EEP4K_NUM_CTLS                 12
 171 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 172 #define AR5416_EEP4K_NUM_PD_GAINS             2
 173 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
 174 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 175 #define AR5416_EEP4K_MAX_CHAINS               1
 176
 177 #define AR9280_TX_GAIN_TABLE_SIZE 22
 178
 179 enum eeprom_param {
 180         EEP_NFTHRESH_5,
 181         EEP_NFTHRESH_2,
 182         EEP_MAC_MSW,
 183         EEP_MAC_MID,
 184         EEP_MAC_LSW,
 185         EEP_REG_0,
 186         EEP_REG_1,
 187         EEP_OP_CAP,
 188         EEP_OP_MODE,
 189         EEP_RF_SILENT,
 190         EEP_OB_5,
 191         EEP_DB_5,
 192         EEP_OB_2,
 193         EEP_DB_2,
 194         EEP_MINOR_REV,
 195         EEP_TX_MASK,
 196         EEP_RX_MASK,
 197         EEP_RXGAIN_TYPE,
 198         EEP_TXGAIN_TYPE,
 199         EEP_OL_PWRCTRL,
 200         EEP_RC_CHAIN_MASK,
 201         EEP_DAC_HPWR_5G,
 202         EEP_FRAC_N_5G
 203 };
 204
 205 enum ar5416_rates {
 206         rate6mb, rate9mb, rate12mb, rate18mb,
 207         rate24mb, rate36mb, rate48mb, rate54mb,
 208         rate1l, rate2l, rate2s, rate5_5l,
 209         rate5_5s, rate11l, rate11s, rateXr,
 210         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 211         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 212         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 213         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 214         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 215         Ar5416RateSize
 216 };
 217
 218 enum ath9k_hal_freq_band {
 219         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 220         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 221 };
 222
 223 struct base_eep_header {
 224         u16 length;
 225         u16 checksum;
 226         u16 version;
 227         u8 opCapFlags;
 228         u8 eepMisc;
 229         u16 regDmn[2];
 230         u8 macAddr[6];
 231         u8 rxMask;
 232         u8 txMask;
 233         u16 rfSilent;
 234         u16 blueToothOptions;
 235         u16 deviceCap;
 236         u32 binBuildNumber;
 237         u8 deviceType;
 238         u8 pwdclkind;
 239         u8 futureBase_1[2];
 240         u8 rxGainType;
 241         u8 dacHiPwrMode_5G;
 242         u8 openLoopPwrCntl;
 243         u8 dacLpMode;
 244         u8 txGainType;
 245         u8 rcChainMask;
 246         u8 desiredScaleCCK;
 247         u8 power_table_offset;
 248         u8 frac_n_5g;
 249         u8 futureBase_3[21];
 250 } __packed;
 251
 252 struct base_eep_header_4k {
 253         u16 length;
 254         u16 checksum;
 255         u16 version;
 256         u8 opCapFlags;
 257         u8 eepMisc;
 258         u16 regDmn[2];
 259         u8 macAddr[6];
 260         u8 rxMask;
 261         u8 txMask;
 262         u16 rfSilent;
 263         u16 blueToothOptions;
 264         u16 deviceCap;
 265         u32 binBuildNumber;
 266         u8 deviceType;
 267         u8 txGainType;
 268 } __packed;
 269
 270
 271 struct spur_chan {
 272         u16 spurChan;
 273         u8 spurRangeLow;
 274         u8 spurRangeHigh;
 275 } __packed;
 276
 277 struct modal_eep_header {
 278         u32 antCtrlChain[AR5416_MAX_CHAINS];
 279         u32 antCtrlCommon;
 280         u8 antennaGainCh[AR5416_MAX_CHAINS];
 281         u8 switchSettling;
 282         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 283         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 284         u8 adcDesiredSize;
 285         u8 pgaDesiredSize;
 286         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 287         u8 txEndToXpaOff;
 288         u8 txEndToRxOn;
 289         u8 txFrameToXpaOn;
 290         u8 thresh62;
 291         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 292         u8 xpdGain;
 293         u8 xpd;
 294         u8 iqCalICh[AR5416_MAX_CHAINS];
 295         u8 iqCalQCh[AR5416_MAX_CHAINS];
 296         u8 pdGainOverlap;
 297         u8 ob;
 298         u8 db;
 299         u8 xpaBiasLvl;
 300         u8 pwrDecreaseFor2Chain;
 301         u8 pwrDecreaseFor3Chain;
 302         u8 txFrameToDataStart;
 303         u8 txFrameToPaOn;
 304         u8 ht40PowerIncForPdadc;
 305         u8 bswAtten[AR5416_MAX_CHAINS];
 306         u8 bswMargin[AR5416_MAX_CHAINS];
 307         u8 swSettleHt40;
 308         u8 xatten2Db[AR5416_MAX_CHAINS];
 309         u8 xatten2Margin[AR5416_MAX_CHAINS];
 310         u8 ob_ch1;
 311         u8 db_ch1;
 312         u8 useAnt1:1,
 313             force_xpaon:1,
 314             local_bias:1,
 315             femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
 316         u8 miscBits;
 317         u16 xpaBiasLvlFreq[3];
 318         u8 futureModal[6];
 319
 320         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 321 } __packed;
 322
 323 struct calDataPerFreqOpLoop {
 324         u8 pwrPdg[2][5];
 325         u8 vpdPdg[2][5];
 326         u8 pcdac[2][5];
 327         u8 empty[2][5];
 328 } __packed;
 329
 330 struct modal_eep_4k_header {
 331         u32  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 332         u32  antCtrlCommon;
 333         u8   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 334         u8   switchSettling;
 335         u8   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 336         u8   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 337         u8   adcDesiredSize;
 338         u8   pgaDesiredSize;
 339         u8   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 340         u8   txEndToXpaOff;
 341         u8   txEndToRxOn;
 342         u8   txFrameToXpaOn;
 343         u8   thresh62;
 344         u8   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 345         u8   xpdGain;
 346         u8   xpd;
 347         u8   iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 348         u8   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 349         u8   pdGainOverlap;
 350         u8   ob_01;
 351         u8   db1_01;
 352         u8   xpaBiasLvl;
 353         u8   txFrameToDataStart;
 354         u8   txFrameToPaOn;
 355         u8   ht40PowerIncForPdadc;
 356         u8   bswAtten[AR5416_EEP4K_MAX_CHAINS];
 357         u8   bswMargin[AR5416_EEP4K_MAX_CHAINS];
 358         u8   swSettleHt40;
 359         u8   xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 360         u8   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 361         u8   db2_01;
 362         u8   version;
 363         u16  ob_234;
 364         u16  db1_234;
 365         u16  db2_234;
 366         u8   futureModal[4];
 367
 368         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 369 } __packed;
 370
 371
 372 struct cal_data_per_freq {
 373         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 374         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 375 } __packed;
 376
 377 struct cal_data_per_freq_4k {
 378         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 379         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 380 } __packed;
 381
 382 struct cal_target_power_leg {
 383         u8 bChannel;
 384         u8 tPow2x[4];
 385 } __packed;
 386
 387 struct cal_target_power_ht {
 388         u8 bChannel;
 389         u8 tPow2x[8];
 390 } __packed;
 391
 392
 393 #ifdef __BIG_ENDIAN_BITFIELD
 394 struct cal_ctl_edges {
 395         u8 bChannel;
 396         u8 flag:2, tPower:6;
 397 } __packed;
 398 #else
 399 struct cal_ctl_edges {
 400         u8 bChannel;
 401         u8 tPower:6, flag:2;
 402 } __packed;
 403 #endif
 404
 405 struct cal_ctl_data {
 406         struct cal_ctl_edges
 407         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 408 } __packed;
 409
 410 struct cal_ctl_data_4k {
 411         struct cal_ctl_edges
 412         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 413 } __packed;
 414
 415 struct ar5416_eeprom_def {
 416         struct base_eep_header baseEepHeader;
 417         u8 custData[64];
 418         struct modal_eep_header modalHeader[2];
 419         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 420         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 421         struct cal_data_per_freq
 422          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 423         struct cal_data_per_freq
 424          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 425         struct cal_target_power_leg
 426          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 427         struct cal_target_power_ht
 428          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 429         struct cal_target_power_ht
 430          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 431         struct cal_target_power_leg
 432          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 433         struct cal_target_power_leg
 434          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 435         struct cal_target_power_ht
 436          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 437         struct cal_target_power_ht
 438          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 439         u8 ctlIndex[AR5416_NUM_CTLS];
 440         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 441         u8 padding;
 442 } __packed;
 443
 444 struct ar5416_eeprom_4k {
 445         struct base_eep_header_4k baseEepHeader;
 446         u8 custData[20];
 447         struct modal_eep_4k_header modalHeader;
 448         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 449         struct cal_data_per_freq_4k
 450         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 451         struct cal_target_power_leg
 452         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 453         struct cal_target_power_leg
 454         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 455         struct cal_target_power_ht
 456         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 457         struct cal_target_power_ht
 458         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 459         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 460         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 461         u8 padding;
 462 } __packed;
 463
 464 enum reg_ext_bitmap {
 465         REG_EXT_JAPAN_MIDBAND = 1,
 466         REG_EXT_FCC_DFS_HT40 = 2,
 467         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 468         REG_EXT_JAPAN_DFS_HT40 = 4
 469 };
 470
 471 struct ath9k_country_entry {
 472         u16 countryCode;
 473         u16 regDmnEnum;
 474         u16 regDmn5G;
 475         u16 regDmn2G;
 476         u8 isMultidomain;
 477         u8 iso[3];
 478 };
 479
 480 enum ath9k_eep_map {
 481         EEP_MAP_DEFAULT = 0x0,
 482         EEP_MAP_4KBITS,
 483         EEP_MAP_MAX
 484 };
 485
 486 struct eeprom_ops {
 487         int (*check_eeprom)(struct ath_hw *hw);
 488         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 489         bool (*fill_eeprom)(struct ath_hw *hw);
 490         int (*get_eeprom_ver)(struct ath_hw *hw);
 491         int (*get_eeprom_rev)(struct ath_hw *hw);
 492         u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
 493         u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
 494                                       struct ath9k_channel *chan);
 495         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 496         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 497         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 498                            u16 cfgCtl, u8 twiceAntennaReduction,
 499                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
 500         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 501 };
 502
 503 #define ar5416_get_ntxchains(_txchainmask)                      \
 504         (((_txchainmask >> 2) & 1) +                            \
 505          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 506
 507 int ath9k_hw_eeprom_attach(struct ath_hw *ah);
 508
 509 #endif /* EEPROM_H */