ath9k: Advertise midband for AR5416 devices
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom.h
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #ifndef EEPROM_H
18 #define EEPROM_H
19
20 #include "../ath.h"
21 #include <net/cfg80211.h>
22
23 #define AH_USE_EEPROM   0x1
24
25 #ifdef __BIG_ENDIAN
26 #define AR5416_EEPROM_MAGIC 0x5aa5
27 #else
28 #define AR5416_EEPROM_MAGIC 0xa55a
29 #endif
30
31 #define CTRY_DEBUG   0x1ff
32 #define CTRY_DEFAULT 0
33
34 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
35 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
36 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
37 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
38 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
39 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
40 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
41 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
42 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
43
44 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
46 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
47 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
50
51 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
52 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
53
54 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
55 #define AR5416_EEPROM_S             2
56 #define AR5416_EEPROM_OFFSET        0x2000
57 #define AR5416_EEPROM_MAX           0xae0
58
59 #define AR5416_EEPROM_START_ADDR \
60         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
61
62 #define SD_NO_CTL               0xE0
63 #define NO_CTL                  0xff
64 #define CTL_MODE_M              7
65 #define CTL_11A                 0
66 #define CTL_11B                 1
67 #define CTL_11G                 2
68 #define CTL_2GHT20              5
69 #define CTL_5GHT20              6
70 #define CTL_2GHT40              7
71 #define CTL_5GHT40              8
72
73 #define EXT_ADDITIVE (0x8000)
74 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
75 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
76 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
77
78 #define SUB_NUM_CTL_MODES_AT_5G_40 2
79 #define SUB_NUM_CTL_MODES_AT_2G_40 3
80
81 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
82 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
83
84 /*
85  * For AR9285 and later chipsets, the following bits are not being programmed
86  * in EEPROM and so need to be enabled always.
87  *
88  * Bit 0: en_fcc_mid
89  * Bit 1: en_jap_mid
90  * Bit 2: en_fcc_dfs_ht40
91  * Bit 3: en_jap_ht40
92  * Bit 4: en_jap_dfs_ht40
93  */
94 #define AR9285_RDEXT_DEFAULT    0x1F
95
96 #define AR_EEPROM_MAC(i)        (0x1d+(i))
97 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
98 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100
101 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
102 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
103                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
104 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
105                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
106
107 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
108 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
109 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
110 #define AR_EEPROM_RFSILENT_POLARITY_S   1
111
112 #define EEP_RFSILENT_ENABLED        0x0001
113 #define EEP_RFSILENT_ENABLED_S      0
114 #define EEP_RFSILENT_POLARITY       0x0002
115 #define EEP_RFSILENT_POLARITY_S     1
116 #define EEP_RFSILENT_GPIO_SEL       0x001c
117 #define EEP_RFSILENT_GPIO_SEL_S     2
118
119 #define AR5416_OPFLAGS_11A           0x01
120 #define AR5416_OPFLAGS_11G           0x02
121 #define AR5416_OPFLAGS_N_5G_HT40     0x04
122 #define AR5416_OPFLAGS_N_2G_HT40     0x08
123 #define AR5416_OPFLAGS_N_5G_HT20     0x10
124 #define AR5416_OPFLAGS_N_2G_HT20     0x20
125
126 #define AR5416_EEP_NO_BACK_VER       0x1
127 #define AR5416_EEP_VER               0xE
128 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
129 #define AR5416_EEP_MINOR_VER_2       0x2
130 #define AR5416_EEP_MINOR_VER_3       0x3
131 #define AR5416_EEP_MINOR_VER_7       0x7
132 #define AR5416_EEP_MINOR_VER_9       0x9
133 #define AR5416_EEP_MINOR_VER_16      0x10
134 #define AR5416_EEP_MINOR_VER_17      0x11
135 #define AR5416_EEP_MINOR_VER_19      0x13
136 #define AR5416_EEP_MINOR_VER_20      0x14
137 #define AR5416_EEP_MINOR_VER_22      0x16
138
139 #define AR5416_NUM_5G_CAL_PIERS         8
140 #define AR5416_NUM_2G_CAL_PIERS         4
141 #define AR5416_NUM_5G_20_TARGET_POWERS  8
142 #define AR5416_NUM_5G_40_TARGET_POWERS  8
143 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
144 #define AR5416_NUM_2G_20_TARGET_POWERS  4
145 #define AR5416_NUM_2G_40_TARGET_POWERS  4
146 #define AR5416_NUM_CTLS                 24
147 #define AR5416_NUM_BAND_EDGES           8
148 #define AR5416_NUM_PD_GAINS             4
149 #define AR5416_PD_GAINS_IN_MASK         4
150 #define AR5416_PD_GAIN_ICEPTS           5
151 #define AR5416_EEPROM_MODAL_SPURS       5
152 #define AR5416_MAX_RATE_POWER           63
153 #define AR5416_NUM_PDADC_VALUES         128
154 #define AR5416_BCHAN_UNUSED             0xFF
155 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
156 #define AR5416_MAX_CHAINS               3
157 #define AR5416_PWR_TABLE_OFFSET         -5
158
159 /* Rx gain type values */
160 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
161 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
162 #define AR5416_EEP_RXGAIN_ORIG             2
163
164 /* Tx gain type values */
165 #define AR5416_EEP_TXGAIN_ORIGINAL         0
166 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
167
168 #define AR5416_EEP4K_START_LOC                64
169 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
170 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
171 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
172 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
173 #define AR5416_EEP4K_NUM_CTLS                 12
174 #define AR5416_EEP4K_NUM_BAND_EDGES           4
175 #define AR5416_EEP4K_NUM_PD_GAINS             2
176 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
177 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
178 #define AR5416_EEP4K_MAX_CHAINS               1
179
180 #define AR9280_TX_GAIN_TABLE_SIZE 22
181
182 #define AR9287_EEP_VER               0xE
183 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
184 #define AR9287_EEP_MINOR_VER_1       0x1
185 #define AR9287_EEP_MINOR_VER_2       0x2
186 #define AR9287_EEP_MINOR_VER_3       0x3
187 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
188 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
189 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
190
191 #define AR9287_EEP_START_LOC            128
192 #define AR9287_NUM_2G_CAL_PIERS         3
193 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
194 #define AR9287_NUM_2G_20_TARGET_POWERS  3
195 #define AR9287_NUM_2G_40_TARGET_POWERS  3
196 #define AR9287_NUM_CTLS                 12
197 #define AR9287_NUM_BAND_EDGES           4
198 #define AR9287_NUM_PD_GAINS             4
199 #define AR9287_PD_GAINS_IN_MASK         4
200 #define AR9287_PD_GAIN_ICEPTS           1
201 #define AR9287_EEPROM_MODAL_SPURS       5
202 #define AR9287_MAX_RATE_POWER           63
203 #define AR9287_NUM_PDADC_VALUES         128
204 #define AR9287_NUM_RATES                16
205 #define AR9287_BCHAN_UNUSED             0xFF
206 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
207 #define AR9287_OPFLAGS_11A              0x01
208 #define AR9287_OPFLAGS_11G              0x02
209 #define AR9287_OPFLAGS_2G_HT40          0x08
210 #define AR9287_OPFLAGS_2G_HT20          0x20
211 #define AR9287_OPFLAGS_5G_HT40          0x04
212 #define AR9287_OPFLAGS_5G_HT20          0x10
213 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
214 #define AR9287_EEPMISC_WOW              0x02
215 #define AR9287_MAX_CHAINS               2
216 #define AR9287_ANT_16S                  32
217 #define AR9287_custdatasize             20
218
219 #define AR9287_NUM_ANT_CHAIN_FIELDS     6
220 #define AR9287_NUM_ANT_COMMON_FIELDS    4
221 #define AR9287_SIZE_ANT_CHAIN_FIELD     2
222 #define AR9287_SIZE_ANT_COMMON_FIELD    4
223 #define AR9287_ANT_CHAIN_MASK           0x3
224 #define AR9287_ANT_COMMON_MASK          0xf
225 #define AR9287_CHAIN_0_IDX              0
226 #define AR9287_CHAIN_1_IDX              1
227 #define AR9287_DATA_SZ                  32
228
229 #define AR9287_PWR_TABLE_OFFSET_DB  -5
230
231 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
232
233 enum eeprom_param {
234         EEP_NFTHRESH_5,
235         EEP_NFTHRESH_2,
236         EEP_MAC_MSW,
237         EEP_MAC_MID,
238         EEP_MAC_LSW,
239         EEP_REG_0,
240         EEP_REG_1,
241         EEP_OP_CAP,
242         EEP_OP_MODE,
243         EEP_RF_SILENT,
244         EEP_OB_5,
245         EEP_DB_5,
246         EEP_OB_2,
247         EEP_DB_2,
248         EEP_MINOR_REV,
249         EEP_TX_MASK,
250         EEP_RX_MASK,
251         EEP_RXGAIN_TYPE,
252         EEP_TXGAIN_TYPE,
253         EEP_OL_PWRCTRL,
254         EEP_RC_CHAIN_MASK,
255         EEP_DAC_HPWR_5G,
256         EEP_FRAC_N_5G,
257         EEP_DEV_TYPE,
258         EEP_TEMPSENSE_SLOPE,
259         EEP_TEMPSENSE_SLOPE_PAL_ON,
260         EEP_PWR_TABLE_OFFSET
261 };
262
263 enum ar5416_rates {
264         rate6mb, rate9mb, rate12mb, rate18mb,
265         rate24mb, rate36mb, rate48mb, rate54mb,
266         rate1l, rate2l, rate2s, rate5_5l,
267         rate5_5s, rate11l, rate11s, rateXr,
268         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
269         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
270         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
271         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
272         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
273         Ar5416RateSize
274 };
275
276 enum ath9k_hal_freq_band {
277         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
278         ATH9K_HAL_FREQ_BAND_2GHZ = 1
279 };
280
281 struct base_eep_header {
282         u16 length;
283         u16 checksum;
284         u16 version;
285         u8 opCapFlags;
286         u8 eepMisc;
287         u16 regDmn[2];
288         u8 macAddr[6];
289         u8 rxMask;
290         u8 txMask;
291         u16 rfSilent;
292         u16 blueToothOptions;
293         u16 deviceCap;
294         u32 binBuildNumber;
295         u8 deviceType;
296         u8 pwdclkind;
297         u8 futureBase_1[2];
298         u8 rxGainType;
299         u8 dacHiPwrMode_5G;
300         u8 openLoopPwrCntl;
301         u8 dacLpMode;
302         u8 txGainType;
303         u8 rcChainMask;
304         u8 desiredScaleCCK;
305         u8 power_table_offset;
306         u8 frac_n_5g;
307         u8 futureBase_3[21];
308 } __packed;
309
310 struct base_eep_header_4k {
311         u16 length;
312         u16 checksum;
313         u16 version;
314         u8 opCapFlags;
315         u8 eepMisc;
316         u16 regDmn[2];
317         u8 macAddr[6];
318         u8 rxMask;
319         u8 txMask;
320         u16 rfSilent;
321         u16 blueToothOptions;
322         u16 deviceCap;
323         u32 binBuildNumber;
324         u8 deviceType;
325         u8 txGainType;
326 } __packed;
327
328
329 struct spur_chan {
330         u16 spurChan;
331         u8 spurRangeLow;
332         u8 spurRangeHigh;
333 } __packed;
334
335 struct modal_eep_header {
336         u32 antCtrlChain[AR5416_MAX_CHAINS];
337         u32 antCtrlCommon;
338         u8 antennaGainCh[AR5416_MAX_CHAINS];
339         u8 switchSettling;
340         u8 txRxAttenCh[AR5416_MAX_CHAINS];
341         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
342         u8 adcDesiredSize;
343         u8 pgaDesiredSize;
344         u8 xlnaGainCh[AR5416_MAX_CHAINS];
345         u8 txEndToXpaOff;
346         u8 txEndToRxOn;
347         u8 txFrameToXpaOn;
348         u8 thresh62;
349         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
350         u8 xpdGain;
351         u8 xpd;
352         u8 iqCalICh[AR5416_MAX_CHAINS];
353         u8 iqCalQCh[AR5416_MAX_CHAINS];
354         u8 pdGainOverlap;
355         u8 ob;
356         u8 db;
357         u8 xpaBiasLvl;
358         u8 pwrDecreaseFor2Chain;
359         u8 pwrDecreaseFor3Chain;
360         u8 txFrameToDataStart;
361         u8 txFrameToPaOn;
362         u8 ht40PowerIncForPdadc;
363         u8 bswAtten[AR5416_MAX_CHAINS];
364         u8 bswMargin[AR5416_MAX_CHAINS];
365         u8 swSettleHt40;
366         u8 xatten2Db[AR5416_MAX_CHAINS];
367         u8 xatten2Margin[AR5416_MAX_CHAINS];
368         u8 ob_ch1;
369         u8 db_ch1;
370         u8 useAnt1:1,
371             force_xpaon:1,
372             local_bias:1,
373             femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
374         u8 miscBits;
375         u16 xpaBiasLvlFreq[3];
376         u8 futureModal[6];
377
378         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
379 } __packed;
380
381 struct calDataPerFreqOpLoop {
382         u8 pwrPdg[2][5];
383         u8 vpdPdg[2][5];
384         u8 pcdac[2][5];
385         u8 empty[2][5];
386 } __packed;
387
388 struct modal_eep_4k_header {
389         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
390         u32 antCtrlCommon;
391         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
392         u8 switchSettling;
393         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
394         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
395         u8 adcDesiredSize;
396         u8 pgaDesiredSize;
397         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
398         u8 txEndToXpaOff;
399         u8 txEndToRxOn;
400         u8 txFrameToXpaOn;
401         u8 thresh62;
402         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
403         u8 xpdGain;
404         u8 xpd;
405         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
406         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
407         u8 pdGainOverlap;
408 #ifdef __BIG_ENDIAN_BITFIELD
409         u8 ob_1:4, ob_0:4;
410         u8 db1_1:4, db1_0:4;
411 #else
412         u8 ob_0:4, ob_1:4;
413         u8 db1_0:4, db1_1:4;
414 #endif
415         u8 xpaBiasLvl;
416         u8 txFrameToDataStart;
417         u8 txFrameToPaOn;
418         u8 ht40PowerIncForPdadc;
419         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
420         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
421         u8 swSettleHt40;
422         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
423         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
424 #ifdef __BIG_ENDIAN_BITFIELD
425         u8 db2_1:4, db2_0:4;
426 #else
427         u8 db2_0:4, db2_1:4;
428 #endif
429         u8 version;
430 #ifdef __BIG_ENDIAN_BITFIELD
431         u8 ob_3:4, ob_2:4;
432         u8 antdiv_ctl1:4, ob_4:4;
433         u8 db1_3:4, db1_2:4;
434         u8 antdiv_ctl2:4, db1_4:4;
435         u8 db2_2:4, db2_3:4;
436         u8 reserved:4, db2_4:4;
437 #else
438         u8 ob_2:4, ob_3:4;
439         u8 ob_4:4, antdiv_ctl1:4;
440         u8 db1_2:4, db1_3:4;
441         u8 db1_4:4, antdiv_ctl2:4;
442         u8 db2_2:4, db2_3:4;
443         u8 db2_4:4, reserved:4;
444 #endif
445         u8 futureModal[4];
446         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
447 } __packed;
448
449 struct base_eep_ar9287_header {
450         u16 length;
451         u16 checksum;
452         u16 version;
453         u8 opCapFlags;
454         u8 eepMisc;
455         u16 regDmn[2];
456         u8 macAddr[6];
457         u8 rxMask;
458         u8 txMask;
459         u16 rfSilent;
460         u16 blueToothOptions;
461         u16 deviceCap;
462         u32 binBuildNumber;
463         u8 deviceType;
464         u8 openLoopPwrCntl;
465         int8_t pwrTableOffset;
466         int8_t tempSensSlope;
467         int8_t tempSensSlopePalOn;
468         u8 futureBase[29];
469 } __packed;
470
471 struct modal_eep_ar9287_header {
472         u32 antCtrlChain[AR9287_MAX_CHAINS];
473         u32 antCtrlCommon;
474         int8_t antennaGainCh[AR9287_MAX_CHAINS];
475         u8 switchSettling;
476         u8 txRxAttenCh[AR9287_MAX_CHAINS];
477         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
478         int8_t adcDesiredSize;
479         u8 txEndToXpaOff;
480         u8 txEndToRxOn;
481         u8 txFrameToXpaOn;
482         u8 thresh62;
483         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
484         u8 xpdGain;
485         u8 xpd;
486         int8_t iqCalICh[AR9287_MAX_CHAINS];
487         int8_t iqCalQCh[AR9287_MAX_CHAINS];
488         u8 pdGainOverlap;
489         u8 xpaBiasLvl;
490         u8 txFrameToDataStart;
491         u8 txFrameToPaOn;
492         u8 ht40PowerIncForPdadc;
493         u8 bswAtten[AR9287_MAX_CHAINS];
494         u8 bswMargin[AR9287_MAX_CHAINS];
495         u8 swSettleHt40;
496         u8 version;
497         u8 db1;
498         u8 db2;
499         u8 ob_cck;
500         u8 ob_psk;
501         u8 ob_qam;
502         u8 ob_pal_off;
503         u8 futureModal[30];
504         struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
505 } __packed;
506
507 struct cal_data_per_freq {
508         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
509         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
510 } __packed;
511
512 struct cal_data_per_freq_4k {
513         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
514         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
515 } __packed;
516
517 struct cal_target_power_leg {
518         u8 bChannel;
519         u8 tPow2x[4];
520 } __packed;
521
522 struct cal_target_power_ht {
523         u8 bChannel;
524         u8 tPow2x[8];
525 } __packed;
526
527
528 #ifdef __BIG_ENDIAN_BITFIELD
529 struct cal_ctl_edges {
530         u8 bChannel;
531         u8 flag:2, tPower:6;
532 } __packed;
533 #else
534 struct cal_ctl_edges {
535         u8 bChannel;
536         u8 tPower:6, flag:2;
537 } __packed;
538 #endif
539
540 struct cal_data_op_loop_ar9287 {
541         u8 pwrPdg[2][5];
542         u8 vpdPdg[2][5];
543         u8 pcdac[2][5];
544         u8 empty[2][5];
545 } __packed;
546
547 struct cal_data_per_freq_ar9287 {
548         u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
549         u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
550 } __packed;
551
552 union cal_data_per_freq_ar9287_u {
553         struct cal_data_op_loop_ar9287 calDataOpen;
554         struct cal_data_per_freq_ar9287 calDataClose;
555 } __packed;
556
557 struct cal_ctl_data_ar9287 {
558         struct cal_ctl_edges
559         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
560 } __packed;
561
562 struct cal_ctl_data {
563         struct cal_ctl_edges
564         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
565 } __packed;
566
567 struct cal_ctl_data_4k {
568         struct cal_ctl_edges
569         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
570 } __packed;
571
572 struct ar5416_eeprom_def {
573         struct base_eep_header baseEepHeader;
574         u8 custData[64];
575         struct modal_eep_header modalHeader[2];
576         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
577         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
578         struct cal_data_per_freq
579          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
580         struct cal_data_per_freq
581          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
582         struct cal_target_power_leg
583          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
584         struct cal_target_power_ht
585          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
586         struct cal_target_power_ht
587          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
588         struct cal_target_power_leg
589          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
590         struct cal_target_power_leg
591          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
592         struct cal_target_power_ht
593          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
594         struct cal_target_power_ht
595          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
596         u8 ctlIndex[AR5416_NUM_CTLS];
597         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
598         u8 padding;
599 } __packed;
600
601 struct ar5416_eeprom_4k {
602         struct base_eep_header_4k baseEepHeader;
603         u8 custData[20];
604         struct modal_eep_4k_header modalHeader;
605         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
606         struct cal_data_per_freq_4k
607         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
608         struct cal_target_power_leg
609         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
610         struct cal_target_power_leg
611         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
612         struct cal_target_power_ht
613         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
614         struct cal_target_power_ht
615         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
616         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
617         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
618         u8 padding;
619 } __packed;
620
621 struct ar9287_eeprom {
622         struct base_eep_ar9287_header baseEepHeader;
623         u8 custData[AR9287_DATA_SZ];
624         struct modal_eep_ar9287_header modalHeader;
625         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
626         union cal_data_per_freq_ar9287_u
627         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
628         struct cal_target_power_leg
629         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
630         struct cal_target_power_leg
631         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
632         struct cal_target_power_ht
633         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
634         struct cal_target_power_ht
635         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
636         u8 ctlIndex[AR9287_NUM_CTLS];
637         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
638         u8 padding;
639 } __packed;
640
641 enum reg_ext_bitmap {
642         REG_EXT_FCC_MIDBAND = 0,
643         REG_EXT_JAPAN_MIDBAND = 1,
644         REG_EXT_FCC_DFS_HT40 = 2,
645         REG_EXT_JAPAN_NONDFS_HT40 = 3,
646         REG_EXT_JAPAN_DFS_HT40 = 4
647 };
648
649 struct ath9k_country_entry {
650         u16 countryCode;
651         u16 regDmnEnum;
652         u16 regDmn5G;
653         u16 regDmn2G;
654         u8 isMultidomain;
655         u8 iso[3];
656 };
657
658 enum ath9k_eep_map {
659         EEP_MAP_DEFAULT = 0x0,
660         EEP_MAP_4KBITS,
661         EEP_MAP_AR9287,
662         EEP_MAP_MAX
663 };
664
665 struct eeprom_ops {
666         int (*check_eeprom)(struct ath_hw *hw);
667         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
668         bool (*fill_eeprom)(struct ath_hw *hw);
669         int (*get_eeprom_ver)(struct ath_hw *hw);
670         int (*get_eeprom_rev)(struct ath_hw *hw);
671         u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
672         u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
673                                       struct ath9k_channel *chan);
674         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
675         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
676         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
677                            u16 cfgCtl, u8 twiceAntennaReduction,
678                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
679         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
680 };
681
682 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
683                                u32 shift, u32 val);
684 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
685                              int16_t targetLeft,
686                              int16_t targetRight);
687 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
688                                     u16 *indexL, u16 *indexR);
689 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
690 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
691                              u8 *pVpdList, u16 numIntercepts,
692                              u8 *pRetVpdList);
693 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
694                                        struct ath9k_channel *chan,
695                                        struct cal_target_power_leg *powInfo,
696                                        u16 numChannels,
697                                        struct cal_target_power_leg *pNewPower,
698                                        u16 numRates, bool isExtTarget);
699 void ath9k_hw_get_target_powers(struct ath_hw *ah,
700                                 struct ath9k_channel *chan,
701                                 struct cal_target_power_ht *powInfo,
702                                 u16 numChannels,
703                                 struct cal_target_power_ht *pNewPower,
704                                 u16 numRates, bool isHt40Target);
705 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
706                                 bool is2GHz, int num_band_edges);
707 int ath9k_hw_eeprom_init(struct ath_hw *ah);
708
709 #define ar5416_get_ntxchains(_txchainmask)                      \
710         (((_txchainmask >> 2) & 1) +                            \
711          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
712
713 extern const struct eeprom_ops eep_def_ops;
714 extern const struct eeprom_ops eep_4k_ops;
715 extern const struct eeprom_ops eep_AR9287_ops;
716
717 #endif /* EEPROM_H */