drivers/net/wireless/ath/ath9k/eeprom.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
  20                                       u32 reg, u32 mask,
  21                                       u32 shift, u32 val)
  22 {
  23         u32 regVal;
  24
  25         regVal = REG_READ(ah, reg) & ~mask;
  26         regVal |= (val << shift) & mask;
  27
  28         REG_WRITE(ah, reg, regVal);
  29
  30         if (ah->config.analog_shiftreg)
  31                 udelay(100);
  32
  33         return;
  34 }
  35
  36 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  37 {
  38
  39         if (fbin == AR5416_BCHAN_UNUSED)
  40                 return fbin;
  41
  42         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
  43 }
  44
  45 static inline int16_t ath9k_hw_interpolate(u16 target,
  46                                            u16 srcLeft, u16 srcRight,
  47                                            int16_t targetLeft,
  48                                            int16_t targetRight)
  49 {
  50         int16_t rv;
  51
  52         if (srcRight == srcLeft) {
  53                 rv = targetLeft;
  54         } else {
  55                 rv = (int16_t) (((target - srcLeft) * targetRight +
  56                                  (srcRight - target) * targetLeft) /
  57                                 (srcRight - srcLeft));
  58         }
  59         return rv;
  60 }
  61
  62 static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
  63                                                   u16 listSize, u16 *indexL,
  64                                                   u16 *indexR)
  65 {
  66         u16 i;
  67
  68         if (target <= pList[0]) {
  69                 *indexL = *indexR = 0;
  70                 return true;
  71         }
  72         if (target >= pList[listSize - 1]) {
  73                 *indexL = *indexR = (u16) (listSize - 1);
  74                 return true;
  75         }
  76
  77         for (i = 0; i < listSize - 1; i++) {
  78                 if (pList[i] == target) {
  79                         *indexL = *indexR = i;
  80                         return true;
  81                 }
  82                 if (target < pList[i + 1]) {
  83                         *indexL = i;
  84                         *indexR = (u16) (i + 1);
  85                         return false;
  86                 }
  87         }
  88         return false;
  89 }
  90
  91 static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
  92 {
  93         struct ath_softc *sc = ah->ah_sc;
  94
  95         return sc->bus_ops->eeprom_read(ah, off, data);
  96 }
  97
  98 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  99                                            u8 *pVpdList, u16 numIntercepts,
 100                                            u8 *pRetVpdList)
 101 {
 102         u16 i, k;
 103         u8 currPwr = pwrMin;
 104         u16 idxL = 0, idxR = 0;
 105
 106         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
 107                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
 108                                                numIntercepts, &(idxL),
 109                                                &(idxR));
 110                 if (idxR < 1)
 111                         idxR = 1;
 112                 if (idxL == numIntercepts - 1)
 113                         idxL = (u16) (numIntercepts - 2);
 114                 if (pPwrList[idxL] == pPwrList[idxR])
 115                         k = pVpdList[idxL];
 116                 else
 117                         k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
 118                                    (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
 119                                   (pPwrList[idxR] - pPwrList[idxL]));
 120                 pRetVpdList[i] = (u8) k;
 121                 currPwr += 2;
 122         }
 123
 124         return true;
 125 }
 126
 127 static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 128                                       struct ath9k_channel *chan,
 129                                       struct cal_target_power_leg *powInfo,
 130                                       u16 numChannels,
 131                                       struct cal_target_power_leg *pNewPower,
 132                                       u16 numRates, bool isExtTarget)
 133 {
 134         struct chan_centers centers;
 135         u16 clo, chi;
 136         int i;
 137         int matchIndex = -1, lowIndex = -1;
 138         u16 freq;
 139
 140         ath9k_hw_get_channel_centers(ah, chan, &centers);
 141         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
 142
 143         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
 144                                        IS_CHAN_2GHZ(chan))) {
 145                 matchIndex = 0;
 146         } else {
 147                 for (i = 0; (i < numChannels) &&
 148                              (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 149                         if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
 150                                                        IS_CHAN_2GHZ(chan))) {
 151                                 matchIndex = i;
 152                                 break;
 153                         } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
 154                                                       IS_CHAN_2GHZ(chan))) &&
 155                                    (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
 156                                                       IS_CHAN_2GHZ(chan)))) {
 157                                 lowIndex = i - 1;
 158                                 break;
 159                         }
 160                 }
 161                 if ((matchIndex == -1) && (lowIndex == -1))
 162                         matchIndex = i - 1;
 163         }
 164
 165         if (matchIndex != -1) {
 166                 *pNewPower = powInfo[matchIndex];
 167         } else {
 168                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
 169                                          IS_CHAN_2GHZ(chan));
 170                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
 171                                          IS_CHAN_2GHZ(chan));
 172
 173                 for (i = 0; i < numRates; i++) {
 174                         pNewPower->tPow2x[i] =
 175                                 (u8)ath9k_hw_interpolate(freq, clo, chi,
 176                                                 powInfo[lowIndex].tPow2x[i],
 177                                                 powInfo[lowIndex + 1].tPow2x[i]);
 178                 }
 179         }
 180 }
 181
 182 static void ath9k_get_txgain_index(struct ath_hw *ah,
 183                 struct ath9k_channel *chan,
 184                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
 185                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
 186 {
 187         u8 pcdac, i = 0;
 188         u16 idxL = 0, idxR = 0, numPiers;
 189         bool match;
 190         struct chan_centers centers;
 191
 192         ath9k_hw_get_channel_centers(ah, chan, &centers);
 193
 194         for (numPiers = 0; numPiers < availPiers; numPiers++)
 195                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
 196                         break;
 197
 198         match = ath9k_hw_get_lower_upper_index(
 199                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
 200                         calChans, numPiers, &idxL, &idxR);
 201         if (match) {
 202                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
 203                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
 204         } else {
 205                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
 206                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
 207                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
 208         }
 209
 210         while (pcdac > ah->originalGain[i] &&
 211                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
 212                 i++;
 213
 214         *pcdacIdx = i;
 215         return;
 216 }
 217
 218 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
 219                                 u32 initTxGain,
 220                                 int txPower,
 221                                 u8 *pPDADCValues)
 222 {
 223         u32 i;
 224         u32 offset;
 225
 226         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
 227                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
 228         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
 229                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
 230
 231         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
 232                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
 233
 234         offset = txPower;
 235         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
 236                 if (i < offset)
 237                         pPDADCValues[i] = 0x0;
 238                 else
 239                         pPDADCValues[i] = 0xFF;
 240 }
 241
 242
 243
 244
 245 static void ath9k_hw_get_target_powers(struct ath_hw *ah,
 246                                        struct ath9k_channel *chan,
 247                                        struct cal_target_power_ht *powInfo,
 248                                        u16 numChannels,
 249                                        struct cal_target_power_ht *pNewPower,
 250                                        u16 numRates, bool isHt40Target)
 251 {
 252         struct chan_centers centers;
 253         u16 clo, chi;
 254         int i;
 255         int matchIndex = -1, lowIndex = -1;
 256         u16 freq;
 257
 258         ath9k_hw_get_channel_centers(ah, chan, &centers);
 259         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
 260
 261         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
 262                 matchIndex = 0;
 263         } else {
 264                 for (i = 0; (i < numChannels) &&
 265                              (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 266                         if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
 267                                                        IS_CHAN_2GHZ(chan))) {
 268                                 matchIndex = i;
 269                                 break;
 270                         } else
 271                                 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
 272                                                        IS_CHAN_2GHZ(chan))) &&
 273                                     (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
 274                                                        IS_CHAN_2GHZ(chan)))) {
 275                                         lowIndex = i - 1;
 276                                         break;
 277                                 }
 278                 }
 279                 if ((matchIndex == -1) && (lowIndex == -1))
 280                         matchIndex = i - 1;
 281         }
 282
 283         if (matchIndex != -1) {
 284                 *pNewPower = powInfo[matchIndex];
 285         } else {
 286                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
 287                                          IS_CHAN_2GHZ(chan));
 288                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
 289                                          IS_CHAN_2GHZ(chan));
 290
 291                 for (i = 0; i < numRates; i++) {
 292                         pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
 293                                                 clo, chi,
 294                                                 powInfo[lowIndex].tPow2x[i],
 295                                                 powInfo[lowIndex + 1].tPow2x[i]);
 296                 }
 297         }
 298 }
 299
 300 static u16 ath9k_hw_get_max_edge_power(u16 freq,
 301                                        struct cal_ctl_edges *pRdEdgesPower,
 302                                        bool is2GHz, int num_band_edges)
 303 {
 304         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 305         int i;
 306
 307         for (i = 0; (i < num_band_edges) &&
 308                      (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 309                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
 310                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
 311                         break;
 312                 } else if ((i > 0) &&
 313                            (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
 314                                                       is2GHz))) {
 315                         if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
 316                                                is2GHz) < freq &&
 317                             pRdEdgesPower[i - 1].flag) {
 318                                 twiceMaxEdgePower =
 319                                         pRdEdgesPower[i - 1].tPower;
 320                         }
 321                         break;
 322                 }
 323         }
 324
 325         return twiceMaxEdgePower;
 326 }
 327
 328 /****************************************/
 329 /* EEPROM Operations for 4K sized cards */
 330 /****************************************/
 331
 332 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
 333 {
 334         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
 335 }
 336
 337 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
 338 {
 339         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
 340 }
 341
 342 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
 343 {
 344 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 345         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
 346         int addr, eep_start_loc = 0;
 347
 348         eep_start_loc = 64;
 349
 350         if (!ath9k_hw_use_flash(ah)) {
 351                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 352                         "Reading from EEPROM, not flash\n");
 353         }
 354
 355         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
 356                 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
 357                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 358                                "Unable to read eeprom region \n");
 359                         return false;
 360                 }
 361                 eep_data++;
 362         }
 363
 364         return true;
 365 #undef SIZE_EEPROM_4K
 366 }
 367
 368 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 369 {
 370 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 371         struct ar5416_eeprom_4k *eep =
 372                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
 373         u16 *eepdata, temp, magic, magic2;
 374         u32 sum = 0, el;
 375         bool need_swap = false;
 376         int i, addr;
 377
 378
 379         if (!ath9k_hw_use_flash(ah)) {
 380                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 381                                          &magic)) {
 382                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 383                                 "Reading Magic # failed\n");
 384                         return false;
 385                 }
 386
 387                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 388                         "Read Magic = 0x%04X\n", magic);
 389
 390                 if (magic != AR5416_EEPROM_MAGIC) {
 391                         magic2 = swab16(magic);
 392
 393                         if (magic2 == AR5416_EEPROM_MAGIC) {
 394                                 need_swap = true;
 395                                 eepdata = (u16 *) (&ah->eeprom);
 396
 397                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 398                                         temp = swab16(*eepdata);
 399                                         *eepdata = temp;
 400                                         eepdata++;
 401                                 }
 402                         } else {
 403                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 404                                         "Invalid EEPROM Magic. "
 405                                         "endianness mismatch.\n");
 406                                 return -EINVAL;
 407                         }
 408                 }
 409         }
 410
 411         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 412                 need_swap ? "True" : "False");
 413
 414         if (need_swap)
 415                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 416         else
 417                 el = ah->eeprom.map4k.baseEepHeader.length;
 418
 419         if (el > sizeof(struct ar5416_eeprom_4k))
 420                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 421         else
 422                 el = el / sizeof(u16);
 423
 424         eepdata = (u16 *)(&ah->eeprom);
 425
 426         for (i = 0; i < el; i++)
 427                 sum ^= *eepdata++;
 428
 429         if (need_swap) {
 430                 u32 integer;
 431                 u16 word;
 432
 433                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 434                         "EEPROM Endianness is not native.. Changing\n");
 435
 436                 word = swab16(eep->baseEepHeader.length);
 437                 eep->baseEepHeader.length = word;
 438
 439                 word = swab16(eep->baseEepHeader.checksum);
 440                 eep->baseEepHeader.checksum = word;
 441
 442                 word = swab16(eep->baseEepHeader.version);
 443                 eep->baseEepHeader.version = word;
 444
 445                 word = swab16(eep->baseEepHeader.regDmn[0]);
 446                 eep->baseEepHeader.regDmn[0] = word;
 447
 448                 word = swab16(eep->baseEepHeader.regDmn[1]);
 449                 eep->baseEepHeader.regDmn[1] = word;
 450
 451                 word = swab16(eep->baseEepHeader.rfSilent);
 452                 eep->baseEepHeader.rfSilent = word;
 453
 454                 word = swab16(eep->baseEepHeader.blueToothOptions);
 455                 eep->baseEepHeader.blueToothOptions = word;
 456
 457                 word = swab16(eep->baseEepHeader.deviceCap);
 458                 eep->baseEepHeader.deviceCap = word;
 459
 460                 integer = swab32(eep->modalHeader.antCtrlCommon);
 461                 eep->modalHeader.antCtrlCommon = integer;
 462
 463                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 464                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 465                         eep->modalHeader.antCtrlChain[i] = integer;
 466                 }
 467
 468                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 469                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 470                         eep->modalHeader.spurChans[i].spurChan = word;
 471                 }
 472         }
 473
 474         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 475             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 476                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 477                         "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 478                         sum, ah->eep_ops->get_eeprom_ver(ah));
 479                 return -EINVAL;
 480         }
 481
 482         return 0;
 483 #undef EEPROM_4K_SIZE
 484 }
 485
 486 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 487                                   enum eeprom_param param)
 488 {
 489         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 490         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 491         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 492
 493         switch (param) {
 494         case EEP_NFTHRESH_2:
 495                 return pModal->noiseFloorThreshCh[0];
 496         case AR_EEPROM_MAC(0):
 497                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 498         case AR_EEPROM_MAC(1):
 499                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 500         case AR_EEPROM_MAC(2):
 501                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 502         case EEP_REG_0:
 503                 return pBase->regDmn[0];
 504         case EEP_REG_1:
 505                 return pBase->regDmn[1];
 506         case EEP_OP_CAP:
 507                 return pBase->deviceCap;
 508         case EEP_OP_MODE:
 509                 return pBase->opCapFlags;
 510         case EEP_RF_SILENT:
 511                 return pBase->rfSilent;
 512         case EEP_OB_2:
 513                 return pModal->ob_01;
 514         case EEP_DB_2:
 515                 return pModal->db1_01;
 516         case EEP_MINOR_REV:
 517                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
 518         case EEP_TX_MASK:
 519                 return pBase->txMask;
 520         case EEP_RX_MASK:
 521                 return pBase->rxMask;
 522         case EEP_FRAC_N_5G:
 523                 return 0;
 524         default:
 525                 return 0;
 526         }
 527 }
 528
 529 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
 530                                 struct ath9k_channel *chan,
 531                                 struct cal_data_per_freq_4k *pRawDataSet,
 532                                 u8 *bChans, u16 availPiers,
 533                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
 534                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 535                                 u16 numXpdGains)
 536 {
 537 #define TMP_VAL_VPD_TABLE \
 538         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
 539         int i, j, k;
 540         int16_t ss;
 541         u16 idxL = 0, idxR = 0, numPiers;
 542         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
 543                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 544         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
 545                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 546         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
 547                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 548
 549         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 550         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 551         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 552         int16_t vpdStep;
 553         int16_t tmpVal;
 554         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 555         bool match;
 556         int16_t minDelta = 0;
 557         struct chan_centers centers;
 558 #define PD_GAIN_BOUNDARY_DEFAULT 58;
 559
 560         ath9k_hw_get_channel_centers(ah, chan, &centers);
 561
 562         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 563                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 564                         break;
 565         }
 566
 567         match = ath9k_hw_get_lower_upper_index(
 568                                         (u8)FREQ2FBIN(centers.synth_center,
 569                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
 570                                         &idxL, &idxR);
 571
 572         if (match) {
 573                 for (i = 0; i < numXpdGains; i++) {
 574                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 575                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 576                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 577                                         pRawDataSet[idxL].pwrPdg[i],
 578                                         pRawDataSet[idxL].vpdPdg[i],
 579                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
 580                                         vpdTableI[i]);
 581                 }
 582         } else {
 583                 for (i = 0; i < numXpdGains; i++) {
 584                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 585                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 586                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 587                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 588
 589                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 590
 591                         maxPwrT4[i] =
 592                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
 593                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
 594
 595
 596                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 597                                                 pPwrL, pVpdL,
 598                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 599                                                 vpdTableL[i]);
 600                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 601                                                 pPwrR, pVpdR,
 602                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 603                                                 vpdTableR[i]);
 604
 605                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 606                                 vpdTableI[i][j] =
 607                                         (u8)(ath9k_hw_interpolate((u16)
 608                                              FREQ2FBIN(centers.
 609                                                        synth_center,
 610                                                        IS_CHAN_2GHZ
 611                                                        (chan)),
 612                                              bChans[idxL], bChans[idxR],
 613                                              vpdTableL[i][j], vpdTableR[i][j]));
 614                         }
 615                 }
 616         }
 617
 618         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
 619
 620         k = 0;
 621
 622         for (i = 0; i < numXpdGains; i++) {
 623                 if (i == (numXpdGains - 1))
 624                         pPdGainBoundaries[i] =
 625                                 (u16)(maxPwrT4[i] / 2);
 626                 else
 627                         pPdGainBoundaries[i] =
 628                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 629
 630                 pPdGainBoundaries[i] =
 631                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 632
 633                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 634                         minDelta = pPdGainBoundaries[0] - 23;
 635                         pPdGainBoundaries[0] = 23;
 636                 } else {
 637                         minDelta = 0;
 638                 }
 639
 640                 if (i == 0) {
 641                         if (AR_SREV_9280_10_OR_LATER(ah))
 642                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 643                         else
 644                                 ss = 0;
 645                 } else {
 646                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 647                                         (minPwrT4[i] / 2)) -
 648                                        tPdGainOverlap + 1 + minDelta);
 649                 }
 650                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 651                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 652
 653                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 654                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 655                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 656                         ss++;
 657                 }
 658
 659                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 660                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 661                                 (minPwrT4[i] / 2));
 662                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 663                         tgtIndex : sizeCurrVpdTable;
 664
 665                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
 666                         pPDADCValues[k++] = vpdTableI[i][ss++];
 667
 668                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 669                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 670                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 671
 672                 if (tgtIndex >= maxIndex) {
 673                         while ((ss <= tgtIndex) &&
 674                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 675                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
 676                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 677                                                          255 : tmpVal);
 678                                 ss++;
 679                         }
 680                 }
 681         }
 682
 683         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
 684                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
 685                 i++;
 686         }
 687
 688         while (k < AR5416_NUM_PDADC_VALUES) {
 689                 pPDADCValues[k] = pPDADCValues[k - 1];
 690                 k++;
 691         }
 692
 693         return;
 694 #undef TMP_VAL_VPD_TABLE
 695 }
 696
 697 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 698                                   struct ath9k_channel *chan,
 699                                   int16_t *pTxPowerIndexOffset)
 700 {
 701         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 702         struct cal_data_per_freq_4k *pRawDataset;
 703         u8 *pCalBChans = NULL;
 704         u16 pdGainOverlap_t2;
 705         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 706         u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
 707         u16 numPiers, i, j;
 708         int16_t tMinCalPower;
 709         u16 numXpdGain, xpdMask;
 710         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 711         u32 reg32, regOffset, regChainOffset;
 712
 713         xpdMask = pEepData->modalHeader.xpdGain;
 714
 715         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 716             AR5416_EEP_MINOR_VER_2) {
 717                 pdGainOverlap_t2 =
 718                         pEepData->modalHeader.pdGainOverlap;
 719         } else {
 720                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 721                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 722         }
 723
 724         pCalBChans = pEepData->calFreqPier2G;
 725         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 726
 727         numXpdGain = 0;
 728
 729         for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
 730                 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
 731                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 732                                 break;
 733                         xpdGainValues[numXpdGain] =
 734                                 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
 735                         numXpdGain++;
 736                 }
 737         }
 738
 739         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 740                       (numXpdGain - 1) & 0x3);
 741         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 742                       xpdGainValues[0]);
 743         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 744                       xpdGainValues[1]);
 745         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 746
 747         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 748                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 749                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 750                     (i != 0)) {
 751                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 752                 } else
 753                         regChainOffset = i * 0x1000;
 754
 755                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 756                         pRawDataset = pEepData->calPierData2G[i];
 757
 758                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
 759                                             pRawDataset, pCalBChans,
 760                                             numPiers, pdGainOverlap_t2,
 761                                             &tMinCalPower, gainBoundaries,
 762                                             pdadcValues, numXpdGain);
 763
 764                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 765                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 766                                           SM(pdGainOverlap_t2,
 767                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 768                                           | SM(gainBoundaries[0],
 769                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 770                                           | SM(gainBoundaries[1],
 771                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 772                                           | SM(gainBoundaries[2],
 773                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 774                                           | SM(gainBoundaries[3],
 775                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 776                         }
 777
 778                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 779                         for (j = 0; j < 32; j++) {
 780                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 781                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 782                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 783                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 784                                 REG_WRITE(ah, regOffset, reg32);
 785
 786                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 787                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 788                                         i, regChainOffset, regOffset,
 789                                         reg32);
 790                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 791                                         "PDADC: Chain %d | "
 792                                         "PDADC %3d Value %3d | "
 793                                         "PDADC %3d Value %3d | "
 794                                         "PDADC %3d Value %3d | "
 795                                         "PDADC %3d Value %3d |\n",
 796                                         i, 4 * j, pdadcValues[4 * j],
 797                                         4 * j + 1, pdadcValues[4 * j + 1],
 798                                         4 * j + 2, pdadcValues[4 * j + 2],
 799                                         4 * j + 3,
 800                                         pdadcValues[4 * j + 3]);
 801
 802                                 regOffset += 4;
 803                         }
 804                 }
 805         }
 806
 807         *pTxPowerIndexOffset = 0;
 808 }
 809
 810 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 811                                                  struct ath9k_channel *chan,
 812                                                  int16_t *ratesArray,
 813                                                  u16 cfgCtl,
 814                                                  u16 AntennaReduction,
 815                                                  u16 twiceMaxRegulatoryPower,
 816                                                  u16 powerLimit)
 817 {
 818         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 819         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 820         static const u16 tpScaleReductionTable[5] =
 821                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 822
 823         int i;
 824         int16_t twiceLargestAntenna;
 825         struct cal_ctl_data_4k *rep;
 826         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 827                 0, { 0, 0, 0, 0}
 828         };
 829         struct cal_target_power_leg targetPowerOfdmExt = {
 830                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 831                 0, { 0, 0, 0, 0 }
 832         };
 833         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 834                 0, {0, 0, 0, 0}
 835         };
 836         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 837         u16 ctlModesFor11g[] =
 838                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 839                   CTL_2GHT40
 840                 };
 841         u16 numCtlModes, *pCtlMode, ctlMode, freq;
 842         struct chan_centers centers;
 843         int tx_chainmask;
 844         u16 twiceMinEdgePower;
 845
 846         tx_chainmask = ah->txchainmask;
 847
 848         ath9k_hw_get_channel_centers(ah, chan, &centers);
 849
 850         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 851
 852         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 853                                            twiceLargestAntenna, 0);
 854
 855         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 856
 857         if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
 858                 maxRegAllowedPower -=
 859                         (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
 860         }
 861
 862         scaledPower = min(powerLimit, maxRegAllowedPower);
 863         scaledPower = max((u16)0, scaledPower);
 864
 865         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 866         pCtlMode = ctlModesFor11g;
 867
 868         ath9k_hw_get_legacy_target_powers(ah, chan,
 869                         pEepData->calTargetPowerCck,
 870                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 871                         &targetPowerCck, 4, false);
 872         ath9k_hw_get_legacy_target_powers(ah, chan,
 873                         pEepData->calTargetPower2G,
 874                         AR5416_NUM_2G_20_TARGET_POWERS,
 875                         &targetPowerOfdm, 4, false);
 876         ath9k_hw_get_target_powers(ah, chan,
 877                         pEepData->calTargetPower2GHT20,
 878                         AR5416_NUM_2G_20_TARGET_POWERS,
 879                         &targetPowerHt20, 8, false);
 880
 881         if (IS_CHAN_HT40(chan)) {
 882                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 883                 ath9k_hw_get_target_powers(ah, chan,
 884                                 pEepData->calTargetPower2GHT40,
 885                                 AR5416_NUM_2G_40_TARGET_POWERS,
 886                                 &targetPowerHt40, 8, true);
 887                 ath9k_hw_get_legacy_target_powers(ah, chan,
 888                                 pEepData->calTargetPowerCck,
 889                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 890                                 &targetPowerCckExt, 4, true);
 891                 ath9k_hw_get_legacy_target_powers(ah, chan,
 892                                 pEepData->calTargetPower2G,
 893                                 AR5416_NUM_2G_20_TARGET_POWERS,
 894                                 &targetPowerOfdmExt, 4, true);
 895         }
 896
 897         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 898                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 899                         (pCtlMode[ctlMode] == CTL_2GHT40);
 900                 if (isHt40CtlMode)
 901                         freq = centers.synth_center;
 902                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 903                         freq = centers.ext_center;
 904                 else
 905                         freq = centers.ctl_center;
 906
 907                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 908                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 909                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 910
 911                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 912                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
 913                         "EXT_ADDITIVE %d\n",
 914                         ctlMode, numCtlModes, isHt40CtlMode,
 915                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
 916
 917                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 918                                 pEepData->ctlIndex[i]; i++) {
 919                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 920                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
 921                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
 922                                 "chan %d\n",
 923                                 i, cfgCtl, pCtlMode[ctlMode],
 924                                 pEepData->ctlIndex[i], chan->channel);
 925
 926                         if ((((cfgCtl & ~CTL_MODE_M) |
 927                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 928                              pEepData->ctlIndex[i]) ||
 929                             (((cfgCtl & ~CTL_MODE_M) |
 930                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 931                              ((pEepData->ctlIndex[i] & CTL_MODE_M) |
 932                               SD_NO_CTL))) {
 933                                 rep = &(pEepData->ctlData[i]);
 934
 935                                 twiceMinEdgePower =
 936                                         ath9k_hw_get_max_edge_power(freq,
 937                                 rep->ctlEdges[ar5416_get_ntxchains
 938                                                 (tx_chainmask) - 1],
 939                                 IS_CHAN_2GHZ(chan),
 940                                 AR5416_EEP4K_NUM_BAND_EDGES);
 941
 942                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 943                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
 944                                         "2xMinEdge %d chainmask %d chains %d\n",
 945                                         i, freq, IS_CHAN_2GHZ(chan),
 946                                         twiceMinEdgePower, tx_chainmask,
 947                                         ar5416_get_ntxchains
 948                                         (tx_chainmask));
 949                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 950                                         twiceMaxEdgePower =
 951                                                 min(twiceMaxEdgePower,
 952                                                     twiceMinEdgePower);
 953                                 } else {
 954                                         twiceMaxEdgePower = twiceMinEdgePower;
 955                                         break;
 956                                 }
 957                         }
 958                 }
 959
 960                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 961
 962                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 963                         "    SEL-Min ctlMode %d pCtlMode %d "
 964                         "2xMaxEdge %d sP %d minCtlPwr %d\n",
 965                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
 966                         scaledPower, minCtlPower);
 967
 968                 switch (pCtlMode[ctlMode]) {
 969                 case CTL_11B:
 970                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
 971                                         i++) {
 972                                 targetPowerCck.tPow2x[i] =
 973                                         min((u16)targetPowerCck.tPow2x[i],
 974                                             minCtlPower);
 975                         }
 976                         break;
 977                 case CTL_11G:
 978                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
 979                                         i++) {
 980                                 targetPowerOfdm.tPow2x[i] =
 981                                         min((u16)targetPowerOfdm.tPow2x[i],
 982                                             minCtlPower);
 983                         }
 984                         break;
 985                 case CTL_2GHT20:
 986                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
 987                                         i++) {
 988                                 targetPowerHt20.tPow2x[i] =
 989                                         min((u16)targetPowerHt20.tPow2x[i],
 990                                             minCtlPower);
 991                         }
 992                         break;
 993                 case CTL_11B_EXT:
 994                         targetPowerCckExt.tPow2x[0] = min((u16)
 995                                         targetPowerCckExt.tPow2x[0],
 996                                         minCtlPower);
 997                         break;
 998                 case CTL_11G_EXT:
 999                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1000                                         targetPowerOfdmExt.tPow2x[0],
1001                                         minCtlPower);
1002                         break;
1003                 case CTL_2GHT40:
1004                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1005                                         i++) {
1006                                 targetPowerHt40.tPow2x[i] =
1007                                         min((u16)targetPowerHt40.tPow2x[i],
1008                                             minCtlPower);
1009                         }
1010                         break;
1011                 default:
1012                         break;
1013                 }
1014         }
1015
1016         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1017                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1018                 targetPowerOfdm.tPow2x[0];
1019         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1020         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1021         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1022         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1023
1024         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1025                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1026
1027         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1028         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1029         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1030         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1031
1032         if (IS_CHAN_HT40(chan)) {
1033                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1034                         ratesArray[rateHt40_0 + i] =
1035                                 targetPowerHt40.tPow2x[i];
1036                 }
1037                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1038                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1039                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1040                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1041         }
1042 }
1043
1044 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1045                                    struct ath9k_channel *chan,
1046                                    u16 cfgCtl,
1047                                    u8 twiceAntennaReduction,
1048                                    u8 twiceMaxRegulatoryPower,
1049                                    u8 powerLimit)
1050 {
1051         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1052         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1053         int16_t ratesArray[Ar5416RateSize];
1054         int16_t txPowerIndexOffset = 0;
1055         u8 ht40PowerIncForPdadc = 2;
1056         int i;
1057
1058         memset(ratesArray, 0, sizeof(ratesArray));
1059
1060         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1061             AR5416_EEP_MINOR_VER_2) {
1062                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1063         }
1064
1065         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1066                                                &ratesArray[0], cfgCtl,
1067                                                twiceAntennaReduction,
1068                                                twiceMaxRegulatoryPower,
1069                                                powerLimit);
1070
1071         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
1072
1073         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1074                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1075                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1076                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1077         }
1078
1079         if (AR_SREV_9280_10_OR_LATER(ah)) {
1080                 for (i = 0; i < Ar5416RateSize; i++)
1081                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1082         }
1083
1084         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1085                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1086                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1087                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1088                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1089         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1090                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1091                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1092                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1093                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1094
1095         if (IS_CHAN_2GHZ(chan)) {
1096                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1097                           ATH9K_POW_SM(ratesArray[rate2s], 24)
1098                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
1099                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
1100                           | ATH9K_POW_SM(ratesArray[rate1l], 0));
1101                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1102                           ATH9K_POW_SM(ratesArray[rate11s], 24)
1103                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
1104                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1105                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1106         }
1107
1108         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1109                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1110                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1111                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1112                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1113         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1114                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1115                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1116                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1117                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1118
1119         if (IS_CHAN_HT40(chan)) {
1120                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1121                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1122                                        ht40PowerIncForPdadc, 24)
1123                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1124                                          ht40PowerIncForPdadc, 16)
1125                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1126                                          ht40PowerIncForPdadc, 8)
1127                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1128                                          ht40PowerIncForPdadc, 0));
1129                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1130                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1131                                        ht40PowerIncForPdadc, 24)
1132                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1133                                          ht40PowerIncForPdadc, 16)
1134                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1135                                          ht40PowerIncForPdadc, 8)
1136                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1137                                          ht40PowerIncForPdadc, 0));
1138
1139                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1140                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1141                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1142                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1143                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1144         }
1145
1146         i = rate6mb;
1147
1148         if (IS_CHAN_HT40(chan))
1149                 i = rateHt40_0;
1150         else if (IS_CHAN_HT20(chan))
1151                 i = rateHt20_0;
1152
1153         if (AR_SREV_9280_10_OR_LATER(ah))
1154                 ah->regulatory.max_power_level =
1155                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1156         else
1157                 ah->regulatory.max_power_level = ratesArray[i];
1158
1159 }
1160
1161 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1162                                   struct ath9k_channel *chan)
1163 {
1164         struct modal_eep_4k_header *pModal;
1165         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1166         u8 biaslevel;
1167
1168         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1169                 return;
1170
1171         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1172                 return;
1173
1174         pModal = &eep->modalHeader;
1175
1176         if (pModal->xpaBiasLvl != 0xff) {
1177                 biaslevel = pModal->xpaBiasLvl;
1178                 INI_RA(&ah->iniAddac, 7, 1) =
1179                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1180         }
1181 }
1182
1183 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
1184                                  struct modal_eep_4k_header *pModal,
1185                                  struct ar5416_eeprom_4k *eep,
1186                                  u8 txRxAttenLocal, int regChainOffset)
1187 {
1188         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1189                   pModal->antCtrlChain[0]);
1190
1191         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1192                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1193                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1194                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1195                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1196                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1197
1198         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1199             AR5416_EEP_MINOR_VER_3) {
1200                 txRxAttenLocal = pModal->txRxAttenCh[0];
1201
1202                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1203                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1204                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1205                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1206                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1207                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1208                               pModal->xatten2Margin[0]);
1209                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1210                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1211
1212                 /* Set the block 1 value to block 0 value */
1213                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1214                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1215                               pModal->bswMargin[0]);
1216                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1217                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1218                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1219                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1220                               pModal->xatten2Margin[0]);
1221                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1222                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1223                               pModal->xatten2Db[0]);
1224         }
1225
1226         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1227                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1228         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1229                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1230
1231         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
1232                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1233         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
1234                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1235
1236         if (AR_SREV_9285_11(ah))
1237                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1238 }
1239
1240 /*
1241  * Read EEPROM header info and program the device for correct operation
1242  * given the channel value.
1243  */
1244 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1245                                          struct ath9k_channel *chan)
1246 {
1247         struct modal_eep_4k_header *pModal;
1248         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1249         u8 txRxAttenLocal;
1250         u8 ob[5], db1[5], db2[5];
1251         u8 ant_div_control1, ant_div_control2;
1252         u32 regVal;
1253
1254         pModal = &eep->modalHeader;
1255         txRxAttenLocal = 23;
1256
1257         REG_WRITE(ah, AR_PHY_SWITCH_COM,
1258                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1259
1260         /* Single chain for 4K EEPROM*/
1261         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
1262
1263         /* Initialize Ant Diversity settings from EEPROM */
1264         if (pModal->version >= 3) {
1265                 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1266                 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1267                 regVal = REG_READ(ah, 0x99ac);
1268                 regVal &= (~(0x7f000000));
1269                 regVal |= ((ant_div_control1 & 0x1) << 24);
1270                 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1271                 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1272                 regVal |= ((ant_div_control2 & 0x3) << 25);
1273                 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1274                 REG_WRITE(ah, 0x99ac, regVal);
1275                 regVal = REG_READ(ah, 0x99ac);
1276                 regVal = REG_READ(ah, 0xa208);
1277                 regVal &= (~(0x1 << 13));
1278                 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1279                 REG_WRITE(ah, 0xa208, regVal);
1280                 regVal = REG_READ(ah, 0xa208);
1281         }
1282
1283         if (pModal->version >= 2) {
1284                 ob[0] = (pModal->ob_01 & 0xf);
1285                 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1286                 ob[2] = (pModal->ob_234 & 0xf);
1287                 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1288                 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1289
1290                 db1[0] = (pModal->db1_01 & 0xf);
1291                 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1292                 db1[2] = (pModal->db1_234 & 0xf);
1293                 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1294                 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1295
1296                 db2[0] = (pModal->db2_01 & 0xf);
1297                 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1298                 db2[2] = (pModal->db2_234 & 0xf);
1299                 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1300                 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1301
1302         } else if (pModal->version == 1) {
1303                 ob[0] = (pModal->ob_01 & 0xf);
1304                 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1305                 db1[0] = (pModal->db1_01 & 0xf);
1306                 db1[1] = db1[2] = db1[3] =
1307                         db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1308                 db2[0] = (pModal->db2_01 & 0xf);
1309                 db2[1] = db2[2] = db2[3] =
1310                         db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1311         } else {
1312                 int i;
1313                 for (i = 0; i < 5; i++) {
1314                         ob[i] = pModal->ob_01;
1315                         db1[i] = pModal->db1_01;
1316                         db2[i] = pModal->db1_01;
1317                 }
1318         }
1319
1320         if (AR_SREV_9271(ah)) {
1321                 ath9k_hw_analog_shift_rmw(ah,
1322                                           AR9285_AN_RF2G3,
1323                                           AR9271_AN_RF2G3_OB_cck,
1324                                           AR9271_AN_RF2G3_OB_cck_S,
1325                                           ob[0]);
1326                 ath9k_hw_analog_shift_rmw(ah,
1327                                           AR9285_AN_RF2G3,
1328                                           AR9271_AN_RF2G3_OB_psk,
1329                                           AR9271_AN_RF2G3_OB_psk_S,
1330                                           ob[1]);
1331                 ath9k_hw_analog_shift_rmw(ah,
1332                                           AR9285_AN_RF2G3,
1333                                           AR9271_AN_RF2G3_OB_qam,
1334                                           AR9271_AN_RF2G3_OB_qam_S,
1335                                           ob[2]);
1336                 ath9k_hw_analog_shift_rmw(ah,
1337                                           AR9285_AN_RF2G3,
1338                                           AR9271_AN_RF2G3_DB_1,
1339                                           AR9271_AN_RF2G3_DB_1_S,
1340                                           db1[0]);
1341                 ath9k_hw_analog_shift_rmw(ah,
1342                                           AR9285_AN_RF2G4,
1343                                           AR9271_AN_RF2G4_DB_2,
1344                                           AR9271_AN_RF2G4_DB_2_S,
1345                                           db2[0]);
1346         } else {
1347                 ath9k_hw_analog_shift_rmw(ah,
1348                                           AR9285_AN_RF2G3,
1349                                           AR9285_AN_RF2G3_OB_0,
1350                                           AR9285_AN_RF2G3_OB_0_S,
1351                                           ob[0]);
1352                 ath9k_hw_analog_shift_rmw(ah,
1353                                           AR9285_AN_RF2G3,
1354                                           AR9285_AN_RF2G3_OB_1,
1355                                           AR9285_AN_RF2G3_OB_1_S,
1356                                           ob[1]);
1357                 ath9k_hw_analog_shift_rmw(ah,
1358                                           AR9285_AN_RF2G3,
1359                                           AR9285_AN_RF2G3_OB_2,
1360                                           AR9285_AN_RF2G3_OB_2_S,
1361                                           ob[2]);
1362                 ath9k_hw_analog_shift_rmw(ah,
1363                                           AR9285_AN_RF2G3,
1364                                           AR9285_AN_RF2G3_OB_3,
1365                                           AR9285_AN_RF2G3_OB_3_S,
1366                                           ob[3]);
1367                 ath9k_hw_analog_shift_rmw(ah,
1368                                           AR9285_AN_RF2G3,
1369                                           AR9285_AN_RF2G3_OB_4,
1370                                           AR9285_AN_RF2G3_OB_4_S,
1371                                           ob[4]);
1372
1373                 ath9k_hw_analog_shift_rmw(ah,
1374                                           AR9285_AN_RF2G3,
1375                                           AR9285_AN_RF2G3_DB1_0,
1376                                           AR9285_AN_RF2G3_DB1_0_S,
1377                                           db1[0]);
1378                 ath9k_hw_analog_shift_rmw(ah,
1379                                           AR9285_AN_RF2G3,
1380                                           AR9285_AN_RF2G3_DB1_1,
1381                                           AR9285_AN_RF2G3_DB1_1_S,
1382                                           db1[1]);
1383                 ath9k_hw_analog_shift_rmw(ah,
1384                                           AR9285_AN_RF2G3,
1385                                           AR9285_AN_RF2G3_DB1_2,
1386                                           AR9285_AN_RF2G3_DB1_2_S,
1387                                           db1[2]);
1388                 ath9k_hw_analog_shift_rmw(ah,
1389                                           AR9285_AN_RF2G4,
1390                                           AR9285_AN_RF2G4_DB1_3,
1391                                           AR9285_AN_RF2G4_DB1_3_S,
1392                                           db1[3]);
1393                 ath9k_hw_analog_shift_rmw(ah,
1394                                           AR9285_AN_RF2G4,
1395                                           AR9285_AN_RF2G4_DB1_4,
1396                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1397
1398                 ath9k_hw_analog_shift_rmw(ah,
1399                                           AR9285_AN_RF2G4,
1400                                           AR9285_AN_RF2G4_DB2_0,
1401                                           AR9285_AN_RF2G4_DB2_0_S,
1402                                           db2[0]);
1403                 ath9k_hw_analog_shift_rmw(ah,
1404                                           AR9285_AN_RF2G4,
1405                                           AR9285_AN_RF2G4_DB2_1,
1406                                           AR9285_AN_RF2G4_DB2_1_S,
1407                                           db2[1]);
1408                 ath9k_hw_analog_shift_rmw(ah,
1409                                           AR9285_AN_RF2G4,
1410                                           AR9285_AN_RF2G4_DB2_2,
1411                                           AR9285_AN_RF2G4_DB2_2_S,
1412                                           db2[2]);
1413                 ath9k_hw_analog_shift_rmw(ah,
1414                                           AR9285_AN_RF2G4,
1415                                           AR9285_AN_RF2G4_DB2_3,
1416                                           AR9285_AN_RF2G4_DB2_3_S,
1417                                           db2[3]);
1418                 ath9k_hw_analog_shift_rmw(ah,
1419                                           AR9285_AN_RF2G4,
1420                                           AR9285_AN_RF2G4_DB2_4,
1421                                           AR9285_AN_RF2G4_DB2_4_S,
1422                                           db2[4]);
1423         }
1424
1425
1426         if (AR_SREV_9285_11(ah))
1427                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1428
1429         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1430                       pModal->switchSettling);
1431         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1432                       pModal->adcDesiredSize);
1433
1434         REG_WRITE(ah, AR_PHY_RF_CTL4,
1435                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1436                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1437                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1438                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1439
1440         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1441                       pModal->txEndToRxOn);
1442         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1443                       pModal->thresh62);
1444         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1445                       pModal->thresh62);
1446
1447         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1448                                                 AR5416_EEP_MINOR_VER_2) {
1449                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1450                               pModal->txFrameToDataStart);
1451                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1452                               pModal->txFrameToPaOn);
1453         }
1454
1455         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1456                                                 AR5416_EEP_MINOR_VER_3) {
1457                 if (IS_CHAN_HT40(chan))
1458                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1459                                       AR_PHY_SETTLING_SWITCH,
1460                                       pModal->swSettleHt40);
1461         }
1462 }
1463
1464 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1465                                               struct ath9k_channel *chan)
1466 {
1467         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1468         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1469
1470         return pModal->antCtrlCommon & 0xFFFF;
1471 }
1472
1473 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1474                                          enum ieee80211_band freq_band)
1475 {
1476         return 1;
1477 }
1478
1479 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1480 {
1481 #define EEP_MAP4K_SPURCHAN \
1482         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1483
1484         u16 spur_val = AR_NO_SPUR;
1485
1486         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1487                 "Getting spur idx %d is2Ghz. %d val %x\n",
1488                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1489
1490         switch (ah->config.spurmode) {
1491         case SPUR_DISABLE:
1492                 break;
1493         case SPUR_ENABLE_IOCTL:
1494                 spur_val = ah->config.spurchans[i][is2GHz];
1495                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1496                         "Getting spur val from new loc. %d\n", spur_val);
1497                 break;
1498         case SPUR_ENABLE_EEPROM:
1499                 spur_val = EEP_MAP4K_SPURCHAN;
1500                 break;
1501         }
1502
1503         return spur_val;
1504
1505 #undef EEP_MAP4K_SPURCHAN
1506 }
1507
1508 static struct eeprom_ops eep_4k_ops = {
1509         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1510         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1511         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1512         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1513         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1514         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1515         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1516         .set_board_values       = ath9k_hw_4k_set_board_values,
1517         .set_addac              = ath9k_hw_4k_set_addac,
1518         .set_txpower            = ath9k_hw_4k_set_txpower,
1519         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1520 };
1521
1522 /************************************************/
1523 /* EEPROM Operations for non-4K (Default) cards */
1524 /************************************************/
1525
1526 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1527 {
1528         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1529 }
1530
1531 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1532 {
1533         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1534 }
1535
1536 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1537 {
1538 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1539         u16 *eep_data = (u16 *)&ah->eeprom.def;
1540         int addr, ar5416_eep_start_loc = 0x100;
1541
1542         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1543                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1544                                          eep_data)) {
1545                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1546                                 "Unable to read eeprom region\n");
1547                         return false;
1548                 }
1549                 eep_data++;
1550         }
1551         return true;
1552 #undef SIZE_EEPROM_DEF
1553 }
1554
1555 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1556 {
1557         struct ar5416_eeprom_def *eep =
1558                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1559         u16 *eepdata, temp, magic, magic2;
1560         u32 sum = 0, el;
1561         bool need_swap = false;
1562         int i, addr, size;
1563
1564         if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
1565                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
1566                 return false;
1567         }
1568
1569         if (!ath9k_hw_use_flash(ah)) {
1570                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1571                         "Read Magic = 0x%04X\n", magic);
1572
1573                 if (magic != AR5416_EEPROM_MAGIC) {
1574                         magic2 = swab16(magic);
1575
1576                         if (magic2 == AR5416_EEPROM_MAGIC) {
1577                                 size = sizeof(struct ar5416_eeprom_def);
1578                                 need_swap = true;
1579                                 eepdata = (u16 *) (&ah->eeprom);
1580
1581                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
1582                                         temp = swab16(*eepdata);
1583                                         *eepdata = temp;
1584                                         eepdata++;
1585                                 }
1586                         } else {
1587                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1588                                         "Invalid EEPROM Magic. "
1589                                         "Endianness mismatch.\n");
1590                                 return -EINVAL;
1591                         }
1592                 }
1593         }
1594
1595         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
1596                 need_swap ? "True" : "False");
1597
1598         if (need_swap)
1599                 el = swab16(ah->eeprom.def.baseEepHeader.length);
1600         else
1601                 el = ah->eeprom.def.baseEepHeader.length;
1602
1603         if (el > sizeof(struct ar5416_eeprom_def))
1604                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1605         else
1606                 el = el / sizeof(u16);
1607
1608         eepdata = (u16 *)(&ah->eeprom);
1609
1610         for (i = 0; i < el; i++)
1611                 sum ^= *eepdata++;
1612
1613         if (need_swap) {
1614                 u32 integer, j;
1615                 u16 word;
1616
1617                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1618                         "EEPROM Endianness is not native.. Changing.\n");
1619
1620                 word = swab16(eep->baseEepHeader.length);
1621                 eep->baseEepHeader.length = word;
1622
1623                 word = swab16(eep->baseEepHeader.checksum);
1624                 eep->baseEepHeader.checksum = word;
1625
1626                 word = swab16(eep->baseEepHeader.version);
1627                 eep->baseEepHeader.version = word;
1628
1629                 word = swab16(eep->baseEepHeader.regDmn[0]);
1630                 eep->baseEepHeader.regDmn[0] = word;
1631
1632                 word = swab16(eep->baseEepHeader.regDmn[1]);
1633                 eep->baseEepHeader.regDmn[1] = word;
1634
1635                 word = swab16(eep->baseEepHeader.rfSilent);
1636                 eep->baseEepHeader.rfSilent = word;
1637
1638                 word = swab16(eep->baseEepHeader.blueToothOptions);
1639                 eep->baseEepHeader.blueToothOptions = word;
1640
1641                 word = swab16(eep->baseEepHeader.deviceCap);
1642                 eep->baseEepHeader.deviceCap = word;
1643
1644                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1645                         struct modal_eep_header *pModal =
1646                                 &eep->modalHeader[j];
1647                         integer = swab32(pModal->antCtrlCommon);
1648                         pModal->antCtrlCommon = integer;
1649
1650                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1651                                 integer = swab32(pModal->antCtrlChain[i]);
1652                                 pModal->antCtrlChain[i] = integer;
1653                         }
1654
1655                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1656                                 word = swab16(pModal->spurChans[i].spurChan);
1657                                 pModal->spurChans[i].spurChan = word;
1658                         }
1659                 }
1660         }
1661
1662         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1663             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1664                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1665                         "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1666                         sum, ah->eep_ops->get_eeprom_ver(ah));
1667                 return -EINVAL;
1668         }
1669
1670         return 0;
1671 }
1672
1673 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1674                                    enum eeprom_param param)
1675 {
1676         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1677         struct modal_eep_header *pModal = eep->modalHeader;
1678         struct base_eep_header *pBase = &eep->baseEepHeader;
1679
1680         switch (param) {
1681         case EEP_NFTHRESH_5:
1682                 return pModal[0].noiseFloorThreshCh[0];
1683         case EEP_NFTHRESH_2:
1684                 return pModal[1].noiseFloorThreshCh[0];
1685         case AR_EEPROM_MAC(0):
1686                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1687         case AR_EEPROM_MAC(1):
1688                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1689         case AR_EEPROM_MAC(2):
1690                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1691         case EEP_REG_0:
1692                 return pBase->regDmn[0];
1693         case EEP_REG_1:
1694                 return pBase->regDmn[1];
1695         case EEP_OP_CAP:
1696                 return pBase->deviceCap;
1697         case EEP_OP_MODE:
1698                 return pBase->opCapFlags;
1699         case EEP_RF_SILENT:
1700                 return pBase->rfSilent;
1701         case EEP_OB_5:
1702                 return pModal[0].ob;
1703         case EEP_DB_5:
1704                 return pModal[0].db;
1705         case EEP_OB_2:
1706                 return pModal[1].ob;
1707         case EEP_DB_2:
1708                 return pModal[1].db;
1709         case EEP_MINOR_REV:
1710                 return AR5416_VER_MASK;
1711         case EEP_TX_MASK:
1712                 return pBase->txMask;
1713         case EEP_RX_MASK:
1714                 return pBase->rxMask;
1715         case EEP_RXGAIN_TYPE:
1716                 return pBase->rxGainType;
1717         case EEP_TXGAIN_TYPE:
1718                 return pBase->txGainType;
1719         case EEP_OL_PWRCTRL:
1720                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1721                         return pBase->openLoopPwrCntl ? true : false;
1722                 else
1723                         return false;
1724         case EEP_RC_CHAIN_MASK:
1725                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1726                         return pBase->rcChainMask;
1727                 else
1728                         return 0;
1729         case EEP_DAC_HPWR_5G:
1730                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1731                         return pBase->dacHiPwrMode_5G;
1732                 else
1733                         return 0;
1734         case EEP_FRAC_N_5G:
1735                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
1736                         return pBase->frac_n_5g;
1737                 else
1738                         return 0;
1739         default:
1740                 return 0;
1741         }
1742 }
1743
1744 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
1745                                   struct modal_eep_header *pModal,
1746                                   struct ar5416_eeprom_def *eep,
1747                                   u8 txRxAttenLocal, int regChainOffset, int i)
1748 {
1749         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1750                 txRxAttenLocal = pModal->txRxAttenCh[i];
1751
1752                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1753                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1754                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1755                               pModal->bswMargin[i]);
1756                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1757                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1758                               pModal->bswAtten[i]);
1759                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1760                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1761                               pModal->xatten2Margin[i]);
1762                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1763                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1764                               pModal->xatten2Db[i]);
1765                 } else {
1766                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1767                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1768                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1769                           | SM(pModal-> bswMargin[i],
1770                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1771                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1772                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1773                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1774                           | SM(pModal->bswAtten[i],
1775                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1776                 }
1777         }
1778
1779         if (AR_SREV_9280_10_OR_LATER(ah)) {
1780                 REG_RMW_FIELD(ah,
1781                       AR_PHY_RXGAIN + regChainOffset,
1782                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1783                 REG_RMW_FIELD(ah,
1784                       AR_PHY_RXGAIN + regChainOffset,
1785                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1786         } else {
1787                 REG_WRITE(ah,
1788                           AR_PHY_RXGAIN + regChainOffset,
1789                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
1790                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
1791                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
1792                 REG_WRITE(ah,
1793                           AR_PHY_GAIN_2GHZ + regChainOffset,
1794                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1795                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1796                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1797         }
1798 }
1799
1800 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
1801                                           struct ath9k_channel *chan)
1802 {
1803         struct modal_eep_header *pModal;
1804         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1805         int i, regChainOffset;
1806         u8 txRxAttenLocal;
1807
1808         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1809         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1810
1811         REG_WRITE(ah, AR_PHY_SWITCH_COM,
1812                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1813
1814         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1815                 if (AR_SREV_9280(ah)) {
1816                         if (i >= 2)
1817                                 break;
1818                 }
1819
1820                 if (AR_SREV_5416_20_OR_LATER(ah) &&
1821                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
1822                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1823                 else
1824                         regChainOffset = i * 0x1000;
1825
1826                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1827                           pModal->antCtrlChain[i]);
1828
1829                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1830                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1831                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1832                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1833                           SM(pModal->iqCalICh[i],
1834                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1835                           SM(pModal->iqCalQCh[i],
1836                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1837
1838                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
1839                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
1840                                               regChainOffset, i);
1841         }
1842
1843         if (AR_SREV_9280_10_OR_LATER(ah)) {
1844                 if (IS_CHAN_2GHZ(chan)) {
1845                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1846                                                   AR_AN_RF2G1_CH0_OB,
1847                                                   AR_AN_RF2G1_CH0_OB_S,
1848                                                   pModal->ob);
1849                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1850                                                   AR_AN_RF2G1_CH0_DB,
1851                                                   AR_AN_RF2G1_CH0_DB_S,
1852                                                   pModal->db);
1853                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1854                                                   AR_AN_RF2G1_CH1_OB,
1855                                                   AR_AN_RF2G1_CH1_OB_S,
1856                                                   pModal->ob_ch1);
1857                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1858                                                   AR_AN_RF2G1_CH1_DB,
1859                                                   AR_AN_RF2G1_CH1_DB_S,
1860                                                   pModal->db_ch1);
1861                 } else {
1862                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1863                                                   AR_AN_RF5G1_CH0_OB5,
1864                                                   AR_AN_RF5G1_CH0_OB5_S,
1865                                                   pModal->ob);
1866                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1867                                                   AR_AN_RF5G1_CH0_DB5,
1868                                                   AR_AN_RF5G1_CH0_DB5_S,
1869                                                   pModal->db);
1870                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1871                                                   AR_AN_RF5G1_CH1_OB5,
1872                                                   AR_AN_RF5G1_CH1_OB5_S,
1873                                                   pModal->ob_ch1);
1874                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1875                                                   AR_AN_RF5G1_CH1_DB5,
1876                                                   AR_AN_RF5G1_CH1_DB5_S,
1877                                                   pModal->db_ch1);
1878                 }
1879                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1880                                           AR_AN_TOP2_XPABIAS_LVL,
1881                                           AR_AN_TOP2_XPABIAS_LVL_S,
1882                                           pModal->xpaBiasLvl);
1883                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1884                                           AR_AN_TOP2_LOCALBIAS,
1885                                           AR_AN_TOP2_LOCALBIAS_S,
1886                                           pModal->local_bias);
1887                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1888                               pModal->force_xpaon);
1889         }
1890
1891         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1892                       pModal->switchSettling);
1893         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1894                       pModal->adcDesiredSize);
1895
1896         if (!AR_SREV_9280_10_OR_LATER(ah))
1897                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1898                               AR_PHY_DESIRED_SZ_PGA,
1899                               pModal->pgaDesiredSize);
1900
1901         REG_WRITE(ah, AR_PHY_RF_CTL4,
1902                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1903                   | SM(pModal->txEndToXpaOff,
1904                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1905                   | SM(pModal->txFrameToXpaOn,
1906                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1907                   | SM(pModal->txFrameToXpaOn,
1908                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1909
1910         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1911                       pModal->txEndToRxOn);
1912
1913         if (AR_SREV_9280_10_OR_LATER(ah)) {
1914                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1915                               pModal->thresh62);
1916                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1917                               AR_PHY_EXT_CCA0_THRESH62,
1918                               pModal->thresh62);
1919         } else {
1920                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1921                               pModal->thresh62);
1922                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1923                               AR_PHY_EXT_CCA_THRESH62,
1924                               pModal->thresh62);
1925         }
1926
1927         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1928                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1929                               AR_PHY_TX_END_DATA_START,
1930                               pModal->txFrameToDataStart);
1931                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1932                               pModal->txFrameToPaOn);
1933         }
1934
1935         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1936                 if (IS_CHAN_HT40(chan))
1937                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1938                                       AR_PHY_SETTLING_SWITCH,
1939                                       pModal->swSettleHt40);
1940         }
1941
1942         if (AR_SREV_9280_20_OR_LATER(ah) &&
1943             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1944                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1945                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1946                               pModal->miscBits);
1947
1948
1949         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
1950                 if (IS_CHAN_2GHZ(chan))
1951                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1952                                         eep->baseEepHeader.dacLpMode);
1953                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1954                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1955                 else
1956                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1957                                       eep->baseEepHeader.dacLpMode);
1958
1959                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1960                               pModal->miscBits >> 2);
1961
1962                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1963                               AR_PHY_TX_DESIRED_SCALE_CCK,
1964                               eep->baseEepHeader.desiredScaleCCK);
1965         }
1966 }
1967
1968 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1969                                    struct ath9k_channel *chan)
1970 {
1971 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1972         struct modal_eep_header *pModal;
1973         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1974         u8 biaslevel;
1975
1976         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1977                 return;
1978
1979         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1980                 return;
1981
1982         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1983
1984         if (pModal->xpaBiasLvl != 0xff) {
1985                 biaslevel = pModal->xpaBiasLvl;
1986         } else {
1987                 u16 resetFreqBin, freqBin, freqCount = 0;
1988                 struct chan_centers centers;
1989
1990                 ath9k_hw_get_channel_centers(ah, chan, &centers);
1991
1992                 resetFreqBin = FREQ2FBIN(centers.synth_center,
1993                                          IS_CHAN_2GHZ(chan));
1994                 freqBin = XPA_LVL_FREQ(0) & 0xff;
1995                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
1996
1997                 freqCount++;
1998
1999                 while (freqCount < 3) {
2000                         if (XPA_LVL_FREQ(freqCount) == 0x0)
2001                                 break;
2002
2003                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
2004                         if (resetFreqBin >= freqBin)
2005                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
2006                         else
2007                                 break;
2008                         freqCount++;
2009                 }
2010         }
2011
2012         if (IS_CHAN_2GHZ(chan)) {
2013                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
2014                                         7, 1) & (~0x18)) | biaslevel << 3;
2015         } else {
2016                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
2017                                         6, 1) & (~0xc0)) | biaslevel << 6;
2018         }
2019 #undef XPA_LVL_FREQ
2020 }
2021
2022 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
2023                                 struct ath9k_channel *chan,
2024                                 struct cal_data_per_freq *pRawDataSet,
2025                                 u8 *bChans, u16 availPiers,
2026                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
2027                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
2028                                 u16 numXpdGains)
2029 {
2030         int i, j, k;
2031         int16_t ss;
2032         u16 idxL = 0, idxR = 0, numPiers;
2033         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
2034                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2035         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
2036                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2037         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
2038                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2039
2040         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2041         u8 minPwrT4[AR5416_NUM_PD_GAINS];
2042         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
2043         int16_t vpdStep;
2044         int16_t tmpVal;
2045         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
2046         bool match;
2047         int16_t minDelta = 0;
2048         struct chan_centers centers;
2049
2050         ath9k_hw_get_channel_centers(ah, chan, &centers);
2051
2052         for (numPiers = 0; numPiers < availPiers; numPiers++) {
2053                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
2054                         break;
2055         }
2056
2057         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2058                                                              IS_CHAN_2GHZ(chan)),
2059                                                bChans, numPiers, &idxL, &idxR);
2060
2061         if (match) {
2062                 for (i = 0; i < numXpdGains; i++) {
2063                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2064                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2065                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2066                                         pRawDataSet[idxL].pwrPdg[i],
2067                                         pRawDataSet[idxL].vpdPdg[i],
2068                                         AR5416_PD_GAIN_ICEPTS,
2069                                         vpdTableI[i]);
2070                 }
2071         } else {
2072                 for (i = 0; i < numXpdGains; i++) {
2073                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
2074                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
2075                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
2076                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
2077
2078                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
2079
2080                         maxPwrT4[i] =
2081                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
2082                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2083
2084
2085                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2086                                                 pPwrL, pVpdL,
2087                                                 AR5416_PD_GAIN_ICEPTS,
2088                                                 vpdTableL[i]);
2089                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2090                                                 pPwrR, pVpdR,
2091                                                 AR5416_PD_GAIN_ICEPTS,
2092                                                 vpdTableR[i]);
2093
2094                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2095                                 vpdTableI[i][j] =
2096                                         (u8)(ath9k_hw_interpolate((u16)
2097                                              FREQ2FBIN(centers.
2098                                                        synth_center,
2099                                                        IS_CHAN_2GHZ
2100                                                        (chan)),
2101                                              bChans[idxL], bChans[idxR],
2102                                              vpdTableL[i][j], vpdTableR[i][j]));
2103                         }
2104                 }
2105         }
2106
2107         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2108
2109         k = 0;
2110
2111         for (i = 0; i < numXpdGains; i++) {
2112                 if (i == (numXpdGains - 1))
2113                         pPdGainBoundaries[i] =
2114                                 (u16)(maxPwrT4[i] / 2);
2115                 else
2116                         pPdGainBoundaries[i] =
2117                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2118
2119                 pPdGainBoundaries[i] =
2120                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2121
2122                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2123                         minDelta = pPdGainBoundaries[0] - 23;
2124                         pPdGainBoundaries[0] = 23;
2125                 } else {
2126                         minDelta = 0;
2127                 }
2128
2129                 if (i == 0) {
2130                         if (AR_SREV_9280_10_OR_LATER(ah))
2131                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2132                         else
2133                                 ss = 0;
2134                 } else {
2135                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
2136                                         (minPwrT4[i] / 2)) -
2137                                        tPdGainOverlap + 1 + minDelta);
2138                 }
2139                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2140                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2141
2142                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2143                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2144                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2145                         ss++;
2146                 }
2147
2148                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2149                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2150                                 (minPwrT4[i] / 2));
2151                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2152                         tgtIndex : sizeCurrVpdTable;
2153
2154                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2155                         pPDADCValues[k++] = vpdTableI[i][ss++];
2156                 }
2157
2158                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2159                                     vpdTableI[i][sizeCurrVpdTable - 2]);
2160                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2161
2162                 if (tgtIndex > maxIndex) {
2163                         while ((ss <= tgtIndex) &&
2164                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2165                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2166                                                     (ss - maxIndex + 1) * vpdStep));
2167                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2168                                                          255 : tmpVal);
2169                                 ss++;
2170                         }
2171                 }
2172         }
2173
2174         while (i < AR5416_PD_GAINS_IN_MASK) {
2175                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2176                 i++;
2177         }
2178
2179         while (k < AR5416_NUM_PDADC_VALUES) {
2180                 pPDADCValues[k] = pPDADCValues[k - 1];
2181                 k++;
2182         }
2183
2184         return;
2185 }
2186
2187 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2188                                   struct ath9k_channel *chan,
2189                                   int16_t *pTxPowerIndexOffset)
2190 {
2191 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2192 #define SM_PDGAIN_B(x, y) \
2193                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2194
2195         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2196         struct cal_data_per_freq *pRawDataset;
2197         u8 *pCalBChans = NULL;
2198         u16 pdGainOverlap_t2;
2199         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2200         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2201         u16 numPiers, i, j;
2202         int16_t tMinCalPower;
2203         u16 numXpdGain, xpdMask;
2204         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2205         u32 reg32, regOffset, regChainOffset;
2206         int16_t modalIdx;
2207
2208         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2209         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2210
2211         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2212             AR5416_EEP_MINOR_VER_2) {
2213                 pdGainOverlap_t2 =
2214                         pEepData->modalHeader[modalIdx].pdGainOverlap;
2215         } else {
2216                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2217                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2218         }
2219
2220         if (IS_CHAN_2GHZ(chan)) {
2221                 pCalBChans = pEepData->calFreqPier2G;
2222                 numPiers = AR5416_NUM_2G_CAL_PIERS;
2223         } else {
2224                 pCalBChans = pEepData->calFreqPier5G;
2225                 numPiers = AR5416_NUM_5G_CAL_PIERS;
2226         }
2227
2228         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
2229                 pRawDataset = pEepData->calPierData2G[0];
2230                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
2231                                  pRawDataset)->vpdPdg[0][0];
2232         }
2233
2234         numXpdGain = 0;
2235
2236         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2237                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2238                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
2239                                 break;
2240                         xpdGainValues[numXpdGain] =
2241                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2242                         numXpdGain++;
2243                 }
2244         }
2245
2246         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2247                       (numXpdGain - 1) & 0x3);
2248         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2249                       xpdGainValues[0]);
2250         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2251                       xpdGainValues[1]);
2252         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2253                       xpdGainValues[2]);
2254
2255         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2256                 if (AR_SREV_5416_20_OR_LATER(ah) &&
2257                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2258                     (i != 0)) {
2259                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2260                 } else
2261                         regChainOffset = i * 0x1000;
2262
2263                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2264                         if (IS_CHAN_2GHZ(chan))
2265                                 pRawDataset = pEepData->calPierData2G[i];
2266                         else
2267                                 pRawDataset = pEepData->calPierData5G[i];
2268
2269
2270                         if (OLC_FOR_AR9280_20_LATER) {
2271                                 u8 pcdacIdx;
2272                                 u8 txPower;
2273
2274                                 ath9k_get_txgain_index(ah, chan,
2275                                 (struct calDataPerFreqOpLoop *)pRawDataset,
2276                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
2277                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
2278                                                      txPower/2, pdadcValues);
2279                         } else {
2280                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
2281                                                         chan, pRawDataset,
2282                                                         pCalBChans, numPiers,
2283                                                         pdGainOverlap_t2,
2284                                                         &tMinCalPower,
2285                                                         gainBoundaries,
2286                                                         pdadcValues,
2287                                                         numXpdGain);
2288                         }
2289
2290                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2291                                 if (OLC_FOR_AR9280_20_LATER) {
2292                                         REG_WRITE(ah,
2293                                                 AR_PHY_TPCRG5 + regChainOffset,
2294                                                 SM(0x6,
2295                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2296                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2297                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2298                                 } else {
2299                                         REG_WRITE(ah,
2300                                                 AR_PHY_TPCRG5 + regChainOffset,
2301                                                 SM(pdGainOverlap_t2,
2302                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2303                                                 SM_PDGAIN_B(0, 1) |
2304                                                 SM_PDGAIN_B(1, 2) |
2305                                                 SM_PDGAIN_B(2, 3) |
2306                                                 SM_PDGAIN_B(3, 4));
2307                                 }
2308                         }
2309
2310                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2311                         for (j = 0; j < 32; j++) {
2312                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2313                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2314                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2315                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2316                                 REG_WRITE(ah, regOffset, reg32);
2317
2318                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2319                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
2320                                         i, regChainOffset, regOffset,
2321                                         reg32);
2322                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2323                                         "PDADC: Chain %d | PDADC %3d "
2324                                         "Value %3d | PDADC %3d Value %3d | "
2325                                         "PDADC %3d Value %3d | PDADC %3d "
2326                                         "Value %3d |\n",
2327                                         i, 4 * j, pdadcValues[4 * j],
2328                                         4 * j + 1, pdadcValues[4 * j + 1],
2329                                         4 * j + 2, pdadcValues[4 * j + 2],
2330                                         4 * j + 3,
2331                                         pdadcValues[4 * j + 3]);
2332
2333                                 regOffset += 4;
2334                         }
2335                 }
2336         }
2337
2338         *pTxPowerIndexOffset = 0;
2339 #undef SM_PD_GAIN
2340 #undef SM_PDGAIN_B
2341 }
2342
2343 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2344                                                   struct ath9k_channel *chan,
2345                                                   int16_t *ratesArray,
2346                                                   u16 cfgCtl,
2347                                                   u16 AntennaReduction,
2348                                                   u16 twiceMaxRegulatoryPower,
2349                                                   u16 powerLimit)
2350 {
2351 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
2352 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
2353
2354         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2355         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2356         static const u16 tpScaleReductionTable[5] =
2357                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2358
2359         int i;
2360         int16_t twiceLargestAntenna;
2361         struct cal_ctl_data *rep;
2362         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2363                 0, { 0, 0, 0, 0}
2364         };
2365         struct cal_target_power_leg targetPowerOfdmExt = {
2366                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2367                 0, { 0, 0, 0, 0 }
2368         };
2369         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2370                 0, {0, 0, 0, 0}
2371         };
2372         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2373         u16 ctlModesFor11a[] =
2374                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2375         u16 ctlModesFor11g[] =
2376                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2377                   CTL_2GHT40
2378                 };
2379         u16 numCtlModes, *pCtlMode, ctlMode, freq;
2380         struct chan_centers centers;
2381         int tx_chainmask;
2382         u16 twiceMinEdgePower;
2383
2384         tx_chainmask = ah->txchainmask;
2385
2386         ath9k_hw_get_channel_centers(ah, chan, &centers);
2387
2388         twiceLargestAntenna = max(
2389                 pEepData->modalHeader
2390                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2391                 pEepData->modalHeader
2392                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2393
2394         twiceLargestAntenna = max((u8)twiceLargestAntenna,
2395                                   pEepData->modalHeader
2396                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2397
2398         twiceLargestAntenna = (int16_t)min(AntennaReduction -
2399                                            twiceLargestAntenna, 0);
2400
2401         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2402
2403         if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2404                 maxRegAllowedPower -=
2405                         (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2406         }
2407
2408         scaledPower = min(powerLimit, maxRegAllowedPower);
2409
2410         switch (ar5416_get_ntxchains(tx_chainmask)) {
2411         case 1:
2412                 break;
2413         case 2:
2414                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2415                 break;
2416         case 3:
2417                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2418                 break;
2419         }
2420
2421         scaledPower = max((u16)0, scaledPower);
2422
2423         if (IS_CHAN_2GHZ(chan)) {
2424                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2425                         SUB_NUM_CTL_MODES_AT_2G_40;
2426                 pCtlMode = ctlModesFor11g;
2427
2428                 ath9k_hw_get_legacy_target_powers(ah, chan,
2429                         pEepData->calTargetPowerCck,
2430                         AR5416_NUM_2G_CCK_TARGET_POWERS,
2431                         &targetPowerCck, 4, false);
2432                 ath9k_hw_get_legacy_target_powers(ah, chan,
2433                         pEepData->calTargetPower2G,
2434                         AR5416_NUM_2G_20_TARGET_POWERS,
2435                         &targetPowerOfdm, 4, false);
2436                 ath9k_hw_get_target_powers(ah, chan,
2437                         pEepData->calTargetPower2GHT20,
2438                         AR5416_NUM_2G_20_TARGET_POWERS,
2439                         &targetPowerHt20, 8, false);
2440
2441                 if (IS_CHAN_HT40(chan)) {
2442                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2443                         ath9k_hw_get_target_powers(ah, chan,
2444                                 pEepData->calTargetPower2GHT40,
2445                                 AR5416_NUM_2G_40_TARGET_POWERS,
2446                                 &targetPowerHt40, 8, true);
2447                         ath9k_hw_get_legacy_target_powers(ah, chan,
2448                                 pEepData->calTargetPowerCck,
2449                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
2450                                 &targetPowerCckExt, 4, true);
2451                         ath9k_hw_get_legacy_target_powers(ah, chan,
2452                                 pEepData->calTargetPower2G,
2453                                 AR5416_NUM_2G_20_TARGET_POWERS,
2454                                 &targetPowerOfdmExt, 4, true);
2455                 }
2456         } else {
2457                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2458                         SUB_NUM_CTL_MODES_AT_5G_40;
2459                 pCtlMode = ctlModesFor11a;
2460
2461                 ath9k_hw_get_legacy_target_powers(ah, chan,
2462                         pEepData->calTargetPower5G,
2463                         AR5416_NUM_5G_20_TARGET_POWERS,
2464                         &targetPowerOfdm, 4, false);
2465                 ath9k_hw_get_target_powers(ah, chan,
2466                         pEepData->calTargetPower5GHT20,
2467                         AR5416_NUM_5G_20_TARGET_POWERS,
2468                         &targetPowerHt20, 8, false);
2469
2470                 if (IS_CHAN_HT40(chan)) {
2471                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2472                         ath9k_hw_get_target_powers(ah, chan,
2473                                 pEepData->calTargetPower5GHT40,
2474                                 AR5416_NUM_5G_40_TARGET_POWERS,
2475                                 &targetPowerHt40, 8, true);
2476                         ath9k_hw_get_legacy_target_powers(ah, chan,
2477                                 pEepData->calTargetPower5G,
2478                                 AR5416_NUM_5G_20_TARGET_POWERS,
2479                                 &targetPowerOfdmExt, 4, true);
2480                 }
2481         }
2482
2483         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2484                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2485                         (pCtlMode[ctlMode] == CTL_2GHT40);
2486                 if (isHt40CtlMode)
2487                         freq = centers.synth_center;
2488                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2489                         freq = centers.ext_center;
2490                 else
2491                         freq = centers.ctl_center;
2492
2493                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2494                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
2495                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2496
2497                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2498                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2499                         "EXT_ADDITIVE %d\n",
2500                         ctlMode, numCtlModes, isHt40CtlMode,
2501                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
2502
2503                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2504                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2505                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2506                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2507                                 "chan %d\n",
2508                                 i, cfgCtl, pCtlMode[ctlMode],
2509                                 pEepData->ctlIndex[i], chan->channel);
2510
2511                         if ((((cfgCtl & ~CTL_MODE_M) |
2512                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2513                              pEepData->ctlIndex[i]) ||
2514                             (((cfgCtl & ~CTL_MODE_M) |
2515                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2516                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2517                                 rep = &(pEepData->ctlData[i]);
2518
2519                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2520                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2521                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2522
2523                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2524                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
2525                                         "2xMinEdge %d chainmask %d chains %d\n",
2526                                         i, freq, IS_CHAN_2GHZ(chan),
2527                                         twiceMinEdgePower, tx_chainmask,
2528                                         ar5416_get_ntxchains
2529                                         (tx_chainmask));
2530                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2531                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
2532                                                                 twiceMinEdgePower);
2533                                 } else {
2534                                         twiceMaxEdgePower = twiceMinEdgePower;
2535                                         break;
2536                                 }
2537                         }
2538                 }
2539
2540                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2541
2542                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2543                         "    SEL-Min ctlMode %d pCtlMode %d "
2544                         "2xMaxEdge %d sP %d minCtlPwr %d\n",
2545                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2546                         scaledPower, minCtlPower);
2547
2548                 switch (pCtlMode[ctlMode]) {
2549                 case CTL_11B:
2550                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2551                                 targetPowerCck.tPow2x[i] =
2552                                         min((u16)targetPowerCck.tPow2x[i],
2553                                             minCtlPower);
2554                         }
2555                         break;
2556                 case CTL_11A:
2557                 case CTL_11G:
2558                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2559                                 targetPowerOfdm.tPow2x[i] =
2560                                         min((u16)targetPowerOfdm.tPow2x[i],
2561                                             minCtlPower);
2562                         }
2563                         break;
2564                 case CTL_5GHT20:
2565                 case CTL_2GHT20:
2566                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2567                                 targetPowerHt20.tPow2x[i] =
2568                                         min((u16)targetPowerHt20.tPow2x[i],
2569                                             minCtlPower);
2570                         }
2571                         break;
2572                 case CTL_11B_EXT:
2573                         targetPowerCckExt.tPow2x[0] = min((u16)
2574                                         targetPowerCckExt.tPow2x[0],
2575                                         minCtlPower);
2576                         break;
2577                 case CTL_11A_EXT:
2578                 case CTL_11G_EXT:
2579                         targetPowerOfdmExt.tPow2x[0] = min((u16)
2580                                         targetPowerOfdmExt.tPow2x[0],
2581                                         minCtlPower);
2582                         break;
2583                 case CTL_5GHT40:
2584                 case CTL_2GHT40:
2585                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2586                                 targetPowerHt40.tPow2x[i] =
2587                                         min((u16)targetPowerHt40.tPow2x[i],
2588                                             minCtlPower);
2589                         }
2590                         break;
2591                 default:
2592                         break;
2593                 }
2594         }
2595
2596         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2597                 ratesArray[rate18mb] = ratesArray[rate24mb] =
2598                 targetPowerOfdm.tPow2x[0];
2599         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2600         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2601         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2602         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2603
2604         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2605                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2606
2607         if (IS_CHAN_2GHZ(chan)) {
2608                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2609                 ratesArray[rate2s] = ratesArray[rate2l] =
2610                         targetPowerCck.tPow2x[1];
2611                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2612                         targetPowerCck.tPow2x[2];
2613                 ratesArray[rate11s] = ratesArray[rate11l] =
2614                         targetPowerCck.tPow2x[3];
2615         }
2616         if (IS_CHAN_HT40(chan)) {
2617                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2618                         ratesArray[rateHt40_0 + i] =
2619                                 targetPowerHt40.tPow2x[i];
2620                 }
2621                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2622                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2623                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2624                 if (IS_CHAN_2GHZ(chan)) {
2625                         ratesArray[rateExtCck] =
2626                                 targetPowerCckExt.tPow2x[0];
2627                 }
2628         }
2629 }
2630
2631 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
2632                                     struct ath9k_channel *chan,
2633                                     u16 cfgCtl,
2634                                     u8 twiceAntennaReduction,
2635                                     u8 twiceMaxRegulatoryPower,
2636                                     u8 powerLimit)
2637 {
2638 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2639         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2640         struct modal_eep_header *pModal =
2641                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2642         int16_t ratesArray[Ar5416RateSize];
2643         int16_t txPowerIndexOffset = 0;
2644         u8 ht40PowerIncForPdadc = 2;
2645         int i, cck_ofdm_delta = 0;
2646
2647         memset(ratesArray, 0, sizeof(ratesArray));
2648
2649         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2650             AR5416_EEP_MINOR_VER_2) {
2651                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2652         }
2653
2654         ath9k_hw_set_def_power_per_rate_table(ah, chan,
2655                                                &ratesArray[0], cfgCtl,
2656                                                twiceAntennaReduction,
2657                                                twiceMaxRegulatoryPower,
2658                                                powerLimit);
2659
2660         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
2661
2662         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2663                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2664                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2665                         ratesArray[i] = AR5416_MAX_RATE_POWER;
2666         }
2667
2668         if (AR_SREV_9280_10_OR_LATER(ah)) {
2669                 for (i = 0; i < Ar5416RateSize; i++)
2670                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2671         }
2672
2673         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2674                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
2675                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2676                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2677                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2678         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2679                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
2680                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2681                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2682                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2683
2684         if (IS_CHAN_2GHZ(chan)) {
2685                 if (OLC_FOR_AR9280_20_LATER) {
2686                         cck_ofdm_delta = 2;
2687                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2688                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
2689                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
2690                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2691                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
2692                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2693                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
2694                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
2695                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
2696                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
2697                 } else {
2698                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2699                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
2700                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2701                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2702                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2703                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2704                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
2705                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2706                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2707                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2708                 }
2709         }
2710
2711         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2712                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2713                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2714                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2715                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2716         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2717                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2718                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2719                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2720                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2721
2722         if (IS_CHAN_HT40(chan)) {
2723                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2724                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
2725                                        ht40PowerIncForPdadc, 24)
2726                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2727                                          ht40PowerIncForPdadc, 16)
2728                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2729                                          ht40PowerIncForPdadc, 8)
2730                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2731                                          ht40PowerIncForPdadc, 0));
2732                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2733                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
2734                                        ht40PowerIncForPdadc, 24)
2735                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2736                                          ht40PowerIncForPdadc, 16)
2737                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2738                                          ht40PowerIncForPdadc, 8)
2739                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2740                                          ht40PowerIncForPdadc, 0));
2741                 if (OLC_FOR_AR9280_20_LATER) {
2742                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2743                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2744                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
2745                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2746                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
2747                 } else {
2748                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2749                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)