0b5358072172a9f0c95d008ea21447aa59ca0595
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18 #include <linux/config.h>
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/workqueue.h>
40 #include <linux/prefetch.h>
41 #include <linux/dma-mapping.h>
42
43 #include <net/checksum.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC64
51 #include <asm/idprom.h>
52 #include <asm/oplib.h>
53 #include <asm/pbm.h>
54 #endif
55
56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57 #define TG3_VLAN_TAG_USED 1
58 #else
59 #define TG3_VLAN_TAG_USED 0
60 #endif
61
62 #ifdef NETIF_F_TSO
63 #define TG3_TSO_SUPPORT 1
64 #else
65 #define TG3_TSO_SUPPORT 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define PFX DRV_MODULE_NAME     ": "
72 #define DRV_MODULE_VERSION      "3.56"
73 #define DRV_MODULE_RELDATE      "Apr 1, 2006"
74
75 #define TG3_DEF_MAC_MODE        0
76 #define TG3_DEF_RX_MODE         0
77 #define TG3_DEF_TX_MODE         0
78 #define TG3_DEF_MSG_ENABLE        \
79         (NETIF_MSG_DRV          | \
80          NETIF_MSG_PROBE        | \
81          NETIF_MSG_LINK         | \
82          NETIF_MSG_TIMER        | \
83          NETIF_MSG_IFDOWN       | \
84          NETIF_MSG_IFUP         | \
85          NETIF_MSG_RX_ERR       | \
86          NETIF_MSG_TX_ERR)
87
88 /* length of time before we decide the hardware is borked,
89  * and dev->tx_timeout() should be called to fix the problem
90  */
91 #define TG3_TX_TIMEOUT                  (5 * HZ)
92
93 /* hardware minimum and maximum for a single frame's data payload */
94 #define TG3_MIN_MTU                     60
95 #define TG3_MAX_MTU(tp) \
96         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97
98 /* These numbers seem to be hard coded in the NIC firmware somehow.
99  * You can't change the ring sizes, but you can change where you place
100  * them in the NIC onboard memory.
101  */
102 #define TG3_RX_RING_SIZE                512
103 #define TG3_DEF_RX_RING_PENDING         200
104 #define TG3_RX_JUMBO_RING_SIZE          256
105 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108  * we really want to expose these constants to GCC so that modulo et
109  * al.  operations are done with shifts and masks instead of with
110  * hw multiply/modulo instructions.  Another solution would be to
111  * replace things like '% foo' with '& (foo - 1)'.
112  */
113 #define TG3_RX_RCB_RING_SIZE(tp)        \
114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
120                                  TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122                                  TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124                                    TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define TX_BUFFS_AVAIL(TP)                                              \
128         ((TP)->tx_pending -                                             \
129          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131
132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
134
135 /* minimum number of free TX descriptors required to wake up TX process */
136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
137
138 /* number of ETHTOOL_GSTATS u64's */
139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140
141 #define TG3_NUM_TEST            6
142
143 static char version[] __devinitdata =
144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145
146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_MODULE_VERSION);
150
151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
152 module_param(tg3_debug, int, 0);
153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154
155 static struct pci_device_id tg3_pci_tbl[] = {
156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
245           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
246         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
247           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
248         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
249           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
250         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
251           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
252         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
253           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
254         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
255           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
256         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
257           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
258         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
259           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
260         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
261           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
262         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
263           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
264         { 0, }
265 };
266
267 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
268
269 static struct {
270         const char string[ETH_GSTRING_LEN];
271 } ethtool_stats_keys[TG3_NUM_STATS] = {
272         { "rx_octets" },
273         { "rx_fragments" },
274         { "rx_ucast_packets" },
275         { "rx_mcast_packets" },
276         { "rx_bcast_packets" },
277         { "rx_fcs_errors" },
278         { "rx_align_errors" },
279         { "rx_xon_pause_rcvd" },
280         { "rx_xoff_pause_rcvd" },
281         { "rx_mac_ctrl_rcvd" },
282         { "rx_xoff_entered" },
283         { "rx_frame_too_long_errors" },
284         { "rx_jabbers" },
285         { "rx_undersize_packets" },
286         { "rx_in_length_errors" },
287         { "rx_out_length_errors" },
288         { "rx_64_or_less_octet_packets" },
289         { "rx_65_to_127_octet_packets" },
290         { "rx_128_to_255_octet_packets" },
291         { "rx_256_to_511_octet_packets" },
292         { "rx_512_to_1023_octet_packets" },
293         { "rx_1024_to_1522_octet_packets" },
294         { "rx_1523_to_2047_octet_packets" },
295         { "rx_2048_to_4095_octet_packets" },
296         { "rx_4096_to_8191_octet_packets" },
297         { "rx_8192_to_9022_octet_packets" },
298
299         { "tx_octets" },
300         { "tx_collisions" },
301
302         { "tx_xon_sent" },
303         { "tx_xoff_sent" },
304         { "tx_flow_control" },
305         { "tx_mac_errors" },
306         { "tx_single_collisions" },
307         { "tx_mult_collisions" },
308         { "tx_deferred" },
309         { "tx_excessive_collisions" },
310         { "tx_late_collisions" },
311         { "tx_collide_2times" },
312         { "tx_collide_3times" },
313         { "tx_collide_4times" },
314         { "tx_collide_5times" },
315         { "tx_collide_6times" },
316         { "tx_collide_7times" },
317         { "tx_collide_8times" },
318         { "tx_collide_9times" },
319         { "tx_collide_10times" },
320         { "tx_collide_11times" },
321         { "tx_collide_12times" },
322         { "tx_collide_13times" },
323         { "tx_collide_14times" },
324         { "tx_collide_15times" },
325         { "tx_ucast_packets" },
326         { "tx_mcast_packets" },
327         { "tx_bcast_packets" },
328         { "tx_carrier_sense_errors" },
329         { "tx_discards" },
330         { "tx_errors" },
331
332         { "dma_writeq_full" },
333         { "dma_write_prioq_full" },
334         { "rxbds_empty" },
335         { "rx_discards" },
336         { "rx_errors" },
337         { "rx_threshold_hit" },
338
339         { "dma_readq_full" },
340         { "dma_read_prioq_full" },
341         { "tx_comp_queue_full" },
342
343         { "ring_set_send_prod_index" },
344         { "ring_status_update" },
345         { "nic_irqs" },
346         { "nic_avoided_irqs" },
347         { "nic_tx_threshold_hit" }
348 };
349
350 static struct {
351         const char string[ETH_GSTRING_LEN];
352 } ethtool_test_keys[TG3_NUM_TEST] = {
353         { "nvram test     (online) " },
354         { "link test      (online) " },
355         { "register test  (offline)" },
356         { "memory test    (offline)" },
357         { "loopback test  (offline)" },
358         { "interrupt test (offline)" },
359 };
360
361 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
362 {
363         writel(val, tp->regs + off);
364 }
365
366 static u32 tg3_read32(struct tg3 *tp, u32 off)
367 {
368         return (readl(tp->regs + off)); 
369 }
370
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372 {
373         unsigned long flags;
374
375         spin_lock_irqsave(&tp->indirect_lock, flags);
376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
379 }
380
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384         readl(tp->regs + off);
385 }
386
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
388 {
389         unsigned long flags;
390         u32 val;
391
392         spin_lock_irqsave(&tp->indirect_lock, flags);
393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
396         return val;
397 }
398
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400 {
401         unsigned long flags;
402
403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405                                        TG3_64BIT_REG_LOW, val);
406                 return;
407         }
408         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410                                        TG3_64BIT_REG_LOW, val);
411                 return;
412         }
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419         /* In indirect mode when disabling interrupts, we also need
420          * to clear the interrupt bit in the GRC local ctrl register.
421          */
422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423             (val == 0x1)) {
424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426         }
427 }
428
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430 {
431         unsigned long flags;
432         u32 val;
433
434         spin_lock_irqsave(&tp->indirect_lock, flags);
435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
438         return val;
439 }
440
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442  * where it is unsafe to read back the register without some delay.
443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445  */
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
447 {
448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450                 /* Non-posted methods */
451                 tp->write32(tp, off, val);
452         else {
453                 /* Posted method */
454                 tg3_write32(tp, off, val);
455                 if (usec_wait)
456                         udelay(usec_wait);
457                 tp->read32(tp, off);
458         }
459         /* Wait again after the read for the posted method to guarantee that
460          * the wait time is met.
461          */
462         if (usec_wait)
463                 udelay(usec_wait);
464 }
465
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467 {
468         tp->write32_mbox(tp, off, val);
469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471                 tp->read32_mbox(tp, off);
472 }
473
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
475 {
476         void __iomem *mbox = tp->regs + off;
477         writel(val, mbox);
478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479                 writel(val, mbox);
480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481                 readl(mbox);
482 }
483
484 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
485 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
486 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
487 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
488 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
489
490 #define tw32(reg,val)           tp->write32(tp, reg, val)
491 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
493 #define tr32(reg)               tp->read32(tp, reg)
494
495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
496 {
497         unsigned long flags;
498
499         spin_lock_irqsave(&tp->indirect_lock, flags);
500         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
501         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
502
503         /* Always leave this as zero. */
504         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
505         spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 }
507
508 static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
509 {
510         /* If no workaround is needed, write to mem space directly */
511         if (tp->write32 != tg3_write_indirect_reg32)
512                 tw32(NIC_SRAM_WIN_BASE + off, val);
513         else
514                 tg3_write_mem(tp, off, val);
515 }
516
517 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
518 {
519         unsigned long flags;
520
521         spin_lock_irqsave(&tp->indirect_lock, flags);
522         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525         /* Always leave this as zero. */
526         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
528 }
529
530 static void tg3_disable_ints(struct tg3 *tp)
531 {
532         tw32(TG3PCI_MISC_HOST_CTRL,
533              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
534         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
535 }
536
537 static inline void tg3_cond_int(struct tg3 *tp)
538 {
539         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
540             (tp->hw_status->status & SD_STATUS_UPDATED))
541                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
542 }
543
544 static void tg3_enable_ints(struct tg3 *tp)
545 {
546         tp->irq_sync = 0;
547         wmb();
548
549         tw32(TG3PCI_MISC_HOST_CTRL,
550              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
551         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
552                        (tp->last_tag << 24));
553         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
554                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
555                                (tp->last_tag << 24));
556         tg3_cond_int(tp);
557 }
558
559 static inline unsigned int tg3_has_work(struct tg3 *tp)
560 {
561         struct tg3_hw_status *sblk = tp->hw_status;
562         unsigned int work_exists = 0;
563
564         /* check for phy events */
565         if (!(tp->tg3_flags &
566               (TG3_FLAG_USE_LINKCHG_REG |
567                TG3_FLAG_POLL_SERDES))) {
568                 if (sblk->status & SD_STATUS_LINK_CHG)
569                         work_exists = 1;
570         }
571         /* check for RX/TX work to do */
572         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
573             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
574                 work_exists = 1;
575
576         return work_exists;
577 }
578
579 /* tg3_restart_ints
580  *  similar to tg3_enable_ints, but it accurately determines whether there
581  *  is new work pending and can return without flushing the PIO write
582  *  which reenables interrupts 
583  */
584 static void tg3_restart_ints(struct tg3 *tp)
585 {
586         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
587                      tp->last_tag << 24);
588         mmiowb();
589
590         /* When doing tagged status, this work check is unnecessary.
591          * The last_tag we write above tells the chip which piece of
592          * work we've completed.
593          */
594         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
595             tg3_has_work(tp))
596                 tw32(HOSTCC_MODE, tp->coalesce_mode |
597                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
598 }
599
600 static inline void tg3_netif_stop(struct tg3 *tp)
601 {
602         tp->dev->trans_start = jiffies; /* prevent tx timeout */
603         netif_poll_disable(tp->dev);
604         netif_tx_disable(tp->dev);
605 }
606
607 static inline void tg3_netif_start(struct tg3 *tp)
608 {
609         netif_wake_queue(tp->dev);
610         /* NOTE: unconditional netif_wake_queue is only appropriate
611          * so long as all callers are assured to have free tx slots
612          * (such as after tg3_init_hw)
613          */
614         netif_poll_enable(tp->dev);
615         tp->hw_status->status |= SD_STATUS_UPDATED;
616         tg3_enable_ints(tp);
617 }
618
619 static void tg3_switch_clocks(struct tg3 *tp)
620 {
621         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
622         u32 orig_clock_ctrl;
623
624         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
625                 return;
626
627         orig_clock_ctrl = clock_ctrl;
628         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
629                        CLOCK_CTRL_CLKRUN_OENABLE |
630                        0x1f);
631         tp->pci_clock_ctrl = clock_ctrl;
632
633         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
634                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
635                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
636                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
637                 }
638         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
639                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
640                             clock_ctrl |
641                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
642                             40);
643                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
644                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
645                             40);
646         }
647         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
648 }
649
650 #define PHY_BUSY_LOOPS  5000
651
652 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
653 {
654         u32 frame_val;
655         unsigned int loops;
656         int ret;
657
658         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
659                 tw32_f(MAC_MI_MODE,
660                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
661                 udelay(80);
662         }
663
664         *val = 0x0;
665
666         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
667                       MI_COM_PHY_ADDR_MASK);
668         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
669                       MI_COM_REG_ADDR_MASK);
670         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
671         
672         tw32_f(MAC_MI_COM, frame_val);
673
674         loops = PHY_BUSY_LOOPS;
675         while (loops != 0) {
676                 udelay(10);
677                 frame_val = tr32(MAC_MI_COM);
678
679                 if ((frame_val & MI_COM_BUSY) == 0) {
680                         udelay(5);
681                         frame_val = tr32(MAC_MI_COM);
682                         break;
683                 }
684                 loops -= 1;
685         }
686
687         ret = -EBUSY;
688         if (loops != 0) {
689                 *val = frame_val & MI_COM_DATA_MASK;
690                 ret = 0;
691         }
692
693         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
694                 tw32_f(MAC_MI_MODE, tp->mi_mode);
695                 udelay(80);
696         }
697
698         return ret;
699 }
700
701 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
702 {
703         u32 frame_val;
704         unsigned int loops;
705         int ret;
706
707         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
708                 tw32_f(MAC_MI_MODE,
709                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
710                 udelay(80);
711         }
712
713         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
714                       MI_COM_PHY_ADDR_MASK);
715         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
716                       MI_COM_REG_ADDR_MASK);
717         frame_val |= (val & MI_COM_DATA_MASK);
718         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
719         
720         tw32_f(MAC_MI_COM, frame_val);
721
722         loops = PHY_BUSY_LOOPS;
723         while (loops != 0) {
724                 udelay(10);
725                 frame_val = tr32(MAC_MI_COM);
726                 if ((frame_val & MI_COM_BUSY) == 0) {
727                         udelay(5);
728                         frame_val = tr32(MAC_MI_COM);
729                         break;
730                 }
731                 loops -= 1;
732         }
733
734         ret = -EBUSY;
735         if (loops != 0)
736                 ret = 0;
737
738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739                 tw32_f(MAC_MI_MODE, tp->mi_mode);
740                 udelay(80);
741         }
742
743         return ret;
744 }
745
746 static void tg3_phy_set_wirespeed(struct tg3 *tp)
747 {
748         u32 val;
749
750         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
751                 return;
752
753         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
754             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
755                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
756                              (val | (1 << 15) | (1 << 4)));
757 }
758
759 static int tg3_bmcr_reset(struct tg3 *tp)
760 {
761         u32 phy_control;
762         int limit, err;
763
764         /* OK, reset it, and poll the BMCR_RESET bit until it
765          * clears or we time out.
766          */
767         phy_control = BMCR_RESET;
768         err = tg3_writephy(tp, MII_BMCR, phy_control);
769         if (err != 0)
770                 return -EBUSY;
771
772         limit = 5000;
773         while (limit--) {
774                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
775                 if (err != 0)
776                         return -EBUSY;
777
778                 if ((phy_control & BMCR_RESET) == 0) {
779                         udelay(40);
780                         break;
781                 }
782                 udelay(10);
783         }
784         if (limit <= 0)
785                 return -EBUSY;
786
787         return 0;
788 }
789
790 static int tg3_wait_macro_done(struct tg3 *tp)
791 {
792         int limit = 100;
793
794         while (limit--) {
795                 u32 tmp32;
796
797                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
798                         if ((tmp32 & 0x1000) == 0)
799                                 break;
800                 }
801         }
802         if (limit <= 0)
803                 return -EBUSY;
804
805         return 0;
806 }
807
808 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
809 {
810         static const u32 test_pat[4][6] = {
811         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
812         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
813         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
814         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
815         };
816         int chan;
817
818         for (chan = 0; chan < 4; chan++) {
819                 int i;
820
821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
822                              (chan * 0x2000) | 0x0200);
823                 tg3_writephy(tp, 0x16, 0x0002);
824
825                 for (i = 0; i < 6; i++)
826                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
827                                      test_pat[chan][i]);
828
829                 tg3_writephy(tp, 0x16, 0x0202);
830                 if (tg3_wait_macro_done(tp)) {
831                         *resetp = 1;
832                         return -EBUSY;
833                 }
834
835                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
836                              (chan * 0x2000) | 0x0200);
837                 tg3_writephy(tp, 0x16, 0x0082);
838                 if (tg3_wait_macro_done(tp)) {
839                         *resetp = 1;
840                         return -EBUSY;
841                 }
842
843                 tg3_writephy(tp, 0x16, 0x0802);
844                 if (tg3_wait_macro_done(tp)) {
845                         *resetp = 1;
846                         return -EBUSY;
847                 }
848
849                 for (i = 0; i < 6; i += 2) {
850                         u32 low, high;
851
852                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
853                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
854                             tg3_wait_macro_done(tp)) {
855                                 *resetp = 1;
856                                 return -EBUSY;
857                         }
858                         low &= 0x7fff;
859                         high &= 0x000f;
860                         if (low != test_pat[chan][i] ||
861                             high != test_pat[chan][i+1]) {
862                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
863                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
864                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
865
866                                 return -EBUSY;
867                         }
868                 }
869         }
870
871         return 0;
872 }
873
874 static int tg3_phy_reset_chanpat(struct tg3 *tp)
875 {
876         int chan;
877
878         for (chan = 0; chan < 4; chan++) {
879                 int i;
880
881                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
882                              (chan * 0x2000) | 0x0200);
883                 tg3_writephy(tp, 0x16, 0x0002);
884                 for (i = 0; i < 6; i++)
885                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
886                 tg3_writephy(tp, 0x16, 0x0202);
887                 if (tg3_wait_macro_done(tp))
888                         return -EBUSY;
889         }
890
891         return 0;
892 }
893
894 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
895 {
896         u32 reg32, phy9_orig;
897         int retries, do_phy_reset, err;
898
899         retries = 10;
900         do_phy_reset = 1;
901         do {
902                 if (do_phy_reset) {
903                         err = tg3_bmcr_reset(tp);
904                         if (err)
905                                 return err;
906                         do_phy_reset = 0;
907                 }
908
909                 /* Disable transmitter and interrupt.  */
910                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
911                         continue;
912
913                 reg32 |= 0x3000;
914                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
915
916                 /* Set full-duplex, 1000 mbps.  */
917                 tg3_writephy(tp, MII_BMCR,
918                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
919
920                 /* Set to master mode.  */
921                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
922                         continue;
923
924                 tg3_writephy(tp, MII_TG3_CTRL,
925                              (MII_TG3_CTRL_AS_MASTER |
926                               MII_TG3_CTRL_ENABLE_AS_MASTER));
927
928                 /* Enable SM_DSP_CLOCK and 6dB.  */
929                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
930
931                 /* Block the PHY control access.  */
932                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
933                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
934
935                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
936                 if (!err)
937                         break;
938         } while (--retries);
939
940         err = tg3_phy_reset_chanpat(tp);
941         if (err)
942                 return err;
943
944         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
945         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
946
947         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
948         tg3_writephy(tp, 0x16, 0x0000);
949
950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
952                 /* Set Extended packet length bit for jumbo frames */
953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
954         }
955         else {
956                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
957         }
958
959         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
960
961         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
962                 reg32 &= ~0x3000;
963                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
964         } else if (!err)
965                 err = -EBUSY;
966
967         return err;
968 }
969
970 /* This will reset the tigon3 PHY if there is no valid
971  * link unless the FORCE argument is non-zero.
972  */
973 static int tg3_phy_reset(struct tg3 *tp)
974 {
975         u32 phy_status;
976         int err;
977
978         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
979         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
980         if (err != 0)
981                 return -EBUSY;
982
983         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
986                 err = tg3_phy_reset_5703_4_5(tp);
987                 if (err)
988                         return err;
989                 goto out;
990         }
991
992         err = tg3_bmcr_reset(tp);
993         if (err)
994                 return err;
995
996 out:
997         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
998                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
999                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1000                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1001                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1002                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1003                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1004         }
1005         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1006                 tg3_writephy(tp, 0x1c, 0x8d68);
1007                 tg3_writephy(tp, 0x1c, 0x8d68);
1008         }
1009         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1010                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1011                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1012                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1014                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1015                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1016                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1018         }
1019         /* Set Extended packet length bit (bit 14) on all chips that */
1020         /* support jumbo frames */
1021         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1022                 /* Cannot do read-modify-write on 5401 */
1023                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1024         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1025                 u32 phy_reg;
1026
1027                 /* Set bit 14 with read-modify-write to preserve other bits */
1028                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1029                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1030                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1031         }
1032
1033         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1034          * jumbo frames transmission.
1035          */
1036         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1037                 u32 phy_reg;
1038
1039                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1040                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1041                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1042         }
1043
1044         tg3_phy_set_wirespeed(tp);
1045         return 0;
1046 }
1047
1048 static void tg3_frob_aux_power(struct tg3 *tp)
1049 {
1050         struct tg3 *tp_peer = tp;
1051
1052         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1053                 return;
1054
1055         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1056             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1057                 struct net_device *dev_peer;
1058
1059                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1060                 /* remove_one() may have been run on the peer. */
1061                 if (!dev_peer)
1062                         tp_peer = tp;
1063                 else
1064                         tp_peer = netdev_priv(dev_peer);
1065         }
1066
1067         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1068             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1069             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1070             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1071                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1072                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1073                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1074                                     (GRC_LCLCTRL_GPIO_OE0 |
1075                                      GRC_LCLCTRL_GPIO_OE1 |
1076                                      GRC_LCLCTRL_GPIO_OE2 |
1077                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1078                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1079                                     100);
1080                 } else {
1081                         u32 no_gpio2;
1082                         u32 grc_local_ctrl = 0;
1083
1084                         if (tp_peer != tp &&
1085                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1086                                 return;
1087
1088                         /* Workaround to prevent overdrawing Amps. */
1089                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1090                             ASIC_REV_5714) {
1091                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1092                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1093                                             grc_local_ctrl, 100);
1094                         }
1095
1096                         /* On 5753 and variants, GPIO2 cannot be used. */
1097                         no_gpio2 = tp->nic_sram_data_cfg &
1098                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1099
1100                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1101                                          GRC_LCLCTRL_GPIO_OE1 |
1102                                          GRC_LCLCTRL_GPIO_OE2 |
1103                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1104                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1105                         if (no_gpio2) {
1106                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1107                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1108                         }
1109                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1110                                                     grc_local_ctrl, 100);
1111
1112                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1113
1114                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1115                                                     grc_local_ctrl, 100);
1116
1117                         if (!no_gpio2) {
1118                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1119                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1120                                             grc_local_ctrl, 100);
1121                         }
1122                 }
1123         } else {
1124                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1125                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1126                         if (tp_peer != tp &&
1127                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1128                                 return;
1129
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                     (GRC_LCLCTRL_GPIO_OE1 |
1132                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1133
1134                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1135                                     GRC_LCLCTRL_GPIO_OE1, 100);
1136
1137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1138                                     (GRC_LCLCTRL_GPIO_OE1 |
1139                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1140                 }
1141         }
1142 }
1143
1144 static int tg3_setup_phy(struct tg3 *, int);
1145
1146 #define RESET_KIND_SHUTDOWN     0
1147 #define RESET_KIND_INIT         1
1148 #define RESET_KIND_SUSPEND      2
1149
1150 static void tg3_write_sig_post_reset(struct tg3 *, int);
1151 static int tg3_halt_cpu(struct tg3 *, u32);
1152 static int tg3_nvram_lock(struct tg3 *);
1153 static void tg3_nvram_unlock(struct tg3 *);
1154
1155 static void tg3_power_down_phy(struct tg3 *tp)
1156 {
1157         /* The PHY should not be powered down on some chips because
1158          * of bugs.
1159          */
1160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1162             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1163              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1164                 return;
1165         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1166 }
1167
1168 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1169 {
1170         u32 misc_host_ctrl;
1171         u16 power_control, power_caps;
1172         int pm = tp->pm_cap;
1173
1174         /* Make sure register accesses (indirect or otherwise)
1175          * will function correctly.
1176          */
1177         pci_write_config_dword(tp->pdev,
1178                                TG3PCI_MISC_HOST_CTRL,
1179                                tp->misc_host_ctrl);
1180
1181         pci_read_config_word(tp->pdev,
1182                              pm + PCI_PM_CTRL,
1183                              &power_control);
1184         power_control |= PCI_PM_CTRL_PME_STATUS;
1185         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1186         switch (state) {
1187         case PCI_D0:
1188                 power_control |= 0;
1189                 pci_write_config_word(tp->pdev,
1190                                       pm + PCI_PM_CTRL,
1191                                       power_control);
1192                 udelay(100);    /* Delay after power state change */
1193
1194                 /* Switch out of Vaux if it is not a LOM */
1195                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1196                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1197
1198                 return 0;
1199
1200         case PCI_D1:
1201                 power_control |= 1;
1202                 break;
1203
1204         case PCI_D2:
1205                 power_control |= 2;
1206                 break;
1207
1208         case PCI_D3hot:
1209                 power_control |= 3;
1210                 break;
1211
1212         default:
1213                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1214                        "requested.\n",
1215                        tp->dev->name, state);
1216                 return -EINVAL;
1217         };
1218
1219         power_control |= PCI_PM_CTRL_PME_ENABLE;
1220
1221         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1222         tw32(TG3PCI_MISC_HOST_CTRL,
1223              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1224
1225         if (tp->link_config.phy_is_low_power == 0) {
1226                 tp->link_config.phy_is_low_power = 1;
1227                 tp->link_config.orig_speed = tp->link_config.speed;
1228                 tp->link_config.orig_duplex = tp->link_config.duplex;
1229                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1230         }
1231
1232         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1233                 tp->link_config.speed = SPEED_10;
1234                 tp->link_config.duplex = DUPLEX_HALF;
1235                 tp->link_config.autoneg = AUTONEG_ENABLE;
1236                 tg3_setup_phy(tp, 0);
1237         }
1238
1239         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1240                 int i;
1241                 u32 val;
1242
1243                 for (i = 0; i < 200; i++) {
1244                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1245                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1246                                 break;
1247                         msleep(1);
1248                 }
1249         }
1250         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1251                                              WOL_DRV_STATE_SHUTDOWN |
1252                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1253
1254         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1255
1256         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1257                 u32 mac_mode;
1258
1259                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1260                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1261                         udelay(40);
1262
1263                         mac_mode = MAC_MODE_PORT_MODE_MII;
1264
1265                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1266                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1267                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1268                 } else {
1269                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1270                 }
1271
1272                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1273                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1274
1275                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1276                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1277                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1278
1279                 tw32_f(MAC_MODE, mac_mode);
1280                 udelay(100);
1281
1282                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1283                 udelay(10);
1284         }
1285
1286         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1287             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1288              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1289                 u32 base_val;
1290
1291                 base_val = tp->pci_clock_ctrl;
1292                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1293                              CLOCK_CTRL_TXCLK_DISABLE);
1294
1295                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1296                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1297         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1298                 /* do nothing */
1299         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1300                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1301                 u32 newbits1, newbits2;
1302
1303                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1304                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1305                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1306                                     CLOCK_CTRL_TXCLK_DISABLE |
1307                                     CLOCK_CTRL_ALTCLK);
1308                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1309                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1310                         newbits1 = CLOCK_CTRL_625_CORE;
1311                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1312                 } else {
1313                         newbits1 = CLOCK_CTRL_ALTCLK;
1314                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1315                 }
1316
1317                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1318                             40);
1319
1320                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1321                             40);
1322
1323                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1324                         u32 newbits3;
1325
1326                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1327                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1328                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1329                                             CLOCK_CTRL_TXCLK_DISABLE |
1330                                             CLOCK_CTRL_44MHZ_CORE);
1331                         } else {
1332                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1333                         }
1334
1335                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1336                                     tp->pci_clock_ctrl | newbits3, 40);
1337                 }
1338         }
1339
1340         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1341             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1342                 /* Turn off the PHY */
1343                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1344                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1345                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1346                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1347                         tg3_power_down_phy(tp);
1348                 }
1349         }
1350
1351         tg3_frob_aux_power(tp);
1352
1353         /* Workaround for unstable PLL clock */
1354         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1355             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1356                 u32 val = tr32(0x7d00);
1357
1358                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1359                 tw32(0x7d00, val);
1360                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1361                         int err;
1362
1363                         err = tg3_nvram_lock(tp);
1364                         tg3_halt_cpu(tp, RX_CPU_BASE);
1365                         if (!err)
1366                                 tg3_nvram_unlock(tp);
1367                 }
1368         }
1369
1370         /* Finally, set the new power state. */
1371         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1372         udelay(100);    /* Delay after power state change */
1373
1374         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1375
1376         return 0;
1377 }
1378
1379 static void tg3_link_report(struct tg3 *tp)
1380 {
1381         if (!netif_carrier_ok(tp->dev)) {
1382                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1383         } else {
1384                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1385                        tp->dev->name,
1386                        (tp->link_config.active_speed == SPEED_1000 ?
1387                         1000 :
1388                         (tp->link_config.active_speed == SPEED_100 ?
1389                          100 : 10)),
1390                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1391                         "full" : "half"));
1392
1393                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1394                        "%s for RX.\n",
1395                        tp->dev->name,
1396                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1397                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1398         }
1399 }
1400
1401 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1402 {
1403         u32 new_tg3_flags = 0;
1404         u32 old_rx_mode = tp->rx_mode;
1405         u32 old_tx_mode = tp->tx_mode;
1406
1407         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1408
1409                 /* Convert 1000BaseX flow control bits to 1000BaseT
1410                  * bits before resolving flow control.
1411                  */
1412                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1413                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1414                                        ADVERTISE_PAUSE_ASYM);
1415                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1416
1417                         if (local_adv & ADVERTISE_1000XPAUSE)
1418                                 local_adv |= ADVERTISE_PAUSE_CAP;
1419                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1420                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1421                         if (remote_adv & LPA_1000XPAUSE)
1422                                 remote_adv |= LPA_PAUSE_CAP;
1423                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1424                                 remote_adv |= LPA_PAUSE_ASYM;
1425                 }
1426
1427                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1428                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1429                                 if (remote_adv & LPA_PAUSE_CAP)
1430                                         new_tg3_flags |=
1431                                                 (TG3_FLAG_RX_PAUSE |
1432                                                 TG3_FLAG_TX_PAUSE);
1433                                 else if (remote_adv & LPA_PAUSE_ASYM)
1434                                         new_tg3_flags |=
1435                                                 (TG3_FLAG_RX_PAUSE);
1436                         } else {
1437                                 if (remote_adv & LPA_PAUSE_CAP)
1438                                         new_tg3_flags |=
1439                                                 (TG3_FLAG_RX_PAUSE |
1440                                                 TG3_FLAG_TX_PAUSE);
1441                         }
1442                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1443                         if ((remote_adv & LPA_PAUSE_CAP) &&
1444                         (remote_adv & LPA_PAUSE_ASYM))
1445                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1446                 }
1447
1448                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1449                 tp->tg3_flags |= new_tg3_flags;
1450         } else {
1451                 new_tg3_flags = tp->tg3_flags;
1452         }
1453
1454         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1455                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1456         else
1457                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1458
1459         if (old_rx_mode != tp->rx_mode) {
1460                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1461         }
1462         
1463         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1464                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1465         else
1466                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1467
1468         if (old_tx_mode != tp->tx_mode) {
1469                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1470         }
1471 }
1472
1473 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1474 {
1475         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1476         case MII_TG3_AUX_STAT_10HALF:
1477                 *speed = SPEED_10;
1478                 *duplex = DUPLEX_HALF;
1479                 break;
1480
1481         case MII_TG3_AUX_STAT_10FULL:
1482                 *speed = SPEED_10;
1483                 *duplex = DUPLEX_FULL;
1484                 break;
1485
1486         case MII_TG3_AUX_STAT_100HALF:
1487                 *speed = SPEED_100;
1488                 *duplex = DUPLEX_HALF;
1489                 break;
1490
1491         case MII_TG3_AUX_STAT_100FULL:
1492                 *speed = SPEED_100;
1493                 *duplex = DUPLEX_FULL;
1494                 break;
1495
1496         case MII_TG3_AUX_STAT_1000HALF:
1497                 *speed = SPEED_1000;
1498                 *duplex = DUPLEX_HALF;
1499                 break;
1500
1501         case MII_TG3_AUX_STAT_1000FULL:
1502                 *speed = SPEED_1000;
1503                 *duplex = DUPLEX_FULL;
1504                 break;
1505
1506         default:
1507                 *speed = SPEED_INVALID;
1508                 *duplex = DUPLEX_INVALID;
1509                 break;
1510         };
1511 }
1512
1513 static void tg3_phy_copper_begin(struct tg3 *tp)
1514 {
1515         u32 new_adv;
1516         int i;
1517
1518         if (tp->link_config.phy_is_low_power) {
1519                 /* Entering low power mode.  Disable gigabit and
1520                  * 100baseT advertisements.
1521                  */
1522                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1523
1524                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1525                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1526                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1527                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1528
1529                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1530         } else if (tp->link_config.speed == SPEED_INVALID) {
1531                 tp->link_config.advertising =
1532                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1533                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1534                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1535                          ADVERTISED_Autoneg | ADVERTISED_MII);
1536
1537                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1538                         tp->link_config.advertising &=
1539                                 ~(ADVERTISED_1000baseT_Half |
1540                                   ADVERTISED_1000baseT_Full);
1541
1542                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1543                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1544                         new_adv |= ADVERTISE_10HALF;
1545                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1546                         new_adv |= ADVERTISE_10FULL;
1547                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1548                         new_adv |= ADVERTISE_100HALF;
1549                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1550                         new_adv |= ADVERTISE_100FULL;
1551                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1552
1553                 if (tp->link_config.advertising &
1554                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1555                         new_adv = 0;
1556                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1557                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1558                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1559                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1560                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1561                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1562                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1563                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1564                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1565                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1566                 } else {
1567                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1568                 }
1569         } else {
1570                 /* Asking for a specific link mode. */
1571                 if (tp->link_config.speed == SPEED_1000) {
1572                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1573                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1574
1575                         if (tp->link_config.duplex == DUPLEX_FULL)
1576                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1577                         else
1578                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1579                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1580                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1581                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1582                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1583                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1584                 } else {
1585                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1586
1587                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1588                         if (tp->link_config.speed == SPEED_100) {
1589                                 if (tp->link_config.duplex == DUPLEX_FULL)
1590                                         new_adv |= ADVERTISE_100FULL;
1591                                 else
1592                                         new_adv |= ADVERTISE_100HALF;
1593                         } else {
1594                                 if (tp->link_config.duplex == DUPLEX_FULL)
1595                                         new_adv |= ADVERTISE_10FULL;
1596                                 else
1597                                         new_adv |= ADVERTISE_10HALF;
1598                         }
1599                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1600                 }
1601         }
1602
1603         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1604             tp->link_config.speed != SPEED_INVALID) {
1605                 u32 bmcr, orig_bmcr;
1606
1607                 tp->link_config.active_speed = tp->link_config.speed;
1608                 tp->link_config.active_duplex = tp->link_config.duplex;
1609
1610                 bmcr = 0;
1611                 switch (tp->link_config.speed) {
1612                 default:
1613                 case SPEED_10:
1614                         break;
1615
1616                 case SPEED_100:
1617                         bmcr |= BMCR_SPEED100;
1618                         break;
1619
1620                 case SPEED_1000:
1621                         bmcr |= TG3_BMCR_SPEED1000;
1622                         break;
1623                 };
1624
1625                 if (tp->link_config.duplex == DUPLEX_FULL)
1626                         bmcr |= BMCR_FULLDPLX;
1627
1628                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1629                     (bmcr != orig_bmcr)) {
1630                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1631                         for (i = 0; i < 1500; i++) {
1632                                 u32 tmp;
1633
1634                                 udelay(10);
1635                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1636                                     tg3_readphy(tp, MII_BMSR, &tmp))
1637                                         continue;
1638                                 if (!(tmp & BMSR_LSTATUS)) {
1639                                         udelay(40);
1640                                         break;
1641                                 }
1642                         }
1643                         tg3_writephy(tp, MII_BMCR, bmcr);
1644                         udelay(40);
1645                 }
1646         } else {
1647                 tg3_writephy(tp, MII_BMCR,
1648                              BMCR_ANENABLE | BMCR_ANRESTART);
1649         }
1650 }
1651
1652 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1653 {
1654         int err;
1655
1656         /* Turn off tap power management. */
1657         /* Set Extended packet length bit */
1658         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1659
1660         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1661         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1662
1663         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1664         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1665
1666         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1667         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1668
1669         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1670         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1671
1672         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1673         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1674
1675         udelay(40);
1676
1677         return err;
1678 }
1679
1680 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1681 {
1682         u32 adv_reg, all_mask;
1683
1684         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1685                 return 0;
1686
1687         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1688                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1689         if ((adv_reg & all_mask) != all_mask)
1690                 return 0;
1691         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1692                 u32 tg3_ctrl;
1693
1694                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1695                         return 0;
1696
1697                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1698                             MII_TG3_CTRL_ADV_1000_FULL);
1699                 if ((tg3_ctrl & all_mask) != all_mask)
1700                         return 0;
1701         }
1702         return 1;
1703 }
1704
1705 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1706 {
1707         int current_link_up;
1708         u32 bmsr, dummy;
1709         u16 current_speed;
1710         u8 current_duplex;
1711         int i, err;
1712
1713         tw32(MAC_EVENT, 0);
1714
1715         tw32_f(MAC_STATUS,
1716              (MAC_STATUS_SYNC_CHANGED |
1717               MAC_STATUS_CFG_CHANGED |
1718               MAC_STATUS_MI_COMPLETION |
1719               MAC_STATUS_LNKSTATE_CHANGED));
1720         udelay(40);
1721
1722         tp->mi_mode = MAC_MI_MODE_BASE;
1723         tw32_f(MAC_MI_MODE, tp->mi_mode);
1724         udelay(80);
1725
1726         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1727
1728         /* Some third-party PHYs need to be reset on link going
1729          * down.
1730          */
1731         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1732              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1733              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1734             netif_carrier_ok(tp->dev)) {
1735                 tg3_readphy(tp, MII_BMSR, &bmsr);
1736                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1737                     !(bmsr & BMSR_LSTATUS))
1738                         force_reset = 1;
1739         }
1740         if (force_reset)
1741                 tg3_phy_reset(tp);
1742
1743         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1744                 tg3_readphy(tp, MII_BMSR, &bmsr);
1745                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1746                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1747                         bmsr = 0;
1748
1749                 if (!(bmsr & BMSR_LSTATUS)) {
1750                         err = tg3_init_5401phy_dsp(tp);
1751                         if (err)
1752                                 return err;
1753
1754                         tg3_readphy(tp, MII_BMSR, &bmsr);
1755                         for (i = 0; i < 1000; i++) {
1756                                 udelay(10);
1757                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1758                                     (bmsr & BMSR_LSTATUS)) {
1759                                         udelay(40);
1760                                         break;
1761                                 }
1762                         }
1763
1764                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1765                             !(bmsr & BMSR_LSTATUS) &&
1766                             tp->link_config.active_speed == SPEED_1000) {
1767                                 err = tg3_phy_reset(tp);
1768                                 if (!err)
1769                                         err = tg3_init_5401phy_dsp(tp);
1770                                 if (err)
1771                                         return err;
1772                         }
1773                 }
1774         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1775                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1776                 /* 5701 {A0,B0} CRC bug workaround */
1777                 tg3_writephy(tp, 0x15, 0x0a75);
1778                 tg3_writephy(tp, 0x1c, 0x8c68);
1779                 tg3_writephy(tp, 0x1c, 0x8d68);
1780                 tg3_writephy(tp, 0x1c, 0x8c68);
1781         }
1782
1783         /* Clear pending interrupts... */
1784         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1785         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1786
1787         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1788                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1789         else
1790                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1791
1792         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1793             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1794                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1795                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1796                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1797                 else
1798                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1799         }
1800
1801         current_link_up = 0;
1802         current_speed = SPEED_INVALID;
1803         current_duplex = DUPLEX_INVALID;
1804
1805         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1806                 u32 val;
1807
1808                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1809                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1810                 if (!(val & (1 << 10))) {
1811                         val |= (1 << 10);
1812                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1813                         goto relink;
1814                 }
1815         }
1816
1817         bmsr = 0;
1818         for (i = 0; i < 100; i++) {
1819                 tg3_readphy(tp, MII_BMSR, &bmsr);
1820                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1821                     (bmsr & BMSR_LSTATUS))
1822                         break;
1823                 udelay(40);
1824         }
1825
1826         if (bmsr & BMSR_LSTATUS) {
1827                 u32 aux_stat, bmcr;
1828
1829                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1830                 for (i = 0; i < 2000; i++) {
1831                         udelay(10);
1832                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1833                             aux_stat)
1834                                 break;
1835                 }
1836
1837                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1838                                              &current_speed,
1839                                              &current_duplex);
1840
1841                 bmcr = 0;
1842                 for (i = 0; i < 200; i++) {
1843                         tg3_readphy(tp, MII_BMCR, &bmcr);
1844                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1845                                 continue;
1846                         if (bmcr && bmcr != 0x7fff)
1847                                 break;
1848                         udelay(10);
1849                 }
1850
1851                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1852                         if (bmcr & BMCR_ANENABLE) {
1853                                 current_link_up = 1;
1854
1855                                 /* Force autoneg restart if we are exiting
1856                                  * low power mode.
1857                                  */
1858                                 if (!tg3_copper_is_advertising_all(tp))
1859                                         current_link_up = 0;
1860                         } else {
1861                                 current_link_up = 0;
1862                         }
1863                 } else {
1864                         if (!(bmcr & BMCR_ANENABLE) &&
1865                             tp->link_config.speed == current_speed &&
1866                             tp->link_config.duplex == current_duplex) {
1867                                 current_link_up = 1;
1868                         } else {
1869                                 current_link_up = 0;
1870                         }
1871                 }
1872
1873                 tp->link_config.active_speed = current_speed;
1874                 tp->link_config.active_duplex = current_duplex;
1875         }
1876
1877         if (current_link_up == 1 &&
1878             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1879             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1880                 u32 local_adv, remote_adv;
1881
1882                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1883                         local_adv = 0;
1884                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1885
1886                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1887                         remote_adv = 0;
1888
1889                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1890
1891                 /* If we are not advertising full pause capability,
1892                  * something is wrong.  Bring the link down and reconfigure.
1893                  */
1894                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1895                         current_link_up = 0;
1896                 } else {
1897                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1898                 }
1899         }
1900 relink:
1901         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1902                 u32 tmp;
1903
1904                 tg3_phy_copper_begin(tp);
1905
1906                 tg3_readphy(tp, MII_BMSR, &tmp);
1907                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1908                     (tmp & BMSR_LSTATUS))
1909                         current_link_up = 1;
1910         }
1911
1912         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1913         if (current_link_up == 1) {
1914                 if (tp->link_config.active_speed == SPEED_100 ||
1915                     tp->link_config.active_speed == SPEED_10)
1916                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1917                 else
1918                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1919         } else
1920                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1921
1922         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1923         if (tp->link_config.active_duplex == DUPLEX_HALF)
1924                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1925
1926         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1928                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1929                     (current_link_up == 1 &&
1930                      tp->link_config.active_speed == SPEED_10))
1931                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1932         } else {
1933                 if (current_link_up == 1)
1934                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1935         }
1936
1937         /* ??? Without this setting Netgear GA302T PHY does not
1938          * ??? send/receive packets...
1939          */
1940         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1941             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1942                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1943                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1944                 udelay(80);
1945         }
1946
1947         tw32_f(MAC_MODE, tp->mac_mode);
1948         udelay(40);
1949
1950         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1951                 /* Polled via timer. */
1952                 tw32_f(MAC_EVENT, 0);
1953         } else {
1954                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1955         }
1956         udelay(40);
1957
1958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1959             current_link_up == 1 &&
1960             tp->link_config.active_speed == SPEED_1000 &&
1961             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1962              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1963                 udelay(120);
1964                 tw32_f(MAC_STATUS,
1965                      (MAC_STATUS_SYNC_CHANGED |
1966                       MAC_STATUS_CFG_CHANGED));
1967                 udelay(40);
1968                 tg3_write_mem(tp,
1969                               NIC_SRAM_FIRMWARE_MBOX,
1970                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1971         }
1972
1973         if (current_link_up != netif_carrier_ok(tp->dev)) {
1974                 if (current_link_up)
1975                         netif_carrier_on(tp->dev);
1976                 else
1977                         netif_carrier_off(tp->dev);
1978                 tg3_link_report(tp);
1979         }
1980
1981         return 0;
1982 }
1983
1984 struct tg3_fiber_aneginfo {
1985         int state;
1986 #define ANEG_STATE_UNKNOWN              0
1987 #define ANEG_STATE_AN_ENABLE            1
1988 #define ANEG_STATE_RESTART_INIT         2
1989 #define ANEG_STATE_RESTART              3
1990 #define ANEG_STATE_DISABLE_LINK_OK      4
1991 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1992 #define ANEG_STATE_ABILITY_DETECT       6
1993 #define ANEG_STATE_ACK_DETECT_INIT      7
1994 #define ANEG_STATE_ACK_DETECT           8
1995 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1996 #define ANEG_STATE_COMPLETE_ACK         10
1997 #define ANEG_STATE_IDLE_DETECT_INIT     11
1998 #define ANEG_STATE_IDLE_DETECT          12
1999 #define ANEG_STATE_LINK_OK              13
2000 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2001 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2002
2003         u32 flags;
2004 #define MR_AN_ENABLE            0x00000001
2005 #define MR_RESTART_AN           0x00000002
2006 #define MR_AN_COMPLETE          0x00000004
2007 #define MR_PAGE_RX              0x00000008
2008 #define MR_NP_LOADED            0x00000010
2009 #define MR_TOGGLE_TX            0x00000020
2010 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2011 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2012 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2013 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2014 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2015 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2016 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2017 #define MR_TOGGLE_RX            0x00002000
2018 #define MR_NP_RX                0x00004000
2019
2020 #define MR_LINK_OK              0x80000000
2021
2022         unsigned long link_time, cur_time;
2023
2024         u32 ability_match_cfg;
2025         int ability_match_count;
2026
2027         char ability_match, idle_match, ack_match;
2028
2029         u32 txconfig, rxconfig;
2030 #define ANEG_CFG_NP             0x00000080
2031 #define ANEG_CFG_ACK            0x00000040
2032 #define ANEG_CFG_RF2            0x00000020
2033 #define ANEG_CFG_RF1            0x00000010
2034 #define ANEG_CFG_PS2            0x00000001
2035 #define ANEG_CFG_PS1            0x00008000
2036 #define ANEG_CFG_HD             0x00004000
2037 #define ANEG_CFG_FD             0x00002000
2038 #define ANEG_CFG_INVAL          0x00001f06
2039
2040 };
2041 #define ANEG_OK         0
2042 #define ANEG_DONE       1
2043 #define ANEG_TIMER_ENAB 2
2044 #define ANEG_FAILED     -1
2045
2046 #define ANEG_STATE_SETTLE_TIME  10000
2047
2048 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2049                                    struct tg3_fiber_aneginfo *ap)
2050 {
2051         unsigned long delta;
2052         u32 rx_cfg_reg;
2053         int ret;
2054
2055         if (ap->state == ANEG_STATE_UNKNOWN) {
2056                 ap->rxconfig = 0;
2057                 ap->link_time = 0;
2058                 ap->cur_time = 0;
2059                 ap->ability_match_cfg = 0;
2060                 ap->ability_match_count = 0;
2061                 ap->ability_match = 0;
2062                 ap->idle_match = 0;
2063                 ap->ack_match = 0;
2064         }
2065         ap->cur_time++;
2066
2067         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2068                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2069
2070                 if (rx_cfg_reg != ap->ability_match_cfg) {
2071                         ap->ability_match_cfg = rx_cfg_reg;
2072                         ap->ability_match = 0;
2073                         ap->ability_match_count = 0;
2074                 } else {
2075                         if (++ap->ability_match_count > 1) {
2076                                 ap->ability_match = 1;
2077                                 ap->ability_match_cfg = rx_cfg_reg;
2078                         }
2079                 }
2080                 if (rx_cfg_reg & ANEG_CFG_ACK)
2081                         ap->ack_match = 1;
2082                 else
2083                         ap->ack_match = 0;
2084
2085                 ap->idle_match = 0;
2086         } else {
2087                 ap->idle_match = 1;
2088                 ap->ability_match_cfg = 0;
2089                 ap->ability_match_count = 0;
2090                 ap->ability_match = 0;
2091                 ap->ack_match = 0;
2092
2093                 rx_cfg_reg = 0;
2094         }
2095
2096         ap->rxconfig = rx_cfg_reg;
2097         ret = ANEG_OK;
2098
2099         switch(ap->state) {
2100         case ANEG_STATE_UNKNOWN:
2101                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2102                         ap->state = ANEG_STATE_AN_ENABLE;
2103
2104                 /* fallthru */
2105         case ANEG_STATE_AN_ENABLE:
2106                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2107                 if (ap->flags & MR_AN_ENABLE) {
2108                         ap->link_time = 0;
2109                         ap->cur_time = 0;
2110                         ap->ability_match_cfg = 0;
2111                         ap->ability_match_count = 0;
2112                         ap->ability_match = 0;
2113                         ap->idle_match = 0;
2114                         ap->ack_match = 0;
2115
2116                         ap->state = ANEG_STATE_RESTART_INIT;
2117                 } else {
2118                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2119                 }
2120                 break;
2121
2122         case ANEG_STATE_RESTART_INIT:
2123                 ap->link_time = ap->cur_time;
2124                 ap->flags &= ~(MR_NP_LOADED);
2125                 ap->txconfig = 0;
2126                 tw32(MAC_TX_AUTO_NEG, 0);
2127                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2128                 tw32_f(MAC_MODE, tp->mac_mode);
2129                 udelay(40);
2130
2131                 ret = ANEG_TIMER_ENAB;
2132                 ap->state = ANEG_STATE_RESTART;
2133
2134                 /* fallthru */
2135         case ANEG_STATE_RESTART:
2136                 delta = ap->cur_time - ap->link_time;
2137                 if (delta > ANEG_STATE_SETTLE_TIME) {
2138                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2139                 } else {
2140                         ret = ANEG_TIMER_ENAB;
2141                 }
2142                 break;
2143
2144         case ANEG_STATE_DISABLE_LINK_OK:
2145                 ret = ANEG_DONE;
2146                 break;
2147
2148         case ANEG_STATE_ABILITY_DETECT_INIT:
2149                 ap->flags &= ~(MR_TOGGLE_TX);
2150                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2151                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2152                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2153                 tw32_f(MAC_MODE, tp->mac_mode);
2154                 udelay(40);
2155
2156                 ap->state = ANEG_STATE_ABILITY_DETECT;
2157                 break;
2158
2159         case ANEG_STATE_ABILITY_DETECT:
2160                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2161                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2162                 }
2163                 break;
2164
2165         case ANEG_STATE_ACK_DETECT_INIT:
2166                 ap->txconfig |= ANEG_CFG_ACK;
2167                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2168                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2169                 tw32_f(MAC_MODE, tp->mac_mode);
2170                 udelay(40);
2171
2172                 ap->state = ANEG_STATE_ACK_DETECT;
2173
2174                 /* fallthru */
2175         case ANEG_STATE_ACK_DETECT:
2176                 if (ap->ack_match != 0) {
2177                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2178                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2179                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2180                         } else {
2181                                 ap->state = ANEG_STATE_AN_ENABLE;
2182                         }
2183                 } else if (ap->ability_match != 0 &&
2184                            ap->rxconfig == 0) {
2185                         ap->state = ANEG_STATE_AN_ENABLE;
2186                 }
2187                 break;
2188
2189         case ANEG_STATE_COMPLETE_ACK_INIT:
2190                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2191                         ret = ANEG_FAILED;
2192                         break;
2193                 }
2194                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2195                                MR_LP_ADV_HALF_DUPLEX |
2196                                MR_LP_ADV_SYM_PAUSE |
2197                                MR_LP_ADV_ASYM_PAUSE |
2198                                MR_LP_ADV_REMOTE_FAULT1 |
2199                                MR_LP_ADV_REMOTE_FAULT2 |
2200                                MR_LP_ADV_NEXT_PAGE |
2201                                MR_TOGGLE_RX |
2202                                MR_NP_RX);
2203                 if (ap->rxconfig & ANEG_CFG_FD)
2204                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2205                 if (ap->rxconfig & ANEG_CFG_HD)
2206                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2207                 if (ap->rxconfig & ANEG_CFG_PS1)
2208                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2209                 if (ap->rxconfig & ANEG_CFG_PS2)
2210                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2211                 if (ap->rxconfig & ANEG_CFG_RF1)
2212                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2213                 if (ap->rxconfig & ANEG_CFG_RF2)
2214                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2215                 if (ap->rxconfig & ANEG_CFG_NP)
2216                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2217
2218                 ap->link_time = ap->cur_time;
2219
2220                 ap->flags ^= (MR_TOGGLE_TX);
2221                 if (ap->rxconfig & 0x0008)
2222                         ap->flags |= MR_TOGGLE_RX;
2223                 if (ap->rxconfig & ANEG_CFG_NP)
2224                         ap->flags |= MR_NP_RX;
2225                 ap->flags |= MR_PAGE_RX;
2226
2227                 ap->state = ANEG_STATE_COMPLETE_ACK;
2228                 ret = ANEG_TIMER_ENAB;
2229                 break;
2230
2231         case ANEG_STATE_COMPLETE_ACK:
2232                 if (ap->ability_match != 0 &&
2233                     ap->rxconfig == 0) {
2234                         ap->state = ANEG_STATE_AN_ENABLE;
2235                         break;
2236                 }
2237                 delta = ap->cur_time - ap->link_time;
2238                 if (delta > ANEG_STATE_SETTLE_TIME) {
2239                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2240                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2241                         } else {
2242                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2243                                     !(ap->flags & MR_NP_RX)) {
2244                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2245                                 } else {
2246                                         ret = ANEG_FAILED;
2247                                 }
2248                         }
2249                 }
2250                 break;
2251
2252         case ANEG_STATE_IDLE_DETECT_INIT:
2253                 ap->link_time = ap->cur_time;
2254                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2255                 tw32_f(MAC_MODE, tp->mac_mode);
2256                 udelay(40);
2257
2258                 ap->state = ANEG_STATE_IDLE_DETECT;
2259                 ret = ANEG_TIMER_ENAB;
2260                 break;
2261
2262         case ANEG_STATE_IDLE_DETECT:
2263                 if (ap->ability_match != 0 &&
2264                     ap->rxconfig == 0) {
2265                         ap->state = ANEG_STATE_AN_ENABLE;
2266                         break;
2267                 }
2268                 delta = ap->cur_time - ap->link_time;
2269                 if (delta > ANEG_STATE_SETTLE_TIME) {
2270                         /* XXX another gem from the Broadcom driver :( */
2271                         ap->state = ANEG_STATE_LINK_OK;
2272                 }
2273                 break;
2274
2275         case ANEG_STATE_LINK_OK:
2276                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2277                 ret = ANEG_DONE;
2278                 break;
2279
2280         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2281                 /* ??? unimplemented */
2282                 break;
2283
2284         case ANEG_STATE_NEXT_PAGE_WAIT:
2285                 /* ??? unimplemented */
2286                 break;
2287
2288         default:
2289                 ret = ANEG_FAILED;
2290                 break;
2291         };
2292
2293         return ret;
2294 }
2295
2296 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2297 {
2298         int res = 0;
2299         struct tg3_fiber_aneginfo aninfo;
2300         int status = ANEG_FAILED;
2301         unsigned int tick;
2302         u32 tmp;
2303
2304         tw32_f(MAC_TX_AUTO_NEG, 0);
2305
2306         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2307         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2308         udelay(40);
2309
2310         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2311         udelay(40);
2312
2313         memset(&aninfo, 0, sizeof(aninfo));
2314         aninfo.flags |= MR_AN_ENABLE;
2315         aninfo.state = ANEG_STATE_UNKNOWN;
2316         aninfo.cur_time = 0;
2317         tick = 0;
2318         while (++tick < 195000) {
2319                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2320                 if (status == ANEG_DONE || status == ANEG_FAILED)
2321                         break;
2322
2323                 udelay(1);
2324         }
2325
2326         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2327         tw32_f(MAC_MODE, tp->mac_mode);
2328         udelay(40);
2329
2330         *flags = aninfo.flags;
2331
2332         if (status == ANEG_DONE &&
2333             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2334                              MR_LP_ADV_FULL_DUPLEX)))
2335                 res = 1;
2336
2337         return res;
2338 }
2339
2340 static void tg3_init_bcm8002(struct tg3 *tp)
2341 {
2342         u32 mac_status = tr32(MAC_STATUS);
2343         int i;
2344
2345         /* Reset when initting first time or we have a link. */
2346         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2347             !(mac_status & MAC_STATUS_PCS_SYNCED))
2348                 return;
2349
2350         /* Set PLL lock range. */
2351         tg3_writephy(tp, 0x16, 0x8007);
2352
2353         /* SW reset */
2354         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2355
2356         /* Wait for reset to complete. */
2357         /* XXX schedule_timeout() ... */
2358         for (i = 0; i < 500; i++)
2359                 udelay(10);
2360
2361         /* Config mode; select PMA/Ch 1 regs. */
2362         tg3_writephy(tp, 0x10, 0x8411);
2363
2364         /* Enable auto-lock and comdet, select txclk for tx. */
2365         tg3_writephy(tp, 0x11, 0x0a10);
2366
2367         tg3_writephy(tp, 0x18, 0x00a0);
2368         tg3_writephy(tp, 0x16, 0x41ff);
2369
2370         /* Assert and deassert POR. */
2371         tg3_writephy(tp, 0x13, 0x0400);
2372         udelay(40);
2373         tg3_writephy(tp, 0x13, 0x0000);
2374
2375         tg3_writephy(tp, 0x11, 0x0a50);
2376         udelay(40);
2377         tg3_writephy(tp, 0x11, 0x0a10);
2378
2379         /* Wait for signal to stabilize */
2380         /* XXX schedule_timeout() ... */
2381         for (i = 0; i < 15000; i++)
2382                 udelay(10);
2383
2384         /* Deselect the channel register so we can read the PHYID
2385          * later.
2386          */
2387         tg3_writephy(tp, 0x10, 0x8011);
2388 }
2389
2390 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2391 {
2392         u32 sg_dig_ctrl, sg_dig_status;
2393         u32 serdes_cfg, expected_sg_dig_ctrl;
2394         int workaround, port_a;
2395         int current_link_up;
2396
2397         serdes_cfg = 0;
2398         expected_sg_dig_ctrl = 0;
2399         workaround = 0;
2400         port_a = 1;
2401         current_link_up = 0;
2402
2403         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2404             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2405                 workaround = 1;
2406                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2407                         port_a = 0;
2408
2409                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2410                 /* preserve bits 20-23 for voltage regulator */
2411                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2412         }
2413
2414         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2415
2416         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2417                 if (sg_dig_ctrl & (1 << 31)) {
2418                         if (workaround) {
2419                                 u32 val = serdes_cfg;
2420
2421                                 if (port_a)
2422                                         val |= 0xc010000;
2423                                 else
2424                                         val |= 0x4010000;
2425                                 tw32_f(MAC_SERDES_CFG, val);
2426                         }
2427                         tw32_f(SG_DIG_CTRL, 0x01388400);
2428                 }
2429                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2430                         tg3_setup_flow_control(tp, 0, 0);
2431                         current_link_up = 1;
2432                 }
2433                 goto out;
2434         }
2435
2436         /* Want auto-negotiation.  */
2437         expected_sg_dig_ctrl = 0x81388400;
2438
2439         /* Pause capability */
2440         expected_sg_dig_ctrl |= (1 << 11);
2441
2442         /* Asymettric pause */
2443         expected_sg_dig_ctrl |= (1 << 12);
2444
2445         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2446                 if (workaround)
2447                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2448                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2449                 udelay(5);
2450                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2451
2452                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2453         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2454                                  MAC_STATUS_SIGNAL_DET)) {
2455                 int i;
2456
2457                 /* Giver time to negotiate (~200ms) */
2458                 for (i = 0; i < 40000; i++) {
2459                         sg_dig_status = tr32(SG_DIG_STATUS);
2460                         if (sg_dig_status & (0x3))
2461                                 break;
2462                         udelay(5);
2463                 }
2464                 mac_status = tr32(MAC_STATUS);
2465
2466                 if ((sg_dig_status & (1 << 1)) &&
2467                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2468                         u32 local_adv, remote_adv;
2469
2470                         local_adv = ADVERTISE_PAUSE_CAP;
2471                         remote_adv = 0;
2472                         if (sg_dig_status & (1 << 19))
2473                                 remote_adv |= LPA_PAUSE_CAP;
2474                         if (sg_dig_status & (1 << 20))
2475                                 remote_adv |= LPA_PAUSE_ASYM;
2476
2477                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2478                         current_link_up = 1;
2479                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2480                 } else if (!(sg_dig_status & (1 << 1))) {
2481                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2482                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2483                         else {
2484                                 if (workaround) {
2485                                         u32 val = serdes_cfg;
2486
2487                                         if (port_a)
2488                                                 val |= 0xc010000;
2489                                         else
2490                                                 val |= 0x4010000;
2491
2492                                         tw32_f(MAC_SERDES_CFG, val);
2493                                 }
2494
2495                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2496                                 udelay(40);
2497
2498                                 /* Link parallel detection - link is up */
2499                                 /* only if we have PCS_SYNC and not */
2500                                 /* receiving config code words */
2501                                 mac_status = tr32(MAC_STATUS);
2502                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2503                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2504                                         tg3_setup_flow_control(tp, 0, 0);
2505                                         current_link_up = 1;
2506                                 }
2507                         }
2508                 }
2509         }
2510
2511 out:
2512         return current_link_up;
2513 }
2514
2515 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2516 {
2517         int current_link_up = 0;
2518
2519         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2520                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2521                 goto out;
2522         }
2523
2524         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2525                 u32 flags;
2526                 int i;
2527   
2528                 if (fiber_autoneg(tp, &flags)) {
2529                         u32 local_adv, remote_adv;
2530
2531                         local_adv = ADVERTISE_PAUSE_CAP;
2532                         remote_adv = 0;
2533                         if (flags & MR_LP_ADV_SYM_PAUSE)
2534                                 remote_adv |= LPA_PAUSE_CAP;
2535                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2536                                 remote_adv |= LPA_PAUSE_ASYM;
2537
2538                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2539
2540                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2541                         current_link_up = 1;
2542                 }
2543                 for (i = 0; i < 30; i++) {
2544                         udelay(20);
2545                         tw32_f(MAC_STATUS,
2546                                (MAC_STATUS_SYNC_CHANGED |
2547                                 MAC_STATUS_CFG_CHANGED));
2548                         udelay(40);
2549                         if ((tr32(MAC_STATUS) &
2550                              (MAC_STATUS_SYNC_CHANGED |
2551                               MAC_STATUS_CFG_CHANGED)) == 0)
2552                                 break;
2553                 }
2554
2555                 mac_status = tr32(MAC_STATUS);
2556                 if (current_link_up == 0 &&
2557                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2558                     !(mac_status & MAC_STATUS_RCVD_CFG))
2559                         current_link_up = 1;
2560         } else {
2561                 /* Forcing 1000FD link up. */
2562                 current_link_up = 1;
2563                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2564
2565                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2566                 udelay(40);
2567         }
2568
2569 out:
2570         return current_link_up;
2571 }
2572
2573 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2574 {
2575         u32 orig_pause_cfg;
2576         u16 orig_active_speed;
2577         u8 orig_active_duplex;
2578         u32 mac_status;
2579         int current_link_up;
2580         int i;
2581
2582         orig_pause_cfg =
2583                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2584                                   TG3_FLAG_TX_PAUSE));
2585         orig_active_speed = tp->link_config.active_speed;
2586         orig_active_duplex = tp->link_config.active_duplex;
2587
2588         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2589             netif_carrier_ok(tp->dev) &&
2590             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2591                 mac_status = tr32(MAC_STATUS);
2592                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2593                                MAC_STATUS_SIGNAL_DET |
2594                                MAC_STATUS_CFG_CHANGED |
2595                                MAC_STATUS_RCVD_CFG);
2596                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2597                                    MAC_STATUS_SIGNAL_DET)) {
2598                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2599                                             MAC_STATUS_CFG_CHANGED));
2600                         return 0;
2601                 }
2602         }
2603
2604         tw32_f(MAC_TX_AUTO_NEG, 0);
2605
2606         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2607         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2608         tw32_f(MAC_MODE, tp->mac_mode);
2609         udelay(40);
2610
2611         if (tp->phy_id == PHY_ID_BCM8002)
2612                 tg3_init_bcm8002(tp);
2613
2614         /* Enable link change event even when serdes polling.  */
2615         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2616         udelay(40);
2617
2618         current_link_up = 0;
2619         mac_status = tr32(MAC_STATUS);
2620
2621         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2622                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2623         else
2624                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2625
2626         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2627         tw32_f(MAC_MODE, tp->mac_mode);
2628         udelay(40);
2629
2630         tp->hw_status->status =
2631                 (SD_STATUS_UPDATED |
2632                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2633
2634         for (i = 0; i < 100; i++) {
2635                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2636                                     MAC_STATUS_CFG_CHANGED));
2637                 udelay(5);
2638                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2639                                          MAC_STATUS_CFG_CHANGED)) == 0)
2640                         break;
2641         }
2642
2643         mac_status = tr32(MAC_STATUS);
2644         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2645                 current_link_up = 0;
2646                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2647                         tw32_f(MAC_MODE, (tp->mac_mode |
2648                                           MAC_MODE_SEND_CONFIGS));
2649                         udelay(1);
2650                         tw32_f(MAC_MODE, tp->mac_mode);
2651                 }
2652         }
2653
2654         if (current_link_up == 1) {
2655                 tp->link_config.active_speed = SPEED_1000;
2656                 tp->link_config.active_duplex = DUPLEX_FULL;
2657                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2658                                     LED_CTRL_LNKLED_OVERRIDE |
2659                                     LED_CTRL_1000MBPS_ON));
2660         } else {
2661                 tp->link_config.active_speed = SPEED_INVALID;
2662                 tp->link_config.active_duplex = DUPLEX_INVALID;
2663                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2664                                     LED_CTRL_LNKLED_OVERRIDE |
2665                                     LED_CTRL_TRAFFIC_OVERRIDE));
2666         }
2667
2668         if (current_link_up != netif_carrier_ok(tp->dev)) {
2669                 if (current_link_up)
2670                         netif_carrier_on(tp->dev);
2671                 else
2672                         netif_carrier_off(tp->dev);
2673                 tg3_link_report(tp);
2674         } else {
2675                 u32 now_pause_cfg =
2676                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2677                                          TG3_FLAG_TX_PAUSE);
2678                 if (orig_pause_cfg != now_pause_cfg ||
2679                     orig_active_speed != tp->link_config.active_speed ||
2680                     orig_active_duplex != tp->link_config.active_duplex)
2681                         tg3_link_report(tp);
2682         }
2683
2684         return 0;
2685 }
2686
2687 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2688 {
2689         int current_link_up, err = 0;
2690         u32 bmsr, bmcr;
2691         u16 current_speed;
2692         u8 current_duplex;
2693
2694         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2695         tw32_f(MAC_MODE, tp->mac_mode);
2696         udelay(40);
2697
2698         tw32(MAC_EVENT, 0);
2699
2700         tw32_f(MAC_STATUS,
2701              (MAC_STATUS_SYNC_CHANGED |
2702               MAC_STATUS_CFG_CHANGED |
2703               MAC_STATUS_MI_COMPLETION |
2704               MAC_STATUS_LNKSTATE_CHANGED));
2705         udelay(40);
2706
2707         if (force_reset)
2708                 tg3_phy_reset(tp);
2709
2710         current_link_up = 0;
2711         current_speed = SPEED_INVALID;
2712         current_duplex = DUPLEX_INVALID;
2713
2714         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2715         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2716         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2717                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2718                         bmsr |= BMSR_LSTATUS;
2719                 else
2720                         bmsr &= ~BMSR_LSTATUS;
2721         }
2722
2723         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2724
2725         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2726             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2727                 /* do nothing, just check for link up at the end */
2728         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2729                 u32 adv, new_adv;
2730
2731                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2732                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2733                                   ADVERTISE_1000XPAUSE |
2734                                   ADVERTISE_1000XPSE_ASYM |
2735                                   ADVERTISE_SLCT);
2736
2737                 /* Always advertise symmetric PAUSE just like copper */
2738                 new_adv |= ADVERTISE_1000XPAUSE;
2739
2740                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2741                         new_adv |= ADVERTISE_1000XHALF;
2742                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2743                         new_adv |= ADVERTISE_1000XFULL;
2744
2745                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2746                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2748                         tg3_writephy(tp, MII_BMCR, bmcr);
2749
2750                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2751                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2752                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2753
2754                         return err;
2755                 }
2756         } else {
2757                 u32 new_bmcr;
2758
2759                 bmcr &= ~BMCR_SPEED1000;
2760                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2761
2762                 if (tp->link_config.duplex == DUPLEX_FULL)
2763                         new_bmcr |= BMCR_FULLDPLX;
2764
2765                 if (new_bmcr != bmcr) {
2766                         /* BMCR_SPEED1000 is a reserved bit that needs
2767                          * to be set on write.
2768                          */
2769                         new_bmcr |= BMCR_SPEED1000;
2770
2771                         /* Force a linkdown */
2772                         if (netif_carrier_ok(tp->dev)) {
2773                                 u32 adv;
2774
2775                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2776                                 adv &= ~(ADVERTISE_1000XFULL |
2777                                          ADVERTISE_1000XHALF |
2778                                          ADVERTISE_SLCT);
2779                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2780                                 tg3_writephy(tp, MII_BMCR, bmcr |
2781                                                            BMCR_ANRESTART |
2782                                                            BMCR_ANENABLE);
2783                                 udelay(10);
2784                                 netif_carrier_off(tp->dev);
2785                         }
2786                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2787                         bmcr = new_bmcr;
2788                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2789                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2790                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2791                             ASIC_REV_5714) {
2792                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2793                                         bmsr |= BMSR_LSTATUS;
2794                                 else
2795                                         bmsr &= ~BMSR_LSTATUS;
2796                         }
2797                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2798                 }
2799         }
2800
2801         if (bmsr & BMSR_LSTATUS) {
2802                 current_speed = SPEED_1000;
2803                 current_link_up = 1;
2804                 if (bmcr & BMCR_FULLDPLX)
2805                         current_duplex = DUPLEX_FULL;
2806                 else
2807                         current_duplex = DUPLEX_HALF;
2808
2809                 if (bmcr & BMCR_ANENABLE) {
2810                         u32 local_adv, remote_adv, common;
2811
2812                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2813                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2814                         common = local_adv & remote_adv;
2815                         if (common & (ADVERTISE_1000XHALF |
2816                                       ADVERTISE_1000XFULL)) {
2817                                 if (common & ADVERTISE_1000XFULL)
2818                                         current_duplex = DUPLEX_FULL;
2819                                 else
2820                                         current_duplex = DUPLEX_HALF;
2821
2822                                 tg3_setup_flow_control(tp, local_adv,
2823                                                        remote_adv);
2824                         }
2825                         else
2826                                 current_link_up = 0;
2827                 }
2828         }
2829
2830         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2831         if (tp->link_config.active_duplex == DUPLEX_HALF)
2832                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2833
2834         tw32_f(MAC_MODE, tp->mac_mode);
2835         udelay(40);
2836
2837         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2838
2839         tp->link_config.active_speed = current_speed;
2840         tp->link_config.active_duplex = current_duplex;
2841
2842         if (current_link_up != netif_carrier_ok(tp->dev)) {
2843                 if (current_link_up)
2844                         netif_carrier_on(tp->dev);
2845                 else {
2846                         netif_carrier_off(tp->dev);
2847                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2848                 }
2849                 tg3_link_report(tp);
2850         }
2851         return err;
2852 }
2853
2854 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2855 {
2856         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2857                 /* Give autoneg time to complete. */
2858                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2859                 return;
2860         }
2861         if (!netif_carrier_ok(tp->dev) &&
2862             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2863                 u32 bmcr;
2864
2865                 tg3_readphy(tp, MII_BMCR, &bmcr);
2866                 if (bmcr & BMCR_ANENABLE) {
2867                         u32 phy1, phy2;
2868
2869                         /* Select shadow register 0x1f */
2870                         tg3_writephy(tp, 0x1c, 0x7c00);
2871                         tg3_readphy(tp, 0x1c, &phy1);
2872
2873                         /* Select expansion interrupt status register */
2874                         tg3_writephy(tp, 0x17, 0x0f01);
2875                         tg3_readphy(tp, 0x15, &phy2);
2876                         tg3_readphy(tp, 0x15, &phy2);
2877
2878                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2879                                 /* We have signal detect and not receiving
2880                                  * config code words, link is up by parallel
2881                                  * detection.
2882                                  */
2883
2884                                 bmcr &= ~BMCR_ANENABLE;
2885                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2886                                 tg3_writephy(tp, MII_BMCR, bmcr);
2887                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2888                         }
2889                 }
2890         }
2891         else if (netif_carrier_ok(tp->dev) &&
2892                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2893                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2894                 u32 phy2;
2895
2896                 /* Select expansion interrupt status register */
2897                 tg3_writephy(tp, 0x17, 0x0f01);
2898                 tg3_readphy(tp, 0x15, &phy2);
2899                 if (phy2 & 0x20) {
2900                         u32 bmcr;
2901
2902                         /* Config code words received, turn on autoneg. */
2903                         tg3_readphy(tp, MII_BMCR, &bmcr);
2904                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2905
2906                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2907
2908                 }
2909         }
2910 }
2911
2912 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2913 {
2914         int err;
2915
2916         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2917                 err = tg3_setup_fiber_phy(tp, force_reset);
2918         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2919                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2920         } else {
2921                 err = tg3_setup_copper_phy(tp, force_reset);
2922         }
2923
2924         if (tp->link_config.active_speed == SPEED_1000 &&
2925             tp->link_config.active_duplex == DUPLEX_HALF)
2926                 tw32(MAC_TX_LENGTHS,
2927                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2928                       (6 << TX_LENGTHS_IPG_SHIFT) |
2929                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2930         else
2931                 tw32(MAC_TX_LENGTHS,
2932                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2933                       (6 << TX_LENGTHS_IPG_SHIFT) |
2934                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2935
2936         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2937                 if (netif_carrier_ok(tp->dev)) {
2938                         tw32(HOSTCC_STAT_COAL_TICKS,
2939                              tp->coal.stats_block_coalesce_usecs);
2940                 } else {
2941                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2942                 }
2943         }
2944
2945         return err;
2946 }
2947
2948 /* Tigon3 never reports partial packet sends.  So we do not
2949  * need special logic to handle SKBs that have not had all
2950  * of their frags sent yet, like SunGEM does.
2951  */
2952 static void tg3_tx(struct tg3 *tp)
2953 {
2954         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2955         u32 sw_idx = tp->tx_cons;
2956
2957         while (sw_idx != hw_idx) {
2958                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2959                 struct sk_buff *skb = ri->skb;
2960                 int i;
2961
2962                 BUG_ON(skb == NULL);
2963                 pci_unmap_single(tp->pdev,
2964                                  pci_unmap_addr(ri, mapping),
2965                                  skb_headlen(skb),
2966                                  PCI_DMA_TODEVICE);
2967
2968                 ri->skb = NULL;
2969
2970                 sw_idx = NEXT_TX(sw_idx);
2971
2972                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2973                         BUG_ON(sw_idx == hw_idx);
2974
2975                         ri = &tp->tx_buffers[sw_idx];
2976                         BUG_ON(ri->skb != NULL);
2977
2978                         pci_unmap_page(tp->pdev,
2979                                        pci_unmap_addr(ri, mapping),
2980                                        skb_shinfo(skb)->frags[i].size,
2981                                        PCI_DMA_TODEVICE);
2982
2983                         sw_idx = NEXT_TX(sw_idx);
2984                 }
2985
2986                 dev_kfree_skb(skb);
2987         }
2988
2989         tp->tx_cons = sw_idx;
2990
2991         if (unlikely(netif_queue_stopped(tp->dev))) {
2992                 spin_lock(&tp->tx_lock);
2993                 if (netif_queue_stopped(tp->dev) &&
2994                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2995                         netif_wake_queue(tp->dev);
2996                 spin_unlock(&tp->tx_lock);
2997         }
2998 }
2999
3000 /* Returns size of skb allocated or < 0 on error.
3001  *
3002  * We only need to fill in the address because the other members
3003  * of the RX descriptor are invariant, see tg3_init_rings.
3004  *
3005  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3006  * posting buffers we only dirty the first cache line of the RX
3007  * descriptor (containing the address).  Whereas for the RX status
3008  * buffers the cpu only reads the last cacheline of the RX descriptor
3009  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3010  */
3011 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3012                             int src_idx, u32 dest_idx_unmasked)
3013 {
3014         struct tg3_rx_buffer_desc *desc;
3015         struct ring_info *map, *src_map;
3016         struct sk_buff *skb;
3017         dma_addr_t mapping;
3018         int skb_size, dest_idx;
3019
3020         src_map = NULL;
3021         switch (opaque_key) {
3022         case RXD_OPAQUE_RING_STD:
3023                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3024                 desc = &tp->rx_std[dest_idx];
3025                 map = &tp->rx_std_buffers[dest_idx];
3026                 if (src_idx >= 0)
3027                         src_map = &tp->rx_std_buffers[src_idx];
3028                 skb_size = tp->rx_pkt_buf_sz;
3029                 break;
3030
3031         case RXD_OPAQUE_RING_JUMBO:
3032                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3033                 desc = &tp->rx_jumbo[dest_idx];
3034                 map = &tp->rx_jumbo_buffers[dest_idx];
3035                 if (src_idx >= 0)
3036                         src_map = &tp->rx_jumbo_buffers[src_idx];
3037                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3038                 break;
3039
3040         default:
3041                 return -EINVAL;
3042         };
3043
3044         /* Do not overwrite any of the map or rp information
3045          * until we are sure we can commit to a new buffer.
3046          *
3047          * Callers depend upon this behavior and assume that
3048          * we leave everything unchanged if we fail.
3049          */
3050         skb = dev_alloc_skb(skb_size);
3051         if (skb == NULL)
3052                 return -ENOMEM;
3053
3054         skb->dev = tp->dev;
3055         skb_reserve(skb, tp->rx_offset);
3056
3057         mapping = pci_map_single(tp->pdev, skb->data,
3058                                  skb_size - tp->rx_offset,
3059                                  PCI_DMA_FROMDEVICE);
3060
3061         map->skb = skb;
3062         pci_unmap_addr_set(map, mapping, mapping);
3063
3064         if (src_map != NULL)
3065                 src_map->skb = NULL;
3066
3067         desc->addr_hi = ((u64)mapping >> 32);
3068         desc->addr_lo = ((u64)mapping & 0xffffffff);
3069
3070         return skb_size;
3071 }
3072
3073 /* We only need to move over in the address because the other
3074  * members of the RX descriptor are invariant.  See notes above
3075  * tg3_alloc_rx_skb for full details.
3076  */
3077 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3078                            int src_idx, u32 dest_idx_unmasked)
3079 {
3080         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3081         struct ring_info *src_map, *dest_map;
3082         int dest_idx;
3083
3084         switch (opaque_key) {
3085         case RXD_OPAQUE_RING_STD:
3086                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3087                 dest_desc = &tp->rx_std[dest_idx];
3088                 dest_map = &tp->rx_std_buffers[dest_idx];
3089                 src_desc = &tp->rx_std[src_idx];
3090                 src_map = &tp->rx_std_buffers[src_idx];
3091                 break;
3092
3093         case RXD_OPAQUE_RING_JUMBO:
3094                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3095                 dest_desc = &tp->rx_jumbo[dest_idx];
3096                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3097                 src_desc = &tp->rx_jumbo[src_idx];
3098                 src_map = &tp->rx_jumbo_buffers[src_idx];
3099                 break;
3100
3101         default:
3102                 return;
3103         };
3104
3105         dest_map->skb = src_map->skb;
3106         pci_unmap_addr_set(dest_map, mapping,
3107                            pci_unmap_addr(src_map, mapping));
3108         dest_desc->addr_hi = src_desc->addr_hi;
3109         dest_desc->addr_lo = src_desc->addr_lo;
3110
3111         src_map->skb = NULL;
3112 }
3113
3114 #if TG3_VLAN_TAG_USED
3115 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3116 {
3117         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3118 }
3119 #endif
3120
3121 /* The RX ring scheme is composed of multiple rings which post fresh
3122  * buffers to the chip, and one special ring the chip uses to report
3123  * status back to the host.
3124  *
3125  * The special ring reports the status of received packets to the
3126  * host.  The chip does not write into the original descriptor the
3127  * RX buffer was obtained from.  The chip simply takes the original
3128  * descriptor as provided by the host, updates the status and length
3129  * field, then writes this into the next status ring entry.
3130  *
3131  * Each ring the host uses to post buffers to the chip is described
3132  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3133  * it is first placed into the on-chip ram.  When the packet's length
3134  * is known, it walks down the TG3_BDINFO entries to select the ring.
3135  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3136  * which is within the range of the new packet's length is chosen.
3137  *
3138  * The "separate ring for rx status" scheme may sound queer, but it makes
3139  * sense from a cache coherency perspective.  If only the host writes
3140  * to the buffer post rings, and only the chip writes to the rx status
3141  * rings, then cache lines never move beyond shared-modified state.
3142  * If both the host and chip were to write into the same ring, cache line
3143  * eviction could occur since both entities want it in an exclusive state.
3144  */
3145 static int tg3_rx(struct tg3 *tp, int budget)
3146 {
3147         u32 work_mask;
3148         u32 sw_idx = tp->rx_rcb_ptr;
3149         u16 hw_idx;
3150         int received;
3151
3152         hw_idx = tp->hw_status->idx[0].rx_producer;
3153         /*
3154          * We need to order the read of hw_idx and the read of
3155          * the opaque cookie.
3156          */
3157         rmb();
3158         work_mask = 0;
3159         received = 0;
3160         while (sw_idx != hw_idx && budget > 0) {
3161                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3162                 unsigned int len;
3163                 struct sk_buff *skb;
3164                 dma_addr_t dma_addr;
3165                 u32 opaque_key, desc_idx, *post_ptr;
3166
3167                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3168                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3169                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3170                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3171                                                   mapping);
3172                         skb = tp->rx_std_buffers[desc_idx].skb;
3173                         post_ptr = &tp->rx_std_ptr;
3174                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3175                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3176                                                   mapping);
3177                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3178                         post_ptr = &tp->rx_jumbo_ptr;
3179                 }
3180                 else {
3181                         goto next_pkt_nopost;
3182                 }
3183
3184                 work_mask |= opaque_key;
3185
3186                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3187                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3188                 drop_it:
3189                         tg3_recycle_rx(tp, opaque_key,
3190                                        desc_idx, *post_ptr);
3191                 drop_it_no_recycle:
3192                         /* Other statistics kept track of by card. */
3193                         tp->net_stats.rx_dropped++;
3194                         goto next_pkt;
3195                 }
3196
3197                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3198
3199                 if (len > RX_COPY_THRESHOLD 
3200                         && tp->rx_offset == 2
3201                         /* rx_offset != 2 iff this is a 5701 card running
3202                          * in PCI-X mode [see tg3_get_invariants()] */
3203                 ) {
3204                         int skb_size;
3205
3206                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3207                                                     desc_idx, *post_ptr);
3208                         if (skb_size < 0)
3209                                 goto drop_it;
3210
3211                         pci_unmap_single(tp->pdev, dma_addr,
3212                                          skb_size - tp->rx_offset,
3213                                          PCI_DMA_FROMDEVICE);
3214
3215                         skb_put(skb, len);
3216                 } else {
3217                         struct sk_buff *copy_skb;
3218
3219                         tg3_recycle_rx(tp, opaque_key,
3220                                        desc_idx, *post_ptr);
3221
3222                         copy_skb = dev_alloc_skb(len + 2);
3223                         if (copy_skb == NULL)
3224                                 goto drop_it_no_recycle;
3225
3226                         copy_skb->dev = tp->dev;