e3c33fa06c863213ca682d01f69199e56a3ecb4f
[linux-2.6.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2008 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Falcon hardware control.
32  * Falcon is the internal codename for the SFC4000 controller that is
33  * present in SFE400X evaluation boards
34  */
35
36 /**
37  * struct falcon_nic_data - Falcon NIC state
38  * @pci_dev2: The secondary PCI device if present
39  * @i2c_data: Operations and state for I2C bit-bashing algorithm
40  */
41 struct falcon_nic_data {
42         struct pci_dev *pci_dev2;
43         struct i2c_algo_bit_data i2c_data;
44 };
45
46 /**************************************************************************
47  *
48  * Configurable values
49  *
50  **************************************************************************
51  */
52
53 static int disable_dma_stats;
54
55 /* This is set to 16 for a good reason.  In summary, if larger than
56  * 16, the descriptor cache holds more than a default socket
57  * buffer's worth of packets (for UDP we can only have at most one
58  * socket buffer's worth outstanding).  This combined with the fact
59  * that we only get 1 TX event per descriptor cache means the NIC
60  * goes idle.
61  */
62 #define TX_DC_ENTRIES 16
63 #define TX_DC_ENTRIES_ORDER 0
64 #define TX_DC_BASE 0x130000
65
66 #define RX_DC_ENTRIES 64
67 #define RX_DC_ENTRIES_ORDER 2
68 #define RX_DC_BASE 0x100000
69
70 static const unsigned int
71 /* "Large" EEPROM device: Atmel AT25640 or similar
72  * 8 KB, 16-bit address, 32 B write block */
73 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
74                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
75                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
76 /* Default flash device: Atmel AT25F1024
77  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
78 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
79                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
80                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
81                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
82                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
83
84 /* RX FIFO XOFF watermark
85  *
86  * When the amount of the RX FIFO increases used increases past this
87  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
88  * This also has an effect on RX/TX arbitration
89  */
90 static int rx_xoff_thresh_bytes = -1;
91 module_param(rx_xoff_thresh_bytes, int, 0644);
92 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
93
94 /* RX FIFO XON watermark
95  *
96  * When the amount of the RX FIFO used decreases below this
97  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
98  * This also has an effect on RX/TX arbitration
99  */
100 static int rx_xon_thresh_bytes = -1;
101 module_param(rx_xon_thresh_bytes, int, 0644);
102 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
103
104 /* If FALCON_MAX_INT_ERRORS internal errors occur within
105  * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
106  * disable it.
107  */
108 #define FALCON_INT_ERROR_EXPIRE 3600
109 #define FALCON_MAX_INT_ERRORS 5
110
111 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
112  */
113 #define FALCON_FLUSH_INTERVAL 10
114 #define FALCON_FLUSH_POLL_COUNT 100
115
116 /**************************************************************************
117  *
118  * Falcon constants
119  *
120  **************************************************************************
121  */
122
123 /* Size and alignment of special buffers (4KB) */
124 #define FALCON_BUF_SIZE 4096
125
126 /* Dummy SRAM size code */
127 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
128
129 #define FALCON_IS_DUAL_FUNC(efx)                \
130         (falcon_rev(efx) < FALCON_REV_B0)
131
132 /**************************************************************************
133  *
134  * Falcon hardware access
135  *
136  **************************************************************************/
137
138 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
139                                         unsigned int index)
140 {
141         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
142                         value, index);
143 }
144
145 /* Read the current event from the event queue */
146 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
147                                         unsigned int index)
148 {
149         return (((efx_qword_t *) (channel->eventq.addr)) + index);
150 }
151
152 /* See if an event is present
153  *
154  * We check both the high and low dword of the event for all ones.  We
155  * wrote all ones when we cleared the event, and no valid event can
156  * have all ones in either its high or low dwords.  This approach is
157  * robust against reordering.
158  *
159  * Note that using a single 64-bit comparison is incorrect; even
160  * though the CPU read will be atomic, the DMA write may not be.
161  */
162 static inline int falcon_event_present(efx_qword_t *event)
163 {
164         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
165                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
166 }
167
168 /**************************************************************************
169  *
170  * I2C bus - this is a bit-bashing interface using GPIO pins
171  * Note that it uses the output enables to tristate the outputs
172  * SDA is the data pin and SCL is the clock
173  *
174  **************************************************************************
175  */
176 static void falcon_setsda(void *data, int state)
177 {
178         struct efx_nic *efx = (struct efx_nic *)data;
179         efx_oword_t reg;
180
181         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
182         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
183         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
184 }
185
186 static void falcon_setscl(void *data, int state)
187 {
188         struct efx_nic *efx = (struct efx_nic *)data;
189         efx_oword_t reg;
190
191         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
192         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
193         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
194 }
195
196 static int falcon_getsda(void *data)
197 {
198         struct efx_nic *efx = (struct efx_nic *)data;
199         efx_oword_t reg;
200
201         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
202         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
203 }
204
205 static int falcon_getscl(void *data)
206 {
207         struct efx_nic *efx = (struct efx_nic *)data;
208         efx_oword_t reg;
209
210         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
211         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
212 }
213
214 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
215         .setsda         = falcon_setsda,
216         .setscl         = falcon_setscl,
217         .getsda         = falcon_getsda,
218         .getscl         = falcon_getscl,
219         .udelay         = 5,
220         /* Wait up to 50 ms for slave to let us pull SCL high */
221         .timeout        = DIV_ROUND_UP(HZ, 20),
222 };
223
224 /**************************************************************************
225  *
226  * Falcon special buffer handling
227  * Special buffers are used for event queues and the TX and RX
228  * descriptor rings.
229  *
230  *************************************************************************/
231
232 /*
233  * Initialise a Falcon special buffer
234  *
235  * This will define a buffer (previously allocated via
236  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
237  * it to be used for event queues, descriptor rings etc.
238  */
239 static void
240 falcon_init_special_buffer(struct efx_nic *efx,
241                            struct efx_special_buffer *buffer)
242 {
243         efx_qword_t buf_desc;
244         int index;
245         dma_addr_t dma_addr;
246         int i;
247
248         EFX_BUG_ON_PARANOID(!buffer->addr);
249
250         /* Write buffer descriptors to NIC */
251         for (i = 0; i < buffer->entries; i++) {
252                 index = buffer->index + i;
253                 dma_addr = buffer->dma_addr + (i * 4096);
254                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
255                         index, (unsigned long long)dma_addr);
256                 EFX_POPULATE_QWORD_3(buf_desc,
257                                      FRF_AZ_BUF_ADR_REGION, 0,
258                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
259                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
260                 falcon_write_buf_tbl(efx, &buf_desc, index);
261         }
262 }
263
264 /* Unmaps a buffer from Falcon and clears the buffer table entries */
265 static void
266 falcon_fini_special_buffer(struct efx_nic *efx,
267                            struct efx_special_buffer *buffer)
268 {
269         efx_oword_t buf_tbl_upd;
270         unsigned int start = buffer->index;
271         unsigned int end = (buffer->index + buffer->entries - 1);
272
273         if (!buffer->entries)
274                 return;
275
276         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
277                 buffer->index, buffer->index + buffer->entries - 1);
278
279         EFX_POPULATE_OWORD_4(buf_tbl_upd,
280                              FRF_AZ_BUF_UPD_CMD, 0,
281                              FRF_AZ_BUF_CLR_CMD, 1,
282                              FRF_AZ_BUF_CLR_END_ID, end,
283                              FRF_AZ_BUF_CLR_START_ID, start);
284         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
285 }
286
287 /*
288  * Allocate a new Falcon special buffer
289  *
290  * This allocates memory for a new buffer, clears it and allocates a
291  * new buffer ID range.  It does not write into Falcon's buffer table.
292  *
293  * This call will allocate 4KB buffers, since Falcon can't use 8KB
294  * buffers for event queues and descriptor rings.
295  */
296 static int falcon_alloc_special_buffer(struct efx_nic *efx,
297                                        struct efx_special_buffer *buffer,
298                                        unsigned int len)
299 {
300         len = ALIGN(len, FALCON_BUF_SIZE);
301
302         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
303                                             &buffer->dma_addr);
304         if (!buffer->addr)
305                 return -ENOMEM;
306         buffer->len = len;
307         buffer->entries = len / FALCON_BUF_SIZE;
308         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
309
310         /* All zeros is a potentially valid event so memset to 0xff */
311         memset(buffer->addr, 0xff, len);
312
313         /* Select new buffer ID */
314         buffer->index = efx->next_buffer_table;
315         efx->next_buffer_table += buffer->entries;
316
317         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
318                 "(virt %p phys %llx)\n", buffer->index,
319                 buffer->index + buffer->entries - 1,
320                 (u64)buffer->dma_addr, len,
321                 buffer->addr, (u64)virt_to_phys(buffer->addr));
322
323         return 0;
324 }
325
326 static void falcon_free_special_buffer(struct efx_nic *efx,
327                                        struct efx_special_buffer *buffer)
328 {
329         if (!buffer->addr)
330                 return;
331
332         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
333                 "(virt %p phys %llx)\n", buffer->index,
334                 buffer->index + buffer->entries - 1,
335                 (u64)buffer->dma_addr, buffer->len,
336                 buffer->addr, (u64)virt_to_phys(buffer->addr));
337
338         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
339                             buffer->dma_addr);
340         buffer->addr = NULL;
341         buffer->entries = 0;
342 }
343
344 /**************************************************************************
345  *
346  * Falcon generic buffer handling
347  * These buffers are used for interrupt status and MAC stats
348  *
349  **************************************************************************/
350
351 static int falcon_alloc_buffer(struct efx_nic *efx,
352                                struct efx_buffer *buffer, unsigned int len)
353 {
354         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
355                                             &buffer->dma_addr);
356         if (!buffer->addr)
357                 return -ENOMEM;
358         buffer->len = len;
359         memset(buffer->addr, 0, len);
360         return 0;
361 }
362
363 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
364 {
365         if (buffer->addr) {
366                 pci_free_consistent(efx->pci_dev, buffer->len,
367                                     buffer->addr, buffer->dma_addr);
368                 buffer->addr = NULL;
369         }
370 }
371
372 /**************************************************************************
373  *
374  * Falcon TX path
375  *
376  **************************************************************************/
377
378 /* Returns a pointer to the specified transmit descriptor in the TX
379  * descriptor queue belonging to the specified channel.
380  */
381 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
382                                                unsigned int index)
383 {
384         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
385 }
386
387 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
388 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
389 {
390         unsigned write_ptr;
391         efx_dword_t reg;
392
393         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
394         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
395         efx_writed_page(tx_queue->efx, &reg,
396                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
397 }
398
399
400 /* For each entry inserted into the software descriptor ring, create a
401  * descriptor in the hardware TX descriptor ring (in host memory), and
402  * write a doorbell.
403  */
404 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
405 {
406
407         struct efx_tx_buffer *buffer;
408         efx_qword_t *txd;
409         unsigned write_ptr;
410
411         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
412
413         do {
414                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
415                 buffer = &tx_queue->buffer[write_ptr];
416                 txd = falcon_tx_desc(tx_queue, write_ptr);
417                 ++tx_queue->write_count;
418
419                 /* Create TX descriptor ring entry */
420                 EFX_POPULATE_QWORD_4(*txd,
421                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
422                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
423                                      FSF_AZ_TX_KER_BUF_REGION, 0,
424                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
425         } while (tx_queue->write_count != tx_queue->insert_count);
426
427         wmb(); /* Ensure descriptors are written before they are fetched */
428         falcon_notify_tx_desc(tx_queue);
429 }
430
431 /* Allocate hardware resources for a TX queue */
432 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
433 {
434         struct efx_nic *efx = tx_queue->efx;
435         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
436                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
437         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
438                                            EFX_TXQ_SIZE * sizeof(efx_qword_t));
439 }
440
441 void falcon_init_tx(struct efx_tx_queue *tx_queue)
442 {
443         efx_oword_t tx_desc_ptr;
444         struct efx_nic *efx = tx_queue->efx;
445
446         tx_queue->flushed = false;
447
448         /* Pin TX descriptor ring */
449         falcon_init_special_buffer(efx, &tx_queue->txd);
450
451         /* Push TX descriptor ring to card */
452         EFX_POPULATE_OWORD_10(tx_desc_ptr,
453                               FRF_AZ_TX_DESCQ_EN, 1,
454                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
455                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
456                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
457                               FRF_AZ_TX_DESCQ_EVQ_ID,
458                               tx_queue->channel->channel,
459                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
460                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
461                               FRF_AZ_TX_DESCQ_SIZE,
462                               __ffs(tx_queue->txd.entries),
463                               FRF_AZ_TX_DESCQ_TYPE, 0,
464                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
465
466         if (falcon_rev(efx) >= FALCON_REV_B0) {
467                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
468                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
469                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
470                                     !csum);
471         }
472
473         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
474                          tx_queue->queue);
475
476         if (falcon_rev(efx) < FALCON_REV_B0) {
477                 efx_oword_t reg;
478
479                 /* Only 128 bits in this register */
480                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
481
482                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
483                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
484                         clear_bit_le(tx_queue->queue, (void *)&reg);
485                 else
486                         set_bit_le(tx_queue->queue, (void *)&reg);
487                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
488         }
489 }
490
491 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
492 {
493         struct efx_nic *efx = tx_queue->efx;
494         efx_oword_t tx_flush_descq;
495
496         /* Post a flush command */
497         EFX_POPULATE_OWORD_2(tx_flush_descq,
498                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
499                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
500         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
501 }
502
503 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
504 {
505         struct efx_nic *efx = tx_queue->efx;
506         efx_oword_t tx_desc_ptr;
507
508         /* The queue should have been flushed */
509         WARN_ON(!tx_queue->flushed);
510
511         /* Remove TX descriptor ring from card */
512         EFX_ZERO_OWORD(tx_desc_ptr);
513         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
514                          tx_queue->queue);
515
516         /* Unpin TX descriptor ring */
517         falcon_fini_special_buffer(efx, &tx_queue->txd);
518 }
519
520 /* Free buffers backing TX queue */
521 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
522 {
523         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
524 }
525
526 /**************************************************************************
527  *
528  * Falcon RX path
529  *
530  **************************************************************************/
531
532 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
533 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
534                                                unsigned int index)
535 {
536         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
537 }
538
539 /* This creates an entry in the RX descriptor queue */
540 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
541                                         unsigned index)
542 {
543         struct efx_rx_buffer *rx_buf;
544         efx_qword_t *rxd;
545
546         rxd = falcon_rx_desc(rx_queue, index);
547         rx_buf = efx_rx_buffer(rx_queue, index);
548         EFX_POPULATE_QWORD_3(*rxd,
549                              FSF_AZ_RX_KER_BUF_SIZE,
550                              rx_buf->len -
551                              rx_queue->efx->type->rx_buffer_padding,
552                              FSF_AZ_RX_KER_BUF_REGION, 0,
553                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
554 }
555
556 /* This writes to the RX_DESC_WPTR register for the specified receive
557  * descriptor ring.
558  */
559 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
560 {
561         efx_dword_t reg;
562         unsigned write_ptr;
563
564         while (rx_queue->notified_count != rx_queue->added_count) {
565                 falcon_build_rx_desc(rx_queue,
566                                      rx_queue->notified_count &
567                                      EFX_RXQ_MASK);
568                 ++rx_queue->notified_count;
569         }
570
571         wmb();
572         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
573         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
574         efx_writed_page(rx_queue->efx, &reg,
575                         FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
576 }
577
578 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
579 {
580         struct efx_nic *efx = rx_queue->efx;
581         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
582                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
583         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
584                                            EFX_RXQ_SIZE * sizeof(efx_qword_t));
585 }
586
587 void falcon_init_rx(struct efx_rx_queue *rx_queue)
588 {
589         efx_oword_t rx_desc_ptr;
590         struct efx_nic *efx = rx_queue->efx;
591         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
592         bool iscsi_digest_en = is_b0;
593
594         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
595                 rx_queue->queue, rx_queue->rxd.index,
596                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
597
598         rx_queue->flushed = false;
599
600         /* Pin RX descriptor ring */
601         falcon_init_special_buffer(efx, &rx_queue->rxd);
602
603         /* Push RX descriptor ring to card */
604         EFX_POPULATE_OWORD_10(rx_desc_ptr,
605                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
606                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
607                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
608                               FRF_AZ_RX_DESCQ_EVQ_ID,
609                               rx_queue->channel->channel,
610                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
611                               FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
612                               FRF_AZ_RX_DESCQ_SIZE,
613                               __ffs(rx_queue->rxd.entries),
614                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
615                               /* For >=B0 this is scatter so disable */
616                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
617                               FRF_AZ_RX_DESCQ_EN, 1);
618         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
619                          rx_queue->queue);
620 }
621
622 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
623 {
624         struct efx_nic *efx = rx_queue->efx;
625         efx_oword_t rx_flush_descq;
626
627         /* Post a flush command */
628         EFX_POPULATE_OWORD_2(rx_flush_descq,
629                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
630                              FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
631         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
632 }
633
634 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
635 {
636         efx_oword_t rx_desc_ptr;
637         struct efx_nic *efx = rx_queue->efx;
638
639         /* The queue should already have been flushed */
640         WARN_ON(!rx_queue->flushed);
641
642         /* Remove RX descriptor ring from card */
643         EFX_ZERO_OWORD(rx_desc_ptr);
644         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
645                          rx_queue->queue);
646
647         /* Unpin RX descriptor ring */
648         falcon_fini_special_buffer(efx, &rx_queue->rxd);
649 }
650
651 /* Free buffers backing RX queue */
652 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
653 {
654         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
655 }
656
657 /**************************************************************************
658  *
659  * Falcon event queue processing
660  * Event queues are processed by per-channel tasklets.
661  *
662  **************************************************************************/
663
664 /* Update a channel's event queue's read pointer (RPTR) register
665  *
666  * This writes the EVQ_RPTR_REG register for the specified channel's
667  * event queue.
668  *
669  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
670  * whereas channel->eventq_read_ptr contains the index of the "next to
671  * read" event.
672  */
673 void falcon_eventq_read_ack(struct efx_channel *channel)
674 {
675         efx_dword_t reg;
676         struct efx_nic *efx = channel->efx;
677
678         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
679         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
680                             channel->channel);
681 }
682
683 /* Use HW to insert a SW defined event */
684 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
685 {
686         efx_oword_t drv_ev_reg;
687
688         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
689                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
690         drv_ev_reg.u32[0] = event->u32[0];
691         drv_ev_reg.u32[1] = event->u32[1];
692         drv_ev_reg.u32[2] = 0;
693         drv_ev_reg.u32[3] = 0;
694         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
695         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
696 }
697
698 /* Handle a transmit completion event
699  *
700  * Falcon batches TX completion events; the message we receive is of
701  * the form "complete all TX events up to this index".
702  */
703 static void falcon_handle_tx_event(struct efx_channel *channel,
704                                    efx_qword_t *event)
705 {
706         unsigned int tx_ev_desc_ptr;
707         unsigned int tx_ev_q_label;
708         struct efx_tx_queue *tx_queue;
709         struct efx_nic *efx = channel->efx;
710
711         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
712                 /* Transmit completion */
713                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
714                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
715                 tx_queue = &efx->tx_queue[tx_ev_q_label];
716                 channel->irq_mod_score +=
717                         (tx_ev_desc_ptr - tx_queue->read_count) &
718                         EFX_TXQ_MASK;
719                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
720         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
721                 /* Rewrite the FIFO write pointer */
722                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
723                 tx_queue = &efx->tx_queue[tx_ev_q_label];
724
725                 if (efx_dev_registered(efx))
726                         netif_tx_lock(efx->net_dev);
727                 falcon_notify_tx_desc(tx_queue);
728                 if (efx_dev_registered(efx))
729                         netif_tx_unlock(efx->net_dev);
730         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
731                    EFX_WORKAROUND_10727(efx)) {
732                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
733         } else {
734                 EFX_ERR(efx, "channel %d unexpected TX event "
735                         EFX_QWORD_FMT"\n", channel->channel,
736                         EFX_QWORD_VAL(*event));
737         }
738 }
739
740 /* Detect errors included in the rx_evt_pkt_ok bit. */
741 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
742                                     const efx_qword_t *event,
743                                     bool *rx_ev_pkt_ok,
744                                     bool *discard)
745 {
746         struct efx_nic *efx = rx_queue->efx;
747         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
748         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
749         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
750         bool rx_ev_other_err, rx_ev_pause_frm;
751         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
752         unsigned rx_ev_pkt_type;
753
754         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
755         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
756         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
757         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
758         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
759                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
760         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
761         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
762                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
763         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
764                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
765         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
766         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
767         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
768                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
769         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
770
771         /* Every error apart from tobe_disc and pause_frm */
772         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
773                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
774                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
775
776         /* Count errors that are not in MAC stats.  Ignore expected
777          * checksum errors during self-test. */
778         if (rx_ev_frm_trunc)
779                 ++rx_queue->channel->n_rx_frm_trunc;
780         else if (rx_ev_tobe_disc)
781                 ++rx_queue->channel->n_rx_tobe_disc;
782         else if (!efx->loopback_selftest) {
783                 if (rx_ev_ip_hdr_chksum_err)
784                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
785                 else if (rx_ev_tcp_udp_chksum_err)
786                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
787         }
788         if (rx_ev_ip_frag_err)
789                 ++rx_queue->channel->n_rx_ip_frag_err;
790
791         /* The frame must be discarded if any of these are true. */
792         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
793                     rx_ev_tobe_disc | rx_ev_pause_frm);
794
795         /* TOBE_DISC is expected on unicast mismatches; don't print out an
796          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
797          * to a FIFO overflow.
798          */
799 #ifdef EFX_ENABLE_DEBUG
800         if (rx_ev_other_err) {
801                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
802                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
803                             rx_queue->queue, EFX_QWORD_VAL(*event),
804                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
805                             rx_ev_ip_hdr_chksum_err ?
806                             " [IP_HDR_CHKSUM_ERR]" : "",
807                             rx_ev_tcp_udp_chksum_err ?
808                             " [TCP_UDP_CHKSUM_ERR]" : "",
809                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
810                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
811                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
812                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
813                             rx_ev_pause_frm ? " [PAUSE]" : "");
814         }
815 #endif
816 }
817
818 /* Handle receive events that are not in-order. */
819 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
820                                        unsigned index)
821 {
822         struct efx_nic *efx = rx_queue->efx;
823         unsigned expected, dropped;
824
825         expected = rx_queue->removed_count & EFX_RXQ_MASK;
826         dropped = (index - expected) & EFX_RXQ_MASK;
827         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
828                 dropped, index, expected);
829
830         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
831                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
832 }
833
834 /* Handle a packet received event
835  *
836  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
837  * wrong destination address
838  * Also "is multicast" and "matches multicast filter" flags can be used to
839  * discard non-matching multicast packets.
840  */
841 static void falcon_handle_rx_event(struct efx_channel *channel,
842                                    const efx_qword_t *event)
843 {
844         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
845         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
846         unsigned expected_ptr;
847         bool rx_ev_pkt_ok, discard = false, checksummed;
848         struct efx_rx_queue *rx_queue;
849         struct efx_nic *efx = channel->efx;
850
851         /* Basic packet information */
852         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
853         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
854         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
855         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
856         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
857         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
858                 channel->channel);
859
860         rx_queue = &efx->rx_queue[channel->channel];
861
862         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
863         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
864         if (unlikely(rx_ev_desc_ptr != expected_ptr))
865                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
866
867         if (likely(rx_ev_pkt_ok)) {
868                 /* If packet is marked as OK and packet type is TCP/IPv4 or
869                  * UDP/IPv4, then we can rely on the hardware checksum.
870                  */
871                 checksummed =
872                         rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
873                         rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
874         } else {
875                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
876                                         &discard);
877                 checksummed = false;
878         }
879
880         /* Detect multicast packets that didn't match the filter */
881         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
882         if (rx_ev_mcast_pkt) {
883                 unsigned int rx_ev_mcast_hash_match =
884                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
885
886                 if (unlikely(!rx_ev_mcast_hash_match))
887                         discard = true;
888         }
889
890         channel->irq_mod_score += 2;
891
892         /* Handle received packet */
893         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
894                       checksummed, discard);
895 }
896
897 /* Global events are basically PHY events */
898 static void falcon_handle_global_event(struct efx_channel *channel,
899                                        efx_qword_t *event)
900 {
901         struct efx_nic *efx = channel->efx;
902         bool handled = false;
903
904         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
905             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
906             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
907                 efx->phy_op->clear_interrupt(efx);
908                 queue_work(efx->workqueue, &efx->phy_work);
909                 handled = true;
910         }
911
912         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
913             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
914                 queue_work(efx->workqueue, &efx->mac_work);
915                 handled = true;
916         }
917
918         if (falcon_rev(efx) <= FALCON_REV_A1 ?
919             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
920             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
921                 EFX_ERR(efx, "channel %d seen global RX_RESET "
922                         "event. Resetting.\n", channel->channel);
923
924                 atomic_inc(&efx->rx_reset);
925                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
926                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
927                 handled = true;
928         }
929
930         if (!handled)
931                 EFX_ERR(efx, "channel %d unknown global event "
932                         EFX_QWORD_FMT "\n", channel->channel,
933                         EFX_QWORD_VAL(*event));
934 }
935
936 static void falcon_handle_driver_event(struct efx_channel *channel,
937                                        efx_qword_t *event)
938 {
939         struct efx_nic *efx = channel->efx;
940         unsigned int ev_sub_code;
941         unsigned int ev_sub_data;
942
943         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
944         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
945
946         switch (ev_sub_code) {
947         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
948                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
949                           channel->channel, ev_sub_data);
950                 break;
951         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
952                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
953                           channel->channel, ev_sub_data);
954                 break;
955         case FSE_AZ_EVQ_INIT_DONE_EV:
956                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
957                         channel->channel, ev_sub_data);
958                 break;
959         case FSE_AZ_SRM_UPD_DONE_EV:
960                 EFX_TRACE(efx, "channel %d SRAM update done\n",
961                           channel->channel);
962                 break;
963         case FSE_AZ_WAKE_UP_EV:
964                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
965                           channel->channel, ev_sub_data);
966                 break;
967         case FSE_AZ_TIMER_EV:
968                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
969                           channel->channel, ev_sub_data);
970                 break;
971         case FSE_AA_RX_RECOVER_EV:
972                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
973                         "Resetting.\n", channel->channel);
974                 atomic_inc(&efx->rx_reset);
975                 efx_schedule_reset(efx,
976                                    EFX_WORKAROUND_6555(efx) ?
977                                    RESET_TYPE_RX_RECOVERY :
978                                    RESET_TYPE_DISABLE);
979                 break;
980         case FSE_BZ_RX_DSC_ERROR_EV:
981                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
982                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
983                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
984                 break;
985         case FSE_BZ_TX_DSC_ERROR_EV:
986                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
987                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
988                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
989                 break;
990         default:
991                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
992                           "data %04x\n", channel->channel, ev_sub_code,
993                           ev_sub_data);
994                 break;
995         }
996 }
997
998 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
999 {
1000         unsigned int read_ptr;
1001         efx_qword_t event, *p_event;
1002         int ev_code;
1003         int rx_packets = 0;
1004
1005         read_ptr = channel->eventq_read_ptr;
1006
1007         do {
1008                 p_event = falcon_event(channel, read_ptr);
1009                 event = *p_event;
1010
1011                 if (!falcon_event_present(&event))
1012                         /* End of events */
1013                         break;
1014
1015                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1016                           channel->channel, EFX_QWORD_VAL(event));
1017
1018                 /* Clear this event by marking it all ones */
1019                 EFX_SET_QWORD(*p_event);
1020
1021                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1022
1023                 switch (ev_code) {
1024                 case FSE_AZ_EV_CODE_RX_EV:
1025                         falcon_handle_rx_event(channel, &event);
1026                         ++rx_packets;
1027                         break;
1028                 case FSE_AZ_EV_CODE_TX_EV:
1029                         falcon_handle_tx_event(channel, &event);
1030                         break;
1031                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1032                         channel->eventq_magic = EFX_QWORD_FIELD(
1033                                 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1034                         EFX_LOG(channel->efx, "channel %d received generated "
1035                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1036                                 EFX_QWORD_VAL(event));
1037                         break;
1038                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1039                         falcon_handle_global_event(channel, &event);
1040                         break;
1041                 case FSE_AZ_EV_CODE_DRIVER_EV:
1042                         falcon_handle_driver_event(channel, &event);
1043                         break;
1044                 default:
1045                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1046                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1047                                 ev_code, EFX_QWORD_VAL(event));
1048                 }
1049
1050                 /* Increment read pointer */
1051                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1052
1053         } while (rx_packets < rx_quota);
1054
1055         channel->eventq_read_ptr = read_ptr;
1056         return rx_packets;
1057 }
1058
1059 void falcon_set_int_moderation(struct efx_channel *channel)
1060 {
1061         efx_dword_t timer_cmd;
1062         struct efx_nic *efx = channel->efx;
1063
1064         /* Set timer register */
1065         if (channel->irq_moderation) {
1066                 EFX_POPULATE_DWORD_2(timer_cmd,
1067                                      FRF_AB_TC_TIMER_MODE,
1068                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
1069                                      FRF_AB_TC_TIMER_VAL,
1070                                      channel->irq_moderation - 1);
1071         } else {
1072                 EFX_POPULATE_DWORD_2(timer_cmd,
1073                                      FRF_AB_TC_TIMER_MODE,
1074                                      FFE_BB_TIMER_MODE_DIS,
1075                                      FRF_AB_TC_TIMER_VAL, 0);
1076         }
1077         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1078         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1079                                channel->channel);
1080
1081 }
1082
1083 /* Allocate buffer table entries for event queue */
1084 int falcon_probe_eventq(struct efx_channel *channel)
1085 {
1086         struct efx_nic *efx = channel->efx;
1087         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1088                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1089         return falcon_alloc_special_buffer(efx, &channel->eventq,
1090                                            EFX_EVQ_SIZE * sizeof(efx_qword_t));
1091 }
1092
1093 void falcon_init_eventq(struct efx_channel *channel)
1094 {
1095         efx_oword_t evq_ptr;
1096         struct efx_nic *efx = channel->efx;
1097
1098         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1099                 channel->channel, channel->eventq.index,
1100                 channel->eventq.index + channel->eventq.entries - 1);
1101
1102         /* Pin event queue buffer */
1103         falcon_init_special_buffer(efx, &channel->eventq);
1104
1105         /* Fill event queue with all ones (i.e. empty events) */
1106         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1107
1108         /* Push event queue to card */
1109         EFX_POPULATE_OWORD_3(evq_ptr,
1110                              FRF_AZ_EVQ_EN, 1,
1111                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1112                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1113         efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1114                          channel->channel);
1115
1116         falcon_set_int_moderation(channel);
1117 }
1118
1119 void falcon_fini_eventq(struct efx_channel *channel)
1120 {
1121         efx_oword_t eventq_ptr;
1122         struct efx_nic *efx = channel->efx;
1123
1124         /* Remove event queue from card */
1125         EFX_ZERO_OWORD(eventq_ptr);
1126         efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1127                          channel->channel);
1128
1129         /* Unpin event queue */
1130         falcon_fini_special_buffer(efx, &channel->eventq);
1131 }
1132
1133 /* Free buffers backing event queue */
1134 void falcon_remove_eventq(struct efx_channel *channel)
1135 {
1136         falcon_free_special_buffer(channel->efx, &channel->eventq);
1137 }
1138
1139
1140 /* Generates a test event on the event queue.  A subsequent call to
1141  * process_eventq() should pick up the event and place the value of
1142  * "magic" into channel->eventq_magic;
1143  */
1144 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1145 {
1146         efx_qword_t test_event;
1147
1148         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1149                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1150                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1151         falcon_generate_event(channel, &test_event);
1152 }
1153
1154 void falcon_sim_phy_event(struct efx_nic *efx)
1155 {
1156         efx_qword_t phy_event;
1157
1158         EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1159                              FSE_AZ_EV_CODE_GLOBAL_EV);
1160         if (EFX_IS10G(efx))
1161                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1162         else
1163                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1164
1165         falcon_generate_event(&efx->channel[0], &phy_event);
1166 }
1167
1168 /**************************************************************************
1169  *
1170  * Flush handling
1171  *
1172  **************************************************************************/
1173
1174
1175 static void falcon_poll_flush_events(struct efx_nic *efx)
1176 {
1177         struct efx_channel *channel = &efx->channel[0];
1178         struct efx_tx_queue *tx_queue;
1179         struct efx_rx_queue *rx_queue;
1180         unsigned int read_ptr = channel->eventq_read_ptr;
1181         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1182
1183         do {
1184                 efx_qword_t *event = falcon_event(channel, read_ptr);
1185                 int ev_code, ev_sub_code, ev_queue;
1186                 bool ev_failed;
1187
1188                 if (!falcon_event_present(event))
1189                         break;
1190
1191                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1192                 ev_sub_code = EFX_QWORD_FIELD(*event,
1193                                               FSF_AZ_DRIVER_EV_SUBCODE);
1194                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1195                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1196                         ev_queue = EFX_QWORD_FIELD(*event,
1197                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1198                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1199                                 tx_queue = efx->tx_queue + ev_queue;
1200                                 tx_queue->flushed = true;
1201                         }
1202                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1203                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1204                         ev_queue = EFX_QWORD_FIELD(
1205                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1206                         ev_failed = EFX_QWORD_FIELD(
1207                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1208                         if (ev_queue < efx->n_rx_queues) {
1209                                 rx_queue = efx->rx_queue + ev_queue;
1210
1211                                 /* retry the rx flush */
1212                                 if (ev_failed)
1213                                         falcon_flush_rx_queue(rx_queue);
1214                                 else
1215                                         rx_queue->flushed = true;
1216                         }
1217                 }
1218
1219                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1220         } while (read_ptr != end_ptr);
1221 }
1222
1223 /* Handle tx and rx flushes at the same time, since they run in
1224  * parallel in the hardware and there's no reason for us to
1225  * serialise them */
1226 int falcon_flush_queues(struct efx_nic *efx)
1227 {
1228         struct efx_rx_queue *rx_queue;
1229         struct efx_tx_queue *tx_queue;
1230         int i;
1231         bool outstanding;
1232
1233         /* Issue flush requests */
1234         efx_for_each_tx_queue(tx_queue, efx) {
1235                 tx_queue->flushed = false;
1236                 falcon_flush_tx_queue(tx_queue);
1237         }
1238         efx_for_each_rx_queue(rx_queue, efx) {
1239                 rx_queue->flushed = false;
1240                 falcon_flush_rx_queue(rx_queue);
1241         }
1242
1243         /* Poll the evq looking for flush completions. Since we're not pushing
1244          * any more rx or tx descriptors at this point, we're in no danger of
1245          * overflowing the evq whilst we wait */
1246         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1247                 msleep(FALCON_FLUSH_INTERVAL);
1248                 falcon_poll_flush_events(efx);
1249
1250                 /* Check if every queue has been succesfully flushed */
1251                 outstanding = false;
1252                 efx_for_each_tx_queue(tx_queue, efx)
1253                         outstanding |= !tx_queue->flushed;
1254                 efx_for_each_rx_queue(rx_queue, efx)
1255                         outstanding |= !rx_queue->flushed;
1256                 if (!outstanding)
1257                         return 0;
1258         }
1259
1260         /* Mark the queues as all flushed. We're going to return failure
1261          * leading to a reset, or fake up success anyway. "flushed" now
1262          * indicates that we tried to flush. */
1263         efx_for_each_tx_queue(tx_queue, efx) {
1264                 if (!tx_queue->flushed)
1265                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1266                                 tx_queue->queue);
1267                 tx_queue->flushed = true;
1268         }
1269         efx_for_each_rx_queue(rx_queue, efx) {
1270                 if (!rx_queue->flushed)
1271                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1272                                 rx_queue->queue);
1273                 rx_queue->flushed = true;
1274         }
1275
1276         if (EFX_WORKAROUND_7803(efx))
1277                 return 0;
1278
1279         return -ETIMEDOUT;
1280 }
1281
1282 /**************************************************************************
1283  *
1284  * Falcon hardware interrupts
1285  * The hardware interrupt handler does very little work; all the event
1286  * queue processing is carried out by per-channel tasklets.
1287  *
1288  **************************************************************************/
1289
1290 /* Enable/disable/generate Falcon interrupts */
1291 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1292                                      int force)
1293 {
1294         efx_oword_t int_en_reg_ker;
1295
1296         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1297                              FRF_AZ_KER_INT_KER, force,
1298                              FRF_AZ_DRV_INT_EN_KER, enabled);
1299         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1300 }
1301
1302 void falcon_enable_interrupts(struct efx_nic *efx)
1303 {
1304         efx_oword_t int_adr_reg_ker;
1305         struct efx_channel *channel;
1306
1307         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1308         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1309
1310         /* Program address */
1311         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1312                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1313                              EFX_INT_MODE_USE_MSI(efx),
1314                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1315         efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1316
1317         /* Enable interrupts */
1318         falcon_interrupts(efx, 1, 0);
1319
1320         /* Force processing of all the channels to get the EVQ RPTRs up to
1321            date */
1322         efx_for_each_channel(channel, efx)
1323                 efx_schedule_channel(channel);
1324 }
1325
1326 void falcon_disable_interrupts(struct efx_nic *efx)
1327 {
1328         /* Disable interrupts */
1329         falcon_interrupts(efx, 0, 0);
1330 }
1331
1332 /* Generate a Falcon test interrupt
1333  * Interrupt must already have been enabled, otherwise nasty things
1334  * may happen.
1335  */
1336 void falcon_generate_interrupt(struct efx_nic *efx)
1337 {
1338         falcon_interrupts(efx, 1, 1);
1339 }
1340
1341 /* Acknowledge a legacy interrupt from Falcon
1342  *
1343  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1344  *
1345  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1346  * BIU. Interrupt acknowledge is read sensitive so must write instead
1347  * (then read to ensure the BIU collector is flushed)
1348  *
1349  * NB most hardware supports MSI interrupts
1350  */
1351 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1352 {
1353         efx_dword_t reg;
1354
1355         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1356         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1357         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1358 }
1359
1360 /* Process a fatal interrupt
1361  * Disable bus mastering ASAP and schedule a reset
1362  */
1363 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1364 {
1365         struct falcon_nic_data *nic_data = efx->nic_data;
1366         efx_oword_t *int_ker = efx->irq_status.addr;
1367         efx_oword_t fatal_intr;
1368         int error, mem_perr;
1369
1370         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1371         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1372
1373         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1374                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1375                 EFX_OWORD_VAL(fatal_intr),
1376                 error ? "disabling bus mastering" : "no recognised error");
1377         if (error == 0)
1378                 goto out;
1379
1380         /* If this is a memory parity error dump which blocks are offending */
1381         mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1382         if (mem_perr) {
1383                 efx_oword_t reg;
1384                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1385                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1386                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1387         }
1388
1389         /* Disable both devices */
1390         pci_clear_master(efx->pci_dev);
1391         if (FALCON_IS_DUAL_FUNC(efx))
1392                 pci_clear_master(nic_data->pci_dev2);
1393         falcon_disable_interrupts(efx);
1394
1395         /* Count errors and reset or disable the NIC accordingly */
1396         if (efx->int_error_count == 0 ||
1397             time_after(jiffies, efx->int_error_expire)) {
1398                 efx->int_error_count = 0;
1399                 efx->int_error_expire =
1400                         jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1401         }
1402         if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1403                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1404                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1405         } else {
1406                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1407                         "NIC will be disabled\n");
1408                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1409         }
1410 out:
1411         return IRQ_HANDLED;
1412 }
1413
1414 /* Handle a legacy interrupt from Falcon
1415  * Acknowledges the interrupt and schedule event queue processing.
1416  */
1417 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1418 {
1419         struct efx_nic *efx = dev_id;
1420         efx_oword_t *int_ker = efx->irq_status.addr;
1421         irqreturn_t result = IRQ_NONE;
1422         struct efx_channel *channel;
1423         efx_dword_t reg;
1424         u32 queues;
1425         int syserr;
1426
1427         /* Read the ISR which also ACKs the interrupts */
1428         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1429         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1430
1431         /* Check to see if we have a serious error condition */
1432         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1433         if (unlikely(syserr))
1434                 return falcon_fatal_interrupt(efx);
1435
1436         /* Schedule processing of any interrupting queues */
1437         efx_for_each_channel(channel, efx) {
1438                 if ((queues & 1) ||
1439                     falcon_event_present(
1440                             falcon_event(channel, channel->eventq_read_ptr))) {
1441                         efx_schedule_channel(channel);
1442                         result = IRQ_HANDLED;
1443                 }
1444                 queues >>= 1;
1445         }
1446
1447         if (result == IRQ_HANDLED) {
1448                 efx->last_irq_cpu = raw_smp_processor_id();
1449                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1450                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1451         }
1452
1453         return result;
1454 }
1455
1456
1457 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1458 {
1459         struct efx_nic *efx = dev_id;
1460         efx_oword_t *int_ker = efx->irq_status.addr;
1461         struct efx_channel *channel;
1462         int syserr;
1463         int queues;
1464
1465         /* Check to see if this is our interrupt.  If it isn't, we
1466          * exit without having touched the hardware.
1467          */
1468         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1469                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1470                           raw_smp_processor_id());
1471                 return IRQ_NONE;
1472         }
1473         efx->last_irq_cpu = raw_smp_processor_id();
1474         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1475                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1476
1477         /* Check to see if we have a serious error condition */
1478         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1479         if (unlikely(syserr))
1480                 return falcon_fatal_interrupt(efx);
1481
1482         /* Determine interrupting queues, clear interrupt status
1483          * register and acknowledge the device interrupt.
1484          */
1485         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1486         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1487         EFX_ZERO_OWORD(*int_ker);
1488         wmb(); /* Ensure the vector is cleared before interrupt ack */
1489         falcon_irq_ack_a1(efx);
1490
1491         /* Schedule processing of any interrupting queues */
1492         channel = &efx->channel[0];
1493         while (queues) {
1494                 if (queues & 0x01)
1495                         efx_schedule_channel(channel);
1496                 channel++;
1497                 queues >>= 1;
1498         }
1499
1500         return IRQ_HANDLED;
1501 }
1502
1503 /* Handle an MSI interrupt from Falcon
1504  *
1505  * Handle an MSI hardware interrupt.  This routine schedules event
1506  * queue processing.  No interrupt acknowledgement cycle is necessary.
1507  * Also, we never need to check that the interrupt is for us, since
1508  * MSI interrupts cannot be shared.
1509  */
1510 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1511 {
1512         struct efx_channel *channel = dev_id;
1513         struct efx_nic *efx = channel->efx;
1514         efx_oword_t *int_ker = efx->irq_status.addr;
1515         int syserr;
1516
1517         efx->last_irq_cpu = raw_smp_processor_id();
1518         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1519                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1520
1521         /* Check to see if we have a serious error condition */
1522         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1523         if (unlikely(syserr))
1524                 return falcon_fatal_interrupt(efx);
1525
1526         /* Schedule processing of the channel */
1527         efx_schedule_channel(channel);
1528
1529         return IRQ_HANDLED;
1530 }
1531
1532
1533 /* Setup RSS indirection table.
1534  * This maps from the hash value of the packet to RXQ
1535  */
1536 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1537 {
1538         int i = 0;
1539         unsigned long offset;
1540         efx_dword_t dword;
1541
1542         if (falcon_rev(efx) < FALCON_REV_B0)
1543                 return;
1544
1545         for (offset = FR_BZ_RX_INDIRECTION_TBL;
1546              offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1547              offset += 0x10) {
1548                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1549                                      i % efx->n_rx_queues);
1550                 efx_writed(efx, &dword, offset);
1551                 i++;
1552         }
1553 }
1554
1555 /* Hook interrupt handler(s)
1556  * Try MSI and then legacy interrupts.
1557  */
1558 int falcon_init_interrupt(struct efx_nic *efx)
1559 {
1560         struct efx_channel *channel;
1561         int rc;
1562
1563         if (!EFX_INT_MODE_USE_MSI(efx)) {
1564                 irq_handler_t handler;
1565                 if (falcon_rev(efx) >= FALCON_REV_B0)
1566                         handler = falcon_legacy_interrupt_b0;
1567                 else
1568                         handler = falcon_legacy_interrupt_a1;
1569
1570                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1571                                  efx->name, efx);
1572                 if (rc) {
1573                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1574                                 efx->pci_dev->irq);
1575                         goto fail1;
1576                 }
1577                 return 0;
1578         }
1579
1580         /* Hook MSI or MSI-X interrupt */
1581         efx_for_each_channel(channel, efx) {
1582                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1583                                  IRQF_PROBE_SHARED, /* Not shared */
1584                                  channel->name, channel);
1585                 if (rc) {
1586                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1587                         goto fail2;
1588                 }
1589         }
1590
1591         return 0;
1592
1593  fail2:
1594         efx_for_each_channel(channel, efx)
1595                 free_irq(channel->irq, channel);
1596  fail1:
1597         return rc;
1598 }
1599
1600 void falcon_fini_interrupt(struct efx_nic *efx)
1601 {
1602         struct efx_channel *channel;
1603         efx_oword_t reg;
1604
1605         /* Disable MSI/MSI-X interrupts */
1606         efx_for_each_channel(channel, efx) {
1607                 if (channel->irq)
1608                         free_irq(channel->irq, channel);
1609         }
1610
1611         /* ACK legacy interrupt */
1612         if (falcon_rev(efx) >= FALCON_REV_B0)
1613                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1614         else
1615                 falcon_irq_ack_a1(efx);
1616
1617         /* Disable legacy interrupt */
1618         if (efx->legacy_irq)
1619                 free_irq(efx->legacy_irq, efx);
1620 }
1621
1622 /**************************************************************************
1623  *
1624  * EEPROM/flash
1625  *
1626  **************************************************************************
1627  */
1628
1629 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1630
1631 static int falcon_spi_poll(struct efx_nic *efx)
1632 {
1633         efx_oword_t reg;
1634         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1635         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1636 }
1637
1638 /* Wait for SPI command completion */
1639 static int falcon_spi_wait(struct efx_nic *efx)
1640 {
1641         /* Most commands will finish quickly, so we start polling at
1642          * very short intervals.  Sometimes the command may have to
1643          * wait for VPD or expansion ROM access outside of our
1644          * control, so we allow up to 100 ms. */
1645         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1646         int i;
1647
1648         for (i = 0; i < 10; i++) {
1649                 if (!falcon_spi_poll(efx))
1650                         return 0;
1651                 udelay(10);
1652         }
1653
1654         for (;;) {
1655                 if (!falcon_spi_poll(efx))
1656                         return 0;
1657                 if (time_after_eq(jiffies, timeout)) {
1658                         EFX_ERR(efx, "timed out waiting for SPI\n");
1659                         return -ETIMEDOUT;
1660                 }
1661                 schedule_timeout_uninterruptible(1);
1662         }
1663 }
1664
1665 int falcon_spi_cmd(const struct efx_spi_device *spi,
1666                    unsigned int command, int address,
1667                    const void *in, void *out, size_t len)
1668 {
1669         struct efx_nic *efx = spi->efx;
1670         bool addressed = (address >= 0);
1671         bool reading = (out != NULL);
1672         efx_oword_t reg;
1673         int rc;
1674
1675         /* Input validation */
1676         if (len > FALCON_SPI_MAX_LEN)
1677                 return -EINVAL;
1678         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1679
1680         /* Check that previous command is not still running */
1681         rc = falcon_spi_poll(efx);
1682         if (rc)
1683                 return rc;
1684
1685         /* Program address register, if we have an address */
1686         if (addressed) {
1687                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1688                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1689         }
1690
1691         /* Program data register, if we have data */
1692         if (in != NULL) {
1693                 memcpy(&reg, in, len);
1694                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1695         }
1696
1697         /* Issue read/write command */
1698         EFX_POPULATE_OWORD_7(reg,
1699                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1700                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1701                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
1702                              FRF_AB_EE_SPI_HCMD_READ, reading,
1703                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1704                              FRF_AB_EE_SPI_HCMD_ADBCNT,
1705                              (addressed ? spi->addr_len : 0),
1706                              FRF_AB_EE_SPI_HCMD_ENC, command);
1707         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1708
1709         /* Wait for read/write to complete */
1710         rc = falcon_spi_wait(efx);
1711         if (rc)
1712                 return rc;
1713
1714         /* Read data */
1715         if (out != NULL) {
1716                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1717                 memcpy(out, &reg, len);
1718         }
1719
1720         return 0;
1721 }
1722
1723 static size_t
1724 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1725 {
1726         return min(FALCON_SPI_MAX_LEN,
1727                    (spi->block_size - (start & (spi->block_size - 1))));
1728 }
1729
1730 static inline u8
1731 efx_spi_munge_command(const struct efx_spi_device *spi,
1732                       const u8 command, const unsigned int address)
1733 {
1734         return command | (((address >> 8) & spi->munge_address) << 3);
1735 }
1736
1737 /* Wait up to 10 ms for buffered write completion */
1738 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1739 {
1740         struct efx_nic *efx = spi->efx;
1741         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1742         u8 status;
1743         int rc;
1744
1745         for (;;) {
1746                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1747                                     &status, sizeof(status));
1748                 if (rc)
1749                         return rc;
1750                 if (!(status & SPI_STATUS_NRDY))
1751                         return 0;
1752                 if (time_after_eq(jiffies, timeout)) {
1753                         EFX_ERR(efx, "SPI write timeout on device %d"
1754                                 " last status=0x%02x\n",
1755                                 spi->device_id, status);
1756                         return -ETIMEDOUT;
1757                 }
1758                 schedule_timeout_uninterruptible(1);
1759         }
1760 }
1761
1762 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1763                     size_t len, size_t *retlen, u8 *buffer)
1764 {
1765         size_t block_len, pos = 0;
1766         unsigned int command;
1767         int rc = 0;
1768
1769         while (pos < len) {
1770                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1771
1772                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1773                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1774                                     buffer + pos, block_len);
1775                 if (rc)
1776                         break;
1777                 pos += block_len;
1778
1779                 /* Avoid locking up the system */
1780                 cond_resched();
1781                 if (signal_pending(current)) {
1782                         rc = -EINTR;
1783                         break;
1784                 }
1785         }
1786
1787         if (retlen)
1788                 *retlen = pos;
1789         return rc;
1790 }
1791
1792 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1793                      size_t len, size_t *retlen, const u8 *buffer)
1794 {
1795         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1796         size_t block_len, pos = 0;
1797         unsigned int command;
1798         int rc = 0;
1799
1800         while (pos < len) {
1801                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1802                 if (rc)
1803                         break;
1804
1805                 block_len = min(len - pos,
1806                                 falcon_spi_write_limit(spi, start + pos));
1807                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1808                 rc = falcon_spi_cmd(spi, command, start + pos,
1809                                     buffer + pos, NULL, block_len);
1810                 if (rc)
1811                         break;
1812
1813                 rc = falcon_spi_wait_write(spi);
1814                 if (rc)
1815                         break;
1816
1817                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1818                 rc = falcon_spi_cmd(spi, command, start + pos,
1819                                     NULL, verify_buffer, block_len);
1820                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1821                         rc = -EIO;
1822                         break;
1823                 }
1824
1825                 pos += block_len;
1826
1827                 /* Avoid locking up the system */
1828                 cond_resched();
1829                 if (signal_pending(current)) {
1830                         rc = -EINTR;
1831                         break;
1832                 }
1833         }
1834
1835         if (retlen)
1836                 *retlen = pos;
1837         return rc;
1838 }
1839
1840 /**************************************************************************
1841  *
1842  * MAC wrapper
1843  *
1844  **************************************************************************
1845  */
1846
1847 static int falcon_reset_macs(struct efx_nic *efx)
1848 {
1849         efx_oword_t reg;
1850         int count;
1851
1852         if (falcon_rev(efx) < FALCON_REV_B0) {
1853                 /* It's not safe to use GLB_CTL_REG to reset the
1854                  * macs, so instead use the internal MAC resets
1855                  */
1856                 if (!EFX_IS10G(efx)) {
1857                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1858                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1859                         udelay(1000);
1860
1861                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1862                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1863                         udelay(1000);
1864                         return 0;
1865                 } else {
1866                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1867                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1868
1869                         for (count = 0; count < 10000; count++) {
1870                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1871                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1872                                     0)
1873                                         return 0;
1874                                 udelay(10);
1875                         }
1876
1877                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1878                         return -ETIMEDOUT;
1879                 }
1880         }
1881
1882         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1883          * the drain sequence with the statistics fetch */
1884         efx_stats_disable(efx);
1885
1886         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1887         EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1888         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1889
1890         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1891         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1892         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1893         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1894         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1895
1896         count = 0;
1897         while (1) {
1898                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1899                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1900                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1901                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1902                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1903                                 count);
1904                         break;
1905                 }
1906                 if (count > 20) {
1907                         EFX_ERR(efx, "MAC reset failed\n");
1908                         break;
1909                 }
1910                 count++;
1911                 udelay(10);
1912         }
1913
1914         efx_stats_enable(efx);
1915
1916         /* If we've reset the EM block and the link is up, then
1917          * we'll have to kick the XAUI link so the PHY can recover */
1918         if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1919                 falcon_reset_xaui(efx);
1920
1921         return 0;
1922 }
1923
1924 void falcon_drain_tx_fifo(struct efx_nic *efx)
1925 {
1926         efx_oword_t reg;
1927
1928         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1929             (efx->loopback_mode != LOOPBACK_NONE))
1930                 return;
1931
1932         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1933         /* There is no point in draining more than once */
1934         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1935                 return;
1936
1937         falcon_reset_macs(efx);
1938 }
1939
1940 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1941 {
1942         efx_oword_t reg;
1943
1944         if (falcon_rev(efx) < FALCON_REV_B0)
1945                 return;
1946
1947         /* Isolate the MAC -> RX */
1948         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1949         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1950         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1951
1952         if (!efx->link_up)
1953                 falcon_drain_tx_fifo(efx);
1954 }
1955
1956 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1957 {
1958         efx_oword_t reg;
1959         int link_speed;
1960         bool tx_fc;
1961
1962         switch (efx->link_speed) {
1963         case 10000: link_speed = 3; break;
1964         case 1000:  link_speed = 2; break;
1965         case 100:   link_speed = 1; break;
1966         default:    link_speed = 0; break;
1967         }
1968         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1969          * as advertised.  Disable to ensure packets are not
1970          * indefinitely held and TX queue can be flushed at any point
1971          * while the link is down. */
1972         EFX_POPULATE_OWORD_5(reg,
1973                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1974                              FRF_AB_MAC_BCAD_ACPT, 1,
1975                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
1976                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1977                              FRF_AB_MAC_SPEED, link_speed);
1978         /* On B0, MAC backpressure can be disabled and packets get
1979          * discarded. */
1980         if (falcon_rev(efx) >= FALCON_REV_B0) {
1981                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1982                                     !efx->link_up);
1983         }
1984
1985         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1986
1987         /* Restore the multicast hash registers. */
1988         falcon_set_multicast_hash(efx);
1989
1990         /* Transmission of pause frames when RX crosses the threshold is
1991          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1992          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1993         tx_fc = !!(efx->link_fc & EFX_FC_TX);
1994         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1995         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
1996
1997         /* Unisolate the MAC -> RX */
1998         if (falcon_rev(efx) >= FALCON_REV_B0)
1999                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2000         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2001 }
2002
2003 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2004 {
2005         efx_oword_t reg;
2006         u32 *dma_done;
2007         int i;
2008
2009         if (disable_dma_stats)
2010                 return 0;
2011
2012         /* Statistics fetch will fail if the MAC is in TX drain */
2013         if (falcon_rev(efx) >= FALCON_REV_B0) {
2014                 efx_oword_t temp;
2015                 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2016                 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2017                         return 0;
2018         }
2019
2020         dma_done = (efx->stats_buffer.addr + done_offset);
2021         *dma_done = FALCON_STATS_NOT_DONE;
2022         wmb(); /* ensure done flag is clear */
2023
2024         /* Initiate DMA transfer of stats */
2025         EFX_POPULATE_OWORD_2(reg,
2026                              FRF_AB_MAC_STAT_DMA_CMD, 1,
2027                              FRF_AB_MAC_STAT_DMA_ADR,
2028                              efx->stats_buffer.dma_addr);
2029         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2030
2031         /* Wait for transfer to complete */
2032         for (i = 0; i < 400; i++) {
2033                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2034                         rmb(); /* Ensure the stats are valid. */
2035                         return 0;
2036                 }
2037                 udelay(10);
2038         }
2039
2040         EFX_ERR(efx, "timed out waiting for statistics\n");
2041         return -ETIMEDOUT;
2042 }
2043
2044 /**************************************************************************
2045  *
2046  * PHY access via GMII
2047  *
2048  **************************************************************************
2049  */
2050
2051 /* Wait for GMII access to complete */
2052 static int falcon_gmii_wait(struct efx_nic *efx)
2053 {
2054         efx_dword_t md_stat;
2055         int count;
2056
2057         /* wait upto 50ms - taken max from datasheet */
2058         for (count = 0; count < 5000; count++) {
2059                 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2060                 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2061                         if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2062                             EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2063                                 EFX_ERR(efx, "error from GMII access "
2064                                         EFX_DWORD_FMT"\n",
2065                                         EFX_DWORD_VAL(md_stat));
2066                                 return -EIO;
2067                         }
2068                         return 0;
2069                 }
2070                 udelay(10);
2071         }
2072         EFX_ERR(efx, "timed out waiting for GMII\n");
2073         return -ETIMEDOUT;
2074 }
2075
2076 /* Write an MDIO register of a PHY connected to Falcon. */
2077 static int falcon_mdio_write(struct net_device *net_dev,
2078                              int prtad, int devad, u16 addr, u16 value)
2079 {
2080         struct efx_nic *efx = netdev_priv(net_dev);
2081         efx_oword_t reg;
2082         int rc;
2083
2084         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2085                     prtad, devad, addr, value);
2086
2087         spin_lock_bh(&efx->phy_lock);
2088
2089         /* Check MDIO not currently being accessed */
2090         rc = falcon_gmii_wait(efx);
2091         if (rc)
2092                 goto out;
2093
2094         /* Write the address/ID register */
2095         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2096         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2097
2098         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2099                              FRF_AB_MD_DEV_ADR, devad);
2100         efx_writeo(efx, &reg, FR_AB_MD_ID);
2101
2102         /* Write data */
2103         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2104         efx_writeo(efx, &reg, FR_AB_MD_TXD);
2105
2106         EFX_POPULATE_OWORD_2(reg,
2107                              FRF_AB_MD_WRC, 1,
2108                              FRF_AB_MD_GC, 0);
2109         efx_writeo(efx, &reg, FR_AB_MD_CS);
2110
2111         /* Wait for data to be written */
2112         rc = falcon_gmii_wait(efx);
2113         if (rc) {
2114                 /* Abort the write operation */
2115                 EFX_POPULATE_OWORD_2(reg,
2116                                      FRF_AB_MD_WRC, 0,
2117                                      FRF_AB_MD_GC, 1);
2118                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2119                 udelay(10);
2120         }
2121
2122  out:
2123         spin_unlock_bh(&efx->phy_lock);
2124         return rc;
2125 }
2126
2127 /* Read an MDIO register of a PHY connected to Falcon. */
2128 static int falcon_mdio_read(struct net_device *net_dev,
2129                             int prtad, int devad, u16 addr)
2130 {
2131         struct efx_nic *efx = netdev_priv(net_dev);
2132         efx_oword_t reg;
2133         int rc;
2134
2135         spin_lock_bh(&efx->phy_lock);
2136
2137         /* Check MDIO not currently being accessed */
2138         rc = falcon_gmii_wait(efx);
2139         if (rc)
2140                 goto out;
2141
2142         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2143         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2144
2145         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2146                              FRF_AB_MD_DEV_ADR, devad);
2147         efx_writeo(efx, &reg, FR_AB_MD_ID);
2148
2149         /* Request data to be read */
2150         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2151         efx_writeo(efx, &reg, FR_AB_MD_CS);
2152
2153         /* Wait for data to become available */
2154         rc = falcon_gmii_wait(efx);
2155         if (rc == 0) {
2156                 efx_reado(efx, &reg, FR_AB_MD_RXD);
2157                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2158                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2159                             prtad, devad, addr, rc);
2160         } else {
2161                 /* Abort the read operation */
2162                 EFX_POPULATE_OWORD_2(reg,
2163                                      FRF_AB_MD_RIC, 0,
2164                                      FRF_AB_MD_GC, 1);
2165                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2166
2167                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2168                         prtad, devad, addr, rc);
2169         }
2170
2171  out:
2172         spin_unlock_bh(&efx->phy_lock);
2173         return rc;
2174 }
2175
2176 static int falcon_probe_phy(struct efx_nic *efx)
2177 {
2178         switch (efx->phy_type) {
2179         case PHY_TYPE_SFX7101:
2180                 efx->phy_op = &falcon_sfx7101_phy_ops;
2181                 break;
2182         case PHY_TYPE_SFT9001A:
2183         case PHY_TYPE_SFT9001B:
2184                 efx->phy_op = &falcon_sft9001_phy_ops;
2185                 break;
2186         case PHY_TYPE_QT2022C2:
2187         case PHY_TYPE_QT2025C:
2188                 efx->phy_op = &falcon_xfp_phy_ops;
2189                 break;
2190         default:
2191                 EFX_ERR(efx, "Unknown PHY type %d\n",
2192                         efx->phy_type);
2193                 return -1;
2194         }
2195
2196         if (efx->phy_op->macs & EFX_XMAC)
2197                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2198                                         (1 << LOOPBACK_XGXS) |
2199                                         (1 << LOOPBACK_XAUI));
2200         if (efx->phy_op->macs & EFX_GMAC)
2201                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2202         efx->loopback_modes |= efx->phy_op->loopbacks;
2203
2204         return 0;
2205 }
2206
2207 int falcon_switch_mac(struct efx_nic *efx)
2208 {
2209         struct efx_mac_operations *old_mac_op = efx->mac_op;
2210         efx_oword_t nic_stat;
2211         unsigned strap_val;
2212         int rc = 0;
2213
2214         /* Don't try to fetch MAC stats while we're switching MACs */
2215         efx_stats_disable(efx);
2216
2217         /* Internal loopbacks override the phy speed setting */
2218         if (efx->loopback_mode == LOOPBACK_GMAC) {
2219                 efx->link_speed = 1000;
2220                 efx->link_fd = true;
2221         } else if (LOOPBACK_INTERNAL(efx)) {
2222                 efx->link_speed = 10000;
2223                 efx->link_fd = true;
2224         }
2225
2226         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2227         efx->mac_op = (EFX_IS10G(efx) ?
2228                        &falcon_xmac_operations : &falcon_gmac_operations);
2229
2230         /* Always push the NIC_STAT_REG setting even if the mac hasn't
2231          * changed, because this function is run post online reset */
2232         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2233         strap_val = EFX_IS10G(efx) ? 5 : 3;
2234         if (falcon_rev(efx) >= FALCON_REV_B0) {
2235                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2236                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2237                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2238         } else {
2239                 /* Falcon A1 does not support 1G/10G speed switching
2240                  * and must not be used with a PHY that does. */
2241                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2242                        strap_val);
2243         }
2244
2245         if (old_mac_op == efx->mac_op)
2246                 goto out;
2247
2248         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2249         /* Not all macs support a mac-level link state */
2250         efx->mac_up = true;
2251
2252         rc = falcon_reset_macs(efx);
2253 out:
2254         efx_stats_enable(efx);
2255         return rc;
2256 }
2257
2258 /* This call is responsible for hooking in the MAC and PHY operations */
2259 int falcon_probe_port(struct efx_nic *efx)
2260 {
2261         int rc;
2262
2263         /* Hook in PHY operations table */
2264         rc = falcon_probe_phy(efx);
2265         if (rc)
2266                 return rc;
2267
2268         /* Set up MDIO structure for PHY */
2269         efx->mdio.mmds = efx->phy_op->mmds;
2270         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2271         efx->mdio.mdio_read = falcon_mdio_read;
2272         efx->mdio.mdio_write = falcon_mdio_write;
2273
2274         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2275         if (falcon_rev(efx) >= FALCON_REV_B0)
2276                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2277         else
2278                 efx->wanted_fc = EFX_FC_RX;
2279
2280         /* Allocate buffer for stats */
2281         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2282                                  FALCON_MAC_STATS_SIZE);
2283         if (rc)
2284                 return rc;
2285         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2286                 (u64)efx->stats_buffer.dma_addr,
2287                 efx->stats_buffer.addr,
2288                 (u64)virt_to_phys(efx->stats_buffer.addr));
2289
2290         return 0;
2291 }
2292
2293 void falcon_remove_port(struct efx_nic *efx)
2294 {
2295         falcon_free_buffer(efx, &efx->stats_buffer);
2296 }
2297
2298 /**************************************************************************
2299  *
2300  * Multicast filtering
2301  *
2302  **************************************************************************
2303  */
2304
2305 void falcon_set_multicast_hash(struct efx_nic *efx)
2306 {
2307         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2308
2309         /* Broadcast packets go through the multicast hash filter.
2310          * ether_crc_le() of the broadcast address is 0xbe2612ff
2311          * so we always add bit 0xff to the mask.
2312          */
2313         set_bit_le(0xff, mc_hash->byte);
2314
2315         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2316         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2317 }
2318
2319
2320 /**************************************************************************
2321  *
2322  * Falcon test code
2323  *
2324  **************************************************************************/
2325
2326 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2327 {
2328         struct falcon_nvconfig *nvconfig;
2329         struct efx_spi_device *spi;
2330         void *region;
2331         int rc, magic_num, struct_ver;
2332         __le16 *word, *limit;
2333         u32 csum;
2334
2335         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2336         if (!spi)
2337                 return -EINVAL;
2338
2339         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2340         if (!region)
2341                 return -ENOMEM;
2342         nvconfig = region + FALCON_NVCONFIG_OFFSET;
2343
2344         mutex_lock(&efx->spi_lock);
2345         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2346         mutex_unlock(&efx->spi_lock);
2347         if (rc) {
2348                 EFX_ERR(efx, "Failed to read %s\n",
2349                         efx->spi_flash ? "flash" : "EEPROM");
2350                 rc = -EIO;
2351                 goto out;
2352         }
2353
2354         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2355         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2356
2357         rc = -EINVAL;
2358         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2359                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2360                 goto out;
2361         }
2362         if (struct_ver < 2) {
2363                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2364                 goto out;
2365         } else if (struct_ver < 4) {
2366                 word = &nvconfig->board_magic_num;
2367                 limit = (__le16 *) (nvconfig + 1);
2368         } else {
2369                 word = region;
2370                 limit = region + FALCON_NVCONFIG_END;
2371         }
2372         for (csum = 0; word < limit; ++word)
2373                 csum += le16_to_cpu(*word);
2374
2375         if (~csum & 0xffff) {
2376                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2377                 goto out;
2378         }
2379
2380         rc = 0;
2381         if (nvconfig_out)
2382                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2383
2384  out:
2385         kfree(region);
2386         return rc;
2387 }
2388
2389 /* Registers tested in the falcon register test */
2390 static struct {
2391         unsigned address;
2392         efx_oword_t mask;
2393 } efx_test_registers[] = {
2394         { FR_AZ_ADR_REGION,
2395           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2396         { FR_AZ_RX_CFG,
2397           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2398         { FR_AZ_TX_CFG,
2399           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2400         { FR_AZ_TX_RESERVED,
2401           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2402         { FR_AB_MAC_CTRL,
2403           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2404         { FR_AZ_SRM_TX_DC_CFG,
2405           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2406         { FR_AZ_RX_DC_CFG,
2407           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2408         { FR_AZ_RX_DC_PF_WM,
2409           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2410         { FR_BZ_DP_CTRL,
2411           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2412         { FR_AB_GM_CFG2,
2413           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2414         { FR_AB_GMF_CFG0,
2415           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2416         { FR_AB_XM_GLB_CFG,
2417           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2418         { FR_AB_XM_TX_CFG,
2419           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2420         { FR_AB_XM_RX_CFG,
2421           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2422         { FR_AB_XM_RX_PARAM,
2423           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2424         { FR_AB_XM_FC,
2425           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2426         { FR_AB_XM_ADR_LO,
2427           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2428         { FR_AB_XX_SD_CTL,
2429           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2430 };
2431
2432 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2433                                      const efx_oword_t *mask)
2434 {
2435         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2436                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2437 }
2438
2439 int falcon_test_registers(struct efx_nic *efx)
2440 {
2441         unsigned address = 0, i, j;
2442         efx_oword_t mask, imask, original, reg, buf;
2443
2444         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2445         WARN_ON(!LOOPBACK_INTERNAL(efx));
2446
2447         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2448                 address = efx_test_registers[i].address;
2449                 mask = imask = efx_test_registers[i].mask;
2450                 EFX_INVERT_OWORD(imask);
2451
2452                 efx_reado(efx, &original, address);
2453
2454                 /* bit sweep on and off */
2455                 for (j = 0; j < 128; j++) {
2456                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2457                                 continue;
2458
2459                         /* Test this testable bit can be set in isolation */
2460                         EFX_AND_OWORD(reg, original, mask);
2461                         EFX_SET_OWORD32(reg, j, j, 1);
2462
2463                         efx_writeo(efx, &reg, address);
2464                         efx_reado(efx, &buf, address);
2465
2466                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2467                                 goto fail;
2468
2469                         /* Test this testable bit can be cleared in isolation */
2470                         EFX_OR_OWORD(reg, original, mask);
2471                         EFX_SET_OWORD32(reg, j, j, 0);
2472
2473                         efx_writeo(efx, &reg, address);
2474                         efx_reado(efx, &buf, address);
2475
2476                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2477                                 goto fail;
2478                 }
2479
2480                 efx_writeo(efx, &original, address);
2481         }
2482
2483         return 0;
2484
2485 fail:
2486         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2487                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2488                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2489         return -EIO;
2490 }
2491
2492 /**************************************************************************
2493  *
2494  * Device reset
2495  *
2496  **************************************************************************
2497  */
2498
2499 /* Resets NIC to known state.  This routine must be called in process
2500  * context and is allowed to sleep. */
2501 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2502 {
2503         struct falcon_nic_data *nic_data = efx->nic_data;
2504         efx_oword_t glb_ctl_reg_ker;
2505         int rc;
2506
2507         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2508
2509         /* Initiate device reset */
2510         if (method == RESET_TYPE_WORLD) {
2511                 rc = pci_save_state(efx->pci_dev);
2512                 if (rc) {
2513                         EFX_ERR(efx, "failed to backup PCI state of primary "
2514                                 "function prior to hardware reset\n");
2515                         goto fail1;
2516                 }
2517                 if (FALCON_IS_DUAL_FUNC(efx)) {
2518                         rc = pci_save_state(nic_data->pci_dev2);
2519                         if (rc) {
2520                                 EFX_ERR(efx, "failed to backup PCI state of "
2521                                         "secondary function prior to "
2522                                         "hardware reset\n");
2523                                 goto fail2;
2524                         }
2525                 }
2526
2527                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2528                                      FRF_AB_EXT_PHY_RST_DUR,
2529                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2530                                      FRF_AB_SWRST, 1);
2531         } else {
2532                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2533                                      /* exclude PHY from "invisible" reset */
2534                                      FRF_AB_EXT_PHY_RST_CTL,
2535                                      method == RESET_TYPE_INVISIBLE,
2536                                      /* exclude EEPROM/flash and PCIe */
2537                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
2538                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2539                                      FRF_AB_PCIE_SD_RST_CTL, 1,
2540                                      FRF_AB_EE_RST_CTL, 1,
2541                                      FRF_AB_EXT_PHY_RST_DUR,
2542                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2543                                      FRF_AB_SWRST, 1);
2544         }
2545         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2546
2547         EFX_LOG(efx, "waiting for hardware reset\n");
2548         schedule_timeout_uninterruptible(HZ / 20);
2549
2550         /* Restore PCI configuration if needed */
2551         if (method == RESET_TYPE_WORLD) {
2552                 if (FALCON_IS_DUAL_FUNC(efx)) {
2553                         rc = pci_restore_state(nic_data->pci_dev2);
2554                         if (rc) {
2555                                 EFX_ERR(efx, "failed to restore PCI config for "
2556                                         "the secondary function\n");
2557                                 goto fail3;
2558                         }
2559                 }
2560                 rc = pci_restore_state(efx->pci_dev);
2561                 if (rc) {
2562                         EFX_ERR(efx, "failed to restore PCI config for the "
2563                                 "primary function\n");
2564                         goto fail4;
2565                 }
2566                 EFX_LOG(efx, "successfully restored PCI config\n");
2567         }
2568
2569         /* Assert that reset complete */
2570         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2571         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2572                 rc = -ETIMEDOUT;
2573                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2574                 goto fail5;
2575         }
2576         EFX_LOG(efx, "hardware reset complete\n");
2577
2578         return 0;
2579
2580         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2581 fail2:
2582 fail3:
2583         pci_restore_state(efx->pci_dev);
2584 fail1:
2585 fail4:
2586 fail5:
2587         return rc;
2588 }
2589
2590 /* Zeroes out the SRAM contents.  This routine must be called in
2591  * process context and is allowed to sleep.
2592  */
2593 static int falcon_reset_sram(struct efx_nic *efx)
2594 {
2595         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2596         int count;
2597
2598         /* Set the SRAM wake/sleep GPIO appropriately. */
2599         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2600         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2601         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2602         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2603
2604         /* Initiate SRAM reset */
2605         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2606                              FRF_AZ_SRM_INIT_EN, 1,
2607                              FRF_AZ_SRM_NB_SZ, 0);
2608         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2609
2610         /* Wait for SRAM reset to complete */
2611         count = 0;
2612         do {
2613                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2614
2615                 /* SRAM reset is slow; expect around 16ms */
2616                 schedule_timeout_uninterruptible(HZ / 50);
2617
2618                 /* Check for reset complete */
2619                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2620                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2621                         EFX_LOG(efx, "SRAM reset complete\n");
2622
2623                         return 0;
2624                 }
2625         } while (++count < 20); /* wait upto 0.4 sec */
2626
2627         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2628         return -ETIMEDOUT;
2629 }
2630
2631 static int falcon_spi_device_init(struct efx_nic *efx,
2632                                   struct efx_spi_device **spi_device_ret,
2633                                   unsigned int device_id, u32 device_type)
2634 {
2635         struct efx_spi_device *spi_device;
2636
2637         if (device_type != 0) {
2638                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2639                 if (!spi_device)
2640                         return -ENOMEM;
2641                 spi_device->device_id = device_id;
2642                 spi_device->size =
2643                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2644                 spi_device->addr_len =
2645                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2646                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2647                                              spi_device->addr_len == 1);
2648                 spi_device->erase_command =
2649                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2650                 spi_device->erase_size =
2651                         1 << SPI_DEV_TYPE_FIELD(device_type,
2652                                                 SPI_DEV_TYPE_ERASE_SIZE);
2653                 spi_device->block_size =
2654                         1 << SPI_DEV_TYPE_FIELD(device_type,
2655                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2656
2657                 spi_device->efx = efx;
2658         } else {
2659                 spi_device = NULL;
2660         }
2661
2662         kfree(*spi_device_ret);
2663         *spi_device_ret = spi_device;
2664         return 0;
2665 }
2666
2667
2668 static void falcon_remove_spi_devices(struct efx_nic *efx)
2669 {
2670         kfree(efx->spi_eeprom);
2671         efx->spi_eeprom = NULL;
2672         kfree(efx->spi_flash);
2673         efx->spi_flash = NULL;
2674 }
2675
2676 /* Extract non-volatile configuration */
2677 static int falcon_probe_nvconfig(struct efx_nic *efx)
2678 {
2679         struct falcon_nvconfig *nvconfig;
2680         int board_rev;
2681         int rc;
2682
2683         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2684         if (!nvconfig)
2685                 return -ENOMEM;
2686
2687         rc = falcon_read_nvram(efx, nvconfig);
2688         if (rc == -EINVAL) {
2689                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2690                 efx->phy_type = PHY_TYPE_NONE;
2691                 efx->mdio.prtad = MDIO_PRTAD_NONE;
2692                 board_rev = 0;
2693                 rc = 0;
2694         } else if (rc) {
2695                 goto fail1;
2696         } else {
2697                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2698                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2699
2700                 efx->phy_type = v2->port0_phy_type;
2701                 efx->mdio.prtad = v2->port0_phy_addr;
2702                 board_rev = le16_to_cpu(v2->board_revision);
2703
2704                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2705                         rc = falcon_spi_device_init(
2706                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2707                                 le32_to_cpu(v3->spi_device_type
2708                                             [FFE_AB_SPI_DEVICE_FLASH]));
2709                         if (rc)
2710                                 goto fail2;
2711                         rc = falcon_spi_device_init(
2712                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2713                                 le32_to_cpu(v3->spi_device_type
2714                                             [FFE_AB_SPI_DEVICE_EEPROM]));
2715                         if (rc)
2716                                 goto fail2;
2717                 }
2718         }
2719
2720         /* Read the MAC addresses */
2721         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2722
2723         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2724
2725         falcon_probe_board(efx, board_rev);
2726
2727         kfree(nvconfig);
2728         return 0;
2729
2730  fail2:
2731         falcon_remove_spi_devices(efx);
2732  fail1:
2733         kfree(nvconfig);
2734         return rc;
2735 }
2736
2737 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2738  * count, port speed).  Set workaround and feature flags accordingly.
2739  */
2740 static int falcon_probe_nic_variant(struct efx_nic *efx)
2741 {
2742         efx_oword_t altera_build;
2743         efx_oword_t nic_stat;
2744
2745         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2746         if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2747                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2748                 return -ENODEV;
2749         }
2750
2751         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2752
2753         switch (falcon_rev(efx)) {
2754         case FALCON_REV_A0:
2755         case 0xff:
2756                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2757                 return -ENODEV;
2758
2759         case FALCON_REV_A1:
2760                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2761                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2762                         return -ENODEV;
2763                 }
2764                 break;
2765
2766         case FALCON_REV_B0:
2767                 break;
2768
2769         default:
2770                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2771                 return -ENODEV;
2772         }
2773
2774         /* Initial assumed speed */
2775         efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2776
2777         return 0;
2778 }
2779
2780 /* Probe all SPI devices on the NIC */
2781 static void falcon_probe_spi_devices(struct efx_nic *efx)
2782 {
2783         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2784         int boot_dev;
2785
2786         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2787         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2788         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2789
2790         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2791                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2792                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2793                 EFX_LOG(efx, "Booted from %s\n",
2794                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2795         } else {
2796                 /* Disable VPD and set clock dividers to safe
2797                  * values for initial programming. */
2798                 boot_dev = -1;
2799                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2800                         " setting SPI config\n");
2801                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2802                                      /* 125 MHz / 7 ~= 20 MHz */
2803                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2804                                      /* 125 MHz / 63 ~= 2 MHz */
2805                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2806                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2807         }
2808
2809         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2810                 falcon_spi_device_init(efx, &efx->spi_flash,
2811                                        FFE_AB_SPI_DEVICE_FLASH,
2812                                        default_flash_type);
2813         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2814                 falcon_spi_device_init(efx, &efx->spi_eeprom,
2815                                        FFE_AB_SPI_DEVICE_EEPROM,
2816                                        large_eeprom_type);
2817 }
2818
2819 int falcon_probe_nic(struct efx_nic *efx)
2820 {
2821         struct falcon_nic_data *nic_data;
2822         int rc;
2823
2824         /* Allocate storage for hardware specific data */
2825         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2826         if (!nic_data)
2827                 return -ENOMEM;
2828         efx->nic_data = nic_data;
2829
2830         /* Determine number of ports etc. */
2831         rc = falcon_probe_nic_variant(efx);
2832         if (rc)
2833                 goto fail1;
2834
2835         /* Probe secondary function if expected */
2836         if (FALCON_IS_DUAL_FUNC(efx)) {
2837                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2838
2839                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2840                                              dev))) {
2841                         if (dev->bus == efx->pci_dev->bus &&
2842                             dev->devfn == efx->pci_dev->devfn + 1) {
2843                                 nic_data->pci_dev2 = dev;
2844                                 break;
2845                         }
2846                 }
2847                 if (!nic_data->pci_dev2) {
2848                         EFX_ERR(efx, "failed to find secondary function\n");
2849                         rc = -ENODEV;
2850                         goto fail2;
2851                 }
2852         }
2853
2854         /* Now we can reset the NIC */
2855         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2856         if (rc) {
2857                 EFX_ERR(efx, "failed to reset NIC\n");
2858                 goto fail3;
2859         }
2860
2861         /* Allocate memory for INT_KER */
2862         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2863         if (rc)
2864                 goto fail4;
2865         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2866
2867         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2868                 (u64)efx->irq_status.dma_addr,
2869                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2870
2871         falcon_probe_spi_devices(efx);
2872
2873         /* Read in the non-volatile configuration */
2874         rc = falcon_probe_nvconfig(efx);
2875         if (rc)
2876                 goto fail5;
2877
2878         /* Initialise I2C adapter */
2879         efx->i2c_adap.owner = THIS_MODULE;
2880         nic_data->i2c_data = falcon_i2c_bit_operations;
2881         nic_data->i2c_data.data = efx;
2882         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2883         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2884         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2885         rc = i2c_bit_add_bus(&efx->i2c_adap);
2886         if (rc)
2887                 goto fail5;
2888
2889         return 0;
2890
2891  fail5:
2892         falcon_remove_spi_devices(efx);
2893         falcon_free_buffer(efx, &efx->irq_status);
2894  fail4:
2895  fail3:
2896         if (nic_data->pci_dev2) {
2897                 pci_dev_put(nic_data->pci_dev2);
2898                 nic_data->pci_dev2 = NULL;
2899         }
2900  fail2:
2901  fail1:
2902         kfree(efx->nic_data);
2903         return rc;
2904 }
2905
2906 static void falcon_init_rx_cfg(struct efx_nic *efx)
2907 {
2908         /* Prior to Siena the RX DMA engine will split each frame at
2909          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2910          * be so large that that never happens. */
2911         const unsigned huge_buf_size = (3 * 4096) >> 5;
2912         /* RX control FIFO thresholds (32 entries) */
2913         const unsigned ctrl_xon_thr = 20;
2914         const unsigned ctrl_xoff_thr = 25;
2915         /* RX data FIFO thresholds (256-byte units; size varies) */
2916         int data_xon_thr = rx_xon_thresh_bytes >> 8;
2917         int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2918         efx_oword_t reg;
2919
2920         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2921         if (falcon_rev(efx) <= FALCON_REV_A1) {
2922                 /* Data FIFO size is 5.5K */
2923                 if (data_xon_thr < 0)
2924                         data_xon_thr = 512 >> 8;
2925                 if (data_xoff_thr < 0)
2926                         data_xoff_thr = 2048 >> 8;
2927                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2928                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2929                                     huge_buf_size);
2930                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2931                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2932                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2933                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2934         } else {
2935                 /* Data FIFO size is 80K; register fields moved */
2936                 if (data_xon_thr < 0)
2937                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2938                 if (data_xoff_thr < 0)
2939                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2940                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2941                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2942                                     huge_buf_size);
2943                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2944                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2945                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2946                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2947                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2948         }
2949         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2950 }
2951
2952 /* This call performs hardware-specific global initialisation, such as
2953  * defining the descriptor cache sizes and number of RSS channels.
2954  * It does not set up any buffers, descriptor rings or event queues.
2955  */
2956 int falcon_init_nic(struct efx_nic *efx)
2957 {
2958         efx_oword_t temp;
2959         int rc;
2960
2961         /* Use on-chip SRAM */
2962         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2963         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2964         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2965
2966         /* Set the source of the GMAC clock */
2967         if (falcon_rev(efx) == FALCON_REV_B0) {
2968                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2969                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2970                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2971         }
2972
2973         rc = falcon_reset_sram(efx);
2974         if (rc)
2975                 return rc;
2976
2977         /* Set positions of descriptor caches in SRAM. */
2978         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2979         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
2980         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2981         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
2982
2983         /* Set TX descriptor cache size. */
2984         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2985         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2986         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
2987
2988         /* Set RX descriptor cache size.  Set low watermark to size-8, as
2989          * this allows most efficient prefetching.
2990          */
2991         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2992         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2993         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
2994         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2995         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
2996
2997         /* Clear the parity enables on the TX data fifos as
2998          * they produce false parity errors because of timing issues
2999          */
3000         if (EFX_WORKAROUND_5129(efx)) {
3001                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3002                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3003                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3004         }
3005
3006         /* Enable all the genuinely fatal interrupts.  (They are still
3007          * masked by the overall interrupt mask, controlled by
3008          * falcon_interrupts()).
3009          *
3010          * Note: All other fatal interrupts are enabled
3011          */
3012         EFX_POPULATE_OWORD_3(temp,
3013                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3014                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3015                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3016         EFX_INVERT_OWORD(temp);
3017         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3018
3019         if (EFX_WORKAROUND_7244(efx)) {
3020                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3021                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3022                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3023                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3024                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3025                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3026         }
3027
3028         falcon_setup_rss_indir_table(efx);
3029
3030         /* XXX This is documented only for Falcon A0/A1 */
3031         /* Setup RX.  Wait for descriptor is broken and must
3032          * be disabled.  RXDP recovery shouldn't be needed, but is.
3033          */
3034         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3035         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3036         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3037         if (EFX_WORKAROUND_5583(efx))
3038                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3039         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3040
3041         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3042          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3043          */
3044         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3045         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3046         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3047         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3048         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3049         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3050         /* Enable SW_EV to inherit in char driver - assume harmless here */
3051         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3052         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3053         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3054         /* Squash TX of packets of 16 bytes or less */
3055         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3056                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3057         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3058
3059         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3060          * descriptors (which is bad).
3061          */
3062         efx_reado(efx, &temp, FR_AZ_TX_CFG);
3063         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3064         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3065
3066         falcon_init_rx_cfg(efx);
3067
3068         /* Set destination of both TX and RX Flush events */
3069         if (falcon_rev(efx) >= FALCON_REV_B0) {
3070                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3071                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3072         }
3073
3074         return 0;
3075 }
3076
3077 void falcon_remove_nic(struct efx_nic *efx)
3078 {
3079         struct falcon_nic_data *nic_data = efx->nic_data;
3080         int rc;
3081
3082         /* Remove I2C adapter and clear it in preparation for a retry */
3083         rc = i2c_del_adapter(&efx->i2c_adap);
3084         BUG_ON(rc);
3085         memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3086
3087         falcon_remove_spi_devices(efx);
3088         falcon_free_buffer(efx, &efx->irq_status);
3089
3090         falcon_reset_hw(efx, RESET_TYPE_ALL);
3091
3092         /* Release the second function after the reset */
3093         if (nic_data->pci_dev2) {
3094                 pci_dev_put(nic_data->pci_dev2);
3095                 nic_data->pci_dev2 = NULL;
3096         }
3097
3098         /* Tear down the private nic state */
3099         kfree(efx->nic_data);
3100         efx->nic_data = NULL;
3101 }
3102
3103 void falcon_update_nic_stats(struct efx_nic *efx)
3104 {
3105         efx_oword_t cnt;
3106
3107         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3108         efx->n_rx_nodesc_drop_cnt +=
3109                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3110 }
3111
3112 /**************************************************************************
3113  *
3114  * Revision-dependent attributes used by efx.c
3115  *
3116  **************************************************************************
3117  */
3118
3119 struct efx_nic_type falcon_a_nic_type = {
3120         .mem_bar = 2,
3121         .mem_map_size = 0x20000,
3122         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3123         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3124         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3125         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3126         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3127         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3128         .rx_buffer_padding = 0x24,
3129         .max_interrupt_mode = EFX_INT_MODE_MSI,
3130         .phys_addr_channels = 4,
3131 };
3132
3133 struct efx_nic_type falcon_b_nic_type = {
3134         .mem_bar = 2,
3135         /* Map everything up to and including the RSS indirection
3136          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3137          * requires that they not be mapped.  */
3138         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3139                          FR_BZ_RX_INDIRECTION_TBL_STEP *
3140                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
3141         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3142         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3143         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3144         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3145         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3146         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3147         .rx_buffer_padding = 0,
3148         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3149         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3150                                    * interrupt handler only supports 32
3151                                    * channels */
3152 };
3153