sfc: Move RX data FIFO thresholds out of struct efx_nic_type
[linux-2.6.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2008 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Falcon hardware control.
32  * Falcon is the internal codename for the SFC4000 controller that is
33  * present in SFE400X evaluation boards
34  */
35
36 /**
37  * struct falcon_nic_data - Falcon NIC state
38  * @next_buffer_table: First available buffer table id
39  * @pci_dev2: The secondary PCI device if present
40  * @i2c_data: Operations and state for I2C bit-bashing algorithm
41  * @int_error_count: Number of internal errors seen recently
42  * @int_error_expire: Time at which error count will be expired
43  */
44 struct falcon_nic_data {
45         unsigned next_buffer_table;
46         struct pci_dev *pci_dev2;
47         struct i2c_algo_bit_data i2c_data;
48
49         unsigned int_error_count;
50         unsigned long int_error_expire;
51 };
52
53 /**************************************************************************
54  *
55  * Configurable values
56  *
57  **************************************************************************
58  */
59
60 static int disable_dma_stats;
61
62 /* This is set to 16 for a good reason.  In summary, if larger than
63  * 16, the descriptor cache holds more than a default socket
64  * buffer's worth of packets (for UDP we can only have at most one
65  * socket buffer's worth outstanding).  This combined with the fact
66  * that we only get 1 TX event per descriptor cache means the NIC
67  * goes idle.
68  */
69 #define TX_DC_ENTRIES 16
70 #define TX_DC_ENTRIES_ORDER 0
71 #define TX_DC_BASE 0x130000
72
73 #define RX_DC_ENTRIES 64
74 #define RX_DC_ENTRIES_ORDER 2
75 #define RX_DC_BASE 0x100000
76
77 static const unsigned int
78 /* "Large" EEPROM device: Atmel AT25640 or similar
79  * 8 KB, 16-bit address, 32 B write block */
80 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
81                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
82                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
83 /* Default flash device: Atmel AT25F1024
84  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
85 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
86                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
87                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
88                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
89                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
90
91 /* RX FIFO XOFF watermark
92  *
93  * When the amount of the RX FIFO increases used increases past this
94  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
95  * This also has an effect on RX/TX arbitration
96  */
97 static int rx_xoff_thresh_bytes = -1;
98 module_param(rx_xoff_thresh_bytes, int, 0644);
99 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
100
101 /* RX FIFO XON watermark
102  *
103  * When the amount of the RX FIFO used decreases below this
104  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
105  * This also has an effect on RX/TX arbitration
106  */
107 static int rx_xon_thresh_bytes = -1;
108 module_param(rx_xon_thresh_bytes, int, 0644);
109 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
110
111 /* TX descriptor ring size - min 512 max 4k */
112 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
113 #define FALCON_TXD_RING_SIZE 1024
114 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
115
116 /* RX descriptor ring size - min 512 max 4k */
117 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
118 #define FALCON_RXD_RING_SIZE 1024
119 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
120
121 /* Event queue size - max 32k */
122 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
123 #define FALCON_EVQ_SIZE 4096
124 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
125
126 /* If FALCON_MAX_INT_ERRORS internal errors occur within
127  * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
128  * disable it.
129  */
130 #define FALCON_INT_ERROR_EXPIRE 3600
131 #define FALCON_MAX_INT_ERRORS 5
132
133 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
134  */
135 #define FALCON_FLUSH_INTERVAL 10
136 #define FALCON_FLUSH_POLL_COUNT 100
137
138 /**************************************************************************
139  *
140  * Falcon constants
141  *
142  **************************************************************************
143  */
144
145 /* DMA address mask */
146 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
147
148 /* TX DMA length mask (13-bit) */
149 #define FALCON_TX_DMA_MASK (4096 - 1)
150
151 /* Size and alignment of special buffers (4KB) */
152 #define FALCON_BUF_SIZE 4096
153
154 /* Dummy SRAM size code */
155 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
156
157 #define FALCON_IS_DUAL_FUNC(efx)                \
158         (falcon_rev(efx) < FALCON_REV_B0)
159
160 /**************************************************************************
161  *
162  * Falcon hardware access
163  *
164  **************************************************************************/
165
166 /* Read the current event from the event queue */
167 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
168                                         unsigned int index)
169 {
170         return (((efx_qword_t *) (channel->eventq.addr)) + index);
171 }
172
173 /* See if an event is present
174  *
175  * We check both the high and low dword of the event for all ones.  We
176  * wrote all ones when we cleared the event, and no valid event can
177  * have all ones in either its high or low dwords.  This approach is
178  * robust against reordering.
179  *
180  * Note that using a single 64-bit comparison is incorrect; even
181  * though the CPU read will be atomic, the DMA write may not be.
182  */
183 static inline int falcon_event_present(efx_qword_t *event)
184 {
185         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
186                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
187 }
188
189 /**************************************************************************
190  *
191  * I2C bus - this is a bit-bashing interface using GPIO pins
192  * Note that it uses the output enables to tristate the outputs
193  * SDA is the data pin and SCL is the clock
194  *
195  **************************************************************************
196  */
197 static void falcon_setsda(void *data, int state)
198 {
199         struct efx_nic *efx = (struct efx_nic *)data;
200         efx_oword_t reg;
201
202         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
203         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
204         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
205 }
206
207 static void falcon_setscl(void *data, int state)
208 {
209         struct efx_nic *efx = (struct efx_nic *)data;
210         efx_oword_t reg;
211
212         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
213         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
214         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
215 }
216
217 static int falcon_getsda(void *data)
218 {
219         struct efx_nic *efx = (struct efx_nic *)data;
220         efx_oword_t reg;
221
222         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
223         return EFX_OWORD_FIELD(reg, GPIO3_IN);
224 }
225
226 static int falcon_getscl(void *data)
227 {
228         struct efx_nic *efx = (struct efx_nic *)data;
229         efx_oword_t reg;
230
231         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
232         return EFX_OWORD_FIELD(reg, GPIO0_IN);
233 }
234
235 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
236         .setsda         = falcon_setsda,
237         .setscl         = falcon_setscl,
238         .getsda         = falcon_getsda,
239         .getscl         = falcon_getscl,
240         .udelay         = 5,
241         /* Wait up to 50 ms for slave to let us pull SCL high */
242         .timeout        = DIV_ROUND_UP(HZ, 20),
243 };
244
245 /**************************************************************************
246  *
247  * Falcon special buffer handling
248  * Special buffers are used for event queues and the TX and RX
249  * descriptor rings.
250  *
251  *************************************************************************/
252
253 /*
254  * Initialise a Falcon special buffer
255  *
256  * This will define a buffer (previously allocated via
257  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
258  * it to be used for event queues, descriptor rings etc.
259  */
260 static void
261 falcon_init_special_buffer(struct efx_nic *efx,
262                            struct efx_special_buffer *buffer)
263 {
264         efx_qword_t buf_desc;
265         int index;
266         dma_addr_t dma_addr;
267         int i;
268
269         EFX_BUG_ON_PARANOID(!buffer->addr);
270
271         /* Write buffer descriptors to NIC */
272         for (i = 0; i < buffer->entries; i++) {
273                 index = buffer->index + i;
274                 dma_addr = buffer->dma_addr + (i * 4096);
275                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
276                         index, (unsigned long long)dma_addr);
277                 EFX_POPULATE_QWORD_4(buf_desc,
278                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
279                                      BUF_ADR_REGION, 0,
280                                      BUF_ADR_FBUF, (dma_addr >> 12),
281                                      BUF_OWNER_ID_FBUF, 0);
282                 falcon_write_sram(efx, &buf_desc, index);
283         }
284 }
285
286 /* Unmaps a buffer from Falcon and clears the buffer table entries */
287 static void
288 falcon_fini_special_buffer(struct efx_nic *efx,
289                            struct efx_special_buffer *buffer)
290 {
291         efx_oword_t buf_tbl_upd;
292         unsigned int start = buffer->index;
293         unsigned int end = (buffer->index + buffer->entries - 1);
294
295         if (!buffer->entries)
296                 return;
297
298         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
299                 buffer->index, buffer->index + buffer->entries - 1);
300
301         EFX_POPULATE_OWORD_4(buf_tbl_upd,
302                              BUF_UPD_CMD, 0,
303                              BUF_CLR_CMD, 1,
304                              BUF_CLR_END_ID, end,
305                              BUF_CLR_START_ID, start);
306         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
307 }
308
309 /*
310  * Allocate a new Falcon special buffer
311  *
312  * This allocates memory for a new buffer, clears it and allocates a
313  * new buffer ID range.  It does not write into Falcon's buffer table.
314  *
315  * This call will allocate 4KB buffers, since Falcon can't use 8KB
316  * buffers for event queues and descriptor rings.
317  */
318 static int falcon_alloc_special_buffer(struct efx_nic *efx,
319                                        struct efx_special_buffer *buffer,
320                                        unsigned int len)
321 {
322         struct falcon_nic_data *nic_data = efx->nic_data;
323
324         len = ALIGN(len, FALCON_BUF_SIZE);
325
326         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
327                                             &buffer->dma_addr);
328         if (!buffer->addr)
329                 return -ENOMEM;
330         buffer->len = len;
331         buffer->entries = len / FALCON_BUF_SIZE;
332         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
333
334         /* All zeros is a potentially valid event so memset to 0xff */
335         memset(buffer->addr, 0xff, len);
336
337         /* Select new buffer ID */
338         buffer->index = nic_data->next_buffer_table;
339         nic_data->next_buffer_table += buffer->entries;
340
341         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
342                 "(virt %p phys %llx)\n", buffer->index,
343                 buffer->index + buffer->entries - 1,
344                 (u64)buffer->dma_addr, len,
345                 buffer->addr, (u64)virt_to_phys(buffer->addr));
346
347         return 0;
348 }
349
350 static void falcon_free_special_buffer(struct efx_nic *efx,
351                                        struct efx_special_buffer *buffer)
352 {
353         if (!buffer->addr)
354                 return;
355
356         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
357                 "(virt %p phys %llx)\n", buffer->index,
358                 buffer->index + buffer->entries - 1,
359                 (u64)buffer->dma_addr, buffer->len,
360                 buffer->addr, (u64)virt_to_phys(buffer->addr));
361
362         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
363                             buffer->dma_addr);
364         buffer->addr = NULL;
365         buffer->entries = 0;
366 }
367
368 /**************************************************************************
369  *
370  * Falcon generic buffer handling
371  * These buffers are used for interrupt status and MAC stats
372  *
373  **************************************************************************/
374
375 static int falcon_alloc_buffer(struct efx_nic *efx,
376                                struct efx_buffer *buffer, unsigned int len)
377 {
378         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
379                                             &buffer->dma_addr);
380         if (!buffer->addr)
381                 return -ENOMEM;
382         buffer->len = len;
383         memset(buffer->addr, 0, len);
384         return 0;
385 }
386
387 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
388 {
389         if (buffer->addr) {
390                 pci_free_consistent(efx->pci_dev, buffer->len,
391                                     buffer->addr, buffer->dma_addr);
392                 buffer->addr = NULL;
393         }
394 }
395
396 /**************************************************************************
397  *
398  * Falcon TX path
399  *
400  **************************************************************************/
401
402 /* Returns a pointer to the specified transmit descriptor in the TX
403  * descriptor queue belonging to the specified channel.
404  */
405 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
406                                                unsigned int index)
407 {
408         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
409 }
410
411 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
412 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
413 {
414         unsigned write_ptr;
415         efx_dword_t reg;
416
417         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
418         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
419         falcon_writel_page(tx_queue->efx, &reg,
420                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
421 }
422
423
424 /* For each entry inserted into the software descriptor ring, create a
425  * descriptor in the hardware TX descriptor ring (in host memory), and
426  * write a doorbell.
427  */
428 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
429 {
430
431         struct efx_tx_buffer *buffer;
432         efx_qword_t *txd;
433         unsigned write_ptr;
434
435         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
436
437         do {
438                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
439                 buffer = &tx_queue->buffer[write_ptr];
440                 txd = falcon_tx_desc(tx_queue, write_ptr);
441                 ++tx_queue->write_count;
442
443                 /* Create TX descriptor ring entry */
444                 EFX_POPULATE_QWORD_5(*txd,
445                                      TX_KER_PORT, 0,
446                                      TX_KER_CONT, buffer->continuation,
447                                      TX_KER_BYTE_CNT, buffer->len,
448                                      TX_KER_BUF_REGION, 0,
449                                      TX_KER_BUF_ADR, buffer->dma_addr);
450         } while (tx_queue->write_count != tx_queue->insert_count);
451
452         wmb(); /* Ensure descriptors are written before they are fetched */
453         falcon_notify_tx_desc(tx_queue);
454 }
455
456 /* Allocate hardware resources for a TX queue */
457 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
458 {
459         struct efx_nic *efx = tx_queue->efx;
460         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
461                                            FALCON_TXD_RING_SIZE *
462                                            sizeof(efx_qword_t));
463 }
464
465 void falcon_init_tx(struct efx_tx_queue *tx_queue)
466 {
467         efx_oword_t tx_desc_ptr;
468         struct efx_nic *efx = tx_queue->efx;
469
470         tx_queue->flushed = false;
471
472         /* Pin TX descriptor ring */
473         falcon_init_special_buffer(efx, &tx_queue->txd);
474
475         /* Push TX descriptor ring to card */
476         EFX_POPULATE_OWORD_10(tx_desc_ptr,
477                               TX_DESCQ_EN, 1,
478                               TX_ISCSI_DDIG_EN, 0,
479                               TX_ISCSI_HDIG_EN, 0,
480                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
481                               TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
482                               TX_DESCQ_OWNER_ID, 0,
483                               TX_DESCQ_LABEL, tx_queue->queue,
484                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
485                               TX_DESCQ_TYPE, 0,
486                               TX_NON_IP_DROP_DIS_B0, 1);
487
488         if (falcon_rev(efx) >= FALCON_REV_B0) {
489                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
490                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
491                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
492         }
493
494         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
495                            tx_queue->queue);
496
497         if (falcon_rev(efx) < FALCON_REV_B0) {
498                 efx_oword_t reg;
499
500                 /* Only 128 bits in this register */
501                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
502
503                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
504                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
505                         clear_bit_le(tx_queue->queue, (void *)&reg);
506                 else
507                         set_bit_le(tx_queue->queue, (void *)&reg);
508                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
509         }
510 }
511
512 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
513 {
514         struct efx_nic *efx = tx_queue->efx;
515         efx_oword_t tx_flush_descq;
516
517         /* Post a flush command */
518         EFX_POPULATE_OWORD_2(tx_flush_descq,
519                              TX_FLUSH_DESCQ_CMD, 1,
520                              TX_FLUSH_DESCQ, tx_queue->queue);
521         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
522 }
523
524 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
525 {
526         struct efx_nic *efx = tx_queue->efx;
527         efx_oword_t tx_desc_ptr;
528
529         /* The queue should have been flushed */
530         WARN_ON(!tx_queue->flushed);
531
532         /* Remove TX descriptor ring from card */
533         EFX_ZERO_OWORD(tx_desc_ptr);
534         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
535                            tx_queue->queue);
536
537         /* Unpin TX descriptor ring */
538         falcon_fini_special_buffer(efx, &tx_queue->txd);
539 }
540
541 /* Free buffers backing TX queue */
542 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
543 {
544         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
545 }
546
547 /**************************************************************************
548  *
549  * Falcon RX path
550  *
551  **************************************************************************/
552
553 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
554 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
555                                                unsigned int index)
556 {
557         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
558 }
559
560 /* This creates an entry in the RX descriptor queue */
561 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
562                                         unsigned index)
563 {
564         struct efx_rx_buffer *rx_buf;
565         efx_qword_t *rxd;
566
567         rxd = falcon_rx_desc(rx_queue, index);
568         rx_buf = efx_rx_buffer(rx_queue, index);
569         EFX_POPULATE_QWORD_3(*rxd,
570                              RX_KER_BUF_SIZE,
571                              rx_buf->len -
572                              rx_queue->efx->type->rx_buffer_padding,
573                              RX_KER_BUF_REGION, 0,
574                              RX_KER_BUF_ADR, rx_buf->dma_addr);
575 }
576
577 /* This writes to the RX_DESC_WPTR register for the specified receive
578  * descriptor ring.
579  */
580 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
581 {
582         efx_dword_t reg;
583         unsigned write_ptr;
584
585         while (rx_queue->notified_count != rx_queue->added_count) {
586                 falcon_build_rx_desc(rx_queue,
587                                      rx_queue->notified_count &
588                                      FALCON_RXD_RING_MASK);
589                 ++rx_queue->notified_count;
590         }
591
592         wmb();
593         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
594         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
595         falcon_writel_page(rx_queue->efx, &reg,
596                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
597 }
598
599 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
600 {
601         struct efx_nic *efx = rx_queue->efx;
602         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
603                                            FALCON_RXD_RING_SIZE *
604                                            sizeof(efx_qword_t));
605 }
606
607 void falcon_init_rx(struct efx_rx_queue *rx_queue)
608 {
609         efx_oword_t rx_desc_ptr;
610         struct efx_nic *efx = rx_queue->efx;
611         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
612         bool iscsi_digest_en = is_b0;
613
614         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
615                 rx_queue->queue, rx_queue->rxd.index,
616                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
617
618         rx_queue->flushed = false;
619
620         /* Pin RX descriptor ring */
621         falcon_init_special_buffer(efx, &rx_queue->rxd);
622
623         /* Push RX descriptor ring to card */
624         EFX_POPULATE_OWORD_10(rx_desc_ptr,
625                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
626                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
627                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
628                               RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
629                               RX_DESCQ_OWNER_ID, 0,
630                               RX_DESCQ_LABEL, rx_queue->queue,
631                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
632                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
633                               /* For >=B0 this is scatter so disable */
634                               RX_DESCQ_JUMBO, !is_b0,
635                               RX_DESCQ_EN, 1);
636         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
637                            rx_queue->queue);
638 }
639
640 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
641 {
642         struct efx_nic *efx = rx_queue->efx;
643         efx_oword_t rx_flush_descq;
644
645         /* Post a flush command */
646         EFX_POPULATE_OWORD_2(rx_flush_descq,
647                              RX_FLUSH_DESCQ_CMD, 1,
648                              RX_FLUSH_DESCQ, rx_queue->queue);
649         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
650 }
651
652 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
653 {
654         efx_oword_t rx_desc_ptr;
655         struct efx_nic *efx = rx_queue->efx;
656
657         /* The queue should already have been flushed */
658         WARN_ON(!rx_queue->flushed);
659
660         /* Remove RX descriptor ring from card */
661         EFX_ZERO_OWORD(rx_desc_ptr);
662         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
663                            rx_queue->queue);
664
665         /* Unpin RX descriptor ring */
666         falcon_fini_special_buffer(efx, &rx_queue->rxd);
667 }
668
669 /* Free buffers backing RX queue */
670 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
671 {
672         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
673 }
674
675 /**************************************************************************
676  *
677  * Falcon event queue processing
678  * Event queues are processed by per-channel tasklets.
679  *
680  **************************************************************************/
681
682 /* Update a channel's event queue's read pointer (RPTR) register
683  *
684  * This writes the EVQ_RPTR_REG register for the specified channel's
685  * event queue.
686  *
687  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
688  * whereas channel->eventq_read_ptr contains the index of the "next to
689  * read" event.
690  */
691 void falcon_eventq_read_ack(struct efx_channel *channel)
692 {
693         efx_dword_t reg;
694         struct efx_nic *efx = channel->efx;
695
696         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
697         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
698                             channel->channel);
699 }
700
701 /* Use HW to insert a SW defined event */
702 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
703 {
704         efx_oword_t drv_ev_reg;
705
706         EFX_POPULATE_OWORD_2(drv_ev_reg,
707                              DRV_EV_QID, channel->channel,
708                              DRV_EV_DATA,
709                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
710         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
711 }
712
713 /* Handle a transmit completion event
714  *
715  * Falcon batches TX completion events; the message we receive is of
716  * the form "complete all TX events up to this index".
717  */
718 static void falcon_handle_tx_event(struct efx_channel *channel,
719                                    efx_qword_t *event)
720 {
721         unsigned int tx_ev_desc_ptr;
722         unsigned int tx_ev_q_label;
723         struct efx_tx_queue *tx_queue;
724         struct efx_nic *efx = channel->efx;
725
726         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
727                 /* Transmit completion */
728                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
729                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
730                 tx_queue = &efx->tx_queue[tx_ev_q_label];
731                 channel->irq_mod_score +=
732                         (tx_ev_desc_ptr - tx_queue->read_count) &
733                         efx->type->txd_ring_mask;
734                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
735         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
736                 /* Rewrite the FIFO write pointer */
737                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
738                 tx_queue = &efx->tx_queue[tx_ev_q_label];
739
740                 if (efx_dev_registered(efx))
741                         netif_tx_lock(efx->net_dev);
742                 falcon_notify_tx_desc(tx_queue);
743                 if (efx_dev_registered(efx))
744                         netif_tx_unlock(efx->net_dev);
745         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
746                    EFX_WORKAROUND_10727(efx)) {
747                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
748         } else {
749                 EFX_ERR(efx, "channel %d unexpected TX event "
750                         EFX_QWORD_FMT"\n", channel->channel,
751                         EFX_QWORD_VAL(*event));
752         }
753 }
754
755 /* Detect errors included in the rx_evt_pkt_ok bit. */
756 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
757                                     const efx_qword_t *event,
758                                     bool *rx_ev_pkt_ok,
759                                     bool *discard)
760 {
761         struct efx_nic *efx = rx_queue->efx;
762         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
763         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
764         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
765         bool rx_ev_other_err, rx_ev_pause_frm;
766         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
767         unsigned rx_ev_pkt_type;
768
769         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
770         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
771         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
772         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
773         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
774                                                  RX_EV_BUF_OWNER_ID_ERR);
775         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
776         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
777                                                   RX_EV_IP_HDR_CHKSUM_ERR);
778         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
779                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
780         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
781         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
782         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
783                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
784         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
785
786         /* Every error apart from tobe_disc and pause_frm */
787         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
788                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
789                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
790
791         /* Count errors that are not in MAC stats.  Ignore expected
792          * checksum errors during self-test. */
793         if (rx_ev_frm_trunc)
794                 ++rx_queue->channel->n_rx_frm_trunc;
795         else if (rx_ev_tobe_disc)
796                 ++rx_queue->channel->n_rx_tobe_disc;
797         else if (!efx->loopback_selftest) {
798                 if (rx_ev_ip_hdr_chksum_err)
799                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
800                 else if (rx_ev_tcp_udp_chksum_err)
801                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
802         }
803         if (rx_ev_ip_frag_err)
804                 ++rx_queue->channel->n_rx_ip_frag_err;
805
806         /* The frame must be discarded if any of these are true. */
807         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
808                     rx_ev_tobe_disc | rx_ev_pause_frm);
809
810         /* TOBE_DISC is expected on unicast mismatches; don't print out an
811          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
812          * to a FIFO overflow.
813          */
814 #ifdef EFX_ENABLE_DEBUG
815         if (rx_ev_other_err) {
816                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
817                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
818                             rx_queue->queue, EFX_QWORD_VAL(*event),
819                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
820                             rx_ev_ip_hdr_chksum_err ?
821                             " [IP_HDR_CHKSUM_ERR]" : "",
822                             rx_ev_tcp_udp_chksum_err ?
823                             " [TCP_UDP_CHKSUM_ERR]" : "",
824                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
825                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
826                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
827                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
828                             rx_ev_pause_frm ? " [PAUSE]" : "");
829         }
830 #endif
831 }
832
833 /* Handle receive events that are not in-order. */
834 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
835                                        unsigned index)
836 {
837         struct efx_nic *efx = rx_queue->efx;
838         unsigned expected, dropped;
839
840         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
841         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
842                    FALCON_RXD_RING_MASK);
843         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
844                 dropped, index, expected);
845
846         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
847                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
848 }
849
850 /* Handle a packet received event
851  *
852  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
853  * wrong destination address
854  * Also "is multicast" and "matches multicast filter" flags can be used to
855  * discard non-matching multicast packets.
856  */
857 static void falcon_handle_rx_event(struct efx_channel *channel,
858                                    const efx_qword_t *event)
859 {
860         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
861         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
862         unsigned expected_ptr;
863         bool rx_ev_pkt_ok, discard = false, checksummed;
864         struct efx_rx_queue *rx_queue;
865         struct efx_nic *efx = channel->efx;
866
867         /* Basic packet information */
868         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
869         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
870         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
871         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
872         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
873         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
874
875         rx_queue = &efx->rx_queue[channel->channel];
876
877         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
878         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
879         if (unlikely(rx_ev_desc_ptr != expected_ptr))
880                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
881
882         if (likely(rx_ev_pkt_ok)) {
883                 /* If packet is marked as OK and packet type is TCP/IPv4 or
884                  * UDP/IPv4, then we can rely on the hardware checksum.
885                  */
886                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
887         } else {
888                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
889                                         &discard);
890                 checksummed = false;
891         }
892
893         /* Detect multicast packets that didn't match the filter */
894         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
895         if (rx_ev_mcast_pkt) {
896                 unsigned int rx_ev_mcast_hash_match =
897                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
898
899                 if (unlikely(!rx_ev_mcast_hash_match))
900                         discard = true;
901         }
902
903         channel->irq_mod_score += 2;
904
905         /* Handle received packet */
906         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
907                       checksummed, discard);
908 }
909
910 /* Global events are basically PHY events */
911 static void falcon_handle_global_event(struct efx_channel *channel,
912                                        efx_qword_t *event)
913 {
914         struct efx_nic *efx = channel->efx;
915         bool handled = false;
916
917         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
918             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
919             EFX_QWORD_FIELD(*event, XG_PHY_INTR) ||
920             EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
921                 efx->phy_op->clear_interrupt(efx);
922                 queue_work(efx->workqueue, &efx->phy_work);
923                 handled = true;
924         }
925
926         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
927             EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) {
928                 queue_work(efx->workqueue, &efx->mac_work);
929                 handled = true;
930         }
931
932         if (falcon_rev(efx) <= FALCON_REV_A1 ?
933             EFX_QWORD_FIELD(*event, RX_RECOVERY_A1) :
934             EFX_QWORD_FIELD(*event, RX_RECOVERY_B0)) {
935                 EFX_ERR(efx, "channel %d seen global RX_RESET "
936                         "event. Resetting.\n", channel->channel);
937
938                 atomic_inc(&efx->rx_reset);
939                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
940                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
941                 handled = true;
942         }
943
944         if (!handled)
945                 EFX_ERR(efx, "channel %d unknown global event "
946                         EFX_QWORD_FMT "\n", channel->channel,
947                         EFX_QWORD_VAL(*event));
948 }
949
950 static void falcon_handle_driver_event(struct efx_channel *channel,
951                                        efx_qword_t *event)
952 {
953         struct efx_nic *efx = channel->efx;
954         unsigned int ev_sub_code;
955         unsigned int ev_sub_data;
956
957         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
958         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
959
960         switch (ev_sub_code) {
961         case TX_DESCQ_FLS_DONE_EV_DECODE:
962                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
963                           channel->channel, ev_sub_data);
964                 break;
965         case RX_DESCQ_FLS_DONE_EV_DECODE:
966                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
967                           channel->channel, ev_sub_data);
968                 break;
969         case EVQ_INIT_DONE_EV_DECODE:
970                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
971                         channel->channel, ev_sub_data);
972                 break;
973         case SRM_UPD_DONE_EV_DECODE:
974                 EFX_TRACE(efx, "channel %d SRAM update done\n",
975                           channel->channel);
976                 break;
977         case WAKE_UP_EV_DECODE:
978                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
979                           channel->channel, ev_sub_data);
980                 break;
981         case TIMER_EV_DECODE:
982                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
983                           channel->channel, ev_sub_data);
984                 break;
985         case RX_RECOVERY_EV_DECODE:
986                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
987                         "Resetting.\n", channel->channel);
988                 atomic_inc(&efx->rx_reset);
989                 efx_schedule_reset(efx,
990                                    EFX_WORKAROUND_6555(efx) ?
991                                    RESET_TYPE_RX_RECOVERY :
992                                    RESET_TYPE_DISABLE);
993                 break;
994         case RX_DSC_ERROR_EV_DECODE:
995                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
996                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
997                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
998                 break;
999         case TX_DSC_ERROR_EV_DECODE:
1000                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1001                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1002                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1003                 break;
1004         default:
1005                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1006                           "data %04x\n", channel->channel, ev_sub_code,
1007                           ev_sub_data);
1008                 break;
1009         }
1010 }
1011
1012 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1013 {
1014         unsigned int read_ptr;
1015         efx_qword_t event, *p_event;
1016         int ev_code;
1017         int rx_packets = 0;
1018
1019         read_ptr = channel->eventq_read_ptr;
1020
1021         do {
1022                 p_event = falcon_event(channel, read_ptr);
1023                 event = *p_event;
1024
1025                 if (!falcon_event_present(&event))
1026                         /* End of events */
1027                         break;
1028
1029                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1030                           channel->channel, EFX_QWORD_VAL(event));
1031
1032                 /* Clear this event by marking it all ones */
1033                 EFX_SET_QWORD(*p_event);
1034
1035                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1036
1037                 switch (ev_code) {
1038                 case RX_IP_EV_DECODE:
1039                         falcon_handle_rx_event(channel, &event);
1040                         ++rx_packets;
1041                         break;
1042                 case TX_IP_EV_DECODE:
1043                         falcon_handle_tx_event(channel, &event);
1044                         break;
1045                 case DRV_GEN_EV_DECODE:
1046                         channel->eventq_magic
1047                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1048                         EFX_LOG(channel->efx, "channel %d received generated "
1049                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1050                                 EFX_QWORD_VAL(event));
1051                         break;
1052                 case GLOBAL_EV_DECODE:
1053                         falcon_handle_global_event(channel, &event);
1054                         break;
1055                 case DRIVER_EV_DECODE:
1056                         falcon_handle_driver_event(channel, &event);
1057                         break;
1058                 default:
1059                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1060                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1061                                 ev_code, EFX_QWORD_VAL(event));
1062                 }
1063
1064                 /* Increment read pointer */
1065                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1066
1067         } while (rx_packets < rx_quota);
1068
1069         channel->eventq_read_ptr = read_ptr;
1070         return rx_packets;
1071 }
1072
1073 void falcon_set_int_moderation(struct efx_channel *channel)
1074 {
1075         efx_dword_t timer_cmd;
1076         struct efx_nic *efx = channel->efx;
1077
1078         /* Set timer register */
1079         if (channel->irq_moderation) {
1080                 /* Round to resolution supported by hardware.  The value we
1081                  * program is based at 0.  So actual interrupt moderation
1082                  * achieved is ((x + 1) * res).
1083                  */
1084                 channel->irq_moderation -= (channel->irq_moderation %
1085                                             FALCON_IRQ_MOD_RESOLUTION);
1086                 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1087                         channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1088                 EFX_POPULATE_DWORD_2(timer_cmd,
1089                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1090                                      TIMER_VAL,
1091                                      channel->irq_moderation /
1092                                      FALCON_IRQ_MOD_RESOLUTION - 1);
1093         } else {
1094                 EFX_POPULATE_DWORD_2(timer_cmd,
1095                                      TIMER_MODE, TIMER_MODE_DIS,
1096                                      TIMER_VAL, 0);
1097         }
1098         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1099                                   channel->channel);
1100
1101 }
1102
1103 /* Allocate buffer table entries for event queue */
1104 int falcon_probe_eventq(struct efx_channel *channel)
1105 {
1106         struct efx_nic *efx = channel->efx;
1107         unsigned int evq_size;
1108
1109         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1110         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1111 }
1112
1113 void falcon_init_eventq(struct efx_channel *channel)
1114 {
1115         efx_oword_t evq_ptr;
1116         struct efx_nic *efx = channel->efx;
1117
1118         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1119                 channel->channel, channel->eventq.index,
1120                 channel->eventq.index + channel->eventq.entries - 1);
1121
1122         /* Pin event queue buffer */
1123         falcon_init_special_buffer(efx, &channel->eventq);
1124
1125         /* Fill event queue with all ones (i.e. empty events) */
1126         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1127
1128         /* Push event queue to card */
1129         EFX_POPULATE_OWORD_3(evq_ptr,
1130                              EVQ_EN, 1,
1131                              EVQ_SIZE, FALCON_EVQ_ORDER,
1132                              EVQ_BUF_BASE_ID, channel->eventq.index);
1133         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1134                            channel->channel);
1135
1136         falcon_set_int_moderation(channel);
1137 }
1138
1139 void falcon_fini_eventq(struct efx_channel *channel)
1140 {
1141         efx_oword_t eventq_ptr;
1142         struct efx_nic *efx = channel->efx;
1143
1144         /* Remove event queue from card */
1145         EFX_ZERO_OWORD(eventq_ptr);
1146         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1147                            channel->channel);
1148
1149         /* Unpin event queue */
1150         falcon_fini_special_buffer(efx, &channel->eventq);
1151 }
1152
1153 /* Free buffers backing event queue */
1154 void falcon_remove_eventq(struct efx_channel *channel)
1155 {
1156         falcon_free_special_buffer(channel->efx, &channel->eventq);
1157 }
1158
1159
1160 /* Generates a test event on the event queue.  A subsequent call to
1161  * process_eventq() should pick up the event and place the value of
1162  * "magic" into channel->eventq_magic;
1163  */
1164 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1165 {
1166         efx_qword_t test_event;
1167
1168         EFX_POPULATE_QWORD_2(test_event,
1169                              EV_CODE, DRV_GEN_EV_DECODE,
1170                              EVQ_MAGIC, magic);
1171         falcon_generate_event(channel, &test_event);
1172 }
1173
1174 void falcon_sim_phy_event(struct efx_nic *efx)
1175 {
1176         efx_qword_t phy_event;
1177
1178         EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1179         if (EFX_IS10G(efx))
1180                 EFX_SET_QWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1181         else
1182                 EFX_SET_QWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1183
1184         falcon_generate_event(&efx->channel[0], &phy_event);
1185 }
1186
1187 /**************************************************************************
1188  *
1189  * Flush handling
1190  *
1191  **************************************************************************/
1192
1193
1194 static void falcon_poll_flush_events(struct efx_nic *efx)
1195 {
1196         struct efx_channel *channel = &efx->channel[0];
1197         struct efx_tx_queue *tx_queue;
1198         struct efx_rx_queue *rx_queue;
1199         unsigned int read_ptr = channel->eventq_read_ptr;
1200         unsigned int end_ptr = (read_ptr - 1) & FALCON_EVQ_MASK;
1201
1202         do {
1203                 efx_qword_t *event = falcon_event(channel, read_ptr);
1204                 int ev_code, ev_sub_code, ev_queue;
1205                 bool ev_failed;
1206
1207                 if (!falcon_event_present(event))
1208                         break;
1209
1210                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1211                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1212                 if (ev_code == DRIVER_EV_DECODE &&
1213                     ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) {
1214                         ev_queue = EFX_QWORD_FIELD(*event,
1215                                                    DRIVER_EV_TX_DESCQ_ID);
1216                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1217                                 tx_queue = efx->tx_queue + ev_queue;
1218                                 tx_queue->flushed = true;
1219                         }
1220                 } else if (ev_code == DRIVER_EV_DECODE &&
1221                            ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) {
1222                         ev_queue = EFX_QWORD_FIELD(*event,
1223                                                    DRIVER_EV_RX_DESCQ_ID);
1224                         ev_failed = EFX_QWORD_FIELD(*event,
1225                                                     DRIVER_EV_RX_FLUSH_FAIL);
1226                         if (ev_queue < efx->n_rx_queues) {
1227                                 rx_queue = efx->rx_queue + ev_queue;
1228
1229                                 /* retry the rx flush */
1230                                 if (ev_failed)
1231                                         falcon_flush_rx_queue(rx_queue);
1232                                 else
1233                                         rx_queue->flushed = true;
1234                         }
1235                 }
1236
1237                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1238         } while (read_ptr != end_ptr);
1239 }
1240
1241 /* Handle tx and rx flushes at the same time, since they run in
1242  * parallel in the hardware and there's no reason for us to
1243  * serialise them */
1244 int falcon_flush_queues(struct efx_nic *efx)
1245 {
1246         struct efx_rx_queue *rx_queue;
1247         struct efx_tx_queue *tx_queue;
1248         int i;
1249         bool outstanding;
1250
1251         /* Issue flush requests */
1252         efx_for_each_tx_queue(tx_queue, efx) {
1253                 tx_queue->flushed = false;
1254                 falcon_flush_tx_queue(tx_queue);
1255         }
1256         efx_for_each_rx_queue(rx_queue, efx) {
1257                 rx_queue->flushed = false;
1258                 falcon_flush_rx_queue(rx_queue);
1259         }
1260
1261         /* Poll the evq looking for flush completions. Since we're not pushing
1262          * any more rx or tx descriptors at this point, we're in no danger of
1263          * overflowing the evq whilst we wait */
1264         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1265                 msleep(FALCON_FLUSH_INTERVAL);
1266                 falcon_poll_flush_events(efx);
1267
1268                 /* Check if every queue has been succesfully flushed */
1269                 outstanding = false;
1270                 efx_for_each_tx_queue(tx_queue, efx)
1271                         outstanding |= !tx_queue->flushed;
1272                 efx_for_each_rx_queue(rx_queue, efx)
1273                         outstanding |= !rx_queue->flushed;
1274                 if (!outstanding)
1275                         return 0;
1276         }
1277
1278         /* Mark the queues as all flushed. We're going to return failure
1279          * leading to a reset, or fake up success anyway. "flushed" now
1280          * indicates that we tried to flush. */
1281         efx_for_each_tx_queue(tx_queue, efx) {
1282                 if (!tx_queue->flushed)
1283                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1284                                 tx_queue->queue);
1285                 tx_queue->flushed = true;
1286         }
1287         efx_for_each_rx_queue(rx_queue, efx) {
1288                 if (!rx_queue->flushed)
1289                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1290                                 rx_queue->queue);
1291                 rx_queue->flushed = true;
1292         }
1293
1294         if (EFX_WORKAROUND_7803(efx))
1295                 return 0;
1296
1297         return -ETIMEDOUT;
1298 }
1299
1300 /**************************************************************************
1301  *
1302  * Falcon hardware interrupts
1303  * The hardware interrupt handler does very little work; all the event
1304  * queue processing is carried out by per-channel tasklets.
1305  *
1306  **************************************************************************/
1307
1308 /* Enable/disable/generate Falcon interrupts */
1309 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1310                                      int force)
1311 {
1312         efx_oword_t int_en_reg_ker;
1313
1314         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1315                              KER_INT_KER, force,
1316                              DRV_INT_EN_KER, enabled);
1317         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1318 }
1319
1320 void falcon_enable_interrupts(struct efx_nic *efx)
1321 {
1322         efx_oword_t int_adr_reg_ker;
1323         struct efx_channel *channel;
1324
1325         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1326         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1327
1328         /* Program address */
1329         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1330                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1331                              INT_ADR_KER, efx->irq_status.dma_addr);
1332         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1333
1334         /* Enable interrupts */
1335         falcon_interrupts(efx, 1, 0);
1336
1337         /* Force processing of all the channels to get the EVQ RPTRs up to
1338            date */
1339         efx_for_each_channel(channel, efx)
1340                 efx_schedule_channel(channel);
1341 }
1342
1343 void falcon_disable_interrupts(struct efx_nic *efx)
1344 {
1345         /* Disable interrupts */
1346         falcon_interrupts(efx, 0, 0);
1347 }
1348
1349 /* Generate a Falcon test interrupt
1350  * Interrupt must already have been enabled, otherwise nasty things
1351  * may happen.
1352  */
1353 void falcon_generate_interrupt(struct efx_nic *efx)
1354 {
1355         falcon_interrupts(efx, 1, 1);
1356 }
1357
1358 /* Acknowledge a legacy interrupt from Falcon
1359  *
1360  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1361  *
1362  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1363  * BIU. Interrupt acknowledge is read sensitive so must write instead
1364  * (then read to ensure the BIU collector is flushed)
1365  *
1366  * NB most hardware supports MSI interrupts
1367  */
1368 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1369 {
1370         efx_dword_t reg;
1371
1372         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1373         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1374         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1375 }
1376
1377 /* Process a fatal interrupt
1378  * Disable bus mastering ASAP and schedule a reset
1379  */
1380 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1381 {
1382         struct falcon_nic_data *nic_data = efx->nic_data;
1383         efx_oword_t *int_ker = efx->irq_status.addr;
1384         efx_oword_t fatal_intr;
1385         int error, mem_perr;
1386
1387         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1388         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1389
1390         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1391                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1392                 EFX_OWORD_VAL(fatal_intr),
1393                 error ? "disabling bus mastering" : "no recognised error");
1394         if (error == 0)
1395                 goto out;
1396
1397         /* If this is a memory parity error dump which blocks are offending */
1398         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1399         if (mem_perr) {
1400                 efx_oword_t reg;
1401                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1402                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1403                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1404         }
1405
1406         /* Disable both devices */
1407         pci_clear_master(efx->pci_dev);
1408         if (FALCON_IS_DUAL_FUNC(efx))
1409                 pci_clear_master(nic_data->pci_dev2);
1410         falcon_disable_interrupts(efx);
1411
1412         /* Count errors and reset or disable the NIC accordingly */
1413         if (nic_data->int_error_count == 0 ||
1414             time_after(jiffies, nic_data->int_error_expire)) {
1415                 nic_data->int_error_count = 0;
1416                 nic_data->int_error_expire =
1417                         jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1418         }
1419         if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1420                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1421                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1422         } else {
1423                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1424                         "NIC will be disabled\n");
1425                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1426         }
1427 out:
1428         return IRQ_HANDLED;
1429 }
1430
1431 /* Handle a legacy interrupt from Falcon
1432  * Acknowledges the interrupt and schedule event queue processing.
1433  */
1434 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1435 {
1436         struct efx_nic *efx = dev_id;
1437         efx_oword_t *int_ker = efx->irq_status.addr;
1438         irqreturn_t result = IRQ_NONE;
1439         struct efx_channel *channel;
1440         efx_dword_t reg;
1441         u32 queues;
1442         int syserr;
1443
1444         /* Read the ISR which also ACKs the interrupts */
1445         falcon_readl(efx, &reg, INT_ISR0_B0);
1446         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1447
1448         /* Check to see if we have a serious error condition */
1449         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1450         if (unlikely(syserr))
1451                 return falcon_fatal_interrupt(efx);
1452
1453         /* Schedule processing of any interrupting queues */
1454         efx_for_each_channel(channel, efx) {
1455                 if ((queues & 1) ||
1456                     falcon_event_present(
1457                             falcon_event(channel, channel->eventq_read_ptr))) {
1458                         efx_schedule_channel(channel);
1459                         result = IRQ_HANDLED;
1460                 }
1461                 queues >>= 1;
1462         }
1463
1464         if (result == IRQ_HANDLED) {
1465                 efx->last_irq_cpu = raw_smp_processor_id();
1466                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1467                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1468         }
1469
1470         return result;
1471 }
1472
1473
1474 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1475 {
1476         struct efx_nic *efx = dev_id;
1477         efx_oword_t *int_ker = efx->irq_status.addr;
1478         struct efx_channel *channel;
1479         int syserr;
1480         int queues;
1481
1482         /* Check to see if this is our interrupt.  If it isn't, we
1483          * exit without having touched the hardware.
1484          */
1485         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1486                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1487                           raw_smp_processor_id());
1488                 return IRQ_NONE;
1489         }
1490         efx->last_irq_cpu = raw_smp_processor_id();
1491         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1492                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1493
1494         /* Check to see if we have a serious error condition */
1495         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1496         if (unlikely(syserr))
1497                 return falcon_fatal_interrupt(efx);
1498
1499         /* Determine interrupting queues, clear interrupt status
1500          * register and acknowledge the device interrupt.
1501          */
1502         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1503         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1504         EFX_ZERO_OWORD(*int_ker);
1505         wmb(); /* Ensure the vector is cleared before interrupt ack */
1506         falcon_irq_ack_a1(efx);
1507
1508         /* Schedule processing of any interrupting queues */
1509         channel = &efx->channel[0];
1510         while (queues) {
1511                 if (queues & 0x01)
1512                         efx_schedule_channel(channel);
1513                 channel++;
1514                 queues >>= 1;
1515         }
1516
1517         return IRQ_HANDLED;
1518 }
1519
1520 /* Handle an MSI interrupt from Falcon
1521  *
1522  * Handle an MSI hardware interrupt.  This routine schedules event
1523  * queue processing.  No interrupt acknowledgement cycle is necessary.
1524  * Also, we never need to check that the interrupt is for us, since
1525  * MSI interrupts cannot be shared.
1526  */
1527 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1528 {
1529         struct efx_channel *channel = dev_id;
1530         struct efx_nic *efx = channel->efx;
1531         efx_oword_t *int_ker = efx->irq_status.addr;
1532         int syserr;
1533
1534         efx->last_irq_cpu = raw_smp_processor_id();
1535         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1536                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1537
1538         /* Check to see if we have a serious error condition */
1539         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1540         if (unlikely(syserr))
1541                 return falcon_fatal_interrupt(efx);
1542
1543         /* Schedule processing of the channel */
1544         efx_schedule_channel(channel);
1545
1546         return IRQ_HANDLED;
1547 }
1548
1549
1550 /* Setup RSS indirection table.
1551  * This maps from the hash value of the packet to RXQ
1552  */
1553 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1554 {
1555         int i = 0;
1556         unsigned long offset;
1557         efx_dword_t dword;
1558
1559         if (falcon_rev(efx) < FALCON_REV_B0)
1560                 return;
1561
1562         for (offset = RX_RSS_INDIR_TBL_B0;
1563              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1564              offset += 0x10) {
1565                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1566                                      i % efx->n_rx_queues);
1567                 falcon_writel(efx, &dword, offset);
1568                 i++;
1569         }
1570 }
1571
1572 /* Hook interrupt handler(s)
1573  * Try MSI and then legacy interrupts.
1574  */
1575 int falcon_init_interrupt(struct efx_nic *efx)
1576 {
1577         struct efx_channel *channel;
1578         int rc;
1579
1580         if (!EFX_INT_MODE_USE_MSI(efx)) {
1581                 irq_handler_t handler;
1582                 if (falcon_rev(efx) >= FALCON_REV_B0)
1583                         handler = falcon_legacy_interrupt_b0;
1584                 else
1585                         handler = falcon_legacy_interrupt_a1;
1586
1587                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1588                                  efx->name, efx);
1589                 if (rc) {
1590                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1591                                 efx->pci_dev->irq);
1592                         goto fail1;
1593                 }
1594                 return 0;
1595         }
1596
1597         /* Hook MSI or MSI-X interrupt */
1598         efx_for_each_channel(channel, efx) {
1599                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1600                                  IRQF_PROBE_SHARED, /* Not shared */
1601                                  channel->name, channel);
1602                 if (rc) {
1603                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1604                         goto fail2;
1605                 }
1606         }
1607
1608         return 0;
1609
1610  fail2:
1611         efx_for_each_channel(channel, efx)
1612                 free_irq(channel->irq, channel);
1613  fail1:
1614         return rc;
1615 }
1616
1617 void falcon_fini_interrupt(struct efx_nic *efx)
1618 {
1619         struct efx_channel *channel;
1620         efx_oword_t reg;
1621
1622         /* Disable MSI/MSI-X interrupts */
1623         efx_for_each_channel(channel, efx) {
1624                 if (channel->irq)
1625                         free_irq(channel->irq, channel);
1626         }
1627
1628         /* ACK legacy interrupt */
1629         if (falcon_rev(efx) >= FALCON_REV_B0)
1630                 falcon_read(efx, &reg, INT_ISR0_B0);
1631         else
1632                 falcon_irq_ack_a1(efx);
1633
1634         /* Disable legacy interrupt */
1635         if (efx->legacy_irq)
1636                 free_irq(efx->legacy_irq, efx);
1637 }
1638
1639 /**************************************************************************
1640  *
1641  * EEPROM/flash
1642  *
1643  **************************************************************************
1644  */
1645
1646 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1647
1648 static int falcon_spi_poll(struct efx_nic *efx)
1649 {
1650         efx_oword_t reg;
1651         falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1652         return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1653 }
1654
1655 /* Wait for SPI command completion */
1656 static int falcon_spi_wait(struct efx_nic *efx)
1657 {
1658         /* Most commands will finish quickly, so we start polling at
1659          * very short intervals.  Sometimes the command may have to
1660          * wait for VPD or expansion ROM access outside of our
1661          * control, so we allow up to 100 ms. */
1662         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1663         int i;
1664
1665         for (i = 0; i < 10; i++) {
1666                 if (!falcon_spi_poll(efx))
1667                         return 0;
1668                 udelay(10);
1669         }
1670
1671         for (;;) {
1672                 if (!falcon_spi_poll(efx))
1673                         return 0;
1674                 if (time_after_eq(jiffies, timeout)) {
1675                         EFX_ERR(efx, "timed out waiting for SPI\n");
1676                         return -ETIMEDOUT;
1677                 }
1678                 schedule_timeout_uninterruptible(1);
1679         }
1680 }
1681
1682 int falcon_spi_cmd(const struct efx_spi_device *spi,
1683                    unsigned int command, int address,
1684                    const void *in, void *out, size_t len)
1685 {
1686         struct efx_nic *efx = spi->efx;
1687         bool addressed = (address >= 0);
1688         bool reading = (out != NULL);
1689         efx_oword_t reg;
1690         int rc;
1691
1692         /* Input validation */
1693         if (len > FALCON_SPI_MAX_LEN)
1694                 return -EINVAL;
1695         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1696
1697         /* Check that previous command is not still running */
1698         rc = falcon_spi_poll(efx);
1699         if (rc)
1700                 return rc;
1701
1702         /* Program address register, if we have an address */
1703         if (addressed) {
1704                 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1705                 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1706         }
1707
1708         /* Program data register, if we have data */
1709         if (in != NULL) {
1710                 memcpy(&reg, in, len);
1711                 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1712         }
1713
1714         /* Issue read/write command */
1715         EFX_POPULATE_OWORD_7(reg,
1716                              EE_SPI_HCMD_CMD_EN, 1,
1717                              EE_SPI_HCMD_SF_SEL, spi->device_id,
1718                              EE_SPI_HCMD_DABCNT, len,
1719                              EE_SPI_HCMD_READ, reading,
1720                              EE_SPI_HCMD_DUBCNT, 0,
1721                              EE_SPI_HCMD_ADBCNT,
1722                              (addressed ? spi->addr_len : 0),
1723                              EE_SPI_HCMD_ENC, command);
1724         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1725
1726         /* Wait for read/write to complete */
1727         rc = falcon_spi_wait(efx);
1728         if (rc)
1729                 return rc;
1730
1731         /* Read data */
1732         if (out != NULL) {
1733                 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1734                 memcpy(out, &reg, len);
1735         }
1736
1737         return 0;
1738 }
1739
1740 static size_t
1741 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1742 {
1743         return min(FALCON_SPI_MAX_LEN,
1744                    (spi->block_size - (start & (spi->block_size - 1))));
1745 }
1746
1747 static inline u8
1748 efx_spi_munge_command(const struct efx_spi_device *spi,
1749                       const u8 command, const unsigned int address)
1750 {
1751         return command | (((address >> 8) & spi->munge_address) << 3);
1752 }
1753
1754 /* Wait up to 10 ms for buffered write completion */
1755 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1756 {
1757         struct efx_nic *efx = spi->efx;
1758         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1759         u8 status;
1760         int rc;
1761
1762         for (;;) {
1763                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1764                                     &status, sizeof(status));
1765                 if (rc)
1766                         return rc;
1767                 if (!(status & SPI_STATUS_NRDY))
1768                         return 0;
1769                 if (time_after_eq(jiffies, timeout)) {
1770                         EFX_ERR(efx, "SPI write timeout on device %d"
1771                                 " last status=0x%02x\n",
1772                                 spi->device_id, status);
1773                         return -ETIMEDOUT;
1774                 }
1775                 schedule_timeout_uninterruptible(1);
1776         }
1777 }
1778
1779 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1780                     size_t len, size_t *retlen, u8 *buffer)
1781 {
1782         size_t block_len, pos = 0;
1783         unsigned int command;
1784         int rc = 0;
1785
1786         while (pos < len) {
1787                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1788
1789                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1790                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1791                                     buffer + pos, block_len);
1792                 if (rc)
1793                         break;
1794                 pos += block_len;
1795
1796                 /* Avoid locking up the system */
1797                 cond_resched();
1798                 if (signal_pending(current)) {
1799                         rc = -EINTR;
1800                         break;
1801                 }
1802         }
1803
1804         if (retlen)
1805                 *retlen = pos;
1806         return rc;
1807 }
1808
1809 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1810                      size_t len, size_t *retlen, const u8 *buffer)
1811 {
1812         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1813         size_t block_len, pos = 0;
1814         unsigned int command;
1815         int rc = 0;
1816
1817         while (pos < len) {
1818                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1819                 if (rc)
1820                         break;
1821
1822                 block_len = min(len - pos,
1823                                 falcon_spi_write_limit(spi, start + pos));
1824                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1825                 rc = falcon_spi_cmd(spi, command, start + pos,
1826                                     buffer + pos, NULL, block_len);
1827                 if (rc)
1828                         break;
1829
1830                 rc = falcon_spi_wait_write(spi);
1831                 if (rc)
1832                         break;
1833
1834                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1835                 rc = falcon_spi_cmd(spi, command, start + pos,
1836                                     NULL, verify_buffer, block_len);
1837                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1838                         rc = -EIO;
1839                         break;
1840                 }
1841
1842                 pos += block_len;
1843
1844                 /* Avoid locking up the system */
1845                 cond_resched();
1846                 if (signal_pending(current)) {
1847                         rc = -EINTR;
1848                         break;
1849                 }
1850         }
1851
1852         if (retlen)
1853                 *retlen = pos;
1854         return rc;
1855 }
1856
1857 /**************************************************************************
1858  *
1859  * MAC wrapper
1860  *
1861  **************************************************************************
1862  */
1863
1864 static int falcon_reset_macs(struct efx_nic *efx)
1865 {
1866         efx_oword_t reg;
1867         int count;
1868
1869         if (falcon_rev(efx) < FALCON_REV_B0) {
1870                 /* It's not safe to use GLB_CTL_REG to reset the
1871                  * macs, so instead use the internal MAC resets
1872                  */
1873                 if (!EFX_IS10G(efx)) {
1874                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1);
1875                         falcon_write(efx, &reg, GM_CFG1_REG);
1876                         udelay(1000);
1877
1878                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0);
1879                         falcon_write(efx, &reg, GM_CFG1_REG);
1880                         udelay(1000);
1881                         return 0;
1882                 } else {
1883                         EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
1884                         falcon_write(efx, &reg, XM_GLB_CFG_REG);
1885
1886                         for (count = 0; count < 10000; count++) {
1887                                 falcon_read(efx, &reg, XM_GLB_CFG_REG);
1888                                 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
1889                                         return 0;
1890                                 udelay(10);
1891                         }
1892
1893                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1894                         return -ETIMEDOUT;
1895                 }
1896         }
1897
1898         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1899          * the drain sequence with the statistics fetch */
1900         efx_stats_disable(efx);
1901
1902         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1903         EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);
1904         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1905
1906         falcon_read(efx, &reg, GLB_CTL_REG_KER);
1907         EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1);
1908         EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1);
1909         EFX_SET_OWORD_FIELD(reg, RST_EM, 1);
1910         falcon_write(efx, &reg, GLB_CTL_REG_KER);
1911
1912         count = 0;
1913         while (1) {
1914                 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1915                 if (!EFX_OWORD_FIELD(reg, RST_XGTX) &&
1916                     !EFX_OWORD_FIELD(reg, RST_XGRX) &&
1917                     !EFX_OWORD_FIELD(reg, RST_EM)) {
1918                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1919                                 count);
1920                         break;
1921                 }
1922                 if (count > 20) {
1923                         EFX_ERR(efx, "MAC reset failed\n");
1924                         break;
1925                 }
1926                 count++;
1927                 udelay(10);
1928         }
1929
1930         efx_stats_enable(efx);
1931
1932         /* If we've reset the EM block and the link is up, then
1933          * we'll have to kick the XAUI link so the PHY can recover */
1934         if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1935                 falcon_reset_xaui(efx);
1936
1937         return 0;
1938 }
1939
1940 void falcon_drain_tx_fifo(struct efx_nic *efx)
1941 {
1942         efx_oword_t reg;
1943
1944         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1945             (efx->loopback_mode != LOOPBACK_NONE))
1946                 return;
1947
1948         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1949         /* There is no point in draining more than once */
1950         if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0))
1951                 return;
1952
1953         falcon_reset_macs(efx);
1954 }
1955
1956 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1957 {
1958         efx_oword_t reg;
1959
1960         if (falcon_rev(efx) < FALCON_REV_B0)
1961                 return;
1962
1963         /* Isolate the MAC -> RX */
1964         falcon_read(efx, &reg, RX_CFG_REG_KER);
1965         EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0);
1966         falcon_write(efx, &reg, RX_CFG_REG_KER);
1967
1968         if (!efx->link_up)
1969                 falcon_drain_tx_fifo(efx);
1970 }
1971
1972 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1973 {
1974         efx_oword_t reg;
1975         int link_speed;
1976         bool tx_fc;
1977
1978         switch (efx->link_speed) {
1979         case 10000: link_speed = 3; break;
1980         case 1000:  link_speed = 2; break;
1981         case 100:   link_speed = 1; break;
1982         default:    link_speed = 0; break;
1983         }
1984         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1985          * as advertised.  Disable to ensure packets are not
1986          * indefinitely held and TX queue can be flushed at any point
1987          * while the link is down. */
1988         EFX_POPULATE_OWORD_5(reg,
1989                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1990                              MAC_BCAD_ACPT, 1,
1991                              MAC_UC_PROM, efx->promiscuous,
1992                              MAC_LINK_STATUS, 1, /* always set */
1993                              MAC_SPEED, link_speed);
1994         /* On B0, MAC backpressure can be disabled and packets get
1995          * discarded. */
1996         if (falcon_rev(efx) >= FALCON_REV_B0) {
1997                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1998                                     !efx->link_up);
1999         }
2000
2001         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
2002
2003         /* Restore the multicast hash registers. */
2004         falcon_set_multicast_hash(efx);
2005
2006         /* Transmission of pause frames when RX crosses the threshold is
2007          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2008          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2009         tx_fc = !!(efx->link_fc & EFX_FC_TX);
2010         falcon_read(efx, &reg, RX_CFG_REG_KER);
2011         EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_EN, tx_fc);
2012
2013         /* Unisolate the MAC -> RX */
2014         if (falcon_rev(efx) >= FALCON_REV_B0)
2015                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2016         falcon_write(efx, &reg, RX_CFG_REG_KER);
2017 }
2018
2019 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2020 {
2021         efx_oword_t reg;
2022         u32 *dma_done;
2023         int i;
2024
2025         if (disable_dma_stats)
2026                 return 0;
2027
2028         /* Statistics fetch will fail if the MAC is in TX drain */
2029         if (falcon_rev(efx) >= FALCON_REV_B0) {
2030                 efx_oword_t temp;
2031                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2032                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2033                         return 0;
2034         }
2035
2036         dma_done = (efx->stats_buffer.addr + done_offset);
2037         *dma_done = FALCON_STATS_NOT_DONE;
2038         wmb(); /* ensure done flag is clear */
2039
2040         /* Initiate DMA transfer of stats */
2041         EFX_POPULATE_OWORD_2(reg,
2042                              MAC_STAT_DMA_CMD, 1,
2043                              MAC_STAT_DMA_ADR,
2044                              efx->stats_buffer.dma_addr);
2045         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
2046
2047         /* Wait for transfer to complete */
2048         for (i = 0; i < 400; i++) {
2049                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2050                         rmb(); /* Ensure the stats are valid. */
2051                         return 0;
2052                 }
2053                 udelay(10);
2054         }
2055
2056         EFX_ERR(efx, "timed out waiting for statistics\n");
2057         return -ETIMEDOUT;
2058 }
2059
2060 /**************************************************************************
2061  *
2062  * PHY access via GMII
2063  *
2064  **************************************************************************
2065  */
2066
2067 /* Wait for GMII access to complete */
2068 static int falcon_gmii_wait(struct efx_nic *efx)
2069 {
2070         efx_dword_t md_stat;
2071         int count;
2072
2073         /* wait upto 50ms - taken max from datasheet */
2074         for (count = 0; count < 5000; count++) {
2075                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2076                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2077                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2078                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2079                                 EFX_ERR(efx, "error from GMII access "
2080                                         EFX_DWORD_FMT"\n",
2081                                         EFX_DWORD_VAL(md_stat));
2082                                 return -EIO;
2083                         }
2084                         return 0;
2085                 }
2086                 udelay(10);
2087         }
2088         EFX_ERR(efx, "timed out waiting for GMII\n");
2089         return -ETIMEDOUT;
2090 }
2091
2092 /* Write an MDIO register of a PHY connected to Falcon. */
2093 static int falcon_mdio_write(struct net_device *net_dev,
2094                              int prtad, int devad, u16 addr, u16 value)
2095 {
2096         struct efx_nic *efx = netdev_priv(net_dev);
2097         efx_oword_t reg;
2098         int rc;
2099
2100         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2101                     prtad, devad, addr, value);
2102
2103         spin_lock_bh(&efx->phy_lock);
2104
2105         /* Check MDIO not currently being accessed */
2106         rc = falcon_gmii_wait(efx);
2107         if (rc)
2108                 goto out;
2109
2110         /* Write the address/ID register */
2111         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2112         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2113
2114         EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2115         falcon_write(efx, &reg, MD_ID_REG_KER);
2116
2117         /* Write data */
2118         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2119         falcon_write(efx, &reg, MD_TXD_REG_KER);
2120
2121         EFX_POPULATE_OWORD_2(reg,
2122                              MD_WRC, 1,
2123                              MD_GC, 0);
2124         falcon_write(efx, &reg, MD_CS_REG_KER);
2125
2126         /* Wait for data to be written */
2127         rc = falcon_gmii_wait(efx);
2128         if (rc) {
2129                 /* Abort the write operation */
2130                 EFX_POPULATE_OWORD_2(reg,
2131                                      MD_WRC, 0,
2132                                      MD_GC, 1);
2133                 falcon_write(efx, &reg, MD_CS_REG_KER);
2134                 udelay(10);
2135         }
2136
2137  out:
2138         spin_unlock_bh(&efx->phy_lock);
2139         return rc;
2140 }
2141
2142 /* Read an MDIO register of a PHY connected to Falcon. */
2143 static int falcon_mdio_read(struct net_device *net_dev,
2144                             int prtad, int devad, u16 addr)
2145 {
2146         struct efx_nic *efx = netdev_priv(net_dev);
2147         efx_oword_t reg;
2148         int rc;
2149
2150         spin_lock_bh(&efx->phy_lock);
2151
2152         /* Check MDIO not currently being accessed */
2153         rc = falcon_gmii_wait(efx);
2154         if (rc)
2155                 goto out;
2156
2157         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2158         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2159
2160         EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2161         falcon_write(efx, &reg, MD_ID_REG_KER);
2162
2163         /* Request data to be read */
2164         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2165         falcon_write(efx, &reg, MD_CS_REG_KER);
2166
2167         /* Wait for data to become available */
2168         rc = falcon_gmii_wait(efx);
2169         if (rc == 0) {
2170                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2171                 rc = EFX_OWORD_FIELD(reg, MD_RXD);
2172                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2173                             prtad, devad, addr, rc);
2174         } else {
2175                 /* Abort the read operation */
2176                 EFX_POPULATE_OWORD_2(reg,
2177                                      MD_RIC, 0,
2178                                      MD_GC, 1);
2179                 falcon_write(efx, &reg, MD_CS_REG_KER);
2180
2181                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2182                         prtad, devad, addr, rc);
2183         }
2184
2185  out:
2186         spin_unlock_bh(&efx->phy_lock);
2187         return rc;
2188 }
2189
2190 static int falcon_probe_phy(struct efx_nic *efx)
2191 {
2192         switch (efx->phy_type) {
2193         case PHY_TYPE_SFX7101:
2194                 efx->phy_op = &falcon_sfx7101_phy_ops;
2195                 break;
2196         case PHY_TYPE_SFT9001A:
2197         case PHY_TYPE_SFT9001B:
2198                 efx->phy_op = &falcon_sft9001_phy_ops;
2199                 break;
2200         case PHY_TYPE_QT2022C2:
2201         case PHY_TYPE_QT2025C:
2202                 efx->phy_op = &falcon_xfp_phy_ops;
2203                 break;
2204         default:
2205                 EFX_ERR(efx, "Unknown PHY type %d\n",
2206                         efx->phy_type);
2207                 return -1;
2208         }
2209
2210         if (efx->phy_op->macs & EFX_XMAC)
2211                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2212                                         (1 << LOOPBACK_XGXS) |
2213                                         (1 << LOOPBACK_XAUI));
2214         if (efx->phy_op->macs & EFX_GMAC)
2215                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2216         efx->loopback_modes |= efx->phy_op->loopbacks;
2217
2218         return 0;
2219 }
2220
2221 int falcon_switch_mac(struct efx_nic *efx)
2222 {
2223         struct efx_mac_operations *old_mac_op = efx->mac_op;
2224         efx_oword_t nic_stat;
2225         unsigned strap_val;
2226         int rc = 0;
2227
2228         /* Don't try to fetch MAC stats while we're switching MACs */
2229         efx_stats_disable(efx);
2230
2231         /* Internal loopbacks override the phy speed setting */
2232         if (efx->loopback_mode == LOOPBACK_GMAC) {
2233                 efx->link_speed = 1000;
2234                 efx->link_fd = true;
2235         } else if (LOOPBACK_INTERNAL(efx)) {
2236                 efx->link_speed = 10000;
2237                 efx->link_fd = true;
2238         }
2239
2240         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2241         efx->mac_op = (EFX_IS10G(efx) ?
2242                        &falcon_xmac_operations : &falcon_gmac_operations);
2243
2244         /* Always push the NIC_STAT_REG setting even if the mac hasn't
2245          * changed, because this function is run post online reset */
2246         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2247         strap_val = EFX_IS10G(efx) ? 5 : 3;
2248         if (falcon_rev(efx) >= FALCON_REV_B0) {
2249                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2250                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2251                 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2252         } else {
2253                 /* Falcon A1 does not support 1G/10G speed switching
2254                  * and must not be used with a PHY that does. */
2255                 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2256         }
2257
2258         if (old_mac_op == efx->mac_op)
2259                 goto out;
2260
2261         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2262         /* Not all macs support a mac-level link state */
2263         efx->mac_up = true;
2264
2265         rc = falcon_reset_macs(efx);
2266 out:
2267         efx_stats_enable(efx);
2268         return rc;
2269 }
2270
2271 /* This call is responsible for hooking in the MAC and PHY operations */
2272 int falcon_probe_port(struct efx_nic *efx)
2273 {
2274         int rc;
2275
2276         /* Hook in PHY operations table */
2277         rc = falcon_probe_phy(efx);
2278         if (rc)
2279                 return rc;
2280
2281         /* Set up MDIO structure for PHY */
2282         efx->mdio.mmds = efx->phy_op->mmds;
2283         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2284         efx->mdio.mdio_read = falcon_mdio_read;
2285         efx->mdio.mdio_write = falcon_mdio_write;
2286
2287         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2288         if (falcon_rev(efx) >= FALCON_REV_B0)
2289                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2290         else
2291                 efx->wanted_fc = EFX_FC_RX;
2292
2293         /* Allocate buffer for stats */
2294         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2295                                  FALCON_MAC_STATS_SIZE);
2296         if (rc)
2297                 return rc;
2298         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2299                 (u64)efx->stats_buffer.dma_addr,
2300                 efx->stats_buffer.addr,
2301                 (u64)virt_to_phys(efx->stats_buffer.addr));
2302
2303         return 0;
2304 }
2305
2306 void falcon_remove_port(struct efx_nic *efx)
2307 {
2308         falcon_free_buffer(efx, &efx->stats_buffer);
2309 }
2310
2311 /**************************************************************************
2312  *
2313  * Multicast filtering
2314  *
2315  **************************************************************************
2316  */
2317
2318 void falcon_set_multicast_hash(struct efx_nic *efx)
2319 {
2320         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2321
2322         /* Broadcast packets go through the multicast hash filter.
2323          * ether_crc_le() of the broadcast address is 0xbe2612ff
2324          * so we always add bit 0xff to the mask.
2325          */
2326         set_bit_le(0xff, mc_hash->byte);
2327
2328         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2329         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2330 }
2331
2332
2333 /**************************************************************************
2334  *
2335  * Falcon test code
2336  *
2337  **************************************************************************/
2338
2339 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2340 {
2341         struct falcon_nvconfig *nvconfig;
2342         struct efx_spi_device *spi;
2343         void *region;
2344         int rc, magic_num, struct_ver;
2345         __le16 *word, *limit;
2346         u32 csum;
2347
2348         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2349         if (!spi)
2350                 return -EINVAL;
2351
2352         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2353         if (!region)
2354                 return -ENOMEM;
2355         nvconfig = region + NVCONFIG_OFFSET;
2356
2357         mutex_lock(&efx->spi_lock);
2358         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2359         mutex_unlock(&efx->spi_lock);
2360         if (rc) {
2361                 EFX_ERR(efx, "Failed to read %s\n",
2362                         efx->spi_flash ? "flash" : "EEPROM");
2363                 rc = -EIO;
2364                 goto out;
2365         }
2366
2367         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2368         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2369
2370         rc = -EINVAL;
2371         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2372                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2373                 goto out;
2374         }
2375         if (struct_ver < 2) {
2376                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2377                 goto out;
2378         } else if (struct_ver < 4) {
2379                 word = &nvconfig->board_magic_num;
2380                 limit = (__le16 *) (nvconfig + 1);
2381         } else {
2382                 word = region;
2383                 limit = region + FALCON_NVCONFIG_END;
2384         }
2385         for (csum = 0; word < limit; ++word)
2386                 csum += le16_to_cpu(*word);
2387
2388         if (~csum & 0xffff) {
2389                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2390                 goto out;
2391         }
2392
2393         rc = 0;
2394         if (nvconfig_out)
2395                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2396
2397  out:
2398         kfree(region);
2399         return rc;
2400 }
2401
2402 /* Registers tested in the falcon register test */
2403 static struct {
2404         unsigned address;
2405         efx_oword_t mask;
2406 } efx_test_registers[] = {
2407         { ADR_REGION_REG_KER,
2408           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2409         { RX_CFG_REG_KER,
2410           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2411         { TX_CFG_REG_KER,
2412           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2413         { TX_CFG2_REG_KER,
2414           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2415         { MAC0_CTRL_REG_KER,
2416           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2417         { SRM_TX_DC_CFG_REG_KER,
2418           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2419         { RX_DC_CFG_REG_KER,
2420           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2421         { RX_DC_PF_WM_REG_KER,
2422           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2423         { DP_CTRL_REG,
2424           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2425         { GM_CFG2_REG,
2426           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2427         { GMF_CFG0_REG,
2428           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2429         { XM_GLB_CFG_REG,
2430           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2431         { XM_TX_CFG_REG,
2432           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2433         { XM_RX_CFG_REG,
2434           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2435         { XM_RX_PARAM_REG,
2436           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2437         { XM_FC_REG,
2438           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2439         { XM_ADR_LO_REG,
2440           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2441         { XX_SD_CTL_REG,
2442           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2443 };
2444
2445 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2446                                      const efx_oword_t *mask)
2447 {
2448         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2449                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2450 }
2451
2452 int falcon_test_registers(struct efx_nic *efx)
2453 {
2454         unsigned address = 0, i, j;
2455         efx_oword_t mask, imask, original, reg, buf;
2456
2457         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2458         WARN_ON(!LOOPBACK_INTERNAL(efx));
2459
2460         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2461                 address = efx_test_registers[i].address;
2462                 mask = imask = efx_test_registers[i].mask;
2463                 EFX_INVERT_OWORD(imask);
2464
2465                 falcon_read(efx, &original, address);
2466
2467                 /* bit sweep on and off */
2468                 for (j = 0; j < 128; j++) {
2469                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2470                                 continue;
2471
2472                         /* Test this testable bit can be set in isolation */
2473                         EFX_AND_OWORD(reg, original, mask);
2474                         EFX_SET_OWORD32(reg, j, j, 1);
2475
2476                         falcon_write(efx, &reg, address);
2477                         falcon_read(efx, &buf, address);
2478
2479                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2480                                 goto fail;
2481
2482                         /* Test this testable bit can be cleared in isolation */
2483                         EFX_OR_OWORD(reg, original, mask);
2484                         EFX_SET_OWORD32(reg, j, j, 0);
2485
2486                         falcon_write(efx, &reg, address);
2487                         falcon_read(efx, &buf, address);
2488
2489                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2490                                 goto fail;
2491                 }
2492
2493                 falcon_write(efx, &original, address);
2494         }
2495
2496         return 0;
2497
2498 fail:
2499         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2500                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2501                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2502         return -EIO;
2503 }
2504
2505 /**************************************************************************
2506  *
2507  * Device reset
2508  *
2509  **************************************************************************
2510  */
2511
2512 /* Resets NIC to known state.  This routine must be called in process
2513  * context and is allowed to sleep. */
2514 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2515 {
2516         struct falcon_nic_data *nic_data = efx->nic_data;
2517         efx_oword_t glb_ctl_reg_ker;
2518         int rc;
2519
2520         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2521
2522         /* Initiate device reset */
2523         if (method == RESET_TYPE_WORLD) {
2524                 rc = pci_save_state(efx->pci_dev);
2525                 if (rc) {
2526                         EFX_ERR(efx, "failed to backup PCI state of primary "
2527                                 "function prior to hardware reset\n");
2528                         goto fail1;
2529                 }
2530                 if (FALCON_IS_DUAL_FUNC(efx)) {
2531                         rc = pci_save_state(nic_data->pci_dev2);
2532                         if (rc) {
2533                                 EFX_ERR(efx, "failed to backup PCI state of "
2534                                         "secondary function prior to "
2535                                         "hardware reset\n");
2536                                 goto fail2;
2537                         }
2538                 }
2539
2540                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2541                                      EXT_PHY_RST_DUR, 0x7,
2542                                      SWRST, 1);
2543         } else {
2544                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2545                                  EXCLUDE_FROM_RESET : 0);
2546
2547                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2548                                      EXT_PHY_RST_CTL, reset_phy,
2549                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2550                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2551                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2552                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2553                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2554                                      SWRST, 1);
2555         }
2556         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2557
2558         EFX_LOG(efx, "waiting for hardware reset\n");
2559         schedule_timeout_uninterruptible(HZ / 20);
2560
2561         /* Restore PCI configuration if needed */
2562         if (method == RESET_TYPE_WORLD) {
2563                 if (FALCON_IS_DUAL_FUNC(efx)) {
2564                         rc = pci_restore_state(nic_data->pci_dev2);
2565                         if (rc) {
2566                                 EFX_ERR(efx, "failed to restore PCI config for "
2567                                         "the secondary function\n");
2568                                 goto fail3;
2569                         }
2570                 }
2571                 rc = pci_restore_state(efx->pci_dev);
2572                 if (rc) {
2573                         EFX_ERR(efx, "failed to restore PCI config for the "
2574                                 "primary function\n");
2575                         goto fail4;
2576                 }
2577                 EFX_LOG(efx, "successfully restored PCI config\n");
2578         }
2579
2580         /* Assert that reset complete */
2581         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2582         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2583                 rc = -ETIMEDOUT;
2584                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2585                 goto fail5;
2586         }
2587         EFX_LOG(efx, "hardware reset complete\n");
2588
2589         return 0;
2590
2591         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2592 fail2:
2593 fail3:
2594         pci_restore_state(efx->pci_dev);
2595 fail1:
2596 fail4:
2597 fail5:
2598         return rc;
2599 }
2600
2601 /* Zeroes out the SRAM contents.  This routine must be called in
2602  * process context and is allowed to sleep.
2603  */
2604 static int falcon_reset_sram(struct efx_nic *efx)
2605 {
2606         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2607         int count;
2608
2609         /* Set the SRAM wake/sleep GPIO appropriately. */
2610         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2611         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2612         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2613         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2614
2615         /* Initiate SRAM reset */
2616         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2617                              SRAM_OOB_BT_INIT_EN, 1,
2618                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2619         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2620
2621         /* Wait for SRAM reset to complete */
2622         count = 0;
2623         do {
2624                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2625
2626                 /* SRAM reset is slow; expect around 16ms */
2627                 schedule_timeout_uninterruptible(HZ / 50);
2628
2629                 /* Check for reset complete */
2630                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2631                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2632                         EFX_LOG(efx, "SRAM reset complete\n");
2633
2634                         return 0;
2635                 }
2636         } while (++count < 20); /* wait upto 0.4 sec */
2637
2638         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2639         return -ETIMEDOUT;
2640 }
2641
2642 static int falcon_spi_device_init(struct efx_nic *efx,
2643                                   struct efx_spi_device **spi_device_ret,
2644                                   unsigned int device_id, u32 device_type)
2645 {
2646         struct efx_spi_device *spi_device;
2647
2648         if (device_type != 0) {
2649                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2650                 if (!spi_device)
2651                         return -ENOMEM;
2652                 spi_device->device_id = device_id;
2653                 spi_device->size =
2654                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2655                 spi_device->addr_len =
2656                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2657                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2658                                              spi_device->addr_len == 1);
2659                 spi_device->erase_command =
2660                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2661                 spi_device->erase_size =
2662                         1 << SPI_DEV_TYPE_FIELD(device_type,
2663                                                 SPI_DEV_TYPE_ERASE_SIZE);
2664                 spi_device->block_size =
2665                         1 << SPI_DEV_TYPE_FIELD(device_type,
2666                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2667
2668                 spi_device->efx = efx;
2669         } else {
2670                 spi_device = NULL;
2671         }
2672
2673         kfree(*spi_device_ret);
2674         *spi_device_ret = spi_device;
2675         return 0;
2676 }
2677
2678
2679 static void falcon_remove_spi_devices(struct efx_nic *efx)
2680 {
2681         kfree(efx->spi_eeprom);
2682         efx->spi_eeprom = NULL;
2683         kfree(efx->spi_flash);
2684         efx->spi_flash = NULL;
2685 }
2686
2687 /* Extract non-volatile configuration */
2688 static int falcon_probe_nvconfig(struct efx_nic *efx)
2689 {
2690         struct falcon_nvconfig *nvconfig;
2691         int board_rev;
2692         int rc;
2693
2694         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2695         if (!nvconfig)
2696                 return -ENOMEM;
2697
2698         rc = falcon_read_nvram(efx, nvconfig);
2699         if (rc == -EINVAL) {
2700                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2701                 efx->phy_type = PHY_TYPE_NONE;
2702                 efx->mdio.prtad = MDIO_PRTAD_NONE;
2703                 board_rev = 0;
2704                 rc = 0;
2705         } else if (rc) {
2706                 goto fail1;
2707         } else {
2708                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2709                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2710
2711                 efx->phy_type = v2->port0_phy_type;
2712                 efx->mdio.prtad = v2->port0_phy_addr;
2713                 board_rev = le16_to_cpu(v2->board_revision);
2714
2715                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2716                         __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2717                         __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2718                         rc = falcon_spi_device_init(efx, &efx->spi_flash,
2719                                                     EE_SPI_FLASH,
2720                                                     le32_to_cpu(fl));
2721                         if (rc)
2722                                 goto fail2;
2723                         rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2724                                                     EE_SPI_EEPROM,
2725                                                     le32_to_cpu(ee));
2726                         if (rc)
2727                                 goto fail2;
2728                 }
2729         }
2730
2731         /* Read the MAC addresses */
2732         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2733
2734         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2735
2736         falcon_probe_board(efx, board_rev);
2737
2738         kfree(nvconfig);
2739         return 0;
2740
2741  fail2:
2742         falcon_remove_spi_devices(efx);
2743  fail1:
2744         kfree(nvconfig);
2745         return rc;
2746 }
2747
2748 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2749  * count, port speed).  Set workaround and feature flags accordingly.
2750  */
2751 static int falcon_probe_nic_variant(struct efx_nic *efx)
2752 {
2753         efx_oword_t altera_build;
2754         efx_oword_t nic_stat;
2755
2756         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2757         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2758                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2759                 return -ENODEV;
2760         }
2761
2762         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2763
2764         switch (falcon_rev(efx)) {
2765         case FALCON_REV_A0:
2766         case 0xff:
2767                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2768                 return -ENODEV;
2769
2770         case FALCON_REV_A1:
2771                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2772                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2773                         return -ENODEV;
2774                 }
2775                 break;
2776
2777         case FALCON_REV_B0:
2778                 break;
2779
2780         default:
2781                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2782                 return -ENODEV;
2783         }
2784
2785         /* Initial assumed speed */
2786         efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2787
2788         return 0;
2789 }
2790
2791 /* Probe all SPI devices on the NIC */
2792 static void falcon_probe_spi_devices(struct efx_nic *efx)
2793 {
2794         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2795         int boot_dev;
2796
2797         falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2798         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2799         falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2800
2801         if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2802                 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2803                             EE_SPI_FLASH : EE_SPI_EEPROM);
2804                 EFX_LOG(efx, "Booted from %s\n",
2805                         boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2806         } else {
2807                 /* Disable VPD and set clock dividers to safe
2808                  * values for initial programming. */
2809                 boot_dev = -1;
2810                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2811                         " setting SPI config\n");
2812                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2813                                      /* 125 MHz / 7 ~= 20 MHz */
2814                                      EE_SF_CLOCK_DIV, 7,
2815                                      /* 125 MHz / 63 ~= 2 MHz */
2816                                      EE_EE_CLOCK_DIV, 63);
2817                 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2818         }
2819
2820         if (boot_dev == EE_SPI_FLASH)
2821                 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2822                                        default_flash_type);
2823         if (boot_dev == EE_SPI_EEPROM)
2824                 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2825                                        large_eeprom_type);
2826 }
2827
2828 int falcon_probe_nic(struct efx_nic *efx)
2829 {
2830         struct falcon_nic_data *nic_data;
2831         int rc;
2832
2833         /* Allocate storage for hardware specific data */
2834         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2835         if (!nic_data)
2836                 return -ENOMEM;
2837         efx->nic_data = nic_data;
2838
2839         /* Determine number of ports etc. */
2840         rc = falcon_probe_nic_variant(efx);
2841         if (rc)
2842                 goto fail1;
2843
2844         /* Probe secondary function if expected */
2845         if (FALCON_IS_DUAL_FUNC(efx)) {
2846                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2847
2848                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2849                                              dev))) {
2850                         if (dev->bus == efx->pci_dev->bus &&
2851                             dev->devfn == efx->pci_dev->devfn + 1) {
2852                                 nic_data->pci_dev2 = dev;
2853                                 break;
2854                         }
2855                 }
2856                 if (!nic_data->pci_dev2) {
2857                         EFX_ERR(efx, "failed to find secondary function\n");
2858                         rc = -ENODEV;
2859                         goto fail2;
2860                 }
2861         }
2862
2863         /* Now we can reset the NIC */
2864         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2865         if (rc) {
2866                 EFX_ERR(efx, "failed to reset NIC\n");
2867                 goto fail3;
2868         }
2869
2870         /* Allocate memory for INT_KER */
2871         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2872         if (rc)
2873                 goto fail4;
2874         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2875
2876         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2877                 (u64)efx->irq_status.dma_addr,
2878                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2879
2880         falcon_probe_spi_devices(efx);
2881
2882         /* Read in the non-volatile configuration */
2883         rc = falcon_probe_nvconfig(efx);
2884         if (rc)
2885                 goto fail5;
2886
2887         /* Initialise I2C adapter */
2888         efx->i2c_adap.owner = THIS_MODULE;
2889         nic_data->i2c_data = falcon_i2c_bit_operations;
2890         nic_data->i2c_data.data = efx;
2891         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2892         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2893         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2894         rc = i2c_bit_add_bus(&efx->i2c_adap);
2895         if (rc)
2896                 goto fail5;
2897
2898         return 0;
2899
2900  fail5:
2901         falcon_remove_spi_devices(efx);
2902         falcon_free_buffer(efx, &efx->irq_status);
2903  fail4:
2904  fail3:
2905         if (nic_data->pci_dev2) {
2906                 pci_dev_put(nic_data->pci_dev2);
2907                 nic_data->pci_dev2 = NULL;
2908         }
2909  fail2:
2910  fail1:
2911         kfree(efx->nic_data);
2912         return rc;
2913 }
2914
2915 static void falcon_init_rx_cfg(struct efx_nic *efx)
2916 {
2917         /* Prior to Siena the RX DMA engine will split each frame at
2918          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2919          * be so large that that never happens. */
2920         const unsigned huge_buf_size = (3 * 4096) >> 5;
2921         /* RX control FIFO thresholds (32 entries) */
2922         const unsigned ctrl_xon_thr = 20;
2923         const unsigned ctrl_xoff_thr = 25;
2924         /* RX data FIFO thresholds (256-byte units; size varies) */
2925         int data_xon_thr = rx_xon_thresh_bytes >> 8;
2926         int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2927         efx_oword_t reg;
2928
2929         falcon_read(efx, &reg, RX_CFG_REG_KER);
2930         if (falcon_rev(efx) <= FALCON_REV_A1) {
2931                 /* Data FIFO size is 5.5K */
2932                 if (data_xon_thr < 0)
2933                         data_xon_thr = 512 >> 8;
2934                 if (data_xoff_thr < 0)
2935                         data_xoff_thr = 2048 >> 8;
2936                 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_A1, 0);
2937                 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_A1, huge_buf_size);
2938                 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_A1, data_xon_thr);
2939                 EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_TH_A1, data_xoff_thr);
2940                 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_A1, ctrl_xon_thr);
2941                 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_A1, ctrl_xoff_thr);
2942         } else {
2943                 /* Data FIFO size is 80K; register fields moved */
2944                 if (data_xon_thr < 0)
2945                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2946                 if (data_xoff_thr < 0)
2947                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2948                 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_B0, 0);
2949                 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_B0, huge_buf_size);
2950                 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_B0, data_xon_thr);
2951                 EFX_SET_OWORD_FIELD(reg, RX_XOFF_MAC_TH_B0, data_xoff_thr);
2952                 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_B0, ctrl_xon_thr);
2953                 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_B0, ctrl_xoff_thr);
2954                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2955         }
2956         falcon_write(efx, &reg, RX_CFG_REG_KER);
2957 }
2958
2959 /* This call performs hardware-specific global initialisation, such as
2960  * defining the descriptor cache sizes and number of RSS channels.
2961  * It does not set up any buffers, descriptor rings or event queues.
2962  */
2963 int falcon_init_nic(struct efx_nic *efx)
2964 {
2965         efx_oword_t temp;
2966         int rc;
2967
2968         /* Use on-chip SRAM */
2969         falcon_read(efx, &temp, NIC_STAT_REG);
2970         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2971         falcon_write(efx, &temp, NIC_STAT_REG);
2972
2973         /* Set the source of the GMAC clock */
2974         if (falcon_rev(efx) == FALCON_REV_B0) {
2975                 falcon_read(efx, &temp, GPIO_CTL_REG_KER);
2976                 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true);
2977                 falcon_write(efx, &temp, GPIO_CTL_REG_KER);
2978         }
2979
2980         rc = falcon_reset_sram(efx);
2981         if (rc)
2982                 return rc;
2983
2984         /* Set positions of descriptor caches in SRAM. */
2985         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2986         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2987         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2988         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2989
2990         /* Set TX descriptor cache size. */
2991         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2992         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2993         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2994
2995         /* Set RX descriptor cache size.  Set low watermark to size-8, as
2996          * this allows most efficient prefetching.
2997          */
2998         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2999         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3000         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
3001         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3002         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
3003
3004         /* Clear the parity enables on the TX data fifos as
3005          * they produce false parity errors because of timing issues
3006          */
3007         if (EFX_WORKAROUND_5129(efx)) {
3008                 falcon_read(efx, &temp, SPARE_REG_KER);
3009                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
3010                 falcon_write(efx, &temp, SPARE_REG_KER);
3011         }
3012
3013         /* Enable all the genuinely fatal interrupts.  (They are still
3014          * masked by the overall interrupt mask, controlled by
3015          * falcon_interrupts()).
3016          *
3017          * Note: All other fatal interrupts are enabled
3018          */
3019         EFX_POPULATE_OWORD_3(temp,
3020                              ILL_ADR_INT_KER_EN, 1,
3021                              RBUF_OWN_INT_KER_EN, 1,
3022                              TBUF_OWN_INT_KER_EN, 1);
3023         EFX_INVERT_OWORD(temp);
3024         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
3025
3026         if (EFX_WORKAROUND_7244(efx)) {
3027                 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
3028                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
3029                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
3030                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
3031                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
3032                 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
3033         }
3034
3035         falcon_setup_rss_indir_table(efx);
3036
3037         /* Setup RX.  Wait for descriptor is broken and must
3038          * be disabled.  RXDP recovery shouldn't be needed, but is.
3039          */
3040         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
3041         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
3042         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
3043         if (EFX_WORKAROUND_5583(efx))
3044                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
3045         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
3046
3047         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3048          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3049          */
3050         falcon_read(efx, &temp, TX_CFG2_REG_KER);
3051         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3052         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3053         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3054         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3055         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3056         /* Enable SW_EV to inherit in char driver - assume harmless here */
3057         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3058         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3059         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3060         /* Squash TX of packets of 16 bytes or less */
3061         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3062                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3063         falcon_write(efx, &temp, TX_CFG2_REG_KER);
3064
3065         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3066          * descriptors (which is bad).
3067          */
3068         falcon_read(efx, &temp, TX_CFG_REG_KER);
3069         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
3070         falcon_write(efx, &temp, TX_CFG_REG_KER);
3071
3072         falcon_init_rx_cfg(efx);
3073
3074         /* Set destination of both TX and RX Flush events */
3075         if (falcon_rev(efx) >= FALCON_REV_B0) {
3076                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3077                 falcon_write(efx, &temp, DP_CTRL_REG);
3078         }
3079
3080         return 0;
3081 }
3082
3083 void falcon_remove_nic(struct efx_nic *efx)
3084 {
3085         struct falcon_nic_data *nic_data = efx->nic_data;
3086         int rc;
3087
3088         /* Remove I2C adapter and clear it in preparation for a retry */
3089         rc = i2c_del_adapter(&efx->i2c_adap);
3090         BUG_ON(rc);
3091         memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3092
3093         falcon_remove_spi_devices(efx);
3094         falcon_free_buffer(efx, &efx->irq_status);
3095
3096         falcon_reset_hw(efx, RESET_TYPE_ALL);
3097
3098         /* Release the second function after the reset */
3099         if (nic_data->pci_dev2) {
3100                 pci_dev_put(nic_data->pci_dev2);
3101                 nic_data->pci_dev2 = NULL;
3102         }
3103
3104         /* Tear down the private nic state */
3105         kfree(efx->nic_data);
3106         efx->nic_data = NULL;
3107 }
3108
3109 void falcon_update_nic_stats(struct efx_nic *efx)
3110 {
3111         efx_oword_t cnt;
3112
3113         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3114         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3115 }
3116
3117 /**************************************************************************
3118  *
3119  * Revision-dependent attributes used by efx.c
3120  *
3121  **************************************************************************
3122  */
3123
3124 struct efx_nic_type falcon_a_nic_type = {
3125         .mem_bar = 2,
3126         .mem_map_size = 0x20000,
3127         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3128         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3129         .buf_tbl_base = BUF_TBL_KER_A1,
3130         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3131         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3132         .txd_ring_mask = FALCON_TXD_RING_MASK,
3133         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3134         .evq_size = FALCON_EVQ_SIZE,
3135         .max_dma_mask = FALCON_DMA_MASK,
3136         .tx_dma_mask = FALCON_TX_DMA_MASK,
3137         .bug5391_mask = 0xf,
3138         .rx_buffer_padding = 0x24,
3139         .max_interrupt_mode = EFX_INT_MODE_MSI,
3140         .phys_addr_channels = 4,
3141 };
3142
3143 struct efx_nic_type falcon_b_nic_type = {
3144         .mem_bar = 2,
3145         /* Map everything up to and including the RSS indirection
3146          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3147          * requires that they not be mapped.  */
3148         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3149         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3150         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3151         .buf_tbl_base = BUF_TBL_KER_B0,
3152         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3153         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3154         .txd_ring_mask = FALCON_TXD_RING_MASK,
3155         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3156         .evq_size = FALCON_EVQ_SIZE,
3157         .max_dma_mask = FALCON_DMA_MASK,
3158         .tx_dma_mask = FALCON_TX_DMA_MASK,
3159         .bug5391_mask = 0,
3160         .rx_buffer_padding = 0,
3161         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3162         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3163                                    * interrupt handler only supports 32
3164                                    * channels */
3165 };
3166