sfc: Define DMA address mask explicitly in terms of descriptor field width
[linux-2.6.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2008 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Falcon hardware control.
32  * Falcon is the internal codename for the SFC4000 controller that is
33  * present in SFE400X evaluation boards
34  */
35
36 /**
37  * struct falcon_nic_data - Falcon NIC state
38  * @next_buffer_table: First available buffer table id
39  * @pci_dev2: The secondary PCI device if present
40  * @i2c_data: Operations and state for I2C bit-bashing algorithm
41  * @int_error_count: Number of internal errors seen recently
42  * @int_error_expire: Time at which error count will be expired
43  */
44 struct falcon_nic_data {
45         unsigned next_buffer_table;
46         struct pci_dev *pci_dev2;
47         struct i2c_algo_bit_data i2c_data;
48
49         unsigned int_error_count;
50         unsigned long int_error_expire;
51 };
52
53 /**************************************************************************
54  *
55  * Configurable values
56  *
57  **************************************************************************
58  */
59
60 static int disable_dma_stats;
61
62 /* This is set to 16 for a good reason.  In summary, if larger than
63  * 16, the descriptor cache holds more than a default socket
64  * buffer's worth of packets (for UDP we can only have at most one
65  * socket buffer's worth outstanding).  This combined with the fact
66  * that we only get 1 TX event per descriptor cache means the NIC
67  * goes idle.
68  */
69 #define TX_DC_ENTRIES 16
70 #define TX_DC_ENTRIES_ORDER 0
71 #define TX_DC_BASE 0x130000
72
73 #define RX_DC_ENTRIES 64
74 #define RX_DC_ENTRIES_ORDER 2
75 #define RX_DC_BASE 0x100000
76
77 static const unsigned int
78 /* "Large" EEPROM device: Atmel AT25640 or similar
79  * 8 KB, 16-bit address, 32 B write block */
80 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
81                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
82                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
83 /* Default flash device: Atmel AT25F1024
84  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
85 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
86                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
87                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
88                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
89                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
90
91 /* RX FIFO XOFF watermark
92  *
93  * When the amount of the RX FIFO increases used increases past this
94  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
95  * This also has an effect on RX/TX arbitration
96  */
97 static int rx_xoff_thresh_bytes = -1;
98 module_param(rx_xoff_thresh_bytes, int, 0644);
99 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
100
101 /* RX FIFO XON watermark
102  *
103  * When the amount of the RX FIFO used decreases below this
104  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
105  * This also has an effect on RX/TX arbitration
106  */
107 static int rx_xon_thresh_bytes = -1;
108 module_param(rx_xon_thresh_bytes, int, 0644);
109 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
110
111 /* If FALCON_MAX_INT_ERRORS internal errors occur within
112  * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
113  * disable it.
114  */
115 #define FALCON_INT_ERROR_EXPIRE 3600
116 #define FALCON_MAX_INT_ERRORS 5
117
118 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
119  */
120 #define FALCON_FLUSH_INTERVAL 10
121 #define FALCON_FLUSH_POLL_COUNT 100
122
123 /**************************************************************************
124  *
125  * Falcon constants
126  *
127  **************************************************************************
128  */
129
130 /* TX DMA length mask (13-bit) */
131 #define FALCON_TX_DMA_MASK (4096 - 1)
132
133 /* Size and alignment of special buffers (4KB) */
134 #define FALCON_BUF_SIZE 4096
135
136 /* Dummy SRAM size code */
137 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
138
139 #define FALCON_IS_DUAL_FUNC(efx)                \
140         (falcon_rev(efx) < FALCON_REV_B0)
141
142 /**************************************************************************
143  *
144  * Falcon hardware access
145  *
146  **************************************************************************/
147
148 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
149                                         unsigned int index)
150 {
151         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
152                         value, index);
153 }
154
155 /* Read the current event from the event queue */
156 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
157                                         unsigned int index)
158 {
159         return (((efx_qword_t *) (channel->eventq.addr)) + index);
160 }
161
162 /* See if an event is present
163  *
164  * We check both the high and low dword of the event for all ones.  We
165  * wrote all ones when we cleared the event, and no valid event can
166  * have all ones in either its high or low dwords.  This approach is
167  * robust against reordering.
168  *
169  * Note that using a single 64-bit comparison is incorrect; even
170  * though the CPU read will be atomic, the DMA write may not be.
171  */
172 static inline int falcon_event_present(efx_qword_t *event)
173 {
174         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
175                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
176 }
177
178 /**************************************************************************
179  *
180  * I2C bus - this is a bit-bashing interface using GPIO pins
181  * Note that it uses the output enables to tristate the outputs
182  * SDA is the data pin and SCL is the clock
183  *
184  **************************************************************************
185  */
186 static void falcon_setsda(void *data, int state)
187 {
188         struct efx_nic *efx = (struct efx_nic *)data;
189         efx_oword_t reg;
190
191         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
192         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
193         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
194 }
195
196 static void falcon_setscl(void *data, int state)
197 {
198         struct efx_nic *efx = (struct efx_nic *)data;
199         efx_oword_t reg;
200
201         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
202         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
203         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
204 }
205
206 static int falcon_getsda(void *data)
207 {
208         struct efx_nic *efx = (struct efx_nic *)data;
209         efx_oword_t reg;
210
211         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
212         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
213 }
214
215 static int falcon_getscl(void *data)
216 {
217         struct efx_nic *efx = (struct efx_nic *)data;
218         efx_oword_t reg;
219
220         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
221         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
222 }
223
224 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
225         .setsda         = falcon_setsda,
226         .setscl         = falcon_setscl,
227         .getsda         = falcon_getsda,
228         .getscl         = falcon_getscl,
229         .udelay         = 5,
230         /* Wait up to 50 ms for slave to let us pull SCL high */
231         .timeout        = DIV_ROUND_UP(HZ, 20),
232 };
233
234 /**************************************************************************
235  *
236  * Falcon special buffer handling
237  * Special buffers are used for event queues and the TX and RX
238  * descriptor rings.
239  *
240  *************************************************************************/
241
242 /*
243  * Initialise a Falcon special buffer
244  *
245  * This will define a buffer (previously allocated via
246  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
247  * it to be used for event queues, descriptor rings etc.
248  */
249 static void
250 falcon_init_special_buffer(struct efx_nic *efx,
251                            struct efx_special_buffer *buffer)
252 {
253         efx_qword_t buf_desc;
254         int index;
255         dma_addr_t dma_addr;
256         int i;
257
258         EFX_BUG_ON_PARANOID(!buffer->addr);
259
260         /* Write buffer descriptors to NIC */
261         for (i = 0; i < buffer->entries; i++) {
262                 index = buffer->index + i;
263                 dma_addr = buffer->dma_addr + (i * 4096);
264                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
265                         index, (unsigned long long)dma_addr);
266                 EFX_POPULATE_QWORD_3(buf_desc,
267                                      FRF_AZ_BUF_ADR_REGION, 0,
268                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
269                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
270                 falcon_write_buf_tbl(efx, &buf_desc, index);
271         }
272 }
273
274 /* Unmaps a buffer from Falcon and clears the buffer table entries */
275 static void
276 falcon_fini_special_buffer(struct efx_nic *efx,
277                            struct efx_special_buffer *buffer)
278 {
279         efx_oword_t buf_tbl_upd;
280         unsigned int start = buffer->index;
281         unsigned int end = (buffer->index + buffer->entries - 1);
282
283         if (!buffer->entries)
284                 return;
285
286         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
287                 buffer->index, buffer->index + buffer->entries - 1);
288
289         EFX_POPULATE_OWORD_4(buf_tbl_upd,
290                              FRF_AZ_BUF_UPD_CMD, 0,
291                              FRF_AZ_BUF_CLR_CMD, 1,
292                              FRF_AZ_BUF_CLR_END_ID, end,
293                              FRF_AZ_BUF_CLR_START_ID, start);
294         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
295 }
296
297 /*
298  * Allocate a new Falcon special buffer
299  *
300  * This allocates memory for a new buffer, clears it and allocates a
301  * new buffer ID range.  It does not write into Falcon's buffer table.
302  *
303  * This call will allocate 4KB buffers, since Falcon can't use 8KB
304  * buffers for event queues and descriptor rings.
305  */
306 static int falcon_alloc_special_buffer(struct efx_nic *efx,
307                                        struct efx_special_buffer *buffer,
308                                        unsigned int len)
309 {
310         struct falcon_nic_data *nic_data = efx->nic_data;
311
312         len = ALIGN(len, FALCON_BUF_SIZE);
313
314         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
315                                             &buffer->dma_addr);
316         if (!buffer->addr)
317                 return -ENOMEM;
318         buffer->len = len;
319         buffer->entries = len / FALCON_BUF_SIZE;
320         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
321
322         /* All zeros is a potentially valid event so memset to 0xff */
323         memset(buffer->addr, 0xff, len);
324
325         /* Select new buffer ID */
326         buffer->index = nic_data->next_buffer_table;
327         nic_data->next_buffer_table += buffer->entries;
328
329         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
330                 "(virt %p phys %llx)\n", buffer->index,
331                 buffer->index + buffer->entries - 1,
332                 (u64)buffer->dma_addr, len,
333                 buffer->addr, (u64)virt_to_phys(buffer->addr));
334
335         return 0;
336 }
337
338 static void falcon_free_special_buffer(struct efx_nic *efx,
339                                        struct efx_special_buffer *buffer)
340 {
341         if (!buffer->addr)
342                 return;
343
344         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
345                 "(virt %p phys %llx)\n", buffer->index,
346                 buffer->index + buffer->entries - 1,
347                 (u64)buffer->dma_addr, buffer->len,
348                 buffer->addr, (u64)virt_to_phys(buffer->addr));
349
350         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
351                             buffer->dma_addr);
352         buffer->addr = NULL;
353         buffer->entries = 0;
354 }
355
356 /**************************************************************************
357  *
358  * Falcon generic buffer handling
359  * These buffers are used for interrupt status and MAC stats
360  *
361  **************************************************************************/
362
363 static int falcon_alloc_buffer(struct efx_nic *efx,
364                                struct efx_buffer *buffer, unsigned int len)
365 {
366         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
367                                             &buffer->dma_addr);
368         if (!buffer->addr)
369                 return -ENOMEM;
370         buffer->len = len;
371         memset(buffer->addr, 0, len);
372         return 0;
373 }
374
375 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
376 {
377         if (buffer->addr) {
378                 pci_free_consistent(efx->pci_dev, buffer->len,
379                                     buffer->addr, buffer->dma_addr);
380                 buffer->addr = NULL;
381         }
382 }
383
384 /**************************************************************************
385  *
386  * Falcon TX path
387  *
388  **************************************************************************/
389
390 /* Returns a pointer to the specified transmit descriptor in the TX
391  * descriptor queue belonging to the specified channel.
392  */
393 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
394                                                unsigned int index)
395 {
396         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
397 }
398
399 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
400 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
401 {
402         unsigned write_ptr;
403         efx_dword_t reg;
404
405         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
406         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
407         efx_writed_page(tx_queue->efx, &reg,
408                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
409 }
410
411
412 /* For each entry inserted into the software descriptor ring, create a
413  * descriptor in the hardware TX descriptor ring (in host memory), and
414  * write a doorbell.
415  */
416 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
417 {
418
419         struct efx_tx_buffer *buffer;
420         efx_qword_t *txd;
421         unsigned write_ptr;
422
423         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
424
425         do {
426                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
427                 buffer = &tx_queue->buffer[write_ptr];
428                 txd = falcon_tx_desc(tx_queue, write_ptr);
429                 ++tx_queue->write_count;
430
431                 /* Create TX descriptor ring entry */
432                 EFX_POPULATE_QWORD_4(*txd,
433                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
434                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
435                                      FSF_AZ_TX_KER_BUF_REGION, 0,
436                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
437         } while (tx_queue->write_count != tx_queue->insert_count);
438
439         wmb(); /* Ensure descriptors are written before they are fetched */
440         falcon_notify_tx_desc(tx_queue);
441 }
442
443 /* Allocate hardware resources for a TX queue */
444 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
445 {
446         struct efx_nic *efx = tx_queue->efx;
447         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
448                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
449         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
450                                            EFX_TXQ_SIZE * sizeof(efx_qword_t));
451 }
452
453 void falcon_init_tx(struct efx_tx_queue *tx_queue)
454 {
455         efx_oword_t tx_desc_ptr;
456         struct efx_nic *efx = tx_queue->efx;
457
458         tx_queue->flushed = false;
459
460         /* Pin TX descriptor ring */
461         falcon_init_special_buffer(efx, &tx_queue->txd);
462
463         /* Push TX descriptor ring to card */
464         EFX_POPULATE_OWORD_10(tx_desc_ptr,
465                               FRF_AZ_TX_DESCQ_EN, 1,
466                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
467                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
468                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
469                               FRF_AZ_TX_DESCQ_EVQ_ID,
470                               tx_queue->channel->channel,
471                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
472                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
473                               FRF_AZ_TX_DESCQ_SIZE,
474                               __ffs(tx_queue->txd.entries),
475                               FRF_AZ_TX_DESCQ_TYPE, 0,
476                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
477
478         if (falcon_rev(efx) >= FALCON_REV_B0) {
479                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
480                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
481                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
482                                     !csum);
483         }
484
485         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
486                          tx_queue->queue);
487
488         if (falcon_rev(efx) < FALCON_REV_B0) {
489                 efx_oword_t reg;
490
491                 /* Only 128 bits in this register */
492                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
493
494                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
495                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
496                         clear_bit_le(tx_queue->queue, (void *)&reg);
497                 else
498                         set_bit_le(tx_queue->queue, (void *)&reg);
499                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
500         }
501 }
502
503 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
504 {
505         struct efx_nic *efx = tx_queue->efx;
506         efx_oword_t tx_flush_descq;
507
508         /* Post a flush command */
509         EFX_POPULATE_OWORD_2(tx_flush_descq,
510                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
511                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
512         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
513 }
514
515 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
516 {
517         struct efx_nic *efx = tx_queue->efx;
518         efx_oword_t tx_desc_ptr;
519
520         /* The queue should have been flushed */
521         WARN_ON(!tx_queue->flushed);
522
523         /* Remove TX descriptor ring from card */
524         EFX_ZERO_OWORD(tx_desc_ptr);
525         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
526                          tx_queue->queue);
527
528         /* Unpin TX descriptor ring */
529         falcon_fini_special_buffer(efx, &tx_queue->txd);
530 }
531
532 /* Free buffers backing TX queue */
533 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
534 {
535         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
536 }
537
538 /**************************************************************************
539  *
540  * Falcon RX path
541  *
542  **************************************************************************/
543
544 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
545 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
546                                                unsigned int index)
547 {
548         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
549 }
550
551 /* This creates an entry in the RX descriptor queue */
552 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
553                                         unsigned index)
554 {
555         struct efx_rx_buffer *rx_buf;
556         efx_qword_t *rxd;
557
558         rxd = falcon_rx_desc(rx_queue, index);
559         rx_buf = efx_rx_buffer(rx_queue, index);
560         EFX_POPULATE_QWORD_3(*rxd,
561                              FSF_AZ_RX_KER_BUF_SIZE,
562                              rx_buf->len -
563                              rx_queue->efx->type->rx_buffer_padding,
564                              FSF_AZ_RX_KER_BUF_REGION, 0,
565                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
566 }
567
568 /* This writes to the RX_DESC_WPTR register for the specified receive
569  * descriptor ring.
570  */
571 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
572 {
573         efx_dword_t reg;
574         unsigned write_ptr;
575
576         while (rx_queue->notified_count != rx_queue->added_count) {
577                 falcon_build_rx_desc(rx_queue,
578                                      rx_queue->notified_count &
579                                      EFX_RXQ_MASK);
580                 ++rx_queue->notified_count;
581         }
582
583         wmb();
584         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
585         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
586         efx_writed_page(rx_queue->efx, &reg,
587                         FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
588 }
589
590 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
591 {
592         struct efx_nic *efx = rx_queue->efx;
593         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
594                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
595         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
596                                            EFX_RXQ_SIZE * sizeof(efx_qword_t));
597 }
598
599 void falcon_init_rx(struct efx_rx_queue *rx_queue)
600 {
601         efx_oword_t rx_desc_ptr;
602         struct efx_nic *efx = rx_queue->efx;
603         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
604         bool iscsi_digest_en = is_b0;
605
606         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
607                 rx_queue->queue, rx_queue->rxd.index,
608                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
609
610         rx_queue->flushed = false;
611
612         /* Pin RX descriptor ring */
613         falcon_init_special_buffer(efx, &rx_queue->rxd);
614
615         /* Push RX descriptor ring to card */
616         EFX_POPULATE_OWORD_10(rx_desc_ptr,
617                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
618                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
619                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
620                               FRF_AZ_RX_DESCQ_EVQ_ID,
621                               rx_queue->channel->channel,
622                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
623                               FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
624                               FRF_AZ_RX_DESCQ_SIZE,
625                               __ffs(rx_queue->rxd.entries),
626                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
627                               /* For >=B0 this is scatter so disable */
628                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
629                               FRF_AZ_RX_DESCQ_EN, 1);
630         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
631                          rx_queue->queue);
632 }
633
634 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
635 {
636         struct efx_nic *efx = rx_queue->efx;
637         efx_oword_t rx_flush_descq;
638
639         /* Post a flush command */
640         EFX_POPULATE_OWORD_2(rx_flush_descq,
641                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
642                              FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
643         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
644 }
645
646 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
647 {
648         efx_oword_t rx_desc_ptr;
649         struct efx_nic *efx = rx_queue->efx;
650
651         /* The queue should already have been flushed */
652         WARN_ON(!rx_queue->flushed);
653
654         /* Remove RX descriptor ring from card */
655         EFX_ZERO_OWORD(rx_desc_ptr);
656         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
657                          rx_queue->queue);
658
659         /* Unpin RX descriptor ring */
660         falcon_fini_special_buffer(efx, &rx_queue->rxd);
661 }
662
663 /* Free buffers backing RX queue */
664 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
665 {
666         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
667 }
668
669 /**************************************************************************
670  *
671  * Falcon event queue processing
672  * Event queues are processed by per-channel tasklets.
673  *
674  **************************************************************************/
675
676 /* Update a channel's event queue's read pointer (RPTR) register
677  *
678  * This writes the EVQ_RPTR_REG register for the specified channel's
679  * event queue.
680  *
681  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
682  * whereas channel->eventq_read_ptr contains the index of the "next to
683  * read" event.
684  */
685 void falcon_eventq_read_ack(struct efx_channel *channel)
686 {
687         efx_dword_t reg;
688         struct efx_nic *efx = channel->efx;
689
690         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
691         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
692                             channel->channel);
693 }
694
695 /* Use HW to insert a SW defined event */
696 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
697 {
698         efx_oword_t drv_ev_reg;
699
700         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
701                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
702         drv_ev_reg.u32[0] = event->u32[0];
703         drv_ev_reg.u32[1] = event->u32[1];
704         drv_ev_reg.u32[2] = 0;
705         drv_ev_reg.u32[3] = 0;
706         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
707         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
708 }
709
710 /* Handle a transmit completion event
711  *
712  * Falcon batches TX completion events; the message we receive is of
713  * the form "complete all TX events up to this index".
714  */
715 static void falcon_handle_tx_event(struct efx_channel *channel,
716                                    efx_qword_t *event)
717 {
718         unsigned int tx_ev_desc_ptr;
719         unsigned int tx_ev_q_label;
720         struct efx_tx_queue *tx_queue;
721         struct efx_nic *efx = channel->efx;
722
723         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
724                 /* Transmit completion */
725                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
726                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
727                 tx_queue = &efx->tx_queue[tx_ev_q_label];
728                 channel->irq_mod_score +=
729                         (tx_ev_desc_ptr - tx_queue->read_count) &
730                         EFX_TXQ_MASK;
731                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
732         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
733                 /* Rewrite the FIFO write pointer */
734                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
735                 tx_queue = &efx->tx_queue[tx_ev_q_label];
736
737                 if (efx_dev_registered(efx))
738                         netif_tx_lock(efx->net_dev);
739                 falcon_notify_tx_desc(tx_queue);
740                 if (efx_dev_registered(efx))
741                         netif_tx_unlock(efx->net_dev);
742         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
743                    EFX_WORKAROUND_10727(efx)) {
744                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
745         } else {
746                 EFX_ERR(efx, "channel %d unexpected TX event "
747                         EFX_QWORD_FMT"\n", channel->channel,
748                         EFX_QWORD_VAL(*event));
749         }
750 }
751
752 /* Detect errors included in the rx_evt_pkt_ok bit. */
753 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
754                                     const efx_qword_t *event,
755                                     bool *rx_ev_pkt_ok,
756                                     bool *discard)
757 {
758         struct efx_nic *efx = rx_queue->efx;
759         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
760         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
761         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
762         bool rx_ev_other_err, rx_ev_pause_frm;
763         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
764         unsigned rx_ev_pkt_type;
765
766         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
767         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
768         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
769         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
770         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
771                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
772         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
773         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
774                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
775         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
776                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
777         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
778         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
779         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
780                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
781         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
782
783         /* Every error apart from tobe_disc and pause_frm */
784         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
785                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
786                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
787
788         /* Count errors that are not in MAC stats.  Ignore expected
789          * checksum errors during self-test. */
790         if (rx_ev_frm_trunc)
791                 ++rx_queue->channel->n_rx_frm_trunc;
792         else if (rx_ev_tobe_disc)
793                 ++rx_queue->channel->n_rx_tobe_disc;
794         else if (!efx->loopback_selftest) {
795                 if (rx_ev_ip_hdr_chksum_err)
796                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
797                 else if (rx_ev_tcp_udp_chksum_err)
798                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
799         }
800         if (rx_ev_ip_frag_err)
801                 ++rx_queue->channel->n_rx_ip_frag_err;
802
803         /* The frame must be discarded if any of these are true. */
804         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
805                     rx_ev_tobe_disc | rx_ev_pause_frm);
806
807         /* TOBE_DISC is expected on unicast mismatches; don't print out an
808          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
809          * to a FIFO overflow.
810          */
811 #ifdef EFX_ENABLE_DEBUG
812         if (rx_ev_other_err) {
813                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
814                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
815                             rx_queue->queue, EFX_QWORD_VAL(*event),
816                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
817                             rx_ev_ip_hdr_chksum_err ?
818                             " [IP_HDR_CHKSUM_ERR]" : "",
819                             rx_ev_tcp_udp_chksum_err ?
820                             " [TCP_UDP_CHKSUM_ERR]" : "",
821                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
822                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
823                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
824                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
825                             rx_ev_pause_frm ? " [PAUSE]" : "");
826         }
827 #endif
828 }
829
830 /* Handle receive events that are not in-order. */
831 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
832                                        unsigned index)
833 {
834         struct efx_nic *efx = rx_queue->efx;
835         unsigned expected, dropped;
836
837         expected = rx_queue->removed_count & EFX_RXQ_MASK;
838         dropped = (index - expected) & EFX_RXQ_MASK;
839         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
840                 dropped, index, expected);
841
842         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
843                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
844 }
845
846 /* Handle a packet received event
847  *
848  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
849  * wrong destination address
850  * Also "is multicast" and "matches multicast filter" flags can be used to
851  * discard non-matching multicast packets.
852  */
853 static void falcon_handle_rx_event(struct efx_channel *channel,
854                                    const efx_qword_t *event)
855 {
856         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
857         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
858         unsigned expected_ptr;
859         bool rx_ev_pkt_ok, discard = false, checksummed;
860         struct efx_rx_queue *rx_queue;
861         struct efx_nic *efx = channel->efx;
862
863         /* Basic packet information */
864         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
865         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
866         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
867         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
868         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
869         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
870                 channel->channel);
871
872         rx_queue = &efx->rx_queue[channel->channel];
873
874         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
875         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
876         if (unlikely(rx_ev_desc_ptr != expected_ptr))
877                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
878
879         if (likely(rx_ev_pkt_ok)) {
880                 /* If packet is marked as OK and packet type is TCP/IPv4 or
881                  * UDP/IPv4, then we can rely on the hardware checksum.
882                  */
883                 checksummed =
884                         rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
885                         rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
886         } else {
887                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
888                                         &discard);
889                 checksummed = false;
890         }
891
892         /* Detect multicast packets that didn't match the filter */
893         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
894         if (rx_ev_mcast_pkt) {
895                 unsigned int rx_ev_mcast_hash_match =
896                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
897
898                 if (unlikely(!rx_ev_mcast_hash_match))
899                         discard = true;
900         }
901
902         channel->irq_mod_score += 2;
903
904         /* Handle received packet */
905         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
906                       checksummed, discard);
907 }
908
909 /* Global events are basically PHY events */
910 static void falcon_handle_global_event(struct efx_channel *channel,
911                                        efx_qword_t *event)
912 {
913         struct efx_nic *efx = channel->efx;
914         bool handled = false;
915
916         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
917             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
918             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
919                 efx->phy_op->clear_interrupt(efx);
920                 queue_work(efx->workqueue, &efx->phy_work);
921                 handled = true;
922         }
923
924         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
925             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
926                 queue_work(efx->workqueue, &efx->mac_work);
927                 handled = true;
928         }
929
930         if (falcon_rev(efx) <= FALCON_REV_A1 ?
931             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
932             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
933                 EFX_ERR(efx, "channel %d seen global RX_RESET "
934                         "event. Resetting.\n", channel->channel);
935
936                 atomic_inc(&efx->rx_reset);
937                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
938                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
939                 handled = true;
940         }
941
942         if (!handled)
943                 EFX_ERR(efx, "channel %d unknown global event "
944                         EFX_QWORD_FMT "\n", channel->channel,
945                         EFX_QWORD_VAL(*event));
946 }
947
948 static void falcon_handle_driver_event(struct efx_channel *channel,
949                                        efx_qword_t *event)
950 {
951         struct efx_nic *efx = channel->efx;
952         unsigned int ev_sub_code;
953         unsigned int ev_sub_data;
954
955         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
956         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
957
958         switch (ev_sub_code) {
959         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
960                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
961                           channel->channel, ev_sub_data);
962                 break;
963         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
964                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
965                           channel->channel, ev_sub_data);
966                 break;
967         case FSE_AZ_EVQ_INIT_DONE_EV:
968                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
969                         channel->channel, ev_sub_data);
970                 break;
971         case FSE_AZ_SRM_UPD_DONE_EV:
972                 EFX_TRACE(efx, "channel %d SRAM update done\n",
973                           channel->channel);
974                 break;
975         case FSE_AZ_WAKE_UP_EV:
976                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
977                           channel->channel, ev_sub_data);
978                 break;
979         case FSE_AZ_TIMER_EV:
980                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
981                           channel->channel, ev_sub_data);
982                 break;
983         case FSE_AA_RX_RECOVER_EV:
984                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
985                         "Resetting.\n", channel->channel);
986                 atomic_inc(&efx->rx_reset);
987                 efx_schedule_reset(efx,
988                                    EFX_WORKAROUND_6555(efx) ?
989                                    RESET_TYPE_RX_RECOVERY :
990                                    RESET_TYPE_DISABLE);
991                 break;
992         case FSE_BZ_RX_DSC_ERROR_EV:
993                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
994                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
995                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
996                 break;
997         case FSE_BZ_TX_DSC_ERROR_EV:
998                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
999                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1000                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1001                 break;
1002         default:
1003                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1004                           "data %04x\n", channel->channel, ev_sub_code,
1005                           ev_sub_data);
1006                 break;
1007         }
1008 }
1009
1010 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1011 {
1012         unsigned int read_ptr;
1013         efx_qword_t event, *p_event;
1014         int ev_code;
1015         int rx_packets = 0;
1016
1017         read_ptr = channel->eventq_read_ptr;
1018
1019         do {
1020                 p_event = falcon_event(channel, read_ptr);
1021                 event = *p_event;
1022
1023                 if (!falcon_event_present(&event))
1024                         /* End of events */
1025                         break;
1026
1027                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1028                           channel->channel, EFX_QWORD_VAL(event));
1029
1030                 /* Clear this event by marking it all ones */
1031                 EFX_SET_QWORD(*p_event);
1032
1033                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1034
1035                 switch (ev_code) {
1036                 case FSE_AZ_EV_CODE_RX_EV:
1037                         falcon_handle_rx_event(channel, &event);
1038                         ++rx_packets;
1039                         break;
1040                 case FSE_AZ_EV_CODE_TX_EV:
1041                         falcon_handle_tx_event(channel, &event);
1042                         break;
1043                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1044                         channel->eventq_magic = EFX_QWORD_FIELD(
1045                                 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1046                         EFX_LOG(channel->efx, "channel %d received generated "
1047                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1048                                 EFX_QWORD_VAL(event));
1049                         break;
1050                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1051                         falcon_handle_global_event(channel, &event);
1052                         break;
1053                 case FSE_AZ_EV_CODE_DRIVER_EV:
1054                         falcon_handle_driver_event(channel, &event);
1055                         break;
1056                 default:
1057                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1058                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1059                                 ev_code, EFX_QWORD_VAL(event));
1060                 }
1061
1062                 /* Increment read pointer */
1063                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1064
1065         } while (rx_packets < rx_quota);
1066
1067         channel->eventq_read_ptr = read_ptr;
1068         return rx_packets;
1069 }
1070
1071 void falcon_set_int_moderation(struct efx_channel *channel)
1072 {
1073         efx_dword_t timer_cmd;
1074         struct efx_nic *efx = channel->efx;
1075
1076         /* Set timer register */
1077         if (channel->irq_moderation) {
1078                 /* Round to resolution supported by hardware.  The value we
1079                  * program is based at 0.  So actual interrupt moderation
1080                  * achieved is ((x + 1) * res).
1081                  */
1082                 channel->irq_moderation -= (channel->irq_moderation %
1083                                             FALCON_IRQ_MOD_RESOLUTION);
1084                 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1085                         channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1086                 EFX_POPULATE_DWORD_2(timer_cmd,
1087                                      FRF_AB_TC_TIMER_MODE,
1088                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
1089                                      FRF_AB_TC_TIMER_VAL,
1090                                      channel->irq_moderation /
1091                                      FALCON_IRQ_MOD_RESOLUTION - 1);
1092         } else {
1093                 EFX_POPULATE_DWORD_2(timer_cmd,
1094                                      FRF_AB_TC_TIMER_MODE,
1095                                      FFE_BB_TIMER_MODE_DIS,
1096                                      FRF_AB_TC_TIMER_VAL, 0);
1097         }
1098         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1099         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1100                                channel->channel);
1101
1102 }
1103
1104 /* Allocate buffer table entries for event queue */
1105 int falcon_probe_eventq(struct efx_channel *channel)
1106 {
1107         struct efx_nic *efx = channel->efx;
1108         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1109                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1110         return falcon_alloc_special_buffer(efx, &channel->eventq,
1111                                            EFX_EVQ_SIZE * sizeof(efx_qword_t));
1112 }
1113
1114 void falcon_init_eventq(struct efx_channel *channel)
1115 {
1116         efx_oword_t evq_ptr;
1117         struct efx_nic *efx = channel->efx;
1118
1119         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1120                 channel->channel, channel->eventq.index,
1121                 channel->eventq.index + channel->eventq.entries - 1);
1122
1123         /* Pin event queue buffer */
1124         falcon_init_special_buffer(efx, &channel->eventq);
1125
1126         /* Fill event queue with all ones (i.e. empty events) */
1127         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1128
1129         /* Push event queue to card */
1130         EFX_POPULATE_OWORD_3(evq_ptr,
1131                              FRF_AZ_EVQ_EN, 1,
1132                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1133                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1134         efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1135                          channel->channel);
1136
1137         falcon_set_int_moderation(channel);
1138 }
1139
1140 void falcon_fini_eventq(struct efx_channel *channel)
1141 {
1142         efx_oword_t eventq_ptr;
1143         struct efx_nic *efx = channel->efx;
1144
1145         /* Remove event queue from card */
1146         EFX_ZERO_OWORD(eventq_ptr);
1147         efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1148                          channel->channel);
1149
1150         /* Unpin event queue */
1151         falcon_fini_special_buffer(efx, &channel->eventq);
1152 }
1153
1154 /* Free buffers backing event queue */
1155 void falcon_remove_eventq(struct efx_channel *channel)
1156 {
1157         falcon_free_special_buffer(channel->efx, &channel->eventq);
1158 }
1159
1160
1161 /* Generates a test event on the event queue.  A subsequent call to
1162  * process_eventq() should pick up the event and place the value of
1163  * "magic" into channel->eventq_magic;
1164  */
1165 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1166 {
1167         efx_qword_t test_event;
1168
1169         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1170                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1171                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1172         falcon_generate_event(channel, &test_event);
1173 }
1174
1175 void falcon_sim_phy_event(struct efx_nic *efx)
1176 {
1177         efx_qword_t phy_event;
1178
1179         EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1180                              FSE_AZ_EV_CODE_GLOBAL_EV);
1181         if (EFX_IS10G(efx))
1182                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1183         else
1184                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1185
1186         falcon_generate_event(&efx->channel[0], &phy_event);
1187 }
1188
1189 /**************************************************************************
1190  *
1191  * Flush handling
1192  *
1193  **************************************************************************/
1194
1195
1196 static void falcon_poll_flush_events(struct efx_nic *efx)
1197 {
1198         struct efx_channel *channel = &efx->channel[0];
1199         struct efx_tx_queue *tx_queue;
1200         struct efx_rx_queue *rx_queue;
1201         unsigned int read_ptr = channel->eventq_read_ptr;
1202         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1203
1204         do {
1205                 efx_qword_t *event = falcon_event(channel, read_ptr);
1206                 int ev_code, ev_sub_code, ev_queue;
1207                 bool ev_failed;
1208
1209                 if (!falcon_event_present(event))
1210                         break;
1211
1212                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1213                 ev_sub_code = EFX_QWORD_FIELD(*event,
1214                                               FSF_AZ_DRIVER_EV_SUBCODE);
1215                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1216                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1217                         ev_queue = EFX_QWORD_FIELD(*event,
1218                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1219                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1220                                 tx_queue = efx->tx_queue + ev_queue;
1221                                 tx_queue->flushed = true;
1222                         }
1223                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1224                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1225                         ev_queue = EFX_QWORD_FIELD(
1226                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1227                         ev_failed = EFX_QWORD_FIELD(
1228                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1229                         if (ev_queue < efx->n_rx_queues) {
1230                                 rx_queue = efx->rx_queue + ev_queue;
1231
1232                                 /* retry the rx flush */
1233                                 if (ev_failed)
1234                                         falcon_flush_rx_queue(rx_queue);
1235                                 else
1236                                         rx_queue->flushed = true;
1237                         }
1238                 }
1239
1240                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1241         } while (read_ptr != end_ptr);
1242 }
1243
1244 /* Handle tx and rx flushes at the same time, since they run in
1245  * parallel in the hardware and there's no reason for us to
1246  * serialise them */
1247 int falcon_flush_queues(struct efx_nic *efx)
1248 {
1249         struct efx_rx_queue *rx_queue;
1250         struct efx_tx_queue *tx_queue;
1251         int i;
1252         bool outstanding;
1253
1254         /* Issue flush requests */
1255         efx_for_each_tx_queue(tx_queue, efx) {
1256                 tx_queue->flushed = false;
1257                 falcon_flush_tx_queue(tx_queue);
1258         }
1259         efx_for_each_rx_queue(rx_queue, efx) {
1260                 rx_queue->flushed = false;
1261                 falcon_flush_rx_queue(rx_queue);
1262         }
1263
1264         /* Poll the evq looking for flush completions. Since we're not pushing
1265          * any more rx or tx descriptors at this point, we're in no danger of
1266          * overflowing the evq whilst we wait */
1267         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1268                 msleep(FALCON_FLUSH_INTERVAL);
1269                 falcon_poll_flush_events(efx);
1270
1271                 /* Check if every queue has been succesfully flushed */
1272                 outstanding = false;
1273                 efx_for_each_tx_queue(tx_queue, efx)
1274                         outstanding |= !tx_queue->flushed;
1275                 efx_for_each_rx_queue(rx_queue, efx)
1276                         outstanding |= !rx_queue->flushed;
1277                 if (!outstanding)
1278                         return 0;
1279         }
1280
1281         /* Mark the queues as all flushed. We're going to return failure
1282          * leading to a reset, or fake up success anyway. "flushed" now
1283          * indicates that we tried to flush. */
1284         efx_for_each_tx_queue(tx_queue, efx) {
1285                 if (!tx_queue->flushed)
1286                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1287                                 tx_queue->queue);
1288                 tx_queue->flushed = true;
1289         }
1290         efx_for_each_rx_queue(rx_queue, efx) {
1291                 if (!rx_queue->flushed)
1292                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1293                                 rx_queue->queue);
1294                 rx_queue->flushed = true;
1295         }
1296
1297         if (EFX_WORKAROUND_7803(efx))
1298                 return 0;
1299
1300         return -ETIMEDOUT;
1301 }
1302
1303 /**************************************************************************
1304  *
1305  * Falcon hardware interrupts
1306  * The hardware interrupt handler does very little work; all the event
1307  * queue processing is carried out by per-channel tasklets.
1308  *
1309  **************************************************************************/
1310
1311 /* Enable/disable/generate Falcon interrupts */
1312 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1313                                      int force)
1314 {
1315         efx_oword_t int_en_reg_ker;
1316
1317         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1318                              FRF_AZ_KER_INT_KER, force,
1319                              FRF_AZ_DRV_INT_EN_KER, enabled);
1320         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1321 }
1322
1323 void falcon_enable_interrupts(struct efx_nic *efx)
1324 {
1325         efx_oword_t int_adr_reg_ker;
1326         struct efx_channel *channel;
1327
1328         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1329         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1330
1331         /* Program address */
1332         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1333                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1334                              EFX_INT_MODE_USE_MSI(efx),
1335                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1336         efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1337
1338         /* Enable interrupts */
1339         falcon_interrupts(efx, 1, 0);
1340
1341         /* Force processing of all the channels to get the EVQ RPTRs up to
1342            date */
1343         efx_for_each_channel(channel, efx)
1344                 efx_schedule_channel(channel);
1345 }
1346
1347 void falcon_disable_interrupts(struct efx_nic *efx)
1348 {
1349         /* Disable interrupts */
1350         falcon_interrupts(efx, 0, 0);
1351 }
1352
1353 /* Generate a Falcon test interrupt
1354  * Interrupt must already have been enabled, otherwise nasty things
1355  * may happen.
1356  */
1357 void falcon_generate_interrupt(struct efx_nic *efx)
1358 {
1359         falcon_interrupts(efx, 1, 1);
1360 }
1361
1362 /* Acknowledge a legacy interrupt from Falcon
1363  *
1364  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1365  *
1366  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1367  * BIU. Interrupt acknowledge is read sensitive so must write instead
1368  * (then read to ensure the BIU collector is flushed)
1369  *
1370  * NB most hardware supports MSI interrupts
1371  */
1372 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1373 {
1374         efx_dword_t reg;
1375
1376         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1377         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1378         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1379 }
1380
1381 /* Process a fatal interrupt
1382  * Disable bus mastering ASAP and schedule a reset
1383  */
1384 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1385 {
1386         struct falcon_nic_data *nic_data = efx->nic_data;
1387         efx_oword_t *int_ker = efx->irq_status.addr;
1388         efx_oword_t fatal_intr;
1389         int error, mem_perr;
1390
1391         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1392         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1393
1394         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1395                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1396                 EFX_OWORD_VAL(fatal_intr),
1397                 error ? "disabling bus mastering" : "no recognised error");
1398         if (error == 0)
1399                 goto out;
1400
1401         /* If this is a memory parity error dump which blocks are offending */
1402         mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1403         if (mem_perr) {
1404                 efx_oword_t reg;
1405                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1406                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1407                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1408         }
1409
1410         /* Disable both devices */
1411         pci_clear_master(efx->pci_dev);
1412         if (FALCON_IS_DUAL_FUNC(efx))
1413                 pci_clear_master(nic_data->pci_dev2);
1414         falcon_disable_interrupts(efx);
1415
1416         /* Count errors and reset or disable the NIC accordingly */
1417         if (nic_data->int_error_count == 0 ||
1418             time_after(jiffies, nic_data->int_error_expire)) {
1419                 nic_data->int_error_count = 0;
1420                 nic_data->int_error_expire =
1421                         jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1422         }
1423         if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1424                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1425                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1426         } else {
1427                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1428                         "NIC will be disabled\n");
1429                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1430         }
1431 out:
1432         return IRQ_HANDLED;
1433 }
1434
1435 /* Handle a legacy interrupt from Falcon
1436  * Acknowledges the interrupt and schedule event queue processing.
1437  */
1438 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1439 {
1440         struct efx_nic *efx = dev_id;
1441         efx_oword_t *int_ker = efx->irq_status.addr;
1442         irqreturn_t result = IRQ_NONE;
1443         struct efx_channel *channel;
1444         efx_dword_t reg;
1445         u32 queues;
1446         int syserr;
1447
1448         /* Read the ISR which also ACKs the interrupts */
1449         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1450         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1451
1452         /* Check to see if we have a serious error condition */
1453         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1454         if (unlikely(syserr))
1455                 return falcon_fatal_interrupt(efx);
1456
1457         /* Schedule processing of any interrupting queues */
1458         efx_for_each_channel(channel, efx) {
1459                 if ((queues & 1) ||
1460                     falcon_event_present(
1461                             falcon_event(channel, channel->eventq_read_ptr))) {
1462                         efx_schedule_channel(channel);
1463                         result = IRQ_HANDLED;
1464                 }
1465                 queues >>= 1;
1466         }
1467
1468         if (result == IRQ_HANDLED) {
1469                 efx->last_irq_cpu = raw_smp_processor_id();
1470                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1471                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1472         }
1473
1474         return result;
1475 }
1476
1477
1478 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1479 {
1480         struct efx_nic *efx = dev_id;
1481         efx_oword_t *int_ker = efx->irq_status.addr;
1482         struct efx_channel *channel;
1483         int syserr;
1484         int queues;
1485
1486         /* Check to see if this is our interrupt.  If it isn't, we
1487          * exit without having touched the hardware.
1488          */
1489         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1490                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1491                           raw_smp_processor_id());
1492                 return IRQ_NONE;
1493         }
1494         efx->last_irq_cpu = raw_smp_processor_id();
1495         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1496                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1497
1498         /* Check to see if we have a serious error condition */
1499         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1500         if (unlikely(syserr))
1501                 return falcon_fatal_interrupt(efx);
1502
1503         /* Determine interrupting queues, clear interrupt status
1504          * register and acknowledge the device interrupt.
1505          */
1506         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1507         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1508         EFX_ZERO_OWORD(*int_ker);
1509         wmb(); /* Ensure the vector is cleared before interrupt ack */
1510         falcon_irq_ack_a1(efx);
1511
1512         /* Schedule processing of any interrupting queues */
1513         channel = &efx->channel[0];
1514         while (queues) {
1515                 if (queues & 0x01)
1516                         efx_schedule_channel(channel);
1517                 channel++;
1518                 queues >>= 1;
1519         }
1520
1521         return IRQ_HANDLED;
1522 }
1523
1524 /* Handle an MSI interrupt from Falcon
1525  *
1526  * Handle an MSI hardware interrupt.  This routine schedules event
1527  * queue processing.  No interrupt acknowledgement cycle is necessary.
1528  * Also, we never need to check that the interrupt is for us, since
1529  * MSI interrupts cannot be shared.
1530  */
1531 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1532 {
1533         struct efx_channel *channel = dev_id;
1534         struct efx_nic *efx = channel->efx;
1535         efx_oword_t *int_ker = efx->irq_status.addr;
1536         int syserr;
1537
1538         efx->last_irq_cpu = raw_smp_processor_id();
1539         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1540                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1541
1542         /* Check to see if we have a serious error condition */
1543         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1544         if (unlikely(syserr))
1545                 return falcon_fatal_interrupt(efx);
1546
1547         /* Schedule processing of the channel */
1548         efx_schedule_channel(channel);
1549
1550         return IRQ_HANDLED;
1551 }
1552
1553
1554 /* Setup RSS indirection table.
1555  * This maps from the hash value of the packet to RXQ
1556  */
1557 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1558 {
1559         int i = 0;
1560         unsigned long offset;
1561         efx_dword_t dword;
1562
1563         if (falcon_rev(efx) < FALCON_REV_B0)
1564                 return;
1565
1566         for (offset = FR_BZ_RX_INDIRECTION_TBL;
1567              offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1568              offset += 0x10) {
1569                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1570                                      i % efx->n_rx_queues);
1571                 efx_writed(efx, &dword, offset);
1572                 i++;
1573         }
1574 }
1575
1576 /* Hook interrupt handler(s)
1577  * Try MSI and then legacy interrupts.
1578  */
1579 int falcon_init_interrupt(struct efx_nic *efx)
1580 {
1581         struct efx_channel *channel;
1582         int rc;
1583
1584         if (!EFX_INT_MODE_USE_MSI(efx)) {
1585                 irq_handler_t handler;
1586                 if (falcon_rev(efx) >= FALCON_REV_B0)
1587                         handler = falcon_legacy_interrupt_b0;
1588                 else
1589                         handler = falcon_legacy_interrupt_a1;
1590
1591                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1592                                  efx->name, efx);
1593                 if (rc) {
1594                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1595                                 efx->pci_dev->irq);
1596                         goto fail1;
1597                 }
1598                 return 0;
1599         }
1600
1601         /* Hook MSI or MSI-X interrupt */
1602         efx_for_each_channel(channel, efx) {
1603                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1604                                  IRQF_PROBE_SHARED, /* Not shared */
1605                                  channel->name, channel);
1606                 if (rc) {
1607                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1608                         goto fail2;
1609                 }
1610         }
1611
1612         return 0;
1613
1614  fail2:
1615         efx_for_each_channel(channel, efx)
1616                 free_irq(channel->irq, channel);
1617  fail1:
1618         return rc;
1619 }
1620
1621 void falcon_fini_interrupt(struct efx_nic *efx)
1622 {
1623         struct efx_channel *channel;
1624         efx_oword_t reg;
1625
1626         /* Disable MSI/MSI-X interrupts */
1627         efx_for_each_channel(channel, efx) {
1628                 if (channel->irq)
1629                         free_irq(channel->irq, channel);
1630         }
1631
1632         /* ACK legacy interrupt */
1633         if (falcon_rev(efx) >= FALCON_REV_B0)
1634                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1635         else
1636                 falcon_irq_ack_a1(efx);
1637
1638         /* Disable legacy interrupt */
1639         if (efx->legacy_irq)
1640                 free_irq(efx->legacy_irq, efx);
1641 }
1642
1643 /**************************************************************************
1644  *
1645  * EEPROM/flash
1646  *
1647  **************************************************************************
1648  */
1649
1650 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1651
1652 static int falcon_spi_poll(struct efx_nic *efx)
1653 {
1654         efx_oword_t reg;
1655         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1656         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1657 }
1658
1659 /* Wait for SPI command completion */
1660 static int falcon_spi_wait(struct efx_nic *efx)
1661 {
1662         /* Most commands will finish quickly, so we start polling at
1663          * very short intervals.  Sometimes the command may have to
1664          * wait for VPD or expansion ROM access outside of our
1665          * control, so we allow up to 100 ms. */
1666         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1667         int i;
1668
1669         for (i = 0; i < 10; i++) {
1670                 if (!falcon_spi_poll(efx))
1671                         return 0;
1672                 udelay(10);
1673         }
1674
1675         for (;;) {
1676                 if (!falcon_spi_poll(efx))
1677                         return 0;
1678                 if (time_after_eq(jiffies, timeout)) {
1679                         EFX_ERR(efx, "timed out waiting for SPI\n");
1680                         return -ETIMEDOUT;
1681                 }
1682                 schedule_timeout_uninterruptible(1);
1683         }
1684 }
1685
1686 int falcon_spi_cmd(const struct efx_spi_device *spi,
1687                    unsigned int command, int address,
1688                    const void *in, void *out, size_t len)
1689 {
1690         struct efx_nic *efx = spi->efx;
1691         bool addressed = (address >= 0);
1692         bool reading = (out != NULL);
1693         efx_oword_t reg;
1694         int rc;
1695
1696         /* Input validation */
1697         if (len > FALCON_SPI_MAX_LEN)
1698                 return -EINVAL;
1699         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1700
1701         /* Check that previous command is not still running */
1702         rc = falcon_spi_poll(efx);
1703         if (rc)
1704                 return rc;
1705
1706         /* Program address register, if we have an address */
1707         if (addressed) {
1708                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1709                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1710         }
1711
1712         /* Program data register, if we have data */
1713         if (in != NULL) {
1714                 memcpy(&reg, in, len);
1715                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1716         }
1717
1718         /* Issue read/write command */
1719         EFX_POPULATE_OWORD_7(reg,
1720                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1721                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1722                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
1723                              FRF_AB_EE_SPI_HCMD_READ, reading,
1724                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1725                              FRF_AB_EE_SPI_HCMD_ADBCNT,
1726                              (addressed ? spi->addr_len : 0),
1727                              FRF_AB_EE_SPI_HCMD_ENC, command);
1728         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1729
1730         /* Wait for read/write to complete */
1731         rc = falcon_spi_wait(efx);
1732         if (rc)
1733                 return rc;
1734
1735         /* Read data */
1736         if (out != NULL) {
1737                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1738                 memcpy(out, &reg, len);
1739         }
1740
1741         return 0;
1742 }
1743
1744 static size_t
1745 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1746 {
1747         return min(FALCON_SPI_MAX_LEN,
1748                    (spi->block_size - (start & (spi->block_size - 1))));
1749 }
1750
1751 static inline u8
1752 efx_spi_munge_command(const struct efx_spi_device *spi,
1753                       const u8 command, const unsigned int address)
1754 {
1755         return command | (((address >> 8) & spi->munge_address) << 3);
1756 }
1757
1758 /* Wait up to 10 ms for buffered write completion */
1759 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1760 {
1761         struct efx_nic *efx = spi->efx;
1762         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1763         u8 status;
1764         int rc;
1765
1766         for (;;) {
1767                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1768                                     &status, sizeof(status));
1769                 if (rc)
1770                         return rc;
1771                 if (!(status & SPI_STATUS_NRDY))
1772                         return 0;
1773                 if (time_after_eq(jiffies, timeout)) {
1774                         EFX_ERR(efx, "SPI write timeout on device %d"
1775                                 " last status=0x%02x\n",
1776                                 spi->device_id, status);
1777                         return -ETIMEDOUT;
1778                 }
1779                 schedule_timeout_uninterruptible(1);
1780         }
1781 }
1782
1783 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1784                     size_t len, size_t *retlen, u8 *buffer)
1785 {
1786         size_t block_len, pos = 0;
1787         unsigned int command;
1788         int rc = 0;
1789
1790         while (pos < len) {
1791                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1792
1793                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1794                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1795                                     buffer + pos, block_len);
1796                 if (rc)
1797                         break;
1798                 pos += block_len;
1799
1800                 /* Avoid locking up the system */
1801                 cond_resched();
1802                 if (signal_pending(current)) {
1803                         rc = -EINTR;
1804                         break;
1805                 }
1806         }
1807
1808         if (retlen)
1809                 *retlen = pos;
1810         return rc;
1811 }
1812
1813 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1814                      size_t len, size_t *retlen, const u8 *buffer)
1815 {
1816         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1817         size_t block_len, pos = 0;
1818         unsigned int command;
1819         int rc = 0;
1820
1821         while (pos < len) {
1822                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1823                 if (rc)
1824                         break;
1825
1826                 block_len = min(len - pos,
1827                                 falcon_spi_write_limit(spi, start + pos));
1828                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1829                 rc = falcon_spi_cmd(spi, command, start + pos,
1830                                     buffer + pos, NULL, block_len);
1831                 if (rc)
1832                         break;
1833
1834                 rc = falcon_spi_wait_write(spi);
1835                 if (rc)
1836                         break;
1837
1838                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1839                 rc = falcon_spi_cmd(spi, command, start + pos,
1840                                     NULL, verify_buffer, block_len);
1841                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1842                         rc = -EIO;
1843                         break;
1844                 }
1845
1846                 pos += block_len;
1847
1848                 /* Avoid locking up the system */
1849                 cond_resched();
1850                 if (signal_pending(current)) {
1851                         rc = -EINTR;
1852                         break;
1853                 }
1854         }
1855
1856         if (retlen)
1857                 *retlen = pos;
1858         return rc;
1859 }
1860
1861 /**************************************************************************
1862  *
1863  * MAC wrapper
1864  *
1865  **************************************************************************
1866  */
1867
1868 static int falcon_reset_macs(struct efx_nic *efx)
1869 {
1870         efx_oword_t reg;
1871         int count;
1872
1873         if (falcon_rev(efx) < FALCON_REV_B0) {
1874                 /* It's not safe to use GLB_CTL_REG to reset the
1875                  * macs, so instead use the internal MAC resets
1876                  */
1877                 if (!EFX_IS10G(efx)) {
1878                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1879                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1880                         udelay(1000);
1881
1882                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1883                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1884                         udelay(1000);
1885                         return 0;
1886                 } else {
1887                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1888                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1889
1890                         for (count = 0; count < 10000; count++) {
1891                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1892                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1893                                     0)
1894                                         return 0;
1895                                 udelay(10);
1896                         }
1897
1898                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1899                         return -ETIMEDOUT;
1900                 }
1901         }
1902
1903         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1904          * the drain sequence with the statistics fetch */
1905         efx_stats_disable(efx);
1906
1907         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1908         EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1909         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1910
1911         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1912         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1913         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1914         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1915         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1916
1917         count = 0;
1918         while (1) {
1919                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1920                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1921                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1922                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1923                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1924                                 count);
1925                         break;
1926                 }
1927                 if (count > 20) {
1928                         EFX_ERR(efx, "MAC reset failed\n");
1929                         break;
1930                 }
1931                 count++;
1932                 udelay(10);
1933         }
1934
1935         efx_stats_enable(efx);
1936
1937         /* If we've reset the EM block and the link is up, then
1938          * we'll have to kick the XAUI link so the PHY can recover */
1939         if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1940                 falcon_reset_xaui(efx);
1941
1942         return 0;
1943 }
1944
1945 void falcon_drain_tx_fifo(struct efx_nic *efx)
1946 {
1947         efx_oword_t reg;
1948
1949         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1950             (efx->loopback_mode != LOOPBACK_NONE))
1951                 return;
1952
1953         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1954         /* There is no point in draining more than once */
1955         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1956                 return;
1957
1958         falcon_reset_macs(efx);
1959 }
1960
1961 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1962 {
1963         efx_oword_t reg;
1964
1965         if (falcon_rev(efx) < FALCON_REV_B0)
1966                 return;
1967
1968         /* Isolate the MAC -> RX */
1969         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1970         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1971         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1972
1973         if (!efx->link_up)
1974                 falcon_drain_tx_fifo(efx);
1975 }
1976
1977 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1978 {
1979         efx_oword_t reg;
1980         int link_speed;
1981         bool tx_fc;
1982
1983         switch (efx->link_speed) {
1984         case 10000: link_speed = 3; break;
1985         case 1000:  link_speed = 2; break;
1986         case 100:   link_speed = 1; break;
1987         default:    link_speed = 0; break;
1988         }
1989         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1990          * as advertised.  Disable to ensure packets are not
1991          * indefinitely held and TX queue can be flushed at any point
1992          * while the link is down. */
1993         EFX_POPULATE_OWORD_5(reg,
1994                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1995                              FRF_AB_MAC_BCAD_ACPT, 1,
1996                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
1997                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1998                              FRF_AB_MAC_SPEED, link_speed);
1999         /* On B0, MAC backpressure can be disabled and packets get
2000          * discarded. */
2001         if (falcon_rev(efx) >= FALCON_REV_B0) {
2002                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
2003                                     !efx->link_up);
2004         }
2005
2006         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
2007
2008         /* Restore the multicast hash registers. */
2009         falcon_set_multicast_hash(efx);
2010
2011         /* Transmission of pause frames when RX crosses the threshold is
2012          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2013          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2014         tx_fc = !!(efx->link_fc & EFX_FC_TX);
2015         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2016         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2017
2018         /* Unisolate the MAC -> RX */
2019         if (falcon_rev(efx) >= FALCON_REV_B0)
2020                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2021         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2022 }
2023
2024 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2025 {
2026         efx_oword_t reg;
2027         u32 *dma_done;
2028         int i;
2029
2030         if (disable_dma_stats)
2031                 return 0;
2032
2033         /* Statistics fetch will fail if the MAC is in TX drain */
2034         if (falcon_rev(efx) >= FALCON_REV_B0) {
2035                 efx_oword_t temp;
2036                 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2037                 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2038                         return 0;
2039         }
2040
2041         dma_done = (efx->stats_buffer.addr + done_offset);
2042         *dma_done = FALCON_STATS_NOT_DONE;
2043         wmb(); /* ensure done flag is clear */
2044
2045         /* Initiate DMA transfer of stats */
2046         EFX_POPULATE_OWORD_2(reg,
2047                              FRF_AB_MAC_STAT_DMA_CMD, 1,
2048                              FRF_AB_MAC_STAT_DMA_ADR,
2049                              efx->stats_buffer.dma_addr);
2050         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2051
2052         /* Wait for transfer to complete */
2053         for (i = 0; i < 400; i++) {
2054                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2055                         rmb(); /* Ensure the stats are valid. */
2056                         return 0;
2057                 }
2058                 udelay(10);
2059         }
2060
2061         EFX_ERR(efx, "timed out waiting for statistics\n");
2062         return -ETIMEDOUT;
2063 }
2064
2065 /**************************************************************************
2066  *
2067  * PHY access via GMII
2068  *
2069  **************************************************************************
2070  */
2071
2072 /* Wait for GMII access to complete */
2073 static int falcon_gmii_wait(struct efx_nic *efx)
2074 {
2075         efx_dword_t md_stat;
2076         int count;
2077
2078         /* wait upto 50ms - taken max from datasheet */
2079         for (count = 0; count < 5000; count++) {
2080                 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2081                 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2082                         if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2083                             EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2084                                 EFX_ERR(efx, "error from GMII access "
2085                                         EFX_DWORD_FMT"\n",
2086                                         EFX_DWORD_VAL(md_stat));
2087                                 return -EIO;
2088                         }
2089                         return 0;
2090                 }
2091                 udelay(10);
2092         }
2093         EFX_ERR(efx, "timed out waiting for GMII\n");
2094         return -ETIMEDOUT;
2095 }
2096
2097 /* Write an MDIO register of a PHY connected to Falcon. */
2098 static int falcon_mdio_write(struct net_device *net_dev,
2099                              int prtad, int devad, u16 addr, u16 value)
2100 {
2101         struct efx_nic *efx = netdev_priv(net_dev);
2102         efx_oword_t reg;
2103         int rc;
2104
2105         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2106                     prtad, devad, addr, value);
2107
2108         spin_lock_bh(&efx->phy_lock);
2109
2110         /* Check MDIO not currently being accessed */
2111         rc = falcon_gmii_wait(efx);
2112         if (rc)
2113                 goto out;
2114
2115         /* Write the address/ID register */
2116         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2117         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2118
2119         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2120                              FRF_AB_MD_DEV_ADR, devad);
2121         efx_writeo(efx, &reg, FR_AB_MD_ID);
2122
2123         /* Write data */
2124         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2125         efx_writeo(efx, &reg, FR_AB_MD_TXD);
2126
2127         EFX_POPULATE_OWORD_2(reg,
2128                              FRF_AB_MD_WRC, 1,
2129                              FRF_AB_MD_GC, 0);
2130         efx_writeo(efx, &reg, FR_AB_MD_CS);
2131
2132         /* Wait for data to be written */
2133         rc = falcon_gmii_wait(efx);
2134         if (rc) {
2135                 /* Abort the write operation */
2136                 EFX_POPULATE_OWORD_2(reg,
2137                                      FRF_AB_MD_WRC, 0,
2138                                      FRF_AB_MD_GC, 1);
2139                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2140                 udelay(10);
2141         }
2142
2143  out:
2144         spin_unlock_bh(&efx->phy_lock);
2145         return rc;
2146 }
2147
2148 /* Read an MDIO register of a PHY connected to Falcon. */
2149 static int falcon_mdio_read(struct net_device *net_dev,
2150                             int prtad, int devad, u16 addr)
2151 {
2152         struct efx_nic *efx = netdev_priv(net_dev);
2153         efx_oword_t reg;
2154         int rc;
2155
2156         spin_lock_bh(&efx->phy_lock);
2157
2158         /* Check MDIO not currently being accessed */
2159         rc = falcon_gmii_wait(efx);
2160         if (rc)
2161                 goto out;
2162
2163         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2164         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2165
2166         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2167                              FRF_AB_MD_DEV_ADR, devad);
2168         efx_writeo(efx, &reg, FR_AB_MD_ID);
2169
2170         /* Request data to be read */
2171         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2172         efx_writeo(efx, &reg, FR_AB_MD_CS);
2173
2174         /* Wait for data to become available */
2175         rc = falcon_gmii_wait(efx);
2176         if (rc == 0) {
2177                 efx_reado(efx, &reg, FR_AB_MD_RXD);
2178                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2179                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2180                             prtad, devad, addr, rc);
2181         } else {
2182                 /* Abort the read operation */
2183                 EFX_POPULATE_OWORD_2(reg,
2184                                      FRF_AB_MD_RIC, 0,
2185                                      FRF_AB_MD_GC, 1);
2186                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2187
2188                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2189                         prtad, devad, addr, rc);
2190         }
2191
2192  out:
2193         spin_unlock_bh(&efx->phy_lock);
2194         return rc;
2195 }
2196
2197 static int falcon_probe_phy(struct efx_nic *efx)
2198 {
2199         switch (efx->phy_type) {
2200         case PHY_TYPE_SFX7101:
2201                 efx->phy_op = &falcon_sfx7101_phy_ops;
2202                 break;
2203         case PHY_TYPE_SFT9001A:
2204         case PHY_TYPE_SFT9001B:
2205                 efx->phy_op = &falcon_sft9001_phy_ops;
2206                 break;
2207         case PHY_TYPE_QT2022C2:
2208         case PHY_TYPE_QT2025C:
2209                 efx->phy_op = &falcon_xfp_phy_ops;
2210                 break;
2211         default:
2212                 EFX_ERR(efx, "Unknown PHY type %d\n",
2213                         efx->phy_type);
2214                 return -1;
2215         }
2216
2217         if (efx->phy_op->macs & EFX_XMAC)
2218                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2219                                         (1 << LOOPBACK_XGXS) |
2220                                         (1 << LOOPBACK_XAUI));
2221         if (efx->phy_op->macs & EFX_GMAC)
2222                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2223         efx->loopback_modes |= efx->phy_op->loopbacks;
2224
2225         return 0;
2226 }
2227
2228 int falcon_switch_mac(struct efx_nic *efx)
2229 {
2230         struct efx_mac_operations *old_mac_op = efx->mac_op;
2231         efx_oword_t nic_stat;
2232         unsigned strap_val;
2233         int rc = 0;
2234
2235         /* Don't try to fetch MAC stats while we're switching MACs */
2236         efx_stats_disable(efx);
2237
2238         /* Internal loopbacks override the phy speed setting */
2239         if (efx->loopback_mode == LOOPBACK_GMAC) {
2240                 efx->link_speed = 1000;
2241                 efx->link_fd = true;
2242         } else if (LOOPBACK_INTERNAL(efx)) {
2243                 efx->link_speed = 10000;
2244                 efx->link_fd = true;
2245         }
2246
2247         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2248         efx->mac_op = (EFX_IS10G(efx) ?
2249                        &falcon_xmac_operations : &falcon_gmac_operations);
2250
2251         /* Always push the NIC_STAT_REG setting even if the mac hasn't
2252          * changed, because this function is run post online reset */
2253         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2254         strap_val = EFX_IS10G(efx) ? 5 : 3;
2255         if (falcon_rev(efx) >= FALCON_REV_B0) {
2256                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2257                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2258                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2259         } else {
2260                 /* Falcon A1 does not support 1G/10G speed switching
2261                  * and must not be used with a PHY that does. */
2262                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2263                        strap_val);
2264         }
2265
2266         if (old_mac_op == efx->mac_op)
2267                 goto out;
2268
2269         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2270         /* Not all macs support a mac-level link state */
2271         efx->mac_up = true;
2272
2273         rc = falcon_reset_macs(efx);
2274 out:
2275         efx_stats_enable(efx);
2276         return rc;
2277 }
2278
2279 /* This call is responsible for hooking in the MAC and PHY operations */
2280 int falcon_probe_port(struct efx_nic *efx)
2281 {
2282         int rc;
2283
2284         /* Hook in PHY operations table */
2285         rc = falcon_probe_phy(efx);
2286         if (rc)
2287                 return rc;
2288
2289         /* Set up MDIO structure for PHY */
2290         efx->mdio.mmds = efx->phy_op->mmds;
2291         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2292         efx->mdio.mdio_read = falcon_mdio_read;
2293         efx->mdio.mdio_write = falcon_mdio_write;
2294
2295         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2296         if (falcon_rev(efx) >= FALCON_REV_B0)
2297                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2298         else
2299                 efx->wanted_fc = EFX_FC_RX;
2300
2301         /* Allocate buffer for stats */
2302         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2303                                  FALCON_MAC_STATS_SIZE);
2304         if (rc)
2305                 return rc;
2306         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2307                 (u64)efx->stats_buffer.dma_addr,
2308                 efx->stats_buffer.addr,
2309                 (u64)virt_to_phys(efx->stats_buffer.addr));
2310
2311         return 0;
2312 }
2313
2314 void falcon_remove_port(struct efx_nic *efx)
2315 {
2316         falcon_free_buffer(efx, &efx->stats_buffer);
2317 }
2318
2319 /**************************************************************************
2320  *
2321  * Multicast filtering
2322  *
2323  **************************************************************************
2324  */
2325
2326 void falcon_set_multicast_hash(struct efx_nic *efx)
2327 {
2328         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2329
2330         /* Broadcast packets go through the multicast hash filter.
2331          * ether_crc_le() of the broadcast address is 0xbe2612ff
2332          * so we always add bit 0xff to the mask.
2333          */
2334         set_bit_le(0xff, mc_hash->byte);
2335
2336         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2337         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2338 }
2339
2340
2341 /**************************************************************************
2342  *
2343  * Falcon test code
2344  *
2345  **************************************************************************/
2346
2347 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2348 {
2349         struct falcon_nvconfig *nvconfig;
2350         struct efx_spi_device *spi;
2351         void *region;
2352         int rc, magic_num, struct_ver;
2353         __le16 *word, *limit;
2354         u32 csum;
2355
2356         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2357         if (!spi)
2358                 return -EINVAL;
2359
2360         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2361         if (!region)
2362                 return -ENOMEM;
2363         nvconfig = region + FALCON_NVCONFIG_OFFSET;
2364
2365         mutex_lock(&efx->spi_lock);
2366         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2367         mutex_unlock(&efx->spi_lock);
2368         if (rc) {
2369                 EFX_ERR(efx, "Failed to read %s\n",
2370                         efx->spi_flash ? "flash" : "EEPROM");
2371                 rc = -EIO;
2372                 goto out;
2373         }
2374
2375         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2376         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2377
2378         rc = -EINVAL;
2379         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2380                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2381                 goto out;
2382         }
2383         if (struct_ver < 2) {
2384                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2385                 goto out;
2386         } else if (struct_ver < 4) {
2387                 word = &nvconfig->board_magic_num;
2388                 limit = (__le16 *) (nvconfig + 1);
2389         } else {
2390                 word = region;
2391                 limit = region + FALCON_NVCONFIG_END;
2392         }
2393         for (csum = 0; word < limit; ++word)
2394                 csum += le16_to_cpu(*word);
2395
2396         if (~csum & 0xffff) {
2397                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2398                 goto out;
2399         }
2400
2401         rc = 0;
2402         if (nvconfig_out)
2403                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2404
2405  out:
2406         kfree(region);
2407         return rc;
2408 }
2409
2410 /* Registers tested in the falcon register test */
2411 static struct {
2412         unsigned address;
2413         efx_oword_t mask;
2414 } efx_test_registers[] = {
2415         { FR_AZ_ADR_REGION,
2416           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2417         { FR_AZ_RX_CFG,
2418           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2419         { FR_AZ_TX_CFG,
2420           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2421         { FR_AZ_TX_RESERVED,
2422           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2423         { FR_AB_MAC_CTRL,
2424           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2425         { FR_AZ_SRM_TX_DC_CFG,
2426           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2427         { FR_AZ_RX_DC_CFG,
2428           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2429         { FR_AZ_RX_DC_PF_WM,
2430           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2431         { FR_BZ_DP_CTRL,
2432           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2433         { FR_AB_GM_CFG2,
2434           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2435         { FR_AB_GMF_CFG0,
2436           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2437         { FR_AB_XM_GLB_CFG,
2438           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2439         { FR_AB_XM_TX_CFG,
2440           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2441         { FR_AB_XM_RX_CFG,
2442           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2443         { FR_AB_XM_RX_PARAM,
2444           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2445         { FR_AB_XM_FC,
2446           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2447         { FR_AB_XM_ADR_LO,
2448           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2449         { FR_AB_XX_SD_CTL,
2450           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2451 };
2452
2453 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2454                                      const efx_oword_t *mask)
2455 {
2456         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2457                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2458 }
2459
2460 int falcon_test_registers(struct efx_nic *efx)
2461 {
2462         unsigned address = 0, i, j;
2463         efx_oword_t mask, imask, original, reg, buf;
2464
2465         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2466         WARN_ON(!LOOPBACK_INTERNAL(efx));
2467
2468         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2469                 address = efx_test_registers[i].address;
2470                 mask = imask = efx_test_registers[i].mask;
2471                 EFX_INVERT_OWORD(imask);
2472
2473                 efx_reado(efx, &original, address);
2474
2475                 /* bit sweep on and off */
2476                 for (j = 0; j < 128; j++) {
2477                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2478                                 continue;
2479
2480                         /* Test this testable bit can be set in isolation */
2481                         EFX_AND_OWORD(reg, original, mask);
2482                         EFX_SET_OWORD32(reg, j, j, 1);
2483
2484                         efx_writeo(efx, &reg, address);
2485                         efx_reado(efx, &buf, address);
2486
2487                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2488                                 goto fail;
2489
2490                         /* Test this testable bit can be cleared in isolation */
2491                         EFX_OR_OWORD(reg, original, mask);
2492                         EFX_SET_OWORD32(reg, j, j, 0);
2493
2494                         efx_writeo(efx, &reg, address);
2495                         efx_reado(efx, &buf, address);
2496
2497                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2498                                 goto fail;
2499                 }
2500
2501                 efx_writeo(efx, &original, address);
2502         }
2503
2504         return 0;
2505
2506 fail:
2507         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2508                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2509                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2510         return -EIO;
2511 }
2512
2513 /**************************************************************************
2514  *
2515  * Device reset
2516  *
2517  **************************************************************************
2518  */
2519
2520 /* Resets NIC to known state.  This routine must be called in process
2521  * context and is allowed to sleep. */
2522 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2523 {
2524         struct falcon_nic_data *nic_data = efx->nic_data;
2525         efx_oword_t glb_ctl_reg_ker;
2526         int rc;
2527
2528         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2529
2530         /* Initiate device reset */
2531         if (method == RESET_TYPE_WORLD) {
2532                 rc = pci_save_state(efx->pci_dev);
2533                 if (rc) {
2534                         EFX_ERR(efx, "failed to backup PCI state of primary "
2535                                 "function prior to hardware reset\n");
2536                         goto fail1;
2537                 }
2538                 if (FALCON_IS_DUAL_FUNC(efx)) {
2539                         rc = pci_save_state(nic_data->pci_dev2);
2540                         if (rc) {
2541                                 EFX_ERR(efx, "failed to backup PCI state of "
2542                                         "secondary function prior to "
2543                                         "hardware reset\n");
2544                                 goto fail2;
2545                         }
2546                 }
2547
2548                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2549                                      FRF_AB_EXT_PHY_RST_DUR,
2550                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2551                                      FRF_AB_SWRST, 1);
2552         } else {
2553                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2554                                      /* exclude PHY from "invisible" reset */
2555                                      FRF_AB_EXT_PHY_RST_CTL,
2556                                      method == RESET_TYPE_INVISIBLE,
2557                                      /* exclude EEPROM/flash and PCIe */
2558                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
2559                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2560                                      FRF_AB_PCIE_SD_RST_CTL, 1,
2561                                      FRF_AB_EE_RST_CTL, 1,
2562                                      FRF_AB_EXT_PHY_RST_DUR,
2563                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2564                                      FRF_AB_SWRST, 1);
2565         }
2566         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2567
2568         EFX_LOG(efx, "waiting for hardware reset\n");
2569         schedule_timeout_uninterruptible(HZ / 20);
2570
2571         /* Restore PCI configuration if needed */
2572         if (method == RESET_TYPE_WORLD) {
2573                 if (FALCON_IS_DUAL_FUNC(efx)) {
2574                         rc = pci_restore_state(nic_data->pci_dev2);
2575                         if (rc) {
2576                                 EFX_ERR(efx, "failed to restore PCI config for "
2577                                         "the secondary function\n");
2578                                 goto fail3;
2579                         }
2580                 }
2581                 rc = pci_restore_state(efx->pci_dev);
2582                 if (rc) {
2583                         EFX_ERR(efx, "failed to restore PCI config for the "
2584                                 "primary function\n");
2585                         goto fail4;
2586                 }
2587                 EFX_LOG(efx, "successfully restored PCI config\n");
2588         }
2589
2590         /* Assert that reset complete */
2591         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2592         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2593                 rc = -ETIMEDOUT;
2594                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2595                 goto fail5;
2596         }
2597         EFX_LOG(efx, "hardware reset complete\n");
2598
2599         return 0;
2600
2601         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2602 fail2:
2603 fail3:
2604         pci_restore_state(efx->pci_dev);
2605 fail1:
2606 fail4:
2607 fail5:
2608         return rc;
2609 }
2610
2611 /* Zeroes out the SRAM contents.  This routine must be called in
2612  * process context and is allowed to sleep.
2613  */
2614 static int falcon_reset_sram(struct efx_nic *efx)
2615 {
2616         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2617         int count;
2618
2619         /* Set the SRAM wake/sleep GPIO appropriately. */
2620         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2621         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2622         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2623         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2624
2625         /* Initiate SRAM reset */
2626         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2627                              FRF_AZ_SRM_INIT_EN, 1,
2628                              FRF_AZ_SRM_NB_SZ, 0);
2629         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2630
2631         /* Wait for SRAM reset to complete */
2632         count = 0;
2633         do {
2634                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2635
2636                 /* SRAM reset is slow; expect around 16ms */
2637                 schedule_timeout_uninterruptible(HZ / 50);
2638
2639                 /* Check for reset complete */
2640                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2641                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2642                         EFX_LOG(efx, "SRAM reset complete\n");
2643
2644                         return 0;
2645                 }
2646         } while (++count < 20); /* wait upto 0.4 sec */
2647
2648         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2649         return -ETIMEDOUT;
2650 }
2651
2652 static int falcon_spi_device_init(struct efx_nic *efx,
2653                                   struct efx_spi_device **spi_device_ret,
2654                                   unsigned int device_id, u32 device_type)
2655 {
2656         struct efx_spi_device *spi_device;
2657
2658         if (device_type != 0) {
2659                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2660                 if (!spi_device)
2661                         return -ENOMEM;
2662                 spi_device->device_id = device_id;
2663                 spi_device->size =
2664                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2665                 spi_device->addr_len =
2666                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2667                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2668                                              spi_device->addr_len == 1);
2669                 spi_device->erase_command =
2670                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2671                 spi_device->erase_size =
2672                         1 << SPI_DEV_TYPE_FIELD(device_type,
2673                                                 SPI_DEV_TYPE_ERASE_SIZE);
2674                 spi_device->block_size =
2675                         1 << SPI_DEV_TYPE_FIELD(device_type,
2676                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2677
2678                 spi_device->efx = efx;
2679         } else {
2680                 spi_device = NULL;
2681         }
2682
2683         kfree(*spi_device_ret);
2684         *spi_device_ret = spi_device;
2685         return 0;
2686 }
2687
2688
2689 static void falcon_remove_spi_devices(struct efx_nic *efx)
2690 {
2691         kfree(efx->spi_eeprom);
2692         efx->spi_eeprom = NULL;
2693         kfree(efx->spi_flash);
2694         efx->spi_flash = NULL;
2695 }
2696
2697 /* Extract non-volatile configuration */
2698 static int falcon_probe_nvconfig(struct efx_nic *efx)
2699 {
2700         struct falcon_nvconfig *nvconfig;
2701         int board_rev;
2702         int rc;
2703
2704         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2705         if (!nvconfig)
2706                 return -ENOMEM;
2707
2708         rc = falcon_read_nvram(efx, nvconfig);
2709         if (rc == -EINVAL) {
2710                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2711                 efx->phy_type = PHY_TYPE_NONE;
2712                 efx->mdio.prtad = MDIO_PRTAD_NONE;
2713                 board_rev = 0;
2714                 rc = 0;
2715         } else if (rc) {
2716                 goto fail1;
2717         } else {
2718                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2719                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2720
2721                 efx->phy_type = v2->port0_phy_type;
2722                 efx->mdio.prtad = v2->port0_phy_addr;
2723                 board_rev = le16_to_cpu(v2->board_revision);
2724
2725                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2726                         rc = falcon_spi_device_init(
2727                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2728                                 le32_to_cpu(v3->spi_device_type
2729                                             [FFE_AB_SPI_DEVICE_FLASH]));
2730                         if (rc)
2731                                 goto fail2;
2732                         rc = falcon_spi_device_init(
2733                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2734                                 le32_to_cpu(v3->spi_device_type
2735                                             [FFE_AB_SPI_DEVICE_EEPROM]));
2736                         if (rc)
2737                                 goto fail2;
2738                 }
2739         }
2740
2741         /* Read the MAC addresses */
2742         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2743
2744         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2745
2746         falcon_probe_board(efx, board_rev);
2747
2748         kfree(nvconfig);
2749         return 0;
2750
2751  fail2:
2752         falcon_remove_spi_devices(efx);
2753  fail1:
2754         kfree(nvconfig);
2755         return rc;
2756 }
2757
2758 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2759  * count, port speed).  Set workaround and feature flags accordingly.
2760  */
2761 static int falcon_probe_nic_variant(struct efx_nic *efx)
2762 {
2763         efx_oword_t altera_build;
2764         efx_oword_t nic_stat;
2765
2766         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2767         if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2768                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2769                 return -ENODEV;
2770         }
2771
2772         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2773
2774         switch (falcon_rev(efx)) {
2775         case FALCON_REV_A0:
2776         case 0xff:
2777                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2778                 return -ENODEV;
2779
2780         case FALCON_REV_A1:
2781                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2782                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2783                         return -ENODEV;
2784                 }
2785                 break;
2786
2787         case FALCON_REV_B0:
2788                 break;
2789
2790         default:
2791                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2792                 return -ENODEV;
2793         }
2794
2795         /* Initial assumed speed */
2796         efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2797
2798         return 0;
2799 }
2800
2801 /* Probe all SPI devices on the NIC */
2802 static void falcon_probe_spi_devices(struct efx_nic *efx)
2803 {
2804         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2805         int boot_dev;
2806
2807         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2808         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2809         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2810
2811         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2812                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2813                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2814                 EFX_LOG(efx, "Booted from %s\n",
2815                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2816         } else {
2817                 /* Disable VPD and set clock dividers to safe
2818                  * values for initial programming. */
2819                 boot_dev = -1;
2820                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2821                         " setting SPI config\n");
2822                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2823                                      /* 125 MHz / 7 ~= 20 MHz */
2824                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2825                                      /* 125 MHz / 63 ~= 2 MHz */
2826                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2827                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2828         }
2829
2830         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2831                 falcon_spi_device_init(efx, &efx->spi_flash,
2832                                        FFE_AB_SPI_DEVICE_FLASH,
2833                                        default_flash_type);
2834         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2835                 falcon_spi_device_init(efx, &efx->spi_eeprom,
2836                                        FFE_AB_SPI_DEVICE_EEPROM,
2837                                        large_eeprom_type);
2838 }
2839
2840 int falcon_probe_nic(struct efx_nic *efx)
2841 {
2842         struct falcon_nic_data *nic_data;
2843         int rc;
2844
2845         /* Allocate storage for hardware specific data */
2846         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2847         if (!nic_data)
2848                 return -ENOMEM;
2849         efx->nic_data = nic_data;
2850
2851         /* Determine number of ports etc. */
2852         rc = falcon_probe_nic_variant(efx);
2853         if (rc)
2854                 goto fail1;
2855
2856         /* Probe secondary function if expected */
2857         if (FALCON_IS_DUAL_FUNC(efx)) {
2858                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2859
2860                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2861                                              dev))) {
2862                         if (dev->bus == efx->pci_dev->bus &&
2863                             dev->devfn == efx->pci_dev->devfn + 1) {
2864                                 nic_data->pci_dev2 = dev;
2865                                 break;
2866                         }
2867                 }
2868                 if (!nic_data->pci_dev2) {
2869                         EFX_ERR(efx, "failed to find secondary function\n");
2870                         rc = -ENODEV;
2871                         goto fail2;
2872                 }
2873         }
2874
2875         /* Now we can reset the NIC */
2876         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2877         if (rc) {
2878                 EFX_ERR(efx, "failed to reset NIC\n");
2879                 goto fail3;
2880         }
2881
2882         /* Allocate memory for INT_KER */
2883         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2884         if (rc)
2885                 goto fail4;
2886         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2887
2888         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2889                 (u64)efx->irq_status.dma_addr,
2890                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2891
2892         falcon_probe_spi_devices(efx);
2893
2894         /* Read in the non-volatile configuration */
2895         rc = falcon_probe_nvconfig(efx);
2896         if (rc)
2897                 goto fail5;
2898
2899         /* Initialise I2C adapter */
2900         efx->i2c_adap.owner = THIS_MODULE;
2901         nic_data->i2c_data = falcon_i2c_bit_operations;
2902         nic_data->i2c_data.data = efx;
2903         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2904         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2905         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2906         rc = i2c_bit_add_bus(&efx->i2c_adap);
2907         if (rc)
2908                 goto fail5;
2909
2910         return 0;
2911
2912  fail5:
2913         falcon_remove_spi_devices(efx);
2914         falcon_free_buffer(efx, &efx->irq_status);
2915  fail4:
2916  fail3:
2917         if (nic_data->pci_dev2) {
2918                 pci_dev_put(nic_data->pci_dev2);
2919                 nic_data->pci_dev2 = NULL;
2920         }
2921  fail2:
2922  fail1:
2923         kfree(efx->nic_data);
2924         return rc;
2925 }
2926
2927 static void falcon_init_rx_cfg(struct efx_nic *efx)
2928 {
2929         /* Prior to Siena the RX DMA engine will split each frame at
2930          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2931          * be so large that that never happens. */
2932         const unsigned huge_buf_size = (3 * 4096) >> 5;
2933         /* RX control FIFO thresholds (32 entries) */
2934         const unsigned ctrl_xon_thr = 20;
2935         const unsigned ctrl_xoff_thr = 25;
2936         /* RX data FIFO thresholds (256-byte units; size varies) */
2937         int data_xon_thr = rx_xon_thresh_bytes >> 8;
2938         int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2939         efx_oword_t reg;
2940
2941         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2942         if (falcon_rev(efx) <= FALCON_REV_A1) {
2943                 /* Data FIFO size is 5.5K */
2944                 if (data_xon_thr < 0)
2945                         data_xon_thr = 512 >> 8;
2946                 if (data_xoff_thr < 0)
2947                         data_xoff_thr = 2048 >> 8;
2948                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2949                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2950                                     huge_buf_size);
2951                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2952                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2953                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2954                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2955         } else {
2956                 /* Data FIFO size is 80K; register fields moved */
2957                 if (data_xon_thr < 0)
2958                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2959                 if (data_xoff_thr < 0)
2960                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2961                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2962                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2963                                     huge_buf_size);
2964                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2965                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2966                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2967                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2968                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2969         }
2970         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2971 }
2972
2973 /* This call performs hardware-specific global initialisation, such as
2974  * defining the descriptor cache sizes and number of RSS channels.
2975  * It does not set up any buffers, descriptor rings or event queues.
2976  */
2977 int falcon_init_nic(struct efx_nic *efx)
2978 {
2979         efx_oword_t temp;
2980         int rc;
2981
2982         /* Use on-chip SRAM */
2983         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2984         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2985         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2986
2987         /* Set the source of the GMAC clock */
2988         if (falcon_rev(efx) == FALCON_REV_B0) {
2989                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2990                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2991                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2992         }
2993
2994         rc = falcon_reset_sram(efx);
2995         if (rc)
2996                 return rc;
2997
2998         /* Set positions of descriptor caches in SRAM. */
2999         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
3000         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3001         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3002         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3003
3004         /* Set TX descriptor cache size. */
3005         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3006         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3007         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3008
3009         /* Set RX descriptor cache size.  Set low watermark to size-8, as
3010          * this allows most efficient prefetching.
3011          */
3012         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3013         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3014         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3015         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3016         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3017
3018         /* Clear the parity enables on the TX data fifos as
3019          * they produce false parity errors because of timing issues
3020          */
3021         if (EFX_WORKAROUND_5129(efx)) {
3022                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3023                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3024                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3025         }
3026
3027         /* Enable all the genuinely fatal interrupts.  (They are still
3028          * masked by the overall interrupt mask, controlled by
3029          * falcon_interrupts()).
3030          *
3031          * Note: All other fatal interrupts are enabled
3032          */
3033         EFX_POPULATE_OWORD_3(temp,
3034                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3035                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3036                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3037         EFX_INVERT_OWORD(temp);
3038         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3039
3040         if (EFX_WORKAROUND_7244(efx)) {
3041                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3042                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3043                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3044                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3045                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3046                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3047         }
3048
3049         falcon_setup_rss_indir_table(efx);
3050
3051         /* XXX This is documented only for Falcon A0/A1 */
3052         /* Setup RX.  Wait for descriptor is broken and must
3053          * be disabled.  RXDP recovery shouldn't be needed, but is.
3054          */
3055         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3056         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3057         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3058         if (EFX_WORKAROUND_5583(efx))
3059                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3060         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3061
3062         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3063          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3064          */
3065         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3066         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3067         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3068         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3069         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3070         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3071         /* Enable SW_EV to inherit in char driver - assume harmless here */
3072         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3073         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3074         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3075         /* Squash TX of packets of 16 bytes or less */
3076         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3077                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3078         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3079
3080         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3081          * descriptors (which is bad).
3082          */
3083         efx_reado(efx, &temp, FR_AZ_TX_CFG);
3084         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3085         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3086
3087         falcon_init_rx_cfg(efx);
3088
3089         /* Set destination of both TX and RX Flush events */
3090         if (falcon_rev(efx) >= FALCON_REV_B0) {
3091                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3092                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3093         }
3094
3095         return 0;
3096 }
3097
3098 void falcon_remove_nic(struct efx_nic *efx)
3099 {
3100         struct falcon_nic_data *nic_data = efx->nic_data;
3101         int rc;
3102
3103         /* Remove I2C adapter and clear it in preparation for a retry */
3104         rc = i2c_del_adapter(&efx->i2c_adap);
3105         BUG_ON(rc);
3106         memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3107
3108         falcon_remove_spi_devices(efx);
3109         falcon_free_buffer(efx, &efx->irq_status);
3110
3111         falcon_reset_hw(efx, RESET_TYPE_ALL);
3112
3113         /* Release the second function after the reset */
3114         if (nic_data->pci_dev2) {
3115                 pci_dev_put(nic_data->pci_dev2);
3116                 nic_data->pci_dev2 = NULL;
3117         }
3118
3119         /* Tear down the private nic state */
3120         kfree(efx->nic_data);
3121         efx->nic_data = NULL;
3122 }
3123
3124 void falcon_update_nic_stats(struct efx_nic *efx)
3125 {
3126         efx_oword_t cnt;
3127
3128         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3129         efx->n_rx_nodesc_drop_cnt +=
3130                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3131 }
3132
3133 /**************************************************************************
3134  *
3135  * Revision-dependent attributes used by efx.c
3136  *
3137  **************************************************************************
3138  */
3139
3140 struct efx_nic_type falcon_a_nic_type = {
3141         .mem_bar = 2,
3142         .mem_map_size = 0x20000,
3143         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3144         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3145         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3146         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3147         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3148         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3149         .tx_dma_mask = FALCON_TX_DMA_MASK,
3150         .bug5391_mask = 0xf,
3151         .rx_buffer_padding = 0x24,
3152         .max_interrupt_mode = EFX_INT_MODE_MSI,
3153         .phys_addr_channels = 4,
3154 };
3155
3156 struct efx_nic_type falcon_b_nic_type = {
3157         .mem_bar = 2,
3158         /* Map everything up to and including the RSS indirection
3159          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3160          * requires that they not be mapped.  */
3161         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3162                          FR_BZ_RX_INDIRECTION_TBL_STEP *
3163                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
3164         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3165         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3166         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3167         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3168         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3169         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3170         .tx_dma_mask = FALCON_TX_DMA_MASK,
3171         .bug5391_mask = 0,
3172         .rx_buffer_padding = 0,
3173         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3174         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3175                                    * interrupt handler only supports 32
3176                                    * channels */
3177 };
3178