[PATCH] s2io: init/shutdown fixes
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2 and 3.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  ************************************************************************/
46
47 #include <linux/config.h>
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/errno.h>
51 #include <linux/ioport.h>
52 #include <linux/pci.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/kernel.h>
55 #include <linux/netdevice.h>
56 #include <linux/etherdevice.h>
57 #include <linux/skbuff.h>
58 #include <linux/init.h>
59 #include <linux/delay.h>
60 #include <linux/stddef.h>
61 #include <linux/ioctl.h>
62 #include <linux/timex.h>
63 #include <linux/sched.h>
64 #include <linux/ethtool.h>
65 #include <linux/workqueue.h>
66 #include <linux/if_vlan.h>
67 #include <linux/ip.h>
68 #include <linux/tcp.h>
69 #include <net/tcp.h>
70
71 #include <asm/system.h>
72 #include <asm/uaccess.h>
73 #include <asm/io.h>
74 #include <asm/div64.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.14.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91         int ret;
92
93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96         return ret;
97 }
98
99 /*
100  * Cards with following subsystem_id have a link state indication
101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102  * macro below identifies these cards given the subsystem_id.
103  */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105         (dev_type == XFRAME_I_DEVICE) ?                 \
106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC   1
113 #define LOW     2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116         mac_info_t *mac_control;
117
118         mac_control = &sp->mac_control;
119         if (rxb_size <= rxd_count[sp->rxd_mode])
120                 return PANIC;
121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122                 return  LOW;
123         return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128         "Register test\t(offline)",
129         "Eeprom test\t(offline)",
130         "Link test\t(online)",
131         "RLDRAM test\t(offline)",
132         "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136         {"tmac_frms"},
137         {"tmac_data_octets"},
138         {"tmac_drop_frms"},
139         {"tmac_mcst_frms"},
140         {"tmac_bcst_frms"},
141         {"tmac_pause_ctrl_frms"},
142         {"tmac_ttl_octets"},
143         {"tmac_ucst_frms"},
144         {"tmac_nucst_frms"},
145         {"tmac_any_err_frms"},
146         {"tmac_ttl_less_fb_octets"},
147         {"tmac_vld_ip_octets"},
148         {"tmac_vld_ip"},
149         {"tmac_drop_ip"},
150         {"tmac_icmp"},
151         {"tmac_rst_tcp"},
152         {"tmac_tcp"},
153         {"tmac_udp"},
154         {"rmac_vld_frms"},
155         {"rmac_data_octets"},
156         {"rmac_fcs_err_frms"},
157         {"rmac_drop_frms"},
158         {"rmac_vld_mcst_frms"},
159         {"rmac_vld_bcst_frms"},
160         {"rmac_in_rng_len_err_frms"},
161         {"rmac_out_rng_len_err_frms"},
162         {"rmac_long_frms"},
163         {"rmac_pause_ctrl_frms"},
164         {"rmac_unsup_ctrl_frms"},
165         {"rmac_ttl_octets"},
166         {"rmac_accepted_ucst_frms"},
167         {"rmac_accepted_nucst_frms"},
168         {"rmac_discarded_frms"},
169         {"rmac_drop_events"},
170         {"rmac_ttl_less_fb_octets"},
171         {"rmac_ttl_frms"},
172         {"rmac_usized_frms"},
173         {"rmac_osized_frms"},
174         {"rmac_frag_frms"},
175         {"rmac_jabber_frms"},
176         {"rmac_ttl_64_frms"},
177         {"rmac_ttl_65_127_frms"},
178         {"rmac_ttl_128_255_frms"},
179         {"rmac_ttl_256_511_frms"},
180         {"rmac_ttl_512_1023_frms"},
181         {"rmac_ttl_1024_1518_frms"},
182         {"rmac_ip"},
183         {"rmac_ip_octets"},
184         {"rmac_hdr_err_ip"},
185         {"rmac_drop_ip"},
186         {"rmac_icmp"},
187         {"rmac_tcp"},
188         {"rmac_udp"},
189         {"rmac_err_drp_udp"},
190         {"rmac_xgmii_err_sym"},
191         {"rmac_frms_q0"},
192         {"rmac_frms_q1"},
193         {"rmac_frms_q2"},
194         {"rmac_frms_q3"},
195         {"rmac_frms_q4"},
196         {"rmac_frms_q5"},
197         {"rmac_frms_q6"},
198         {"rmac_frms_q7"},
199         {"rmac_full_q0"},
200         {"rmac_full_q1"},
201         {"rmac_full_q2"},
202         {"rmac_full_q3"},
203         {"rmac_full_q4"},
204         {"rmac_full_q5"},
205         {"rmac_full_q6"},
206         {"rmac_full_q7"},
207         {"rmac_pause_cnt"},
208         {"rmac_xgmii_data_err_cnt"},
209         {"rmac_xgmii_ctrl_err_cnt"},
210         {"rmac_accepted_ip"},
211         {"rmac_err_tcp"},
212         {"rd_req_cnt"},
213         {"new_rd_req_cnt"},
214         {"new_rd_req_rtry_cnt"},
215         {"rd_rtry_cnt"},
216         {"wr_rtry_rd_ack_cnt"},
217         {"wr_req_cnt"},
218         {"new_wr_req_cnt"},
219         {"new_wr_req_rtry_cnt"},
220         {"wr_rtry_cnt"},
221         {"wr_disc_cnt"},
222         {"rd_rtry_wr_ack_cnt"},
223         {"txp_wr_cnt"},
224         {"txd_rd_cnt"},
225         {"txd_wr_cnt"},
226         {"rxd_rd_cnt"},
227         {"rxd_wr_cnt"},
228         {"txf_rd_cnt"},
229         {"rxf_wr_cnt"},
230         {"rmac_ttl_1519_4095_frms"},
231         {"rmac_ttl_4096_8191_frms"},
232         {"rmac_ttl_8192_max_frms"},
233         {"rmac_ttl_gt_max_frms"},
234         {"rmac_osized_alt_frms"},
235         {"rmac_jabber_alt_frms"},
236         {"rmac_gt_max_alt_frms"},
237         {"rmac_vlan_frms"},
238         {"rmac_len_discard"},
239         {"rmac_fcs_discard"},
240         {"rmac_pf_discard"},
241         {"rmac_da_discard"},
242         {"rmac_red_discard"},
243         {"rmac_rts_discard"},
244         {"rmac_ingm_full_discard"},
245         {"link_fault_cnt"},
246         {"\n DRIVER STATISTICS"},
247         {"single_bit_ecc_errs"},
248         {"double_bit_ecc_errs"},
249         {"parity_err_cnt"},
250         {"serious_err_cnt"},
251         {"soft_reset_cnt"},
252         {"fifo_full_cnt"},
253         {"ring_full_cnt"},
254         ("alarm_transceiver_temp_high"),
255         ("alarm_transceiver_temp_low"),
256         ("alarm_laser_bias_current_high"),
257         ("alarm_laser_bias_current_low"),
258         ("alarm_laser_output_power_high"),
259         ("alarm_laser_output_power_low"),
260         ("warn_transceiver_temp_high"),
261         ("warn_transceiver_temp_low"),
262         ("warn_laser_bias_current_high"),
263         ("warn_laser_bias_current_low"),
264         ("warn_laser_output_power_high"),
265         ("warn_laser_output_power_low"),
266         ("lro_aggregated_pkts"),
267         ("lro_flush_both_count"),
268         ("lro_out_of_sequence_pkts"),
269         ("lro_flush_due_to_max_pkts"),
270         ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
280                         init_timer(&timer);                     \
281                         timer.function = handle;                \
282                         timer.data = (unsigned long) arg;       \
283                         mod_timer(&timer, (jiffies + exp))      \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287                                         struct vlan_group *grp)
288 {
289         nic_t *nic = dev->priv;
290         unsigned long flags;
291
292         spin_lock_irqsave(&nic->tx_lock, flags);
293         nic->vlgrp = grp;
294         spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300         nic_t *nic = dev->priv;
301         unsigned long flags;
302
303         spin_lock_irqsave(&nic->tx_lock, flags);
304         if (nic->vlgrp)
305                 nic->vlgrp->vlan_devices[vid] = NULL;
306         spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310  * Constants to be programmed into the Xena's registers, to configure
311  * the XAUI.
312  */
313
314 #define END_SIGN        0x0
315 static const u64 herc_act_dtx_cfg[] = {
316         /* Set address */
317         0x8000051536750000ULL, 0x80000515367500E0ULL,
318         /* Write data */
319         0x8000051536750004ULL, 0x80000515367500E4ULL,
320         /* Set address */
321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322         /* Write data */
323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324         /* Set address */
325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
326         /* Write data */
327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
328         /* Set address */
329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330         /* Write data */
331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332         /* Done */
333         END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337         /* Set address */
338         0x8000051500000000ULL, 0x80000515000000E0ULL,
339         /* Write data */
340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341         /* Set address */
342         0x8001051500000000ULL, 0x80010515000000E0ULL,
343         /* Write data */
344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345         /* Set address */
346         0x8002051500000000ULL, 0x80020515000000E0ULL,
347         /* Write data */
348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349         END_SIGN
350 };
351
352 /*
353  * Constants for Fixing the MacAddress problem seen mostly on
354  * Alpha machines.
355  */
356 static const u64 fix_mac[] = {
357         0x0060000000000000ULL, 0x0060600000000000ULL,
358         0x0040600000000000ULL, 0x0000600000000000ULL,
359         0x0020600000000000ULL, 0x0060600000000000ULL,
360         0x0020600000000000ULL, 0x0060600000000000ULL,
361         0x0020600000000000ULL, 0x0060600000000000ULL,
362         0x0020600000000000ULL, 0x0060600000000000ULL,
363         0x0020600000000000ULL, 0x0060600000000000ULL,
364         0x0020600000000000ULL, 0x0060600000000000ULL,
365         0x0020600000000000ULL, 0x0060600000000000ULL,
366         0x0020600000000000ULL, 0x0060600000000000ULL,
367         0x0020600000000000ULL, 0x0060600000000000ULL,
368         0x0020600000000000ULL, 0x0060600000000000ULL,
369         0x0020600000000000ULL, 0x0000600000000000ULL,
370         0x0040600000000000ULL, 0x0060600000000000ULL,
371         END_SIGN
372 };
373
374 /* Module Loadable parameters. */
375 static unsigned int tx_fifo_num = 1;
376 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
377     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
378 static unsigned int rx_ring_num = 1;
379 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
380     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
381 static unsigned int rts_frm_len[MAX_RX_RINGS] =
382     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
383 static unsigned int rx_ring_mode = 1;
384 static unsigned int use_continuous_tx_intrs = 1;
385 static unsigned int rmac_pause_time = 0x100;
386 static unsigned int mc_pause_threshold_q0q3 = 187;
387 static unsigned int mc_pause_threshold_q4q7 = 187;
388 static unsigned int shared_splits;
389 static unsigned int tmac_util_period = 5;
390 static unsigned int rmac_util_period = 5;
391 static unsigned int bimodal = 0;
392 static unsigned int l3l4hdr_size = 128;
393 #ifndef CONFIG_S2IO_NAPI
394 static unsigned int indicate_max_pkts;
395 #endif
396 /* Frequency of Rx desc syncs expressed as power of 2 */
397 static unsigned int rxsync_frequency = 3;
398 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
399 static unsigned int intr_type = 0;
400 /* Large receive offload feature */
401 static unsigned int lro = 0;
402 /* Max pkts to be aggregated by LRO at one time. If not specified,
403  * aggregation happens until we hit max IP pkt size(64K)
404  */
405 static unsigned int lro_max_pkts = 0xFFFF;
406
407 /*
408  * S2IO device table.
409  * This table lists all the devices that this driver supports.
410  */
411 static struct pci_device_id s2io_tbl[] __devinitdata = {
412         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
413          PCI_ANY_ID, PCI_ANY_ID},
414         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
415          PCI_ANY_ID, PCI_ANY_ID},
416         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
417          PCI_ANY_ID, PCI_ANY_ID},
418         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
419          PCI_ANY_ID, PCI_ANY_ID},
420         {0,}
421 };
422
423 MODULE_DEVICE_TABLE(pci, s2io_tbl);
424
425 static struct pci_driver s2io_driver = {
426       .name = "S2IO",
427       .id_table = s2io_tbl,
428       .probe = s2io_init_nic,
429       .remove = __devexit_p(s2io_rem_nic),
430 };
431
432 /* A simplifier macro used both by init and free shared_mem Fns(). */
433 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
434
435 /**
436  * init_shared_mem - Allocation and Initialization of Memory
437  * @nic: Device private variable.
438  * Description: The function allocates all the memory areas shared
439  * between the NIC and the driver. This includes Tx descriptors,
440  * Rx descriptors and the statistics block.
441  */
442
443 static int init_shared_mem(struct s2io_nic *nic)
444 {
445         u32 size;
446         void *tmp_v_addr, *tmp_v_addr_next;
447         dma_addr_t tmp_p_addr, tmp_p_addr_next;
448         RxD_block_t *pre_rxd_blk = NULL;
449         int i, j, blk_cnt, rx_sz, tx_sz;
450         int lst_size, lst_per_page;
451         struct net_device *dev = nic->dev;
452         unsigned long tmp;
453         buffAdd_t *ba;
454
455         mac_info_t *mac_control;
456         struct config_param *config;
457
458         mac_control = &nic->mac_control;
459         config = &nic->config;
460
461
462         /* Allocation and initialization of TXDLs in FIOFs */
463         size = 0;
464         for (i = 0; i < config->tx_fifo_num; i++) {
465                 size += config->tx_cfg[i].fifo_len;
466         }
467         if (size > MAX_AVAILABLE_TXDS) {
468                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
469                           __FUNCTION__);
470                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
471                 return FAILURE;
472         }
473
474         lst_size = (sizeof(TxD_t) * config->max_txds);
475         tx_sz = lst_size * size;
476         lst_per_page = PAGE_SIZE / lst_size;
477
478         for (i = 0; i < config->tx_fifo_num; i++) {
479                 int fifo_len = config->tx_cfg[i].fifo_len;
480                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
481                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
482                                                           GFP_KERNEL);
483                 if (!mac_control->fifos[i].list_info) {
484                         DBG_PRINT(ERR_DBG,
485                                   "Malloc failed for list_info\n");
486                         return -ENOMEM;
487                 }
488                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
489         }
490         for (i = 0; i < config->tx_fifo_num; i++) {
491                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
492                                                 lst_per_page);
493                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
494                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
495                     config->tx_cfg[i].fifo_len - 1;
496                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
497                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
498                     config->tx_cfg[i].fifo_len - 1;
499                 mac_control->fifos[i].fifo_no = i;
500                 mac_control->fifos[i].nic = nic;
501                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
502
503                 for (j = 0; j < page_num; j++) {
504                         int k = 0;
505                         dma_addr_t tmp_p;
506                         void *tmp_v;
507                         tmp_v = pci_alloc_consistent(nic->pdev,
508                                                      PAGE_SIZE, &tmp_p);
509                         if (!tmp_v) {
510                                 DBG_PRINT(ERR_DBG,
511                                           "pci_alloc_consistent ");
512                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
513                                 return -ENOMEM;
514                         }
515                         /* If we got a zero DMA address(can happen on
516                          * certain platforms like PPC), reallocate.
517                          * Store virtual address of page we don't want,
518                          * to be freed later.
519                          */
520                         if (!tmp_p) {
521                                 mac_control->zerodma_virt_addr = tmp_v;
522                                 DBG_PRINT(INIT_DBG, 
523                                 "%s: Zero DMA address for TxDL. ", dev->name);
524                                 DBG_PRINT(INIT_DBG, 
525                                 "Virtual address %p\n", tmp_v);
526                                 tmp_v = pci_alloc_consistent(nic->pdev,
527                                                      PAGE_SIZE, &tmp_p);
528                                 if (!tmp_v) {
529                                         DBG_PRINT(ERR_DBG,
530                                           "pci_alloc_consistent ");
531                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
532                                         return -ENOMEM;
533                                 }
534                         }
535                         while (k < lst_per_page) {
536                                 int l = (j * lst_per_page) + k;
537                                 if (l == config->tx_cfg[i].fifo_len)
538                                         break;
539                                 mac_control->fifos[i].list_info[l].list_virt_addr =
540                                     tmp_v + (k * lst_size);
541                                 mac_control->fifos[i].list_info[l].list_phy_addr =
542                                     tmp_p + (k * lst_size);
543                                 k++;
544                         }
545                 }
546         }
547
548         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
549         if (!nic->ufo_in_band_v)
550                 return -ENOMEM;
551
552         /* Allocation and initialization of RXDs in Rings */
553         size = 0;
554         for (i = 0; i < config->rx_ring_num; i++) {
555                 if (config->rx_cfg[i].num_rxd %
556                     (rxd_count[nic->rxd_mode] + 1)) {
557                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
558                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
559                                   i);
560                         DBG_PRINT(ERR_DBG, "RxDs per Block");
561                         return FAILURE;
562                 }
563                 size += config->rx_cfg[i].num_rxd;
564                 mac_control->rings[i].block_count =
565                         config->rx_cfg[i].num_rxd /
566                         (rxd_count[nic->rxd_mode] + 1 );
567                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
568                         mac_control->rings[i].block_count;
569         }
570         if (nic->rxd_mode == RXD_MODE_1)
571                 size = (size * (sizeof(RxD1_t)));
572         else
573                 size = (size * (sizeof(RxD3_t)));
574         rx_sz = size;
575
576         for (i = 0; i < config->rx_ring_num; i++) {
577                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
578                 mac_control->rings[i].rx_curr_get_info.offset = 0;
579                 mac_control->rings[i].rx_curr_get_info.ring_len =
580                     config->rx_cfg[i].num_rxd - 1;
581                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
582                 mac_control->rings[i].rx_curr_put_info.offset = 0;
583                 mac_control->rings[i].rx_curr_put_info.ring_len =
584                     config->rx_cfg[i].num_rxd - 1;
585                 mac_control->rings[i].nic = nic;
586                 mac_control->rings[i].ring_no = i;
587
588                 blk_cnt = config->rx_cfg[i].num_rxd /
589                                 (rxd_count[nic->rxd_mode] + 1);
590                 /*  Allocating all the Rx blocks */
591                 for (j = 0; j < blk_cnt; j++) {
592                         rx_block_info_t *rx_blocks;
593                         int l;
594
595                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
596                         size = SIZE_OF_BLOCK; //size is always page size
597                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
598                                                           &tmp_p_addr);
599                         if (tmp_v_addr == NULL) {
600                                 /*
601                                  * In case of failure, free_shared_mem()
602                                  * is called, which should free any
603                                  * memory that was alloced till the
604                                  * failure happened.
605                                  */
606                                 rx_blocks->block_virt_addr = tmp_v_addr;
607                                 return -ENOMEM;
608                         }
609                         memset(tmp_v_addr, 0, size);
610                         rx_blocks->block_virt_addr = tmp_v_addr;
611                         rx_blocks->block_dma_addr = tmp_p_addr;
612                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
613                                                   rxd_count[nic->rxd_mode],
614                                                   GFP_KERNEL);
615                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
616                                 rx_blocks->rxds[l].virt_addr =
617                                         rx_blocks->block_virt_addr +
618                                         (rxd_size[nic->rxd_mode] * l);
619                                 rx_blocks->rxds[l].dma_addr =
620                                         rx_blocks->block_dma_addr +
621                                         (rxd_size[nic->rxd_mode] * l);
622                         }
623                 }
624                 /* Interlinking all Rx Blocks */
625                 for (j = 0; j < blk_cnt; j++) {
626                         tmp_v_addr =
627                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
628                         tmp_v_addr_next =
629                                 mac_control->rings[i].rx_blocks[(j + 1) %
630                                               blk_cnt].block_virt_addr;
631                         tmp_p_addr =
632                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
633                         tmp_p_addr_next =
634                                 mac_control->rings[i].rx_blocks[(j + 1) %
635                                               blk_cnt].block_dma_addr;
636
637                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
638                         pre_rxd_blk->reserved_2_pNext_RxD_block =
639                             (unsigned long) tmp_v_addr_next;
640                         pre_rxd_blk->pNext_RxD_Blk_physical =
641                             (u64) tmp_p_addr_next;
642                 }
643         }
644         if (nic->rxd_mode >= RXD_MODE_3A) {
645                 /*
646                  * Allocation of Storages for buffer addresses in 2BUFF mode
647                  * and the buffers as well.
648                  */
649                 for (i = 0; i < config->rx_ring_num; i++) {
650                         blk_cnt = config->rx_cfg[i].num_rxd /
651                            (rxd_count[nic->rxd_mode]+ 1);
652                         mac_control->rings[i].ba =
653                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
654                                      GFP_KERNEL);
655                         if (!mac_control->rings[i].ba)
656                                 return -ENOMEM;
657                         for (j = 0; j < blk_cnt; j++) {
658                                 int k = 0;
659                                 mac_control->rings[i].ba[j] =
660                                         kmalloc((sizeof(buffAdd_t) *
661                                                 (rxd_count[nic->rxd_mode] + 1)),
662                                                 GFP_KERNEL);
663                                 if (!mac_control->rings[i].ba[j])
664                                         return -ENOMEM;
665                                 while (k != rxd_count[nic->rxd_mode]) {
666                                         ba = &mac_control->rings[i].ba[j][k];
667
668                                         ba->ba_0_org = (void *) kmalloc
669                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
670                                         if (!ba->ba_0_org)
671                                                 return -ENOMEM;
672                                         tmp = (unsigned long)ba->ba_0_org;
673                                         tmp += ALIGN_SIZE;
674                                         tmp &= ~((unsigned long) ALIGN_SIZE);
675                                         ba->ba_0 = (void *) tmp;
676
677                                         ba->ba_1_org = (void *) kmalloc
678                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
679                                         if (!ba->ba_1_org)
680                                                 return -ENOMEM;
681                                         tmp = (unsigned long) ba->ba_1_org;
682                                         tmp += ALIGN_SIZE;
683                                         tmp &= ~((unsigned long) ALIGN_SIZE);
684                                         ba->ba_1 = (void *) tmp;
685                                         k++;
686                                 }
687                         }
688                 }
689         }
690
691         /* Allocation and initialization of Statistics block */
692         size = sizeof(StatInfo_t);
693         mac_control->stats_mem = pci_alloc_consistent
694             (nic->pdev, size, &mac_control->stats_mem_phy);
695
696         if (!mac_control->stats_mem) {
697                 /*
698                  * In case of failure, free_shared_mem() is called, which
699                  * should free any memory that was alloced till the
700                  * failure happened.
701                  */
702                 return -ENOMEM;
703         }
704         mac_control->stats_mem_sz = size;
705
706         tmp_v_addr = mac_control->stats_mem;
707         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
708         memset(tmp_v_addr, 0, size);
709         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
710                   (unsigned long long) tmp_p_addr);
711
712         return SUCCESS;
713 }
714
715 /**
716  * free_shared_mem - Free the allocated Memory
717  * @nic:  Device private variable.
718  * Description: This function is to free all memory locations allocated by
719  * the init_shared_mem() function and return it to the kernel.
720  */
721
722 static void free_shared_mem(struct s2io_nic *nic)
723 {
724         int i, j, blk_cnt, size;
725         void *tmp_v_addr;
726         dma_addr_t tmp_p_addr;
727         mac_info_t *mac_control;
728         struct config_param *config;
729         int lst_size, lst_per_page;
730         struct net_device *dev = nic->dev;
731
732         if (!nic)
733                 return;
734
735         mac_control = &nic->mac_control;
736         config = &nic->config;
737
738         lst_size = (sizeof(TxD_t) * config->max_txds);
739         lst_per_page = PAGE_SIZE / lst_size;
740
741         for (i = 0; i < config->tx_fifo_num; i++) {
742                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
743                                                 lst_per_page);
744                 for (j = 0; j < page_num; j++) {
745                         int mem_blks = (j * lst_per_page);
746                         if (!mac_control->fifos[i].list_info)
747                                 return; 
748                         if (!mac_control->fifos[i].list_info[mem_blks].
749                                  list_virt_addr)
750                                 break;
751                         pci_free_consistent(nic->pdev, PAGE_SIZE,
752                                             mac_control->fifos[i].
753                                             list_info[mem_blks].
754                                             list_virt_addr,
755                                             mac_control->fifos[i].
756                                             list_info[mem_blks].
757                                             list_phy_addr);
758                 }
759                 /* If we got a zero DMA address during allocation,
760                  * free the page now
761                  */
762                 if (mac_control->zerodma_virt_addr) {
763                         pci_free_consistent(nic->pdev, PAGE_SIZE,
764                                             mac_control->zerodma_virt_addr,
765                                             (dma_addr_t)0);
766                         DBG_PRINT(INIT_DBG, 
767                                 "%s: Freeing TxDL with zero DMA addr. ",
768                                 dev->name);
769                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
770                                 mac_control->zerodma_virt_addr);
771                 }
772                 kfree(mac_control->fifos[i].list_info);
773         }
774
775         size = SIZE_OF_BLOCK;
776         for (i = 0; i < config->rx_ring_num; i++) {
777                 blk_cnt = mac_control->rings[i].block_count;
778                 for (j = 0; j < blk_cnt; j++) {
779                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
780                                 block_virt_addr;
781                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
782                                 block_dma_addr;
783                         if (tmp_v_addr == NULL)
784                                 break;
785                         pci_free_consistent(nic->pdev, size,
786                                             tmp_v_addr, tmp_p_addr);
787                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
788                 }
789         }
790
791         if (nic->rxd_mode >= RXD_MODE_3A) {
792                 /* Freeing buffer storage addresses in 2BUFF mode. */
793                 for (i = 0; i < config->rx_ring_num; i++) {
794                         blk_cnt = config->rx_cfg[i].num_rxd /
795                             (rxd_count[nic->rxd_mode] + 1);
796                         for (j = 0; j < blk_cnt; j++) {
797                                 int k = 0;
798                                 if (!mac_control->rings[i].ba[j])
799                                         continue;
800                                 while (k != rxd_count[nic->rxd_mode]) {
801                                         buffAdd_t *ba =
802                                                 &mac_control->rings[i].ba[j][k];
803                                         kfree(ba->ba_0_org);
804                                         kfree(ba->ba_1_org);
805                                         k++;
806                                 }
807                                 kfree(mac_control->rings[i].ba[j]);
808                         }
809                         kfree(mac_control->rings[i].ba);
810                 }
811         }
812
813         if (mac_control->stats_mem) {
814                 pci_free_consistent(nic->pdev,
815                                     mac_control->stats_mem_sz,
816                                     mac_control->stats_mem,
817                                     mac_control->stats_mem_phy);
818         }
819         if (nic->ufo_in_band_v)
820                 kfree(nic->ufo_in_band_v);
821 }
822
823 /**
824  * s2io_verify_pci_mode -
825  */
826
827 static int s2io_verify_pci_mode(nic_t *nic)
828 {
829         XENA_dev_config_t __iomem *bar0 = nic->bar0;
830         register u64 val64 = 0;
831         int     mode;
832
833         val64 = readq(&bar0->pci_mode);
834         mode = (u8)GET_PCI_MODE(val64);
835
836         if ( val64 & PCI_MODE_UNKNOWN_MODE)
837                 return -1;      /* Unknown PCI mode */
838         return mode;
839 }
840
841 #define NEC_VENID   0x1033
842 #define NEC_DEVID   0x0125
843 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
844 {
845         struct pci_dev *tdev = NULL;
846         while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
847                 if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
848                         if (tdev->bus == s2io_pdev->bus->parent)
849                                 return 1;
850                 }
851         }
852         return 0;
853 }
854
855 int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
856 /**
857  * s2io_print_pci_mode -
858  */
859 static int s2io_print_pci_mode(nic_t *nic)
860 {
861         XENA_dev_config_t __iomem *bar0 = nic->bar0;
862         register u64 val64 = 0;
863         int     mode;
864         struct config_param *config = &nic->config;
865
866         val64 = readq(&bar0->pci_mode);
867         mode = (u8)GET_PCI_MODE(val64);
868
869         if ( val64 & PCI_MODE_UNKNOWN_MODE)
870                 return -1;      /* Unknown PCI mode */
871
872         config->bus_speed = bus_speed[mode];
873
874         if (s2io_on_nec_bridge(nic->pdev)) {
875                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
876                                                         nic->dev->name);
877                 return mode;
878         }
879
880         if (val64 & PCI_MODE_32_BITS) {
881                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
882         } else {
883                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
884         }
885
886         switch(mode) {
887                 case PCI_MODE_PCI_33:
888                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
889                         break;
890                 case PCI_MODE_PCI_66:
891                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
892                         break;
893                 case PCI_MODE_PCIX_M1_66:
894                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
895                         break;
896                 case PCI_MODE_PCIX_M1_100:
897                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
898                         break;
899                 case PCI_MODE_PCIX_M1_133:
900                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
901                         break;
902                 case PCI_MODE_PCIX_M2_66:
903                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
904                         break;
905                 case PCI_MODE_PCIX_M2_100:
906                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
907                         break;
908                 case PCI_MODE_PCIX_M2_133:
909                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
910                         break;
911                 default:
912                         return -1;      /* Unsupported bus speed */
913         }
914
915         return mode;
916 }
917
918 /**
919  *  init_nic - Initialization of hardware
920  *  @nic: device peivate variable
921  *  Description: The function sequentially configures every block
922  *  of the H/W from their reset values.
923  *  Return Value:  SUCCESS on success and
924  *  '-1' on failure (endian settings incorrect).
925  */
926
927 static int init_nic(struct s2io_nic *nic)
928 {
929         XENA_dev_config_t __iomem *bar0 = nic->bar0;
930         struct net_device *dev = nic->dev;
931         register u64 val64 = 0;
932         void __iomem *add;
933         u32 time;
934         int i, j;
935         mac_info_t *mac_control;
936         struct config_param *config;
937         int dtx_cnt = 0;
938         unsigned long long mem_share;
939         int mem_size;
940
941         mac_control = &nic->mac_control;
942         config = &nic->config;
943
944         /* to set the swapper controle on the card */
945         if(s2io_set_swapper(nic)) {
946                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
947                 return -1;
948         }
949
950         /*
951          * Herc requires EOI to be removed from reset before XGXS, so..
952          */
953         if (nic->device_type & XFRAME_II_DEVICE) {
954                 val64 = 0xA500000000ULL;
955                 writeq(val64, &bar0->sw_reset);
956                 msleep(500);
957                 val64 = readq(&bar0->sw_reset);
958         }
959
960         /* Remove XGXS from reset state */
961         val64 = 0;
962         writeq(val64, &bar0->sw_reset);
963         msleep(500);
964         val64 = readq(&bar0->sw_reset);
965
966         /*  Enable Receiving broadcasts */
967         add = &bar0->mac_cfg;
968         val64 = readq(&bar0->mac_cfg);
969         val64 |= MAC_RMAC_BCAST_ENABLE;
970         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
971         writel((u32) val64, add);
972         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
973         writel((u32) (val64 >> 32), (add + 4));
974
975         /* Read registers in all blocks */
976         val64 = readq(&bar0->mac_int_mask);
977         val64 = readq(&bar0->mc_int_mask);
978         val64 = readq(&bar0->xgxs_int_mask);
979
980         /*  Set MTU */
981         val64 = dev->mtu;
982         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
983
984         if (nic->device_type & XFRAME_II_DEVICE) {
985                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
986                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
987                                           &bar0->dtx_control, UF);
988                         if (dtx_cnt & 0x1)
989                                 msleep(1); /* Necessary!! */
990                         dtx_cnt++;
991                 }
992         } else {
993                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
994                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
995                                           &bar0->dtx_control, UF);
996                         val64 = readq(&bar0->dtx_control);
997                         dtx_cnt++;
998                 }
999         }
1000
1001         /*  Tx DMA Initialization */
1002         val64 = 0;
1003         writeq(val64, &bar0->tx_fifo_partition_0);
1004         writeq(val64, &bar0->tx_fifo_partition_1);
1005         writeq(val64, &bar0->tx_fifo_partition_2);
1006         writeq(val64, &bar0->tx_fifo_partition_3);
1007
1008
1009         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1010                 val64 |=
1011                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1012                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1013                                     ((i * 32) + 5), 3);
1014
1015                 if (i == (config->tx_fifo_num - 1)) {
1016                         if (i % 2 == 0)
1017                                 i++;
1018                 }
1019
1020                 switch (i) {
1021                 case 1:
1022                         writeq(val64, &bar0->tx_fifo_partition_0);
1023                         val64 = 0;
1024                         break;
1025                 case 3:
1026                         writeq(val64, &bar0->tx_fifo_partition_1);
1027                         val64 = 0;
1028                         break;
1029                 case 5:
1030                         writeq(val64, &bar0->tx_fifo_partition_2);
1031                         val64 = 0;
1032                         break;
1033                 case 7:
1034                         writeq(val64, &bar0->tx_fifo_partition_3);
1035                         break;
1036                 }
1037         }
1038
1039         /*
1040          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1041          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1042          */
1043         if ((nic->device_type == XFRAME_I_DEVICE) &&
1044                 (get_xena_rev_id(nic->pdev) < 4))
1045                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1046
1047         val64 = readq(&bar0->tx_fifo_partition_0);
1048         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1049                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1050
1051         /*
1052          * Initialization of Tx_PA_CONFIG register to ignore packet
1053          * integrity checking.
1054          */
1055         val64 = readq(&bar0->tx_pa_cfg);
1056         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1057             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1058         writeq(val64, &bar0->tx_pa_cfg);
1059
1060         /* Rx DMA intialization. */
1061         val64 = 0;
1062         for (i = 0; i < config->rx_ring_num; i++) {
1063                 val64 |=
1064                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1065                          3);
1066         }
1067         writeq(val64, &bar0->rx_queue_priority);
1068
1069         /*
1070          * Allocating equal share of memory to all the
1071          * configured Rings.
1072          */
1073         val64 = 0;
1074         if (nic->device_type & XFRAME_II_DEVICE)
1075                 mem_size = 32;
1076         else
1077                 mem_size = 64;
1078
1079         for (i = 0; i < config->rx_ring_num; i++) {
1080                 switch (i) {
1081                 case 0:
1082                         mem_share = (mem_size / config->rx_ring_num +
1083                                      mem_size % config->rx_ring_num);
1084                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1085                         continue;
1086                 case 1:
1087                         mem_share = (mem_size / config->rx_ring_num);
1088                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1089                         continue;
1090                 case 2:
1091                         mem_share = (mem_size / config->rx_ring_num);
1092                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1093                         continue;
1094                 case 3:
1095                         mem_share = (mem_size / config->rx_ring_num);
1096                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1097                         continue;
1098                 case 4:
1099                         mem_share = (mem_size / config->rx_ring_num);
1100                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1101                         continue;
1102                 case 5:
1103                         mem_share = (mem_size / config->rx_ring_num);
1104                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1105                         continue;
1106                 case 6:
1107                         mem_share = (mem_size / config->rx_ring_num);
1108                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1109                         continue;
1110                 case 7:
1111                         mem_share = (mem_size / config->rx_ring_num);
1112                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1113                         continue;
1114                 }
1115         }
1116         writeq(val64, &bar0->rx_queue_cfg);
1117
1118         /*
1119          * Filling Tx round robin registers
1120          * as per the number of FIFOs
1121          */
1122         switch (config->tx_fifo_num) {
1123         case 1:
1124                 val64 = 0x0000000000000000ULL;
1125                 writeq(val64, &bar0->tx_w_round_robin_0);
1126                 writeq(val64, &bar0->tx_w_round_robin_1);
1127                 writeq(val64, &bar0->tx_w_round_robin_2);
1128                 writeq(val64, &bar0->tx_w_round_robin_3);
1129                 writeq(val64, &bar0->tx_w_round_robin_4);
1130                 break;
1131         case 2:
1132                 val64 = 0x0000010000010000ULL;
1133                 writeq(val64, &bar0->tx_w_round_robin_0);
1134                 val64 = 0x0100000100000100ULL;
1135                 writeq(val64, &bar0->tx_w_round_robin_1);
1136                 val64 = 0x0001000001000001ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_2);
1138                 val64 = 0x0000010000010000ULL;
1139                 writeq(val64, &bar0->tx_w_round_robin_3);
1140                 val64 = 0x0100000000000000ULL;
1141                 writeq(val64, &bar0->tx_w_round_robin_4);
1142                 break;
1143         case 3:
1144                 val64 = 0x0001000102000001ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_0);
1146                 val64 = 0x0001020000010001ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_1);
1148                 val64 = 0x0200000100010200ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_2);
1150                 val64 = 0x0001000102000001ULL;
1151                 writeq(val64, &bar0->tx_w_round_robin_3);
1152                 val64 = 0x0001020000000000ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_4);
1154                 break;
1155         case 4:
1156                 val64 = 0x0001020300010200ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_0);
1158                 val64 = 0x0100000102030001ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_1);
1160                 val64 = 0x0200010000010203ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_2);
1162                 val64 = 0x0001020001000001ULL;
1163                 writeq(val64, &bar0->tx_w_round_robin_3);
1164                 val64 = 0x0203000100000000ULL;
1165                 writeq(val64, &bar0->tx_w_round_robin_4);
1166                 break;
1167         case 5:
1168                 val64 = 0x0001000203000102ULL;
1169                 writeq(val64, &bar0->tx_w_round_robin_0);
1170                 val64 = 0x0001020001030004ULL;
1171                 writeq(val64, &bar0->tx_w_round_robin_1);
1172                 val64 = 0x0001000203000102ULL;
1173                 writeq(val64, &bar0->tx_w_round_robin_2);
1174                 val64 = 0x0001020001030004ULL;
1175                 writeq(val64, &bar0->tx_w_round_robin_3);
1176                 val64 = 0x0001000000000000ULL;
1177                 writeq(val64, &bar0->tx_w_round_robin_4);
1178                 break;
1179         case 6:
1180                 val64 = 0x0001020304000102ULL;
1181                 writeq(val64, &bar0->tx_w_round_robin_0);
1182                 val64 = 0x0304050001020001ULL;
1183                 writeq(val64, &bar0->tx_w_round_robin_1);
1184                 val64 = 0x0203000100000102ULL;
1185                 writeq(val64, &bar0->tx_w_round_robin_2);
1186                 val64 = 0x0304000102030405ULL;
1187                 writeq(val64, &bar0->tx_w_round_robin_3);
1188                 val64 = 0x0001000200000000ULL;
1189                 writeq(val64, &bar0->tx_w_round_robin_4);
1190                 break;
1191         case 7:
1192                 val64 = 0x0001020001020300ULL;
1193                 writeq(val64, &bar0->tx_w_round_robin_0);
1194                 val64 = 0x0102030400010203ULL;
1195                 writeq(val64, &bar0->tx_w_round_robin_1);
1196                 val64 = 0x0405060001020001ULL;
1197                 writeq(val64, &bar0->tx_w_round_robin_2);
1198                 val64 = 0x0304050000010200ULL;
1199                 writeq(val64, &bar0->tx_w_round_robin_3);
1200                 val64 = 0x0102030000000000ULL;
1201                 writeq(val64, &bar0->tx_w_round_robin_4);
1202                 break;
1203         case 8:
1204                 val64 = 0x0001020300040105ULL;
1205                 writeq(val64, &bar0->tx_w_round_robin_0);
1206                 val64 = 0x0200030106000204ULL;
1207                 writeq(val64, &bar0->tx_w_round_robin_1);
1208                 val64 = 0x0103000502010007ULL;
1209                 writeq(val64, &bar0->tx_w_round_robin_2);
1210                 val64 = 0x0304010002060500ULL;
1211                 writeq(val64, &bar0->tx_w_round_robin_3);
1212                 val64 = 0x0103020400000000ULL;
1213                 writeq(val64, &bar0->tx_w_round_robin_4);
1214                 break;
1215         }
1216
1217         /* Enable Tx FIFO partition 0. */
1218         val64 = readq(&bar0->tx_fifo_partition_0);
1219         val64 |= (TX_FIFO_PARTITION_EN);
1220         writeq(val64, &bar0->tx_fifo_partition_0);
1221
1222         /* Filling the Rx round robin registers as per the
1223          * number of Rings and steering based on QoS.
1224          */
1225         switch (config->rx_ring_num) {
1226         case 1:
1227                 val64 = 0x8080808080808080ULL;
1228                 writeq(val64, &bar0->rts_qos_steering);
1229                 break;
1230         case 2:
1231                 val64 = 0x0000010000010000ULL;
1232                 writeq(val64, &bar0->rx_w_round_robin_0);
1233                 val64 = 0x0100000100000100ULL;
1234                 writeq(val64, &bar0->rx_w_round_robin_1);
1235                 val64 = 0x0001000001000001ULL;
1236                 writeq(val64, &bar0->rx_w_round_robin_2);
1237                 val64 = 0x0000010000010000ULL;
1238                 writeq(val64, &bar0->rx_w_round_robin_3);
1239                 val64 = 0x0100000000000000ULL;
1240                 writeq(val64, &bar0->rx_w_round_robin_4);
1241
1242                 val64 = 0x8080808040404040ULL;
1243                 writeq(val64, &bar0->rts_qos_steering);
1244                 break;
1245         case 3:
1246                 val64 = 0x0001000102000001ULL;
1247                 writeq(val64, &bar0->rx_w_round_robin_0);
1248                 val64 = 0x0001020000010001ULL;
1249                 writeq(val64, &bar0->rx_w_round_robin_1);
1250                 val64 = 0x0200000100010200ULL;
1251                 writeq(val64, &bar0->rx_w_round_robin_2);
1252                 val64 = 0x0001000102000001ULL;
1253                 writeq(val64, &bar0->rx_w_round_robin_3);
1254                 val64 = 0x0001020000000000ULL;
1255                 writeq(val64, &bar0->rx_w_round_robin_4);
1256
1257                 val64 = 0x8080804040402020ULL;
1258                 writeq(val64, &bar0->rts_qos_steering);
1259                 break;
1260         case 4:
1261                 val64 = 0x0001020300010200ULL;
1262                 writeq(val64, &bar0->rx_w_round_robin_0);
1263                 val64 = 0x0100000102030001ULL;
1264                 writeq(val64, &bar0->rx_w_round_robin_1);
1265                 val64 = 0x0200010000010203ULL;
1266                 writeq(val64, &bar0->rx_w_round_robin_2);
1267                 val64 = 0x0001020001000001ULL;  
1268                 writeq(val64, &bar0->rx_w_round_robin_3);
1269                 val64 = 0x0203000100000000ULL;
1270                 writeq(val64, &bar0->rx_w_round_robin_4);
1271
1272                 val64 = 0x8080404020201010ULL;
1273                 writeq(val64, &bar0->rts_qos_steering);
1274                 break;
1275         case 5:
1276                 val64 = 0x0001000203000102ULL;
1277                 writeq(val64, &bar0->rx_w_round_robin_0);
1278                 val64 = 0x0001020001030004ULL;
1279                 writeq(val64, &bar0->rx_w_round_robin_1);
1280                 val64 = 0x0001000203000102ULL;
1281                 writeq(val64, &bar0->rx_w_round_robin_2);
1282                 val64 = 0x0001020001030004ULL;
1283                 writeq(val64, &bar0->rx_w_round_robin_3);
1284                 val64 = 0x0001000000000000ULL;
1285                 writeq(val64, &bar0->rx_w_round_robin_4);
1286
1287                 val64 = 0x8080404020201008ULL;
1288                 writeq(val64, &bar0->rts_qos_steering);
1289                 break;
1290         case 6:
1291                 val64 = 0x0001020304000102ULL;
1292                 writeq(val64, &bar0->rx_w_round_robin_0);
1293                 val64 = 0x0304050001020001ULL;
1294                 writeq(val64, &bar0->rx_w_round_robin_1);
1295                 val64 = 0x0203000100000102ULL;
1296                 writeq(val64, &bar0->rx_w_round_robin_2);
1297                 val64 = 0x0304000102030405ULL;
1298                 writeq(val64, &bar0->rx_w_round_robin_3);
1299                 val64 = 0x0001000200000000ULL;
1300                 writeq(val64, &bar0->rx_w_round_robin_4);
1301
1302                 val64 = 0x8080404020100804ULL;
1303                 writeq(val64, &bar0->rts_qos_steering);
1304                 break;
1305         case 7:
1306                 val64 = 0x0001020001020300ULL;
1307                 writeq(val64, &bar0->rx_w_round_robin_0);
1308                 val64 = 0x0102030400010203ULL;
1309                 writeq(val64, &bar0->rx_w_round_robin_1);
1310                 val64 = 0x0405060001020001ULL;
1311                 writeq(val64, &bar0->rx_w_round_robin_2);
1312                 val64 = 0x0304050000010200ULL;
1313                 writeq(val64, &bar0->rx_w_round_robin_3);
1314                 val64 = 0x0102030000000000ULL;
1315                 writeq(val64, &bar0->rx_w_round_robin_4);
1316
1317                 val64 = 0x8080402010080402ULL;
1318                 writeq(val64, &bar0->rts_qos_steering);
1319                 break;
1320         case 8:
1321                 val64 = 0x0001020300040105ULL;
1322                 writeq(val64, &bar0->rx_w_round_robin_0);
1323                 val64 = 0x0200030106000204ULL;
1324                 writeq(val64, &bar0->rx_w_round_robin_1);
1325                 val64 = 0x0103000502010007ULL;
1326                 writeq(val64, &bar0->rx_w_round_robin_2);
1327                 val64 = 0x0304010002060500ULL;
1328                 writeq(val64, &bar0->rx_w_round_robin_3);
1329                 val64 = 0x0103020400000000ULL;
1330                 writeq(val64, &bar0->rx_w_round_robin_4);
1331
1332                 val64 = 0x8040201008040201ULL;
1333                 writeq(val64, &bar0->rts_qos_steering);
1334                 break;
1335         }
1336
1337         /* UDP Fix */
1338         val64 = 0;
1339         for (i = 0; i < 8; i++)
1340                 writeq(val64, &bar0->rts_frm_len_n[i]);
1341
1342         /* Set the default rts frame length for the rings configured */
1343         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1344         for (i = 0 ; i < config->rx_ring_num ; i++)
1345                 writeq(val64, &bar0->rts_frm_len_n[i]);
1346
1347         /* Set the frame length for the configured rings
1348          * desired by the user
1349          */
1350         for (i = 0; i < config->rx_ring_num; i++) {
1351                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1352                  * specified frame length steering.
1353                  * If the user provides the frame length then program
1354                  * the rts_frm_len register for those values or else
1355                  * leave it as it is.
1356                  */
1357                 if (rts_frm_len[i] != 0) {
1358                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1359                                 &bar0->rts_frm_len_n[i]);
1360                 }
1361         }
1362
1363         /* Program statistics memory */
1364         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1365
1366         if (nic->device_type == XFRAME_II_DEVICE) {
1367                 val64 = STAT_BC(0x320);
1368                 writeq(val64, &bar0->stat_byte_cnt);
1369         }
1370
1371         /*
1372          * Initializing the sampling rate for the device to calculate the
1373          * bandwidth utilization.
1374          */
1375         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1376             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1377         writeq(val64, &bar0->mac_link_util);
1378
1379
1380         /*
1381          * Initializing the Transmit and Receive Traffic Interrupt
1382          * Scheme.
1383          */
1384         /*
1385          * TTI Initialization. Default Tx timer gets us about
1386          * 250 interrupts per sec. Continuous interrupts are enabled
1387          * by default.
1388          */
1389         if (nic->device_type == XFRAME_II_DEVICE) {
1390                 int count = (nic->config.bus_speed * 125)/2;
1391                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1392         } else {
1393
1394                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1395         }
1396         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1397             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1398             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1399                 if (use_continuous_tx_intrs)
1400                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1401         writeq(val64, &bar0->tti_data1_mem);
1402
1403         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1404             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1405             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1406         writeq(val64, &bar0->tti_data2_mem);
1407
1408         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1409         writeq(val64, &bar0->tti_command_mem);
1410
1411         /*
1412          * Once the operation completes, the Strobe bit of the command
1413          * register will be reset. We poll for this particular condition
1414          * We wait for a maximum of 500ms for the operation to complete,
1415          * if it's not complete by then we return error.
1416          */
1417         time = 0;
1418         while (TRUE) {
1419                 val64 = readq(&bar0->tti_command_mem);
1420                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1421                         break;
1422                 }
1423                 if (time > 10) {
1424                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1425                                   dev->name);
1426                         return -1;
1427                 }
1428                 msleep(50);
1429                 time++;
1430         }
1431
1432         if (nic->config.bimodal) {
1433                 int k = 0;
1434                 for (k = 0; k < config->rx_ring_num; k++) {
1435                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1436                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1437                         writeq(val64, &bar0->tti_command_mem);
1438
1439                 /*
1440                  * Once the operation completes, the Strobe bit of the command
1441                  * register will be reset. We poll for this particular condition
1442                  * We wait for a maximum of 500ms for the operation to complete,
1443                  * if it's not complete by then we return error.
1444                 */
1445                         time = 0;
1446                         while (TRUE) {
1447                                 val64 = readq(&bar0->tti_command_mem);
1448                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1449                                         break;
1450                                 }
1451                                 if (time > 10) {
1452                                         DBG_PRINT(ERR_DBG,
1453                                                 "%s: TTI init Failed\n",
1454                                         dev->name);
1455                                         return -1;
1456                                 }
1457                                 time++;
1458                                 msleep(50);
1459                         }
1460                 }
1461         } else {
1462
1463                 /* RTI Initialization */
1464                 if (nic->device_type == XFRAME_II_DEVICE) {
1465                         /*
1466                          * Programmed to generate Apprx 500 Intrs per
1467                          * second
1468                          */
1469                         int count = (nic->config.bus_speed * 125)/4;
1470                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1471                 } else {
1472                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1473                 }
1474                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1475                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1476                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1477
1478                 writeq(val64, &bar0->rti_data1_mem);
1479
1480                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1481                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1482                 if (nic->intr_type == MSI_X)
1483                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1484                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1485                 else
1486                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1487                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1488                 writeq(val64, &bar0->rti_data2_mem);
1489
1490                 for (i = 0; i < config->rx_ring_num; i++) {
1491                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1492                                         | RTI_CMD_MEM_OFFSET(i);
1493                         writeq(val64, &bar0->rti_command_mem);
1494
1495                         /*
1496                          * Once the operation completes, the Strobe bit of the
1497                          * command register will be reset. We poll for this
1498                          * particular condition. We wait for a maximum of 500ms
1499                          * for the operation to complete, if it's not complete
1500                          * by then we return error.
1501                          */
1502                         time = 0;
1503                         while (TRUE) {
1504                                 val64 = readq(&bar0->rti_command_mem);
1505                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1506                                         break;
1507                                 }
1508                                 if (time > 10) {
1509                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1510                                                   dev->name);
1511                                         return -1;
1512                                 }
1513                                 time++;
1514                                 msleep(50);
1515                         }
1516                 }
1517         }
1518
1519         /*
1520          * Initializing proper values as Pause threshold into all
1521          * the 8 Queues on Rx side.
1522          */
1523         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1524         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1525
1526         /* Disable RMAC PAD STRIPPING */
1527         add = &bar0->mac_cfg;
1528         val64 = readq(&bar0->mac_cfg);
1529         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1530         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1531         writel((u32) (val64), add);
1532         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1533         writel((u32) (val64 >> 32), (add + 4));
1534         val64 = readq(&bar0->mac_cfg);
1535
1536         /* Enable FCS stripping by adapter */
1537         add = &bar0->mac_cfg;
1538         val64 = readq(&bar0->mac_cfg);
1539         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1540         if (nic->device_type == XFRAME_II_DEVICE)
1541                 writeq(val64, &bar0->mac_cfg);
1542         else {
1543                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544                 writel((u32) (val64), add);
1545                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546                 writel((u32) (val64 >> 32), (add + 4));
1547         }
1548
1549         /*
1550          * Set the time value to be inserted in the pause frame
1551          * generated by xena.
1552          */
1553         val64 = readq(&bar0->rmac_pause_cfg);
1554         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1555         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1556         writeq(val64, &bar0->rmac_pause_cfg);
1557
1558         /*
1559          * Set the Threshold Limit for Generating the pause frame
1560          * If the amount of data in any Queue exceeds ratio of
1561          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1562          * pause frame is generated
1563          */
1564         val64 = 0;
1565         for (i = 0; i < 4; i++) {
1566                 val64 |=
1567                     (((u64) 0xFF00 | nic->mac_control.
1568                       mc_pause_threshold_q0q3)
1569                      << (i * 2 * 8));
1570         }
1571         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1572
1573         val64 = 0;
1574         for (i = 0; i < 4; i++) {
1575                 val64 |=
1576                     (((u64) 0xFF00 | nic->mac_control.
1577                       mc_pause_threshold_q4q7)
1578                      << (i * 2 * 8));
1579         }
1580         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1581
1582         /*
1583          * TxDMA will stop Read request if the number of read split has
1584          * exceeded the limit pointed by shared_splits
1585          */
1586         val64 = readq(&bar0->pic_control);
1587         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1588         writeq(val64, &bar0->pic_control);
1589
1590         if (nic->config.bus_speed == 266) {
1591                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1592                 writeq(0x0, &bar0->read_retry_delay);
1593                 writeq(0x0, &bar0->write_retry_delay);
1594         }
1595
1596         /*
1597          * Programming the Herc to split every write transaction
1598          * that does not start on an ADB to reduce disconnects.
1599          */
1600         if (nic->device_type == XFRAME_II_DEVICE) {
1601                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1602                 writeq(val64, &bar0->misc_control);
1603                 val64 = readq(&bar0->pic_control2);
1604                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1605                 writeq(val64, &bar0->pic_control2);
1606         }
1607         if (strstr(nic->product_name, "CX4")) {
1608                 val64 = TMAC_AVG_IPG(0x17);
1609                 writeq(val64, &bar0->tmac_avg_ipg);
1610         }
1611
1612         return SUCCESS;
1613 }
1614 #define LINK_UP_DOWN_INTERRUPT          1
1615 #define MAC_RMAC_ERR_TIMER              2
1616
1617 static int s2io_link_fault_indication(nic_t *nic)
1618 {
1619         if (nic->intr_type != INTA)
1620                 return MAC_RMAC_ERR_TIMER;
1621         if (nic->device_type == XFRAME_II_DEVICE)
1622                 return LINK_UP_DOWN_INTERRUPT;
1623         else
1624                 return MAC_RMAC_ERR_TIMER;
1625 }
1626
1627 /**
1628  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1629  *  @nic: device private variable,
1630  *  @mask: A mask indicating which Intr block must be modified and,
1631  *  @flag: A flag indicating whether to enable or disable the Intrs.
1632  *  Description: This function will either disable or enable the interrupts
1633  *  depending on the flag argument. The mask argument can be used to
1634  *  enable/disable any Intr block.
1635  *  Return Value: NONE.
1636  */
1637
1638 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1639 {
1640         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1641         register u64 val64 = 0, temp64 = 0;
1642
1643         /*  Top level interrupt classification */
1644         /*  PIC Interrupts */
1645         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1646                 /*  Enable PIC Intrs in the general intr mask register */
1647                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1648                 if (flag == ENABLE_INTRS) {
1649                         temp64 = readq(&bar0->general_int_mask);
1650                         temp64 &= ~((u64) val64);
1651                         writeq(temp64, &bar0->general_int_mask);
1652                         /*
1653                          * If Hercules adapter enable GPIO otherwise
1654                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1655                          * interrupts for now.
1656                          * TODO
1657                          */
1658                         if (s2io_link_fault_indication(nic) ==
1659                                         LINK_UP_DOWN_INTERRUPT ) {
1660                                 temp64 = readq(&bar0->pic_int_mask);
1661                                 temp64 &= ~((u64) PIC_INT_GPIO);
1662                                 writeq(temp64, &bar0->pic_int_mask);
1663                                 temp64 = readq(&bar0->gpio_int_mask);
1664                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1665                                 writeq(temp64, &bar0->gpio_int_mask);
1666                         } else {
1667                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1668                         }
1669                         /*
1670                          * No MSI Support is available presently, so TTI and
1671                          * RTI interrupts are also disabled.
1672                          */
1673                 } else if (flag == DISABLE_INTRS) {
1674                         /*
1675                          * Disable PIC Intrs in the general
1676                          * intr mask register
1677                          */
1678                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1679                         temp64 = readq(&bar0->general_int_mask);
1680                         val64 |= temp64;
1681                         writeq(val64, &bar0->general_int_mask);
1682                 }
1683         }
1684
1685         /*  DMA Interrupts */
1686         /*  Enabling/Disabling Tx DMA interrupts */
1687         if (mask & TX_DMA_INTR) {
1688                 /* Enable TxDMA Intrs in the general intr mask register */
1689                 val64 = TXDMA_INT_M;
1690                 if (flag == ENABLE_INTRS) {
1691                         temp64 = readq(&bar0->general_int_mask);
1692                         temp64 &= ~((u64) val64);
1693                         writeq(temp64, &bar0->general_int_mask);
1694                         /*
1695                          * Keep all interrupts other than PFC interrupt
1696                          * and PCC interrupt disabled in DMA level.
1697                          */
1698                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1699                                                       TXDMA_PCC_INT_M);
1700                         writeq(val64, &bar0->txdma_int_mask);
1701                         /*
1702                          * Enable only the MISC error 1 interrupt in PFC block
1703                          */
1704                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1705                         writeq(val64, &bar0->pfc_err_mask);
1706                         /*
1707                          * Enable only the FB_ECC error interrupt in PCC block
1708                          */
1709                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1710                         writeq(val64, &bar0->pcc_err_mask);
1711                 } else if (flag == DISABLE_INTRS) {
1712                         /*
1713                          * Disable TxDMA Intrs in the general intr mask
1714                          * register
1715                          */
1716                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1717                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1718                         temp64 = readq(&bar0->general_int_mask);
1719                         val64 |= temp64;
1720                         writeq(val64, &bar0->general_int_mask);
1721                 }
1722         }
1723
1724         /*  Enabling/Disabling Rx DMA interrupts */
1725         if (mask & RX_DMA_INTR) {
1726                 /*  Enable RxDMA Intrs in the general intr mask register */
1727                 val64 = RXDMA_INT_M;
1728                 if (flag == ENABLE_INTRS) {
1729                         temp64 = readq(&bar0->general_int_mask);
1730                         temp64 &= ~((u64) val64);
1731                         writeq(temp64, &bar0->general_int_mask);
1732                         /*
1733                          * All RxDMA block interrupts are disabled for now
1734                          * TODO
1735                          */
1736                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1737                 } else if (flag == DISABLE_INTRS) {
1738                         /*
1739                          * Disable RxDMA Intrs in the general intr mask
1740                          * register
1741                          */
1742                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1743                         temp64 = readq(&bar0->general_int_mask);
1744                         val64 |= temp64;
1745                         writeq(val64, &bar0->general_int_mask);
1746                 }
1747         }
1748
1749         /*  MAC Interrupts */
1750         /*  Enabling/Disabling MAC interrupts */
1751         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1752                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1753                 if (flag == ENABLE_INTRS) {
1754                         temp64 = readq(&bar0->general_int_mask);
1755                         temp64 &= ~((u64) val64);
1756                         writeq(temp64, &bar0->general_int_mask);
1757                         /*
1758                          * All MAC block error interrupts are disabled for now
1759                          * TODO
1760                          */
1761                 } else if (flag == DISABLE_INTRS) {
1762                         /*
1763                          * Disable MAC Intrs in the general intr mask register
1764                          */
1765                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1766                         writeq(DISABLE_ALL_INTRS,
1767                                &bar0->mac_rmac_err_mask);
1768
1769                         temp64 = readq(&bar0->general_int_mask);
1770                         val64 |= temp64;
1771                         writeq(val64, &bar0->general_int_mask);
1772                 }
1773         }
1774
1775         /*  XGXS Interrupts */
1776         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1777                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1778                 if (flag == ENABLE_INTRS) {
1779                         temp64 = readq(&bar0->general_int_mask);
1780                         temp64 &= ~((u64) val64);
1781                         writeq(temp64, &bar0->general_int_mask);
1782                         /*
1783                          * All XGXS block error interrupts are disabled for now
1784                          * TODO
1785                          */
1786                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1787                 } else if (flag == DISABLE_INTRS) {
1788                         /*
1789                          * Disable MC Intrs in the general intr mask register
1790                          */
1791                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1792                         temp64 = readq(&bar0->general_int_mask);
1793                         val64 |= temp64;
1794                         writeq(val64, &bar0->general_int_mask);
1795                 }
1796         }
1797
1798         /*  Memory Controller(MC) interrupts */
1799         if (mask & MC_INTR) {
1800                 val64 = MC_INT_M;
1801                 if (flag == ENABLE_INTRS) {
1802                         temp64 = readq(&bar0->general_int_mask);
1803                         temp64 &= ~((u64) val64);
1804                         writeq(temp64, &bar0->general_int_mask);
1805                         /*
1806                          * Enable all MC Intrs.
1807                          */
1808                         writeq(0x0, &bar0->mc_int_mask);
1809                         writeq(0x0, &bar0->mc_err_mask);
1810                 } else if (flag == DISABLE_INTRS) {
1811                         /*
1812                          * Disable MC Intrs in the general intr mask register
1813                          */
1814                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1815                         temp64 = readq(&bar0->general_int_mask);
1816                         val64 |= temp64;
1817                         writeq(val64, &bar0->general_int_mask);
1818                 }
1819         }
1820
1821
1822         /*  Tx traffic interrupts */
1823         if (mask & TX_TRAFFIC_INTR) {
1824                 val64 = TXTRAFFIC_INT_M;
1825                 if (flag == ENABLE_INTRS) {
1826                         temp64 = readq(&bar0->general_int_mask);
1827                         temp64 &= ~((u64) val64);
1828                         writeq(temp64, &bar0->general_int_mask);
1829                         /*
1830                          * Enable all the Tx side interrupts
1831                          * writing 0 Enables all 64 TX interrupt levels
1832                          */
1833                         writeq(0x0, &bar0->tx_traffic_mask);
1834                 } else if (flag == DISABLE_INTRS) {
1835                         /*
1836                          * Disable Tx Traffic Intrs in the general intr mask
1837                          * register.
1838                          */
1839                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1840                         temp64 = readq(&bar0->general_int_mask);
1841                         val64 |= temp64;
1842                         writeq(val64, &bar0->general_int_mask);
1843                 }
1844         }
1845
1846         /*  Rx traffic interrupts */
1847         if (mask & RX_TRAFFIC_INTR) {
1848                 val64 = RXTRAFFIC_INT_M;
1849                 if (flag == ENABLE_INTRS) {
1850                         temp64 = readq(&bar0->general_int_mask);
1851                         temp64 &= ~((u64) val64);
1852                         writeq(temp64, &bar0->general_int_mask);
1853                         /* writing 0 Enables all 8 RX interrupt levels */
1854                         writeq(0x0, &bar0->rx_traffic_mask);
1855                 } else if (flag == DISABLE_INTRS) {
1856                         /*
1857                          * Disable Rx Traffic Intrs in the general intr mask
1858                          * register.
1859                          */
1860                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1861                         temp64 = readq(&bar0->general_int_mask);
1862                         val64 |= temp64;
1863                         writeq(val64, &bar0->general_int_mask);
1864                 }
1865         }
1866 }
1867
1868 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1869 {
1870         int ret = 0;
1871
1872         if (flag == FALSE) {
1873                 if ((!herc && (rev_id >= 4)) || herc) {
1874                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1875                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1876                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1877                                 ret = 1;
1878                         }
1879                 }else {
1880                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1881                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1882                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1883                                 ret = 1;
1884                         }
1885                 }
1886         } else {
1887                 if ((!herc && (rev_id >= 4)) || herc) {
1888                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1889                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1890                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1891                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1892                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1893                                 ret = 1;
1894                         }
1895                 } else {
1896                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1897                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1898                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1899                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1900                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1901                                 ret = 1;
1902                         }
1903                 }
1904         }
1905
1906         return ret;
1907 }
1908 /**
1909  *  verify_xena_quiescence - Checks whether the H/W is ready
1910  *  @val64 :  Value read from adapter status register.
1911  *  @flag : indicates if the adapter enable bit was ever written once
1912  *  before.
1913  *  Description: Returns whether the H/W is ready to go or not. Depending
1914  *  on whether adapter enable bit was written or not the comparison
1915  *  differs and the calling function passes the input argument flag to
1916  *  indicate this.
1917  *  Return: 1 If xena is quiescence
1918  *          0 If Xena is not quiescence
1919  */
1920
1921 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1922 {
1923         int ret = 0, herc;
1924         u64 tmp64 = ~((u64) val64);
1925         int rev_id = get_xena_rev_id(sp->pdev);
1926
1927         herc = (sp->device_type == XFRAME_II_DEVICE);
1928         if (!
1929             (tmp64 &
1930              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1931               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1932               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1933               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1934               ADAPTER_STATUS_P_PLL_LOCK))) {
1935                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1936         }
1937
1938         return ret;
1939 }
1940
1941 /**
1942  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1943  * @sp: Pointer to device specifc structure
1944  * Description :
1945  * New procedure to clear mac address reading  problems on Alpha platforms
1946  *
1947  */
1948
1949 static void fix_mac_address(nic_t * sp)
1950 {
1951         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1952         u64 val64;
1953         int i = 0;
1954
1955         while (fix_mac[i] != END_SIGN) {
1956                 writeq(fix_mac[i++], &bar0->gpio_control);
1957                 udelay(10);
1958                 val64 = readq(&bar0->gpio_control);
1959         }
1960 }
1961
1962 /**
1963  *  start_nic - Turns the device on
1964  *  @nic : device private variable.
1965  *  Description:
1966  *  This function actually turns the device on. Before this  function is
1967  *  called,all Registers are configured from their reset states
1968  *  and shared memory is allocated but the NIC is still quiescent. On
1969  *  calling this function, the device interrupts are cleared and the NIC is
1970  *  literally switched on by writing into the adapter control register.
1971  *  Return Value:
1972  *  SUCCESS on success and -1 on failure.
1973  */
1974
1975 static int start_nic(struct s2io_nic *nic)
1976 {
1977         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1978         struct net_device *dev = nic->dev;
1979         register u64 val64 = 0;
1980         u16 interruptible;
1981         u16 subid, i;
1982         mac_info_t *mac_control;
1983         struct config_param *config;
1984
1985         mac_control = &nic->mac_control;
1986         config = &nic->config;
1987
1988         /*  PRC Initialization and configuration */
1989         for (i = 0; i < config->rx_ring_num; i++) {
1990                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1991                        &bar0->prc_rxd0_n[i]);
1992
1993                 val64 = readq(&bar0->prc_ctrl_n[i]);
1994                 if (nic->config.bimodal)
1995                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1996                 if (nic->rxd_mode == RXD_MODE_1)
1997                         val64 |= PRC_CTRL_RC_ENABLED;
1998                 else
1999                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2000                 if (nic->device_type == XFRAME_II_DEVICE)
2001                         val64 |= PRC_CTRL_GROUP_READS;
2002                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2003                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2004                 writeq(val64, &bar0->prc_ctrl_n[i]);
2005         }
2006
2007         if (nic->rxd_mode == RXD_MODE_3B) {
2008                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2009                 val64 = readq(&bar0->rx_pa_cfg);
2010                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2011                 writeq(val64, &bar0->rx_pa_cfg);
2012         }
2013
2014         /*
2015          * Enabling MC-RLDRAM. After enabling the device, we timeout
2016          * for around 100ms, which is approximately the time required
2017          * for the device to be ready for operation.
2018          */
2019         val64 = readq(&bar0->mc_rldram_mrs);
2020         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2021         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2022         val64 = readq(&bar0->mc_rldram_mrs);
2023
2024         msleep(100);    /* Delay by around 100 ms. */
2025
2026         /* Enabling ECC Protection. */
2027         val64 = readq(&bar0->adapter_control);
2028         val64 &= ~ADAPTER_ECC_EN;
2029         writeq(val64, &bar0->adapter_control);
2030
2031         /*
2032          * Clearing any possible Link state change interrupts that
2033          * could have popped up just before Enabling the card.
2034          */
2035         val64 = readq(&bar0->mac_rmac_err_reg);
2036         if (val64)
2037                 writeq(val64, &bar0->mac_rmac_err_reg);
2038
2039         /*
2040          * Verify if the device is ready to be enabled, if so enable
2041          * it.
2042          */
2043         val64 = readq(&bar0->adapter_status);
2044         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2045                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2046                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2047                           (unsigned long long) val64);
2048                 return FAILURE;
2049         }
2050
2051         /*  Enable select interrupts */
2052         if (nic->intr_type != INTA)
2053                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2054         else {
2055                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2056                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2057                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2058                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
2059         }
2060
2061         /*
2062          * With some switches, link might be already up at this point.
2063          * Because of this weird behavior, when we enable laser,
2064          * we may not get link. We need to handle this. We cannot
2065          * figure out which switch is misbehaving. So we are forced to
2066          * make a global change.
2067          */
2068
2069         /* Enabling Laser. */
2070         val64 = readq(&bar0->adapter_control);
2071         val64 |= ADAPTER_EOI_TX_ON;
2072         writeq(val64, &bar0->adapter_control);
2073
2074         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2075                 /*
2076                  * Dont see link state interrupts initally on some switches,
2077                  * so directly scheduling the link state task here.
2078                  */
2079                 schedule_work(&nic->set_link_task);
2080         }
2081         /* SXE-002: Initialize link and activity LED */
2082         subid = nic->pdev->subsystem_device;
2083         if (((subid & 0xFF) >= 0x07) &&
2084             (nic->device_type == XFRAME_I_DEVICE)) {
2085                 val64 = readq(&bar0->gpio_control);
2086                 val64 |= 0x0000800000000000ULL;
2087                 writeq(val64, &bar0->gpio_control);
2088                 val64 = 0x0411040400000000ULL;
2089                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2090         }
2091
2092         return SUCCESS;
2093 }
2094 /**
2095  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2096  */
2097 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2098 {
2099         nic_t *nic = fifo_data->nic;
2100         struct sk_buff *skb;
2101         TxD_t *txds;
2102         u16 j, frg_cnt;
2103
2104         txds = txdlp;
2105         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2106                 pci_unmap_single(nic->pdev, (dma_addr_t)
2107                         txds->Buffer_Pointer, sizeof(u64),
2108                         PCI_DMA_TODEVICE);
2109                 txds++;
2110         }
2111
2112         skb = (struct sk_buff *) ((unsigned long)
2113                         txds->Host_Control);
2114         if (!skb) {
2115                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2116                 return NULL;
2117         }
2118         pci_unmap_single(nic->pdev, (dma_addr_t)
2119                          txds->Buffer_Pointer,
2120                          skb->len - skb->data_len,
2121                          PCI_DMA_TODEVICE);
2122         frg_cnt = skb_shinfo(skb)->nr_frags;
2123         if (frg_cnt) {
2124                 txds++;
2125                 for (j = 0; j < frg_cnt; j++, txds++) {
2126                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2127                         if (!txds->Buffer_Pointer)
2128                                 break;
2129                         pci_unmap_page(nic->pdev, (dma_addr_t) 
2130                                         txds->Buffer_Pointer,
2131                                        frag->size, PCI_DMA_TODEVICE);
2132                 }
2133         }
2134         txdlp->Host_Control = 0;
2135         return(skb);
2136 }
2137
2138 /**
2139  *  free_tx_buffers - Free all queued Tx buffers
2140  *  @nic : device private variable.
2141  *  Description:
2142  *  Free all queued Tx buffers.
2143  *  Return Value: void
2144 */
2145
2146 static void free_tx_buffers(struct s2io_nic *nic)
2147 {
2148         struct net_device *dev = nic->dev;
2149         struct sk_buff *skb;
2150         TxD_t *txdp;
2151         int i, j;
2152         mac_info_t *mac_control;
2153         struct config_param *config;
2154         int cnt = 0;
2155
2156         mac_control = &nic->mac_control;
2157         config = &nic->config;
2158
2159         for (i = 0; i < config->tx_fifo_num; i++) {
2160                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2161                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2162                             list_virt_addr;
2163                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2164                         if (skb) {
2165                                 dev_kfree_skb(skb);
2166                                 cnt++;
2167                         }
2168                 }
2169                 DBG_PRINT(INTR_DBG,
2170                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2171                           dev->name, cnt, i);
2172                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2173                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2174         }
2175 }
2176
2177 /**
2178  *   stop_nic -  To stop the nic
2179  *   @nic ; device private variable.
2180  *   Description:
2181  *   This function does exactly the opposite of what the start_nic()
2182  *   function does. This function is called to stop the device.
2183  *   Return Value:
2184  *   void.
2185  */
2186
2187 static void stop_nic(struct s2io_nic *nic)
2188 {
2189         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2190         register u64 val64 = 0;
2191         u16 interruptible;
2192         mac_info_t *mac_control;
2193         struct config_param *config;
2194
2195         mac_control = &nic->mac_control;
2196         config = &nic->config;
2197
2198         /*  Disable all interrupts */
2199         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2200         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2201         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2202         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2203
2204         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2205         val64 = readq(&bar0->adapter_control);
2206         val64 &= ~(ADAPTER_CNTL_EN);
2207         writeq(val64, &bar0->adapter_control);
2208 }
2209
2210 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2211 {
2212         struct net_device *dev = nic->dev;
2213         struct sk_buff *frag_list;
2214         void *tmp;
2215
2216         /* Buffer-1 receives L3/L4 headers */
2217         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2218                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2219                         PCI_DMA_FROMDEVICE);
2220
2221         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2222         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2223         if (skb_shinfo(skb)->frag_list == NULL) {
2224                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2225                 return -ENOMEM ;
2226         }
2227         frag_list = skb_shinfo(skb)->frag_list;
2228         frag_list->next = NULL;
2229         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2230         frag_list->data = tmp;
2231         frag_list->tail = tmp;
2232
2233         /* Buffer-2 receives L4 data payload */
2234         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2235                                 frag_list->data, dev->mtu,
2236                                 PCI_DMA_FROMDEVICE);
2237         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2238         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2239
2240         return SUCCESS;
2241 }
2242
2243 /**
2244  *  fill_rx_buffers - Allocates the Rx side skbs
2245  *  @nic:  device private variable
2246  *  @ring_no: ring number
2247  *  Description:
2248  *  The function allocates Rx side skbs and puts the physical
2249  *  address of these buffers into the RxD buffer pointers, so that the NIC
2250  *  can DMA the received frame into these locations.
2251  *  The NIC supports 3 receive modes, viz
2252  *  1. single buffer,
2253  *  2. three buffer and
2254  *  3. Five buffer modes.
2255  *  Each mode defines how many fragments the received frame will be split
2256  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2257  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2258  *  is split into 3 fragments. As of now only single buffer mode is
2259  *  supported.
2260  *   Return Value:
2261  *  SUCCESS on success or an appropriate -ve value on failure.
2262  */
2263
2264 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2265 {
2266         struct net_device *dev = nic->dev;
2267         struct sk_buff *skb;
2268         RxD_t *rxdp;
2269         int off, off1, size, block_no, block_no1;
2270         u32 alloc_tab = 0;
2271         u32 alloc_cnt;
2272         mac_info_t *mac_control;
2273         struct config_param *config;
2274         u64 tmp;
2275         buffAdd_t *ba;
2276 #ifndef CONFIG_S2IO_NAPI
2277         unsigned long flags;
2278 #endif
2279         RxD_t *first_rxdp = NULL;
2280
2281         mac_control = &nic->mac_control;
2282         config = &nic->config;
2283         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2284             atomic_read(&nic->rx_bufs_left[ring_no]);
2285
2286         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2287         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2288         while (alloc_tab < alloc_cnt) {
2289                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2290                     block_index;
2291                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2292
2293                 rxdp = mac_control->rings[ring_no].
2294                                 rx_blocks[block_no].rxds[off].virt_addr;
2295
2296                 if ((block_no == block_no1) && (off == off1) &&
2297                                         (rxdp->Host_Control)) {
2298                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2299                                   dev->name);
2300                         DBG_PRINT(INTR_DBG, " info equated\n");
2301                         goto end;
2302                 }
2303                 if (off && (off == rxd_count[nic->rxd_mode])) {
2304                         mac_control->rings[ring_no].rx_curr_put_info.
2305                             block_index++;
2306                         if (mac_control->rings[ring_no].rx_curr_put_info.
2307                             block_index == mac_control->rings[ring_no].
2308                                         block_count)
2309                                 mac_control->rings[ring_no].rx_curr_put_info.
2310                                         block_index = 0;
2311                         block_no = mac_control->rings[ring_no].
2312                                         rx_curr_put_info.block_index;
2313                         if (off == rxd_count[nic->rxd_mode])
2314                                 off = 0;
2315                         mac_control->rings[ring_no].rx_curr_put_info.
2316                                 offset = off;
2317                         rxdp = mac_control->rings[ring_no].
2318                                 rx_blocks[block_no].block_virt_addr;
2319                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2320                                   dev->name, rxdp);
2321                 }
2322 #ifndef CONFIG_S2IO_NAPI
2323                 spin_lock_irqsave(&nic->put_lock, flags);
2324                 mac_control->rings[ring_no].put_pos =
2325                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2326                 spin_unlock_irqrestore(&nic->put_lock, flags);
2327 #endif
2328                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2329                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2330                                 (rxdp->Control_2 & BIT(0)))) {
2331                         mac_control->rings[ring_no].rx_curr_put_info.
2332                                         offset = off;
2333                         goto end;
2334                 }
2335                 /* calculate size of skb based on ring mode */
2336                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2337                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2338                 if (nic->rxd_mode == RXD_MODE_1)
2339                         size += NET_IP_ALIGN;
2340                 else if (nic->rxd_mode == RXD_MODE_3B)
2341                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2342                 else
2343                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2344
2345                 /* allocate skb */
2346                 skb = dev_alloc_skb(size);
2347                 if(!skb) {
2348                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2349                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2350                         if (first_rxdp) {
2351                                 wmb();
2352                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2353                         }
2354                         return -ENOMEM ;
2355                 }
2356                 if (nic->rxd_mode == RXD_MODE_1) {
2357                         /* 1 buffer mode - normal operation mode */
2358                         memset(rxdp, 0, sizeof(RxD1_t));
2359                         skb_reserve(skb, NET_IP_ALIGN);
2360                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2361                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2362                                 PCI_DMA_FROMDEVICE);
2363                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2364
2365                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2366                         /*
2367                          * 2 or 3 buffer mode -
2368                          * Both 2 buffer mode and 3 buffer mode provides 128
2369                          * byte aligned receive buffers.
2370                          *
2371                          * 3 buffer mode provides header separation where in
2372                          * skb->data will have L3/L4 headers where as
2373                          * skb_shinfo(skb)->frag_list will have the L4 data
2374                          * payload
2375                          */
2376
2377                         memset(rxdp, 0, sizeof(RxD3_t));
2378                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2379                         skb_reserve(skb, BUF0_LEN);
2380                         tmp = (u64)(unsigned long) skb->data;
2381                         tmp += ALIGN_SIZE;
2382                         tmp &= ~ALIGN_SIZE;
2383                         skb->data = (void *) (unsigned long)tmp;
2384                         skb->tail = (void *) (unsigned long)tmp;
2385
2386                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2387                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2388                                            PCI_DMA_FROMDEVICE);
2389                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2390                         if (nic->rxd_mode == RXD_MODE_3B) {
2391                                 /* Two buffer mode */
2392
2393                                 /*
2394                                  * Buffer2 will have L3/L4 header plus 
2395                                  * L4 payload
2396                                  */
2397                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2398                                 (nic->pdev, skb->data, dev->mtu + 4,
2399                                                 PCI_DMA_FROMDEVICE);
2400
2401                                 /* Buffer-1 will be dummy buffer not used */
2402                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2403                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2404                                         PCI_DMA_FROMDEVICE);
2405                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2406                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2407                                                                 (dev->mtu + 4);
2408                         } else {
2409                                 /* 3 buffer mode */
2410                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2411                                         dev_kfree_skb_irq(skb);
2412                                         if (first_rxdp) {
2413                                                 wmb();
2414                                                 first_rxdp->Control_1 |=
2415                                                         RXD_OWN_XENA;
2416                                         }
2417                                         return -ENOMEM ;
2418                                 }
2419                         }
2420                         rxdp->Control_2 |= BIT(0);
2421                 }
2422                 rxdp->Host_Control = (unsigned long) (skb);
2423                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2424                         rxdp->Control_1 |= RXD_OWN_XENA;
2425                 off++;
2426                 if (off == (rxd_count[nic->rxd_mode] + 1))
2427                         off = 0;
2428                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2429
2430                 rxdp->Control_2 |= SET_RXD_MARKER;
2431                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2432                         if (first_rxdp) {
2433                                 wmb();
2434                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2435                         }
2436                         first_rxdp = rxdp;
2437                 }
2438                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2439                 alloc_tab++;
2440         }
2441
2442       end:
2443         /* Transfer ownership of first descriptor to adapter just before
2444          * exiting. Before that, use memory barrier so that ownership
2445          * and other fields are seen by adapter correctly.
2446          */
2447         if (first_rxdp) {
2448                 wmb();
2449                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2450         }
2451
2452         return SUCCESS;
2453 }
2454
2455 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2456 {
2457         struct net_device *dev = sp->dev;
2458         int j;
2459         struct sk_buff *skb;
2460         RxD_t *rxdp;
2461         mac_info_t *mac_control;
2462         buffAdd_t *ba;
2463
2464         mac_control = &sp->mac_control;
2465         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2466                 rxdp = mac_control->rings[ring_no].
2467                                 rx_blocks[blk].rxds[j].virt_addr;
2468                 skb = (struct sk_buff *)
2469                         ((unsigned long) rxdp->Host_Control);
2470                 if (!skb) {
2471                         continue;
2472                 }
2473                 if (sp->rxd_mode == RXD_MODE_1) {
2474                         pci_unmap_single(sp->pdev, (dma_addr_t)
2475                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2476                                  dev->mtu +
2477                                  HEADER_ETHERNET_II_802_3_SIZE
2478                                  + HEADER_802_2_SIZE +
2479                                  HEADER_SNAP_SIZE,
2480                                  PCI_DMA_FROMDEVICE);
2481                         memset(rxdp, 0, sizeof(RxD1_t));
2482                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2483                         ba = &mac_control->rings[ring_no].
2484                                 ba[blk][j];
2485                         pci_unmap_single(sp->pdev, (dma_addr_t)
2486                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2487                                  BUF0_LEN,
2488                                  PCI_DMA_FROMDEVICE);
2489                         pci_unmap_single(sp->pdev, (dma_addr_t)
2490                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2491                                  BUF1_LEN,
2492                                  PCI_DMA_FROMDEVICE);
2493                         pci_unmap_single(sp->pdev, (dma_addr_t)
2494                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2495                                  dev->mtu + 4,
2496                                  PCI_DMA_FROMDEVICE);
2497                         memset(rxdp, 0, sizeof(RxD3_t));
2498                 } else {
2499                         pci_unmap_single(sp->pdev, (dma_addr_t)
2500                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2501                                 PCI_DMA_FROMDEVICE);
2502                         pci_unmap_single(sp->pdev, (dma_addr_t)
2503                                 ((RxD3_t*)rxdp)->Buffer1_ptr, 
2504                                 l3l4hdr_size + 4,
2505                                 PCI_DMA_FROMDEVICE);
2506                         pci_unmap_single(sp->pdev, (dma_addr_t)
2507                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2508                                 PCI_DMA_FROMDEVICE);
2509                         memset(rxdp, 0, sizeof(RxD3_t));
2510                 }
2511                 dev_kfree_skb(skb);
2512                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2513         }
2514 }
2515
2516 /**
2517  *  free_rx_buffers - Frees all Rx buffers
2518  *  @sp: device private variable.
2519  *  Description:
2520  *  This function will free all Rx buffers allocated by host.
2521  *  Return Value:
2522  *  NONE.
2523  */
2524
2525 static void free_rx_buffers(struct s2io_nic *sp)
2526 {
2527         struct net_device *dev = sp->dev;
2528         int i, blk = 0, buf_cnt = 0;
2529         mac_info_t *mac_control;
2530         struct config_param *config;
2531
2532         mac_control = &sp->mac_control;
2533         config = &sp->config;
2534
2535         for (i = 0; i < config->rx_ring_num; i++) {
2536                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2537                         free_rxd_blk(sp,i,blk);
2538
2539                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2540                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2541                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2542                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2543                 atomic_set(&sp->rx_bufs_left[i], 0);
2544                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2545                           dev->name, buf_cnt, i);
2546         }
2547 }
2548
2549 /**
2550  * s2io_poll - Rx interrupt handler for NAPI support
2551  * @dev : pointer to the device structure.
2552  * @budget : The number of packets that were budgeted to be processed
2553  * during  one pass through the 'Poll" function.
2554  * Description:
2555  * Comes into picture only if NAPI support has been incorporated. It does
2556  * the same thing that rx_intr_handler does, but not in a interrupt context
2557  * also It will process only a given number of packets.
2558  * Return value:
2559  * 0 on success and 1 if there are No Rx packets to be processed.
2560  */
2561
2562 #if defined(CONFIG_S2IO_NAPI)
2563 static int s2io_poll(struct net_device *dev, int *budget)
2564 {
2565         nic_t *nic = dev->priv;
2566         int pkt_cnt = 0, org_pkts_to_process;
2567         mac_info_t *mac_control;
2568         struct config_param *config;
2569         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2570         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2571         int i;
2572
2573         atomic_inc(&nic->isr_cnt);
2574         mac_control = &nic->mac_control;
2575         config = &nic->config;
2576
2577         nic->pkts_to_process = *budget;
2578         if (nic->pkts_to_process > dev->quota)
2579                 nic->pkts_to_process = dev->quota;
2580         org_pkts_to_process = nic->pkts_to_process;
2581
2582         writeq(val64, &bar0->rx_traffic_int);
2583         val64 = readl(&bar0->rx_traffic_int);
2584
2585         for (i = 0; i < config->rx_ring_num; i++) {
2586                 rx_intr_handler(&mac_control->rings[i]);
2587                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2588                 if (!nic->pkts_to_process) {
2589                         /* Quota for the current iteration has been met */
2590                         goto no_rx;
2591                 }
2592         }
2593         if (!pkt_cnt)
2594                 pkt_cnt = 1;
2595
2596         dev->quota -= pkt_cnt;
2597         *budget -= pkt_cnt;
2598         netif_rx_complete(dev);
2599
2600         for (i = 0; i < config->rx_ring_num; i++) {
2601                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2602                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2603                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2604                         break;
2605                 }
2606         }
2607         /* Re enable the Rx interrupts. */
2608         writeq(0x0, &bar0->rx_traffic_mask);
2609         val64 = readl(&bar0->rx_traffic_mask);
2610         atomic_dec(&nic->isr_cnt);
2611         return 0;
2612
2613 no_rx:
2614         dev->quota -= pkt_cnt;
2615         *budget -= pkt_cnt;
2616
2617         for (i = 0; i < config->rx_ring_num; i++) {
2618                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2619                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2620                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2621                         break;
2622                 }
2623         }
2624         atomic_dec(&nic->isr_cnt);
2625         return 1;
2626 }
2627 #endif
2628
2629 /**
2630  *  rx_intr_handler - Rx interrupt handler
2631  *  @nic: device private variable.
2632  *  Description:
2633  *  If the interrupt is because of a received frame or if the
2634  *  receive ring contains fresh as yet un-processed frames,this function is
2635  *  called. It picks out the RxD at which place the last Rx processing had
2636  *  stopped and sends the skb to the OSM's Rx handler and then increments
2637  *  the offset.
2638  *  Return Value:
2639  *  NONE.
2640  */
2641 static void rx_intr_handler(ring_info_t *ring_data)
2642 {
2643         nic_t *nic = ring_data->nic;
2644         struct net_device *dev = (struct net_device *) nic->dev;
2645         int get_block, put_block, put_offset;
2646         rx_curr_get_info_t get_info, put_info;
2647         RxD_t *rxdp;
2648         struct sk_buff *skb;
2649 #ifndef CONFIG_S2IO_NAPI
2650         int pkt_cnt = 0;
2651 #endif
2652         int i;
2653
2654         spin_lock(&nic->rx_lock);
2655         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2656                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2657                           __FUNCTION__, dev->name);
2658                 spin_unlock(&nic->rx_lock);
2659                 return;
2660         }
2661
2662         get_info = ring_data->rx_curr_get_info;
2663         get_block = get_info.block_index;
2664         put_info = ring_data->rx_curr_put_info;
2665         put_block = put_info.block_index;
2666         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2667 #ifndef CONFIG_S2IO_NAPI
2668         spin_lock(&nic->put_lock);
2669         put_offset = ring_data->put_pos;
2670         spin_unlock(&nic->put_lock);
2671 #else
2672         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2673                 put_info.offset;
2674 #endif
2675         while (RXD_IS_UP2DT(rxdp)) {
2676                 /* If your are next to put index then it's FIFO full condition */
2677                 if ((get_block == put_block) &&
2678                     (get_info.offset + 1) == put_info.offset) {
2679                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2680                         break;
2681                 }
2682                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2683                 if (skb == NULL) {
2684                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2685                                   dev->name);
2686                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2687                         spin_unlock(&nic->rx_lock);
2688                         return;
2689                 }
2690                 if (nic->rxd_mode == RXD_MODE_1) {
2691                         pci_unmap_single(nic->pdev, (dma_addr_t)
2692                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2693                                  dev->mtu +
2694                                  HEADER_ETHERNET_II_802_3_SIZE +
2695                                  HEADER_802_2_SIZE +
2696                                  HEADER_SNAP_SIZE,
2697                                  PCI_DMA_FROMDEVICE);
2698                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2699                         pci_unmap_single(nic->pdev, (dma_addr_t)
2700                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2701                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2702                         pci_unmap_single(nic->pdev, (dma_addr_t)
2703                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2704                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2705                         pci_unmap_single(nic->pdev, (dma_addr_t)
2706                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2707                                  dev->mtu + 4,
2708                                  PCI_DMA_FROMDEVICE);
2709                 } else {
2710                         pci_unmap_single(nic->pdev, (dma_addr_t)
2711                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2712                                          PCI_DMA_FROMDEVICE);
2713                         pci_unmap_single(nic->pdev, (dma_addr_t)
2714                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2715                                          l3l4hdr_size + 4,
2716                                          PCI_DMA_FROMDEVICE);
2717                         pci_unmap_single(nic->pdev, (dma_addr_t)
2718                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2719                                          dev->mtu, PCI_DMA_FROMDEVICE);
2720                 }
2721                 prefetch(skb->data);
2722                 rx_osm_handler(ring_data, rxdp);
2723                 get_info.offset++;
2724                 ring_data->rx_curr_get_info.offset = get_info.offset;
2725                 rxdp = ring_data->rx_blocks[get_block].
2726                                 rxds[get_info.offset].virt_addr;
2727                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2728                         get_info.offset = 0;
2729                         ring_data->rx_curr_get_info.offset = get_info.offset;
2730                         get_block++;
2731                         if (get_block == ring_data->block_count)
2732                                 get_block = 0;
2733                         ring_data->rx_curr_get_info.block_index = get_block;
2734                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2735                 }
2736
2737 #ifdef CONFIG_S2IO_NAPI
2738                 nic->pkts_to_process -= 1;
2739                 if (!nic->pkts_to_process)
2740                         break;
2741 #else
2742                 pkt_cnt++;
2743                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2744                         break;
2745 #endif
2746         }
2747         if (nic->lro) {
2748                 /* Clear all LRO sessions before exiting */
2749                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2750                         lro_t *lro = &nic->lro0_n[i];
2751                         if (lro->in_use) {
2752                                 update_L3L4_header(nic, lro);
2753                                 queue_rx_frame(lro->parent);
2754                                 clear_lro_session(lro);
2755                         }
2756                 }
2757         }
2758
2759         spin_unlock(&nic->rx_lock);
2760 }
2761
2762 /**
2763  *  tx_intr_handler - Transmit interrupt handler
2764  *  @nic : device private variable
2765  *  Description:
2766  *  If an interrupt was raised to indicate DMA complete of the
2767  *  Tx packet, this function is called. It identifies the last TxD
2768  *  whose buffer was freed and frees all skbs whose data have already
2769  *  DMA'ed into the NICs internal memory.
2770  *  Return Value:
2771  *  NONE
2772  */
2773
2774 static void tx_intr_handler(fifo_info_t *fifo_data)
2775 {
2776         nic_t *nic = fifo_data->nic;
2777         struct net_device *dev = (struct net_device *) nic->dev;
2778         tx_curr_get_info_t get_info, put_info;
2779         struct sk_buff *skb;
2780         TxD_t *txdlp;
2781
2782         get_info = fifo_data->tx_curr_get_info;
2783         put_info = fifo_data->tx_curr_put_info;
2784         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2785             list_virt_addr;
2786         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2787                (get_info.offset != put_info.offset) &&
2788                (txdlp->Host_Control)) {
2789                 /* Check for TxD errors */
2790                 if (txdlp->Control_1 & TXD_T_CODE) {
2791                         unsigned long long err;
2792                         err = txdlp->Control_1 & TXD_T_CODE;
2793                         if (err & 0x1) {
2794                                 nic->mac_control.stats_info->sw_stat.
2795                                                 parity_err_cnt++;
2796                         }
2797                         if ((err >> 48) == 0xA) {
2798                                 DBG_PRINT(TX_DBG, "TxD returned due \
2799 to loss of link\n");
2800                         }
2801                         else {
2802                                 DBG_PRINT(ERR_DBG, "***TxD error \
2803 %llx\n", err);
2804                         }
2805                 }
2806
2807                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2808                 if (skb == NULL) {
2809                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2810                         __FUNCTION__);
2811                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2812                         return;
2813                 }
2814
2815                 /* Updating the statistics block */
2816                 nic->stats.tx_bytes += skb->len;
2817                 dev_kfree_skb_irq(skb);
2818
2819                 get_info.offset++;
2820                 if (get_info.offset == get_info.fifo_len + 1)
2821                         get_info.offset = 0;
2822                 txdlp = (TxD_t *) fifo_data->list_info
2823                     [get_info.offset].list_virt_addr;
2824                 fifo_data->tx_curr_get_info.offset =
2825                     get_info.offset;
2826         }
2827
2828         spin_lock(&nic->tx_lock);
2829         if (netif_queue_stopped(dev))
2830                 netif_wake_queue(dev);
2831         spin_unlock(&nic->tx_lock);
2832 }
2833
2834 /**
2835  *  s2io_mdio_write - Function to write in to MDIO registers
2836  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2837  *  @addr     : address value
2838  *  @value    : data value
2839  *  @dev      : pointer to net_device structure
2840  *  Description:
2841  *  This function is used to write values to the MDIO registers
2842  *  NONE
2843  */
2844 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2845 {
2846         u64 val64 = 0x0;
2847         nic_t *sp = dev->priv;
2848         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2849
2850         //address transaction
2851         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2852                         | MDIO_MMD_DEV_ADDR(mmd_type)
2853                         | MDIO_MMS_PRT_ADDR(0x0);
2854         writeq(val64, &bar0->mdio_control);
2855         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2856         writeq(val64, &bar0->mdio_control);
2857         udelay(100);
2858
2859         //Data transaction
2860         val64 = 0x0;
2861         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2862                         | MDIO_MMD_DEV_ADDR(mmd_type)
2863                         | MDIO_MMS_PRT_ADDR(0x0)
2864                         | MDIO_MDIO_DATA(value)
2865                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2866         writeq(val64, &bar0->mdio_control);
2867         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2868         writeq(val64, &bar0->mdio_control);
2869         udelay(100);
2870
2871         val64 = 0x0;
2872         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2873         | MDIO_MMD_DEV_ADDR(mmd_type)
2874         | MDIO_MMS_PRT_ADDR(0x0)
2875         | MDIO_OP(MDIO_OP_READ_TRANS);
2876         writeq(val64, &bar0->mdio_control);
2877         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2878         writeq(val64, &bar0->mdio_control);
2879         udelay(100);
2880
2881 }
2882
2883 /**
2884  *  s2io_mdio_read - Function to write in to MDIO registers
2885  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2886  *  @addr     : address value
2887  *  @dev      : pointer to net_device structure
2888  *  Description:
2889  *  This function is used to read values to the MDIO registers
2890  *  NONE
2891  */
2892 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2893 {
2894         u64 val64 = 0x0;
2895         u64 rval64 = 0x0;
2896         nic_t *sp = dev->priv;
2897         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2898
2899         /* address transaction */
2900         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2901                         | MDIO_MMD_DEV_ADDR(mmd_type)
2902                         | MDIO_MMS_PRT_ADDR(0x0);
2903         writeq(val64, &bar0->mdio_control);
2904         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2905         writeq(val64, &bar0->mdio_control);
2906         udelay(100);
2907
2908         /* Data transaction */
2909         val64 = 0x0;
2910         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2911                         | MDIO_MMD_DEV_ADDR(mmd_type)
2912                         | MDIO_MMS_PRT_ADDR(0x0)
2913                         | MDIO_OP(MDIO_OP_READ_TRANS);
2914         writeq(val64, &bar0->mdio_control);
2915         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2916         writeq(val64, &bar0->mdio_control);
2917         udelay(100);
2918
2919         /* Read the value from regs */
2920         rval64 = readq(&bar0->mdio_control);
2921         rval64 = rval64 & 0xFFFF0000;
2922         rval64 = rval64 >> 16;
2923         return rval64;
2924 }
2925 /**
2926  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2927  *  @counter      : couter value to be updated
2928  *  @flag         : flag to indicate the status
2929  *  @type         : counter type
2930  *  Description:
2931  *  This function is to check the status of the xpak counters value
2932  *  NONE
2933  */
2934
2935 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2936 {
2937         u64 mask = 0x3;
2938         u64 val64;
2939         int i;
2940         for(i = 0; i <index; i++)
2941                 mask = mask << 0x2;
2942
2943         if(flag > 0)
2944         {
2945                 *counter = *counter + 1;
2946                 val64 = *regs_stat & mask;
2947                 val64 = val64 >> (index * 0x2);
2948                 val64 = val64 + 1;
2949                 if(val64 == 3)
2950                 {
2951                         switch(type)
2952                         {
2953                         case 1:
2954                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2955                                           "service. Excessive temperatures may "
2956                                           "result in premature transceiver "
2957                                           "failure \n");
2958                         break;
2959                         case 2:
2960                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2961                                           "service Excessive bias currents may "
2962                                           "indicate imminent laser diode "
2963                                           "failure \n");
2964                         break;
2965                         case 3:
2966                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2967                                           "service Excessive laser output "
2968                                           "power may saturate far-end "
2969                                           "receiver\n");
2970                         break;
2971                         default:
2972                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
2973                                           "type \n");
2974                         }
2975                         val64 = 0x0;
2976                 }
2977                 val64 = val64 << (index * 0x2);
2978                 *regs_stat = (*regs_stat & (~mask)) | (val64);
2979
2980         } else {
2981                 *regs_stat = *regs_stat & (~mask);
2982         }
2983 }
2984
2985 /**
2986  *  s2io_updt_xpak_counter - Function to update the xpak counters
2987  *  @dev         : pointer to net_device struct
2988  *  Description:
2989  *  This function is to upate the status of the xpak counters value
2990  *  NONE
2991  */
2992 static void s2io_updt_xpak_counter(struct net_device *dev)
2993 {
2994         u16 flag  = 0x0;
2995         u16 type  = 0x0;
2996         u16 val16 = 0x0;
2997         u64 val64 = 0x0;
2998         u64 addr  = 0x0;
2999
3000         nic_t *sp = dev->priv;
3001         StatInfo_t *stat_info = sp->mac_control.stats_info;
3002
3003         /* Check the communication with the MDIO slave */
3004         addr = 0x0000;
3005         val64 = 0x0;
3006         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3007         if((val64 == 0xFFFF) || (val64 == 0x0000))
3008         {
3009                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3010                           "Returned %llx\n", (unsigned long long)val64);
3011                 return;
3012         }
3013
3014         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3015         if(val64 != 0x2040)
3016         {
3017                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3018                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3019                           (unsigned long long)val64);
3020                 return;
3021         }
3022
3023         /* Loading the DOM register to MDIO register */
3024         addr = 0xA100;
3025         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3026         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3027
3028         /* Reading the Alarm flags */
3029         addr = 0xA070;
3030         val64 = 0x0;
3031         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3032
3033         flag = CHECKBIT(val64, 0x7);
3034         type = 1;
3035         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3036                                 &stat_info->xpak_stat.xpak_regs_stat,
3037                                 0x0, flag, type);
3038
3039         if(CHECKBIT(val64, 0x6))
3040                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3041
3042         flag = CHECKBIT(val64, 0x3);
3043         type = 2;
3044         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3045                                 &stat_info->xpak_stat.xpak_regs_stat,
3046                                 0x2, flag, type);
3047
3048         if(CHECKBIT(val64, 0x2))
3049                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3050
3051         flag = CHECKBIT(val64, 0x1);
3052         type = 3;
3053         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3054                                 &stat_info->xpak_stat.xpak_regs_stat,
3055                                 0x4, flag, type);
3056
3057         if(CHECKBIT(val64, 0x0))
3058                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3059
3060         /* Reading the Warning flags */
3061         addr = 0xA074;
3062         val64 = 0x0;
3063         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3064
3065         if(CHECKBIT(val64, 0x7))
3066                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3067
3068         if(CHECKBIT(val64, 0x6))
3069                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3070
3071         if(CHECKBIT(val64, 0x3))
3072                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3073
3074         if(CHECKBIT(val64, 0x2))
3075                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3076
3077         if(CHECKBIT(val64, 0x1))
3078                 stat_info->xpak_stat.warn_laser_output_power_high++;
3079
3080         if(CHECKBIT(val64, 0x0))
3081                 stat_info->xpak_stat.warn_laser_output_power_low++;
3082 }
3083
3084 /**
3085  *  alarm_intr_handler - Alarm Interrrupt handler
3086  *  @nic: device private variable
3087  *  Description: If the interrupt was neither because of Rx packet or Tx
3088  *  complete, this function is called. If the interrupt was to indicate
3089  *  a loss of link, the OSM link status handler is invoked for any other
3090  *  alarm interrupt the block that raised the interrupt is displayed
3091  *  and a H/W reset is issued.
3092  *  Return Value:
3093  *  NONE
3094 */
3095
3096 static void alarm_intr_handler(struct s2io_nic *nic)
3097 {
3098         struct net_device *dev = (struct net_device *) nic->dev;
3099         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3100         register u64 val64 = 0, err_reg = 0;
3101         u64 cnt;
3102         int i;
3103         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3104         /* Handling the XPAK counters update */
3105         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3106                 /* waiting for an hour */
3107                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3108         } else {
3109                 s2io_updt_xpak_counter(dev);
3110                 /* reset the count to zero */
3111                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3112         }
3113
3114         /* Handling link status change error Intr */
3115         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3116                 err_reg = readq(&bar0->mac_rmac_err_reg);
3117                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3118                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3119                         schedule_work(&nic->set_link_task);
3120                 }