drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int wait_count = 30;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 udelay(100);
 135         } while (--wait_count);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 218         if (status)
 219                 return status;
 220
 221         status = ql_wait_cfg(qdev, bit);
 222         if (status) {
 223                 QPRINTK(qdev, IFUP, ERR,
 224                         "Timed out waiting for CFG to come ready.\n");
 225                 goto exit;
 226         }
 227
 228         ql_write32(qdev, ICB_L, (u32) map);
 229         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 241         pci_unmap_single(qdev->pdev, map, size, direction);
 242         return status;
 243 }
 244
 245 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 246 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 247                         u32 *value)
 248 {
 249         u32 offset = 0;
 250         int status;
 251
 252         switch (type) {
 253         case MAC_ADDR_TYPE_MULTI_MAC:
 254         case MAC_ADDR_TYPE_CAM_MAC:
 255                 {
 256                         status =
 257                             ql_wait_reg_rdy(qdev,
 258                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 259                         if (status)
 260                                 goto exit;
 261                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 262                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 263                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 264                         status =
 265                             ql_wait_reg_rdy(qdev,
 266                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 267                         if (status)
 268                                 goto exit;
 269                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 270                         status =
 271                             ql_wait_reg_rdy(qdev,
 272                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 273                         if (status)
 274                                 goto exit;
 275                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 276                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 277                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 278                         status =
 279                             ql_wait_reg_rdy(qdev,
 280                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 281                         if (status)
 282                                 goto exit;
 283                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 284                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 285                                 status =
 286                                     ql_wait_reg_rdy(qdev,
 287                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 288                                 if (status)
 289                                         goto exit;
 290                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 291                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 292                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 293                                 status =
 294                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 295                                                     MAC_ADDR_MR, 0);
 296                                 if (status)
 297                                         goto exit;
 298                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 299                         }
 300                         break;
 301                 }
 302         case MAC_ADDR_TYPE_VLAN:
 303         case MAC_ADDR_TYPE_MULTI_FLTR:
 304         default:
 305                 QPRINTK(qdev, IFUP, CRIT,
 306                         "Address type %d not yet supported.\n", type);
 307                 status = -EPERM;
 308         }
 309 exit:
 310         return status;
 311 }
 312
 313 /* Set up a MAC, multicast or VLAN address for the
 314  * inbound frame matching.
 315  */
 316 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 317                                u16 index)
 318 {
 319         u32 offset = 0;
 320         int status = 0;
 321
 322         switch (type) {
 323         case MAC_ADDR_TYPE_MULTI_MAC:
 324         case MAC_ADDR_TYPE_CAM_MAC:
 325                 {
 326                         u32 cam_output;
 327                         u32 upper = (addr[0] << 8) | addr[1];
 328                         u32 lower =
 329                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 330                             (addr[5]);
 331
 332                         QPRINTK(qdev, IFUP, DEBUG,
 333                                 "Adding %s address %pM"
 334                                 " at index %d in the CAM.\n",
 335                                 ((type ==
 336                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 337                                  "UNICAST"), addr, index);
 338
 339                         status =
 340                             ql_wait_reg_rdy(qdev,
 341                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 342                         if (status)
 343                                 goto exit;
 344                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 345                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 346                                    type);       /* type */
 347                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 348                         status =
 349                             ql_wait_reg_rdy(qdev,
 350                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 351                         if (status)
 352                                 goto exit;
 353                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 354                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 355                                    type);       /* type */
 356                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 357                         status =
 358                             ql_wait_reg_rdy(qdev,
 359                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 360                         if (status)
 361                                 goto exit;
 362                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 363                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 364                                    type);       /* type */
 365                         /* This field should also include the queue id
 366                            and possibly the function id.  Right now we hardcode
 367                            the route field to NIC core.
 368                          */
 369                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 370                                 cam_output = (CAM_OUT_ROUTE_NIC |
 371                                               (qdev->
 372                                                func << CAM_OUT_FUNC_SHIFT) |
 373                                                 (0 << CAM_OUT_CQ_ID_SHIFT));
 374                                 if (qdev->vlgrp)
 375                                         cam_output |= CAM_OUT_RV;
 376                                 /* route to NIC core */
 377                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 378                         }
 379                         break;
 380                 }
 381         case MAC_ADDR_TYPE_VLAN:
 382                 {
 383                         u32 enable_bit = *((u32 *) &addr[0]);
 384                         /* For VLAN, the addr actually holds a bit that
 385                          * either enables or disables the vlan id we are
 386                          * addressing. It's either MAC_ADDR_E on or off.
 387                          * That's bit-27 we're talking about.
 388                          */
 389                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 390                                 (enable_bit ? "Adding" : "Removing"),
 391                                 index, (enable_bit ? "to" : "from"));
 392
 393                         status =
 394                             ql_wait_reg_rdy(qdev,
 395                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 396                         if (status)
 397                                 goto exit;
 398                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 399                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 400                                    type |       /* type */
 401                                    enable_bit); /* enable/disable */
 402                         break;
 403                 }
 404         case MAC_ADDR_TYPE_MULTI_FLTR:
 405         default:
 406                 QPRINTK(qdev, IFUP, CRIT,
 407                         "Address type %d not yet supported.\n", type);
 408                 status = -EPERM;
 409         }
 410 exit:
 411         return status;
 412 }
 413
 414 /* Set or clear MAC address in hardware. We sometimes
 415  * have to clear it to prevent wrong frame routing
 416  * especially in a bonding environment.
 417  */
 418 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
 419 {
 420         int status;
 421         char zero_mac_addr[ETH_ALEN];
 422         char *addr;
 423
 424         if (set) {
 425                 addr = &qdev->ndev->dev_addr[0];
 426                 QPRINTK(qdev, IFUP, DEBUG,
 427                         "Set Mac addr %02x:%02x:%02x:%02x:%02x:%02x\n",
 428                         addr[0], addr[1], addr[2], addr[3],
 429                         addr[4], addr[5]);
 430         } else {
 431                 memset(zero_mac_addr, 0, ETH_ALEN);
 432                 addr = &zero_mac_addr[0];
 433                 QPRINTK(qdev, IFUP, DEBUG,
 434                                 "Clearing MAC address on %s\n",
 435                                 qdev->ndev->name);
 436         }
 437         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 438         if (status)
 439                 return status;
 440         status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
 441                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
 442         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 443         if (status)
 444                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac "
 445                         "address.\n");
 446         return status;
 447 }
 448
 449 void ql_link_on(struct ql_adapter *qdev)
 450 {
 451         QPRINTK(qdev, LINK, ERR, "%s: Link is up.\n",
 452                                  qdev->ndev->name);
 453         netif_carrier_on(qdev->ndev);
 454         ql_set_mac_addr(qdev, 1);
 455 }
 456
 457 void ql_link_off(struct ql_adapter *qdev)
 458 {
 459         QPRINTK(qdev, LINK, ERR, "%s: Link is down.\n",
 460                                  qdev->ndev->name);
 461         netif_carrier_off(qdev->ndev);
 462         ql_set_mac_addr(qdev, 0);
 463 }
 464
 465 /* Get a specific frame routing value from the CAM.
 466  * Used for debug and reg dump.
 467  */
 468 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 469 {
 470         int status = 0;
 471
 472         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 473         if (status)
 474                 goto exit;
 475
 476         ql_write32(qdev, RT_IDX,
 477                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 478         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 479         if (status)
 480                 goto exit;
 481         *value = ql_read32(qdev, RT_DATA);
 482 exit:
 483         return status;
 484 }
 485
 486 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 487  * to route different frame types to various inbound queues.  We send broadcast/
 488  * multicast/error frames to the default queue for slow handling,
 489  * and CAM hit/RSS frames to the fast handling queues.
 490  */
 491 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 492                               int enable)
 493 {
 494         int status = -EINVAL; /* Return error if no mask match. */
 495         u32 value = 0;
 496
 497         QPRINTK(qdev, IFUP, DEBUG,
 498                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 499                 (enable ? "Adding" : "Removing"),
 500                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 501                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 502                 ((index ==
 503                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 504                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 505                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 506                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 507                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 508                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 509                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 510                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 511                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 512                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 513                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 514                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 515                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 516                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 517                 (enable ? "to" : "from"));
 518
 519         switch (mask) {
 520         case RT_IDX_CAM_HIT:
 521                 {
 522                         value = RT_IDX_DST_CAM_Q |      /* dest */
 523                             RT_IDX_TYPE_NICQ |  /* type */
 524                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 525                         break;
 526                 }
 527         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 528                 {
 529                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 530                             RT_IDX_TYPE_NICQ |  /* type */
 531                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 532                         break;
 533                 }
 534         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 535                 {
 536                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 537                             RT_IDX_TYPE_NICQ |  /* type */
 538                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 539                         break;
 540                 }
 541         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 542                 {
 543                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 544                             RT_IDX_TYPE_NICQ |  /* type */
 545                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 546                         break;
 547                 }
 548         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 549                 {
 550                         value = RT_IDX_DST_CAM_Q |      /* dest */
 551                             RT_IDX_TYPE_NICQ |  /* type */
 552                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 553                         break;
 554                 }
 555         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 556                 {
 557                         value = RT_IDX_DST_CAM_Q |      /* dest */
 558                             RT_IDX_TYPE_NICQ |  /* type */
 559                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 560                         break;
 561                 }
 562         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 563                 {
 564                         value = RT_IDX_DST_RSS |        /* dest */
 565                             RT_IDX_TYPE_NICQ |  /* type */
 566                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 567                         break;
 568                 }
 569         case 0:         /* Clear the E-bit on an entry. */
 570                 {
 571                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 572                             RT_IDX_TYPE_NICQ |  /* type */
 573                             (index << RT_IDX_IDX_SHIFT);/* index */
 574                         break;
 575                 }
 576         default:
 577                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 578                         mask);
 579                 status = -EPERM;
 580                 goto exit;
 581         }
 582
 583         if (value) {
 584                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 585                 if (status)
 586                         goto exit;
 587                 value |= (enable ? RT_IDX_E : 0);
 588                 ql_write32(qdev, RT_IDX, value);
 589                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 590         }
 591 exit:
 592         return status;
 593 }
 594
 595 static void ql_enable_interrupts(struct ql_adapter *qdev)
 596 {
 597         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 598 }
 599
 600 static void ql_disable_interrupts(struct ql_adapter *qdev)
 601 {
 602         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 603 }
 604
 605 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 606  * Otherwise, we may have multiple outstanding workers and don't want to
 607  * enable until the last one finishes. In this case, the irq_cnt gets
 608  * incremented everytime we queue a worker and decremented everytime
 609  * a worker finishes.  Once it hits zero we enable the interrupt.
 610  */
 611 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 612 {
 613         u32 var = 0;
 614         unsigned long hw_flags = 0;
 615         struct intr_context *ctx = qdev->intr_context + intr;
 616
 617         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 618                 /* Always enable if we're MSIX multi interrupts and
 619                  * it's not the default (zeroeth) interrupt.
 620                  */
 621                 ql_write32(qdev, INTR_EN,
 622                            ctx->intr_en_mask);
 623                 var = ql_read32(qdev, STS);
 624                 return var;
 625         }
 626
 627         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 628         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 629                 ql_write32(qdev, INTR_EN,
 630                            ctx->intr_en_mask);
 631                 var = ql_read32(qdev, STS);
 632         }
 633         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 634         return var;
 635 }
 636
 637 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 638 {
 639         u32 var = 0;
 640         struct intr_context *ctx;
 641
 642         /* HW disables for us if we're MSIX multi interrupts and
 643          * it's not the default (zeroeth) interrupt.
 644          */
 645         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 646                 return 0;
 647
 648         ctx = qdev->intr_context + intr;
 649         spin_lock(&qdev->hw_lock);
 650         if (!atomic_read(&ctx->irq_cnt)) {
 651                 ql_write32(qdev, INTR_EN,
 652                 ctx->intr_dis_mask);
 653                 var = ql_read32(qdev, STS);
 654         }
 655         atomic_inc(&ctx->irq_cnt);
 656         spin_unlock(&qdev->hw_lock);
 657         return var;
 658 }
 659
 660 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 661 {
 662         int i;
 663         for (i = 0; i < qdev->intr_count; i++) {
 664                 /* The enable call does a atomic_dec_and_test
 665                  * and enables only if the result is zero.
 666                  * So we precharge it here.
 667                  */
 668                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 669                         i == 0))
 670                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 671                 ql_enable_completion_interrupt(qdev, i);
 672         }
 673
 674 }
 675
 676 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 677 {
 678         int status, i;
 679         u16 csum = 0;
 680         __le16 *flash = (__le16 *)&qdev->flash;
 681
 682         status = strncmp((char *)&qdev->flash, str, 4);
 683         if (status) {
 684                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
 685                 return  status;
 686         }
 687
 688         for (i = 0; i < size; i++)
 689                 csum += le16_to_cpu(*flash++);
 690
 691         if (csum)
 692                 QPRINTK(qdev, IFUP, ERR,
 693                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 694
 695         return csum;
 696 }
 697
 698 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 699 {
 700         int status = 0;
 701         /* wait for reg to come ready */
 702         status = ql_wait_reg_rdy(qdev,
 703                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 704         if (status)
 705                 goto exit;
 706         /* set up for reg read */
 707         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 708         /* wait for reg to come ready */
 709         status = ql_wait_reg_rdy(qdev,
 710                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 711         if (status)
 712                 goto exit;
 713          /* This data is stored on flash as an array of
 714          * __le32.  Since ql_read32() returns cpu endian
 715          * we need to swap it back.
 716          */
 717         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 718 exit:
 719         return status;
 720 }
 721
 722 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 723 {
 724         u32 i, size;
 725         int status;
 726         __le32 *p = (__le32 *)&qdev->flash;
 727         u32 offset;
 728         u8 mac_addr[6];
 729
 730         /* Get flash offset for function and adjust
 731          * for dword access.
 732          */
 733         if (!qdev->port)
 734                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 735         else
 736                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 737
 738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 739                 return -ETIMEDOUT;
 740
 741         size = sizeof(struct flash_params_8000) / sizeof(u32);
 742         for (i = 0; i < size; i++, p++) {
 743                 status = ql_read_flash_word(qdev, i+offset, p);
 744                 if (status) {
 745                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 746                         goto exit;
 747                 }
 748         }
 749
 750         status = ql_validate_flash(qdev,
 751                         sizeof(struct flash_params_8000) / sizeof(u16),
 752                         "8000");
 753         if (status) {
 754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 755                 status = -EINVAL;
 756                 goto exit;
 757         }
 758
 759         /* Extract either manufacturer or BOFM modified
 760          * MAC address.
 761          */
 762         if (qdev->flash.flash_params_8000.data_type1 == 2)
 763                 memcpy(mac_addr,
 764                         qdev->flash.flash_params_8000.mac_addr1,
 765                         qdev->ndev->addr_len);
 766         else
 767                 memcpy(mac_addr,
 768                         qdev->flash.flash_params_8000.mac_addr,
 769                         qdev->ndev->addr_len);
 770
 771         if (!is_valid_ether_addr(mac_addr)) {
 772                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
 773                 status = -EINVAL;
 774                 goto exit;
 775         }
 776
 777         memcpy(qdev->ndev->dev_addr,
 778                 mac_addr,
 779                 qdev->ndev->addr_len);
 780
 781 exit:
 782         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 783         return status;
 784 }
 785
 786 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 787 {
 788         int i;
 789         int status;
 790         __le32 *p = (__le32 *)&qdev->flash;
 791         u32 offset = 0;
 792         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 793
 794         /* Second function's parameters follow the first
 795          * function's.
 796          */
 797         if (qdev->port)
 798                 offset = size;
 799
 800         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 801                 return -ETIMEDOUT;
 802
 803         for (i = 0; i < size; i++, p++) {
 804                 status = ql_read_flash_word(qdev, i+offset, p);
 805                 if (status) {
 806                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 807                         goto exit;
 808                 }
 809
 810         }
 811
 812         status = ql_validate_flash(qdev,
 813                         sizeof(struct flash_params_8012) / sizeof(u16),
 814                         "8012");
 815         if (status) {
 816                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 817                 status = -EINVAL;
 818                 goto exit;
 819         }
 820
 821         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 822                 status = -EINVAL;
 823                 goto exit;
 824         }
 825
 826         memcpy(qdev->ndev->dev_addr,
 827                 qdev->flash.flash_params_8012.mac_addr,
 828                 qdev->ndev->addr_len);
 829
 830 exit:
 831         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 832         return status;
 833 }
 834
 835 /* xgmac register are located behind the xgmac_addr and xgmac_data
 836  * register pair.  Each read/write requires us to wait for the ready
 837  * bit before reading/writing the data.
 838  */
 839 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 840 {
 841         int status;
 842         /* wait for reg to come ready */
 843         status = ql_wait_reg_rdy(qdev,
 844                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 845         if (status)
 846                 return status;
 847         /* write the data to the data reg */
 848         ql_write32(qdev, XGMAC_DATA, data);
 849         /* trigger the write */
 850         ql_write32(qdev, XGMAC_ADDR, reg);
 851         return status;
 852 }
 853
 854 /* xgmac register are located behind the xgmac_addr and xgmac_data
 855  * register pair.  Each read/write requires us to wait for the ready
 856  * bit before reading/writing the data.
 857  */
 858 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 859 {
 860         int status = 0;
 861         /* wait for reg to come ready */
 862         status = ql_wait_reg_rdy(qdev,
 863                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 864         if (status)
 865                 goto exit;
 866         /* set up for reg read */
 867         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 868         /* wait for reg to come ready */
 869         status = ql_wait_reg_rdy(qdev,
 870                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 871         if (status)
 872                 goto exit;
 873         /* get the data */
 874         *data = ql_read32(qdev, XGMAC_DATA);
 875 exit:
 876         return status;
 877 }
 878
 879 /* This is used for reading the 64-bit statistics regs. */
 880 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 881 {
 882         int status = 0;
 883         u32 hi = 0;
 884         u32 lo = 0;
 885
 886         status = ql_read_xgmac_reg(qdev, reg, &lo);
 887         if (status)
 888                 goto exit;
 889
 890         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 891         if (status)
 892                 goto exit;
 893
 894         *data = (u64) lo | ((u64) hi << 32);
 895
 896 exit:
 897         return status;
 898 }
 899
 900 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 901 {
 902         int status;
 903         /*
 904          * Get MPI firmware version for driver banner
 905          * and ethool info.
 906          */
 907         status = ql_mb_about_fw(qdev);
 908         if (status)
 909                 goto exit;
 910         status = ql_mb_get_fw_state(qdev);
 911         if (status)
 912                 goto exit;
 913         /* Wake up a worker to get/set the TX/RX frame sizes. */
 914         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 915 exit:
 916         return status;
 917 }
 918
 919 /* Take the MAC Core out of reset.
 920  * Enable statistics counting.
 921  * Take the transmitter/receiver out of reset.
 922  * This functionality may be done in the MPI firmware at a
 923  * later date.
 924  */
 925 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 926 {
 927         int status = 0;
 928         u32 data;
 929
 930         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 931                 /* Another function has the semaphore, so
 932                  * wait for the port init bit to come ready.
 933                  */
 934                 QPRINTK(qdev, LINK, INFO,
 935                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 936                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 937                 if (status) {
 938                         QPRINTK(qdev, LINK, CRIT,
 939                                 "Port initialize timed out.\n");
 940                 }
 941                 return status;
 942         }
 943
 944         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 945         /* Set the core reset. */
 946         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 947         if (status)
 948                 goto end;
 949         data |= GLOBAL_CFG_RESET;
 950         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 951         if (status)
 952                 goto end;
 953
 954         /* Clear the core reset and turn on jumbo for receiver. */
 955         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 956         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 957         data |= GLOBAL_CFG_TX_STAT_EN;
 958         data |= GLOBAL_CFG_RX_STAT_EN;
 959         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 960         if (status)
 961                 goto end;
 962
 963         /* Enable transmitter, and clear it's reset. */
 964         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 965         if (status)
 966                 goto end;
 967         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 968         data |= TX_CFG_EN;      /* Enable the transmitter. */
 969         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 970         if (status)
 971                 goto end;
 972
 973         /* Enable receiver and clear it's reset. */
 974         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 975         if (status)
 976                 goto end;
 977         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 978         data |= RX_CFG_EN;      /* Enable the receiver. */
 979         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 980         if (status)
 981                 goto end;
 982
 983         /* Turn on jumbo. */
 984         status =
 985             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 986         if (status)
 987                 goto end;
 988         status =
 989             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 990         if (status)
 991                 goto end;
 992
 993         /* Signal to the world that the port is enabled.        */
 994         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 995 end:
 996         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 997         return status;
 998 }
 999
1000 /* Get the next large buffer. */
1001 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1002 {
1003         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1004         rx_ring->lbq_curr_idx++;
1005         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1006                 rx_ring->lbq_curr_idx = 0;
1007         rx_ring->lbq_free_cnt++;
1008         return lbq_desc;
1009 }
1010
1011 /* Get the next small buffer. */
1012 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1013 {
1014         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1015         rx_ring->sbq_curr_idx++;
1016         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1017                 rx_ring->sbq_curr_idx = 0;
1018         rx_ring->sbq_free_cnt++;
1019         return sbq_desc;
1020 }
1021
1022 /* Update an rx ring index. */
1023 static void ql_update_cq(struct rx_ring *rx_ring)
1024 {
1025         rx_ring->cnsmr_idx++;
1026         rx_ring->curr_entry++;
1027         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1028                 rx_ring->cnsmr_idx = 0;
1029                 rx_ring->curr_entry = rx_ring->cq_base;
1030         }
1031 }
1032
1033 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1034 {
1035         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1036 }
1037
1038 /* Process (refill) a large buffer queue. */
1039 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1040 {
1041         u32 clean_idx = rx_ring->lbq_clean_idx;
1042         u32 start_idx = clean_idx;
1043         struct bq_desc *lbq_desc;
1044         u64 map;
1045         int i;
1046
1047         while (rx_ring->lbq_free_cnt > 16) {
1048                 for (i = 0; i < 16; i++) {
1049                         QPRINTK(qdev, RX_STATUS, DEBUG,
1050                                 "lbq: try cleaning clean_idx = %d.\n",
1051                                 clean_idx);
1052                         lbq_desc = &rx_ring->lbq[clean_idx];
1053                         if (lbq_desc->p.lbq_page == NULL) {
1054                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1055                                         "lbq: getting new page for index %d.\n",
1056                                         lbq_desc->index);
1057                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
1058                                 if (lbq_desc->p.lbq_page == NULL) {
1059                                         rx_ring->lbq_clean_idx = clean_idx;
1060                                         QPRINTK(qdev, RX_STATUS, ERR,
1061                                                 "Couldn't get a page.\n");
1062                                         return;
1063                                 }
1064                                 map = pci_map_page(qdev->pdev,
1065                                                    lbq_desc->p.lbq_page,
1066                                                    0, PAGE_SIZE,
1067                                                    PCI_DMA_FROMDEVICE);
1068                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1069                                         rx_ring->lbq_clean_idx = clean_idx;
1070                                         put_page(lbq_desc->p.lbq_page);
1071                                         lbq_desc->p.lbq_page = NULL;
1072                                         QPRINTK(qdev, RX_STATUS, ERR,
1073                                                 "PCI mapping failed.\n");
1074                                         return;
1075                                 }
1076                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1077                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1078                                 *lbq_desc->addr = cpu_to_le64(map);
1079                         }
1080                         clean_idx++;
1081                         if (clean_idx == rx_ring->lbq_len)
1082                                 clean_idx = 0;
1083                 }
1084
1085                 rx_ring->lbq_clean_idx = clean_idx;
1086                 rx_ring->lbq_prod_idx += 16;
1087                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1088                         rx_ring->lbq_prod_idx = 0;
1089                 rx_ring->lbq_free_cnt -= 16;
1090         }
1091
1092         if (start_idx != clean_idx) {
1093                 QPRINTK(qdev, RX_STATUS, DEBUG,
1094                         "lbq: updating prod idx = %d.\n",
1095                         rx_ring->lbq_prod_idx);
1096                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1097                                 rx_ring->lbq_prod_idx_db_reg);
1098         }
1099 }
1100
1101 /* Process (refill) a small buffer queue. */
1102 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1103 {
1104         u32 clean_idx = rx_ring->sbq_clean_idx;
1105         u32 start_idx = clean_idx;
1106         struct bq_desc *sbq_desc;
1107         u64 map;
1108         int i;
1109
1110         while (rx_ring->sbq_free_cnt > 16) {
1111                 for (i = 0; i < 16; i++) {
1112                         sbq_desc = &rx_ring->sbq[clean_idx];
1113                         QPRINTK(qdev, RX_STATUS, DEBUG,
1114                                 "sbq: try cleaning clean_idx = %d.\n",
1115                                 clean_idx);
1116                         if (sbq_desc->p.skb == NULL) {
1117                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1118                                         "sbq: getting new skb for index %d.\n",
1119                                         sbq_desc->index);
1120                                 sbq_desc->p.skb =
1121                                     netdev_alloc_skb(qdev->ndev,
1122                                                      rx_ring->sbq_buf_size);
1123                                 if (sbq_desc->p.skb == NULL) {
1124                                         QPRINTK(qdev, PROBE, ERR,
1125                                                 "Couldn't get an skb.\n");
1126                                         rx_ring->sbq_clean_idx = clean_idx;
1127                                         return;
1128                                 }
1129                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1130                                 map = pci_map_single(qdev->pdev,
1131                                                      sbq_desc->p.skb->data,
1132                                                      rx_ring->sbq_buf_size /
1133                                                      2, PCI_DMA_FROMDEVICE);
1134                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1135                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1136                                         rx_ring->sbq_clean_idx = clean_idx;
1137                                         dev_kfree_skb_any(sbq_desc->p.skb);
1138                                         sbq_desc->p.skb = NULL;
1139                                         return;
1140                                 }
1141                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1142                                 pci_unmap_len_set(sbq_desc, maplen,
1143                                                   rx_ring->sbq_buf_size / 2);
1144                                 *sbq_desc->addr = cpu_to_le64(map);
1145                         }
1146
1147                         clean_idx++;
1148                         if (clean_idx == rx_ring->sbq_len)
1149                                 clean_idx = 0;
1150                 }
1151                 rx_ring->sbq_clean_idx = clean_idx;
1152                 rx_ring->sbq_prod_idx += 16;
1153                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1154                         rx_ring->sbq_prod_idx = 0;
1155                 rx_ring->sbq_free_cnt -= 16;
1156         }
1157
1158         if (start_idx != clean_idx) {
1159                 QPRINTK(qdev, RX_STATUS, DEBUG,
1160                         "sbq: updating prod idx = %d.\n",
1161                         rx_ring->sbq_prod_idx);
1162                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1163                                 rx_ring->sbq_prod_idx_db_reg);
1164         }
1165 }
1166
1167 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1168                                     struct rx_ring *rx_ring)
1169 {
1170         ql_update_sbq(qdev, rx_ring);
1171         ql_update_lbq(qdev, rx_ring);
1172 }
1173
1174 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1175  * fails at some stage, or from the interrupt when a tx completes.
1176  */
1177 static void ql_unmap_send(struct ql_adapter *qdev,
1178                           struct tx_ring_desc *tx_ring_desc, int mapped)
1179 {
1180         int i;
1181         for (i = 0; i < mapped; i++) {
1182                 if (i == 0 || (i == 7 && mapped > 7)) {
1183                         /*
1184                          * Unmap the skb->data area, or the
1185                          * external sglist (AKA the Outbound
1186                          * Address List (OAL)).
1187                          * If its the zeroeth element, then it's
1188                          * the skb->data area.  If it's the 7th
1189                          * element and there is more than 6 frags,
1190                          * then its an OAL.
1191                          */
1192                         if (i == 7) {
1193                                 QPRINTK(qdev, TX_DONE, DEBUG,
1194                                         "unmapping OAL area.\n");
1195                         }
1196                         pci_unmap_single(qdev->pdev,
1197                                          pci_unmap_addr(&tx_ring_desc->map[i],
1198                                                         mapaddr),
1199                                          pci_unmap_len(&tx_ring_desc->map[i],
1200                                                        maplen),
1201                                          PCI_DMA_TODEVICE);
1202                 } else {
1203                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1204                                 i);
1205                         pci_unmap_page(qdev->pdev,
1206                                        pci_unmap_addr(&tx_ring_desc->map[i],
1207                                                       mapaddr),
1208                                        pci_unmap_len(&tx_ring_desc->map[i],
1209                                                      maplen), PCI_DMA_TODEVICE);
1210                 }
1211         }
1212
1213 }
1214
1215 /* Map the buffers for this transmit.  This will return
1216  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1217  */
1218 static int ql_map_send(struct ql_adapter *qdev,
1219                        struct ob_mac_iocb_req *mac_iocb_ptr,
1220                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1221 {
1222         int len = skb_headlen(skb);
1223         dma_addr_t map;
1224         int frag_idx, err, map_idx = 0;
1225         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1226         int frag_cnt = skb_shinfo(skb)->nr_frags;
1227
1228         if (frag_cnt) {
1229                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1230         }
1231         /*
1232          * Map the skb buffer first.
1233          */
1234         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1235
1236         err = pci_dma_mapping_error(qdev->pdev, map);
1237         if (err) {
1238                 QPRINTK(qdev, TX_QUEUED, ERR,
1239                         "PCI mapping failed with error: %d\n", err);
1240
1241                 return NETDEV_TX_BUSY;
1242         }
1243
1244         tbd->len = cpu_to_le32(len);
1245         tbd->addr = cpu_to_le64(map);
1246         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1247         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1248         map_idx++;
1249
1250         /*
1251          * This loop fills the remainder of the 8 address descriptors
1252          * in the IOCB.  If there are more than 7 fragments, then the
1253          * eighth address desc will point to an external list (OAL).
1254          * When this happens, the remainder of the frags will be stored
1255          * in this list.
1256          */
1257         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1258                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1259                 tbd++;
1260                 if (frag_idx == 6 && frag_cnt > 7) {
1261                         /* Let's tack on an sglist.
1262                          * Our control block will now
1263                          * look like this:
1264                          * iocb->seg[0] = skb->data
1265                          * iocb->seg[1] = frag[0]
1266                          * iocb->seg[2] = frag[1]
1267                          * iocb->seg[3] = frag[2]
1268                          * iocb->seg[4] = frag[3]
1269                          * iocb->seg[5] = frag[4]
1270                          * iocb->seg[6] = frag[5]
1271                          * iocb->seg[7] = ptr to OAL (external sglist)
1272                          * oal->seg[0] = frag[6]
1273                          * oal->seg[1] = frag[7]
1274                          * oal->seg[2] = frag[8]
1275                          * oal->seg[3] = frag[9]
1276                          * oal->seg[4] = frag[10]
1277                          *      etc...
1278                          */
1279                         /* Tack on the OAL in the eighth segment of IOCB. */
1280                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1281                                              sizeof(struct oal),
1282                                              PCI_DMA_TODEVICE);
1283                         err = pci_dma_mapping_error(qdev->pdev, map);
1284                         if (err) {
1285                                 QPRINTK(qdev, TX_QUEUED, ERR,
1286                                         "PCI mapping outbound address list with error: %d\n",
1287                                         err);
1288                                 goto map_error;
1289                         }
1290
1291                         tbd->addr = cpu_to_le64(map);
1292                         /*
1293                          * The length is the number of fragments
1294                          * that remain to be mapped times the length
1295                          * of our sglist (OAL).
1296                          */
1297                         tbd->len =
1298                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1299                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1300                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1301                                            map);
1302                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1303                                           sizeof(struct oal));
1304                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1305                         map_idx++;
1306                 }
1307
1308                 map =
1309                     pci_map_page(qdev->pdev, frag->page,
1310                                  frag->page_offset, frag->size,
1311                                  PCI_DMA_TODEVICE);
1312
1313                 err = pci_dma_mapping_error(qdev->pdev, map);
1314                 if (err) {
1315                         QPRINTK(qdev, TX_QUEUED, ERR,
1316                                 "PCI mapping frags failed with error: %d.\n",
1317                                 err);
1318                         goto map_error;
1319                 }
1320
1321                 tbd->addr = cpu_to_le64(map);
1322                 tbd->len = cpu_to_le32(frag->size);
1323                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1324                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1325                                   frag->size);
1326
1327         }
1328         /* Save the number of segments we've mapped. */
1329         tx_ring_desc->map_cnt = map_idx;
1330         /* Terminate the last segment. */
1331         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1332         return NETDEV_TX_OK;
1333
1334 map_error:
1335         /*
1336          * If the first frag mapping failed, then i will be zero.
1337          * This causes the unmap of the skb->data area.  Otherwise
1338          * we pass in the number of frags that mapped successfully
1339          * so they can be umapped.
1340          */
1341         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1342         return NETDEV_TX_BUSY;
1343 }
1344
1345 static void ql_realign_skb(struct sk_buff *skb, int len)
1346 {
1347         void *temp_addr = skb->data;
1348
1349         /* Undo the skb_reserve(skb,32) we did before
1350          * giving to hardware, and realign data on
1351          * a 2-byte boundary.
1352          */
1353         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1354         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1355         skb_copy_to_linear_data(skb, temp_addr,
1356                 (unsigned int)len);
1357 }
1358
1359 /*
1360  * This function builds an skb for the given inbound
1361  * completion.  It will be rewritten for readability in the near
1362  * future, but for not it works well.
1363  */
1364 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1365                                        struct rx_ring *rx_ring,
1366                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1367 {
1368         struct bq_desc *lbq_desc;
1369         struct bq_desc *sbq_desc;
1370         struct sk_buff *skb = NULL;
1371         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1372        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1373
1374         /*
1375          * Handle the header buffer if present.
1376          */
1377         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1378             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1379                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1380                 /*
1381                  * Headers fit nicely into a small buffer.
1382                  */
1383                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1384                 pci_unmap_single(qdev->pdev,
1385                                 pci_unmap_addr(sbq_desc, mapaddr),
1386                                 pci_unmap_len(sbq_desc, maplen),
1387                                 PCI_DMA_FROMDEVICE);
1388                 skb = sbq_desc->p.skb;
1389                 ql_realign_skb(skb, hdr_len);
1390                 skb_put(skb, hdr_len);
1391                 sbq_desc->p.skb = NULL;
1392         }
1393
1394         /*
1395          * Handle the data buffer(s).
1396          */
1397         if (unlikely(!length)) {        /* Is there data too? */
1398                 QPRINTK(qdev, RX_STATUS, DEBUG,
1399                         "No Data buffer in this packet.\n");
1400                 return skb;
1401         }
1402
1403         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1404                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1405                         QPRINTK(qdev, RX_STATUS, DEBUG,
1406                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1407                         /*
1408                          * Data is less than small buffer size so it's
1409                          * stuffed in a small buffer.
1410                          * For this case we append the data
1411                          * from the "data" small buffer to the "header" small
1412                          * buffer.
1413                          */
1414                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1415                         pci_dma_sync_single_for_cpu(qdev->pdev,
1416                                                     pci_unmap_addr
1417                                                     (sbq_desc, mapaddr),
1418                                                     pci_unmap_len
1419                                                     (sbq_desc, maplen),
1420                                                     PCI_DMA_FROMDEVICE);
1421                         memcpy(skb_put(skb, length),
1422                                sbq_desc->p.skb->data, length);
1423                         pci_dma_sync_single_for_device(qdev->pdev,
1424                                                        pci_unmap_addr
1425                                                        (sbq_desc,
1426                                                         mapaddr),
1427                                                        pci_unmap_len
1428                                                        (sbq_desc,
1429                                                         maplen),
1430                                                        PCI_DMA_FROMDEVICE);
1431                 } else {
1432                         QPRINTK(qdev, RX_STATUS, DEBUG,
1433                                 "%d bytes in a single small buffer.\n", length);
1434                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1435                         skb = sbq_desc->p.skb;
1436                         ql_realign_skb(skb, length);
1437                         skb_put(skb, length);
1438                         pci_unmap_single(qdev->pdev,
1439                                          pci_unmap_addr(sbq_desc,
1440                                                         mapaddr),
1441                                          pci_unmap_len(sbq_desc,
1442                                                        maplen),
1443                                          PCI_DMA_FROMDEVICE);
1444                         sbq_desc->p.skb = NULL;
1445                 }
1446         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1447                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1448                         QPRINTK(qdev, RX_STATUS, DEBUG,
1449                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1450                         /*
1451                          * The data is in a single large buffer.  We
1452                          * chain it to the header buffer's skb and let
1453                          * it rip.
1454                          */
1455                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1456                         pci_unmap_page(qdev->pdev,
1457                                        pci_unmap_addr(lbq_desc,
1458                                                       mapaddr),
1459                                        pci_unmap_len(lbq_desc, maplen),
1460                                        PCI_DMA_FROMDEVICE);
1461                         QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                 "Chaining page to skb.\n");
1463                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1464                                            0, length);
1465                         skb->len += length;
1466                         skb->data_len += length;
1467                         skb->truesize += length;
1468                         lbq_desc->p.lbq_page = NULL;
1469                 } else {
1470                         /*
1471                          * The headers and data are in a single large buffer. We
1472                          * copy it to a new skb and let it go. This can happen with
1473                          * jumbo mtu on a non-TCP/UDP frame.
1474                          */
1475                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1476                         skb = netdev_alloc_skb(qdev->ndev, length);
1477                         if (skb == NULL) {
1478                                 QPRINTK(qdev, PROBE, DEBUG,
1479                                         "No skb available, drop the packet.\n");
1480                                 return NULL;
1481                         }
1482                         pci_unmap_page(qdev->pdev,
1483                                        pci_unmap_addr(lbq_desc,
1484                                                       mapaddr),
1485                                        pci_unmap_len(lbq_desc, maplen),
1486                                        PCI_DMA_FROMDEVICE);
1487                         skb_reserve(skb, NET_IP_ALIGN);
1488                         QPRINTK(qdev, RX_STATUS, DEBUG,
1489                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1490                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1491                                            0, length);
1492                         skb->len += length;
1493                         skb->data_len += length;
1494                         skb->truesize += length;
1495                         length -= length;
1496                         lbq_desc->p.lbq_page = NULL;
1497                         __pskb_pull_tail(skb,
1498                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1499                                 VLAN_ETH_HLEN : ETH_HLEN);
1500                 }
1501         } else {
1502                 /*
1503                  * The data is in a chain of large buffers
1504                  * pointed to by a small buffer.  We loop
1505                  * thru and chain them to the our small header
1506                  * buffer's skb.
1507                  * frags:  There are 18 max frags and our small
1508                  *         buffer will hold 32 of them. The thing is,
1509                  *         we'll use 3 max for our 9000 byte jumbo
1510                  *         frames.  If the MTU goes up we could
1511                  *          eventually be in trouble.
1512                  */
1513                 int size, offset, i = 0;
1514                 __le64 *bq, bq_array[8];
1515                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1516                 pci_unmap_single(qdev->pdev,
1517                                  pci_unmap_addr(sbq_desc, mapaddr),
1518                                  pci_unmap_len(sbq_desc, maplen),
1519                                  PCI_DMA_FROMDEVICE);
1520                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1521                         /*
1522                          * This is an non TCP/UDP IP frame, so
1523                          * the headers aren't split into a small
1524                          * buffer.  We have to use the small buffer
1525                          * that contains our sg list as our skb to
1526                          * send upstairs. Copy the sg list here to
1527                          * a local buffer and use it to find the
1528                          * pages to chain.
1529                          */
1530                         QPRINTK(qdev, RX_STATUS, DEBUG,
1531                                 "%d bytes of headers & data in chain of large.\n", length);
1532                         skb = sbq_desc->p.skb;
1533                         bq = &bq_array[0];
1534                         memcpy(bq, skb->data, sizeof(bq_array));
1535                         sbq_desc->p.skb = NULL;
1536                         skb_reserve(skb, NET_IP_ALIGN);
1537                 } else {
1538                         QPRINTK(qdev, RX_STATUS, DEBUG,
1539                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1540                         bq = (__le64 *)sbq_desc->p.skb->data;
1541                 }
1542                 while (length > 0) {
1543                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1544                         pci_unmap_page(qdev->pdev,
1545                                        pci_unmap_addr(lbq_desc,
1546                                                       mapaddr),
1547                                        pci_unmap_len(lbq_desc,
1548                                                      maplen),
1549                                        PCI_DMA_FROMDEVICE);
1550                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1551                         offset = 0;
1552
1553                         QPRINTK(qdev, RX_STATUS, DEBUG,
1554                                 "Adding page %d to skb for %d bytes.\n",
1555                                 i, size);
1556                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1557                                            offset, size);
1558                         skb->len += size;
1559                         skb->data_len += size;
1560                         skb->truesize += size;
1561                         length -= size;
1562                         lbq_desc->p.lbq_page = NULL;
1563                         bq++;
1564                         i++;
1565                 }
1566                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1567                                 VLAN_ETH_HLEN : ETH_HLEN);
1568         }
1569         return skb;
1570 }
1571
1572 /* Process an inbound completion from an rx ring. */
1573 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1574                                    struct rx_ring *rx_ring,
1575                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1576 {
1577         struct net_device *ndev = qdev->ndev;
1578         struct sk_buff *skb = NULL;
1579         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1580                         IB_MAC_IOCB_RSP_VLAN_MASK)
1581
1582         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1583
1584         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1585         if (unlikely(!skb)) {
1586                 QPRINTK(qdev, RX_STATUS, DEBUG,
1587                         "No skb available, drop packet.\n");
1588                 return;
1589         }
1590
1591         /* Frame error, so drop the packet. */
1592         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1593                 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1594                                         ib_mac_rsp->flags2);
1595                 dev_kfree_skb_any(skb);
1596                 return;
1597         }
1598
1599         /* The max framesize filter on this chip is set higher than
1600          * MTU since FCoE uses 2k frames.
1601          */
1602         if (skb->len > ndev->mtu + ETH_HLEN) {
1603                 dev_kfree_skb_any(skb);
1604                 return;
1605         }
1606
1607         prefetch(skb->data);
1608         skb->dev = ndev;
1609         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1610                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1611                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1612                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1613                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1614                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1615                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1616                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1617         }
1618         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1619                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1620         }
1621
1622         skb->protocol = eth_type_trans(skb, ndev);
1623         skb->ip_summed = CHECKSUM_NONE;
1624
1625         /* If rx checksum is on, and there are no
1626          * csum or frame errors.
1627          */
1628         if (qdev->rx_csum &&
1629                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1630                 /* TCP frame. */
1631                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1632                         QPRINTK(qdev, RX_STATUS, DEBUG,
1633                                         "TCP checksum done!\n");
1634                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1635                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1636                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1637                 /* Unfragmented ipv4 UDP frame. */
1638                         struct iphdr *iph = (struct iphdr *) skb->data;
1639                         if (!(iph->frag_off &
1640                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1641                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1642                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1643                                                 "TCP checksum done!\n");
1644                         }
1645                 }
1646         }
1647
1648         qdev->stats.rx_packets++;
1649         qdev->stats.rx_bytes += skb->len;
1650         skb_record_rx_queue(skb, rx_ring->cq_id);
1651         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1652                 if (qdev->vlgrp &&
1653                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1654                         (vlan_id != 0))
1655                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1656                                 vlan_id, skb);
1657                 else
1658                         napi_gro_receive(&rx_ring->napi, skb);
1659         } else {
1660                 if (qdev->vlgrp &&
1661                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1662                         (vlan_id != 0))
1663                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1664                 else
1665                         netif_receive_skb(skb);
1666         }
1667 }
1668
1669 /* Process an outbound completion from an rx ring. */
1670 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1671                                    struct ob_mac_iocb_rsp *mac_rsp)
1672 {
1673         struct tx_ring *tx_ring;
1674         struct tx_ring_desc *tx_ring_desc;
1675
1676         QL_DUMP_OB_MAC_RSP(mac_rsp);
1677         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1678         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1679         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1680         qdev->stats.tx_bytes += (tx_ring_desc->skb)->len;
1681         qdev->stats.tx_packets++;
1682         dev_kfree_skb(tx_ring_desc->skb);
1683         tx_ring_desc->skb = NULL;
1684
1685         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1686                                         OB_MAC_IOCB_RSP_S |
1687                                         OB_MAC_IOCB_RSP_L |
1688                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1689                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1690                         QPRINTK(qdev, TX_DONE, WARNING,
1691                                 "Total descriptor length did not match transfer length.\n");
1692                 }
1693                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1694                         QPRINTK(qdev, TX_DONE, WARNING,
1695                                 "Frame too short to be legal, not sent.\n");
1696                 }
1697                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1698                         QPRINTK(qdev, TX_DONE, WARNING,
1699                                 "Frame too long, but sent anyway.\n");
1700                 }
1701                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1702                         QPRINTK(qdev, TX_DONE, WARNING,
1703                                 "PCI backplane error. Frame not sent.\n");
1704                 }
1705         }
1706         atomic_inc(&tx_ring->tx_count);
1707 }
1708
1709 /* Fire up a handler to reset the MPI processor. */
1710 void ql_queue_fw_error(struct ql_adapter *qdev)
1711 {
1712         ql_link_off(qdev);
1713         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1714 }
1715
1716 void ql_queue_asic_error(struct ql_adapter *qdev)
1717 {
1718         ql_link_off(qdev);
1719         ql_disable_interrupts(qdev);
1720         /* Clear adapter up bit to signal the recovery
1721          * process that it shouldn't kill the reset worker
1722          * thread
1723          */
1724         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1725         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1726 }
1727
1728 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1729                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1730 {
1731         switch (ib_ae_rsp->event) {
1732         case MGMT_ERR_EVENT:
1733                 QPRINTK(qdev, RX_ERR, ERR,
1734                         "Management Processor Fatal Error.\n");
1735                 ql_queue_fw_error(qdev);
1736                 return;
1737
1738         case CAM_LOOKUP_ERR_EVENT:
1739                 QPRINTK(qdev, LINK, ERR,
1740                         "Multiple CAM hits lookup occurred.\n");
1741                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1742                 ql_queue_asic_error(qdev);
1743                 return;
1744
1745         case SOFT_ECC_ERROR_EVENT:
1746                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1747                 ql_queue_asic_error(qdev);
1748                 break;
1749
1750         case PCI_ERR_ANON_BUF_RD:
1751                 QPRINTK(qdev, RX_ERR, ERR,
1752                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1753                         ib_ae_rsp->q_id);
1754                 ql_queue_asic_error(qdev);
1755                 break;
1756
1757         default:
1758                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1759                         ib_ae_rsp->event);
1760                 ql_queue_asic_error(qdev);
1761                 break;
1762         }
1763 }
1764
1765 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1766 {
1767         struct ql_adapter *qdev = rx_ring->qdev;
1768         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1769         struct ob_mac_iocb_rsp *net_rsp = NULL;
1770         int count = 0;
1771
1772         struct tx_ring *tx_ring;
1773         /* While there are entries in the completion queue. */
1774         while (prod != rx_ring->cnsmr_idx) {
1775
1776                 QPRINTK(qdev, RX_STATUS, DEBUG,
1777                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1778                         prod, rx_ring->cnsmr_idx);
1779
1780                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1781                 rmb();
1782                 switch (net_rsp->opcode) {
1783
1784                 case OPCODE_OB_MAC_TSO_IOCB:
1785                 case OPCODE_OB_MAC_IOCB:
1786                         ql_process_mac_tx_intr(qdev, net_rsp);
1787                         break;
1788                 default:
1789                         QPRINTK(qdev, RX_STATUS, DEBUG,
1790                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1791                                 net_rsp->opcode);
1792                 }
1793                 count++;
1794                 ql_update_cq(rx_ring);
1795                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1796         }
1797         ql_write_cq_idx(rx_ring);
1798         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1799         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1800                                         net_rsp != NULL) {
1801                 if (atomic_read(&tx_ring->queue_stopped) &&
1802                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1803                         /*
1804                          * The queue got stopped because the tx_ring was full.
1805                          * Wake it up, because it's now at least 25% empty.
1806                          */
1807                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1808         }
1809
1810         return count;
1811 }
1812
1813 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1814 {
1815         struct ql_adapter *qdev = rx_ring->qdev;
1816         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1817         struct ql_net_rsp_iocb *net_rsp;
1818         int count = 0;
1819
1820         /* While there are entries in the completion queue. */
1821         while (prod != rx_ring->cnsmr_idx) {
1822
1823                 QPRINTK(qdev, RX_STATUS, DEBUG,
1824                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1825                         prod, rx_ring->cnsmr_idx);
1826
1827                 net_rsp = rx_ring->curr_entry;
1828                 rmb();
1829                 switch (net_rsp->opcode) {
1830                 case OPCODE_IB_MAC_IOCB:
1831                         ql_process_mac_rx_intr(qdev, rx_ring,
1832                                                (struct ib_mac_iocb_rsp *)
1833                                                net_rsp);
1834                         break;
1835
1836                 case OPCODE_IB_AE_IOCB:
1837                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1838                                                 net_rsp);
1839                         break;
1840                 default:
1841                         {
1842                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1843                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1844                                         net_rsp->opcode);
1845                         }
1846                 }
1847                 count++;
1848                 ql_update_cq(rx_ring);
1849                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1850                 if (count == budget)
1851                         break;
1852         }
1853         ql_update_buffer_queues(qdev, rx_ring);
1854         ql_write_cq_idx(rx_ring);
1855         return count;
1856 }
1857
1858 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1859 {
1860         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1861         struct ql_adapter *qdev = rx_ring->qdev;
1862         struct rx_ring *trx_ring;
1863         int i, work_done = 0;
1864         struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
1865
1866         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1867                 rx_ring->cq_id);
1868
1869         /* Service the TX rings first.  They start
1870          * right after the RSS rings. */
1871         for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
1872                 trx_ring = &qdev->rx_ring[i];
1873                 /* If this TX completion ring belongs to this vector and
1874                  * it's not empty then service it.
1875                  */
1876                 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
1877                         (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
1878                                         trx_ring->cnsmr_idx)) {
1879                         QPRINTK(qdev, INTR, DEBUG,
1880                                 "%s: Servicing TX completion ring %d.\n",
1881                                 __func__, trx_ring->cq_id);
1882                         ql_clean_outbound_rx_ring(trx_ring);
1883                 }
1884         }
1885
1886         /*
1887          * Now service the RSS ring if it's active.
1888          */
1889         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1890                                         rx_ring->cnsmr_idx) {
1891                 QPRINTK(qdev, INTR, DEBUG,
1892                         "%s: Servicing RX completion ring %d.\n",
1893                         __func__, rx_ring->cq_id);
1894                 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1895         }
1896
1897         if (work_done < budget) {
1898                 napi_complete(napi);
1899                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1900         }
1901         return work_done;
1902 }
1903
1904 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1905 {
1906         struct ql_adapter *qdev = netdev_priv(ndev);
1907
1908         qdev->vlgrp = grp;
1909         if (grp) {
1910                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1911                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1912                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1913         } else {
1914                 QPRINTK(qdev, IFUP, DEBUG,
1915                         "Turning off VLAN in NIC_RCV_CFG.\n");
1916                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1917         }
1918 }
1919
1920 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1921 {
1922         struct ql_adapter *qdev = netdev_priv(ndev);
1923         u32 enable_bit = MAC_ADDR_E;
1924         int status;
1925
1926         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1927         if (status)
1928                 return;
1929         spin_lock(&qdev->hw_lock);
1930         if (ql_set_mac_addr_reg
1931             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1932                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1933         }
1934         spin_unlock(&qdev->hw_lock);
1935         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1936 }
1937
1938 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1939 {
1940         struct ql_adapter *qdev = netdev_priv(ndev);
1941         u32 enable_bit = 0;
1942         int status;
1943
1944         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1945         if (status)
1946                 return;
1947
1948         spin_lock(&qdev->hw_lock);
1949         if (ql_set_mac_addr_reg
1950             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1951                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1952         }
1953         spin_unlock(&qdev->hw_lock);
1954         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1955
1956 }
1957
1958 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1959 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1960 {
1961         struct rx_ring *rx_ring = dev_id;
1962         napi_schedule(&rx_ring->napi);
1963         return IRQ_HANDLED;
1964 }
1965
1966 /* This handles a fatal error, MPI activity, and the default
1967  * rx_ring in an MSI-X multiple vector environment.
1968  * In MSI/Legacy environment it also process the rest of
1969  * the rx_rings.
1970  */
1971 static irqreturn_t qlge_isr(int irq, void *dev_id)
1972 {
1973         struct rx_ring *rx_ring = dev_id;
1974         struct ql_adapter *qdev = rx_ring->qdev;
1975         struct intr_context *intr_context = &qdev->intr_context[0];
1976         u32 var;
1977         int work_done = 0;
1978
1979         spin_lock(&qdev->hw_lock);
1980         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1981                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1982                 spin_unlock(&qdev->hw_lock);
1983                 return IRQ_NONE;
1984         }
1985         spin_unlock(&qdev->hw_lock);
1986
1987         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1988
1989         /*
1990          * Check for fatal error.
1991          */
1992         if (var & STS_FE) {
1993                 ql_queue_asic_error(qdev);
1994                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1995                 var = ql_read32(qdev, ERR_STS);
1996                 QPRINTK(qdev, INTR, ERR,
1997                         "Resetting chip. Error Status Register = 0x%x\n", var);
1998                 return IRQ_HANDLED;
1999         }
2000
2001         /*
2002          * Check MPI processor activity.
2003          */
2004         if (var & STS_PI) {
2005                 /*
2006                  * We've got an async event or mailbox completion.
2007                  * Handle it and clear the source of the interrupt.
2008                  */
2009                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
2010                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2011                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
2012                                       &qdev->mpi_work, 0);
2013                 work_done++;
2014         }
2015
2016         /*
2017          * Get the bit-mask that shows the active queues for this
2018          * pass.  Compare it to the queues that this irq services
2019          * and call napi if there's a match.
2020          */
2021         var = ql_read32(qdev, ISR1);
2022         if (var & intr_context->irq_mask) {
2023                                 QPRINTK(qdev, INTR, INFO,
2024                         "Waking handler for rx_ring[0].\n");
2025                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2026                                         napi_schedule(&rx_ring->napi);
2027                                 work_done++;
2028                         }
2029         ql_enable_completion_interrupt(qdev, intr_context->intr);
2030         return work_done ? IRQ_HANDLED : IRQ_NONE;
2031 }
2032
2033 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2034 {
2035
2036         if (skb_is_gso(skb)) {
2037                 int err;
2038                 if (skb_header_cloned(skb)) {
2039                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2040                         if (err)
2041                                 return err;
2042                 }
2043
2044                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2045                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2046                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2047                 mac_iocb_ptr->total_hdrs_len =
2048                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2049                 mac_iocb_ptr->net_trans_offset =
2050                     cpu_to_le16(skb_network_offset(skb) |
2051                                 skb_transport_offset(skb)
2052                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
2053                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2054                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2055                 if (likely(skb->protocol == htons(ETH_P_IP))) {
2056                         struct iphdr *iph = ip_hdr(skb);
2057                         iph->check = 0;
2058                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2059                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2060                                                                  iph->daddr, 0,
2061                                                                  IPPROTO_TCP,
2062                                                                  0);
2063                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2064                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2065                         tcp_hdr(skb)->check =
2066                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2067                                              &ipv6_hdr(skb)->daddr,
2068                                              0, IPPROTO_TCP, 0);
2069                 }
2070                 return 1;
2071         }
2072         return 0;
2073 }
2074
2075 static void ql_hw_csum_setup(struct sk_buff *skb,
2076                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2077 {
2078         int len;
2079         struct iphdr *iph = ip_hdr(skb);
2080         __sum16 *check;
2081         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2082         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2083         mac_iocb_ptr->net_trans_offset =
2084                 cpu_to_le16(skb_network_offset(skb) |
2085                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2086
2087         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2088         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2089         if (likely(iph->protocol == IPPROTO_TCP)) {
2090                 check = &(tcp_hdr(skb)->check);
2091                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2092                 mac_iocb_ptr->total_hdrs_len =
2093                     cpu_to_le16(skb_transport_offset(skb) +
2094                                 (tcp_hdr(skb)->doff << 2));
2095         } else {
2096                 check = &(udp_hdr(skb)->check);
2097                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2098                 mac_iocb_ptr->total_hdrs_len =
2099                     cpu_to_le16(skb_transport_offset(skb) +
2100                                 sizeof(struct udphdr));
2101         }
2102         *check = ~csum_tcpudp_magic(iph->saddr,
2103                                     iph->daddr, len, iph->protocol, 0);
2104 }
2105
2106 static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
2107 {
2108         struct tx_ring_desc *tx_ring_desc;
2109         struct ob_mac_iocb_req *mac_iocb_ptr;
2110         struct ql_adapter *qdev = netdev_priv(ndev);
2111         int tso;
2112         struct tx_ring *tx_ring;
2113         u32 tx_ring_idx = (u32) skb->queue_mapping;
2114
2115         tx_ring = &qdev->tx_ring[tx_ring_idx];
2116
2117         if (skb_padto(skb, ETH_ZLEN))
2118                 return NETDEV_TX_OK;
2119
2120         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2121                 QPRINTK(qdev, TX_QUEUED, INFO,
2122                         "%s: shutting down tx queue %d du to lack of resources.\n",
2123                         __func__, tx_ring_idx);
2124                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2125                 atomic_inc(&tx_ring->queue_stopped);
2126                 return NETDEV_TX_BUSY;
2127         }
2128         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2129         mac_iocb_ptr = tx_ring_desc->queue_entry;
2130         memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2131
2132         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2133         mac_iocb_ptr->tid = tx_ring_desc->index;
2134         /* We use the upper 32-bits to store the tx queue for this IO.
2135          * When we get the completion we can use it to establish the context.
2136          */
2137         mac_iocb_ptr->txq_idx = tx_ring_idx;
2138         tx_ring_desc->skb = skb;
2139
2140         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2141
2142         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2143                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2144                         vlan_tx_tag_get(skb));
2145                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2146                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2147         }
2148         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2149         if (tso < 0) {
2150                 dev_kfree_skb_any(skb);
2151                 return NETDEV_TX_OK;
2152         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2153                 ql_hw_csum_setup(skb,
2154                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2155         }
2156         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2157                         NETDEV_TX_OK) {
2158                 QPRINTK(qdev, TX_QUEUED, ERR,
2159                                 "Could not map the segments.\n");
2160                 return NETDEV_TX_BUSY;
2161         }
2162         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2163         tx_ring->prod_idx++;
2164         if (tx_ring->prod_idx == tx_ring->wq_len)
2165                 tx_ring->prod_idx = 0;
2166         wmb();
2167
2168         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2169         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2170                 tx_ring->prod_idx, skb->len);
2171
2172         atomic_dec(&tx_ring->tx_count);
2173         return NETDEV_TX_OK;
2174 }
2175
2176 static void ql_free_shadow_space(struct ql_adapter *qdev)
2177 {
2178         if (qdev->rx_ring_shadow_reg_area) {
2179                 pci_free_consistent(qdev->pdev,
2180                                     PAGE_SIZE,
2181                                     qdev->rx_ring_shadow_reg_area,
2182                                     qdev->rx_ring_shadow_reg_dma);
2183                 qdev->rx_ring_shadow_reg_area = NULL;
2184         }
2185         if (qdev->tx_ring_shadow_reg_area) {
2186                 pci_free_consistent(qdev->pdev,
2187                                     PAGE_SIZE,
2188                                     qdev->tx_ring_shadow_reg_area,
2189                                     qdev->tx_ring_shadow_reg_dma);
2190                 qdev->tx_ring_shadow_reg_area = NULL;
2191         }
2192 }
2193
2194 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2195 {
2196         qdev->rx_ring_shadow_reg_area =
2197             pci_alloc_consistent(qdev->pdev,
2198                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2199         if (qdev->rx_ring_shadow_reg_area == NULL) {
2200                 QPRINTK(qdev, IFUP, ERR,
2201                         "Allocation of RX shadow space failed.\n");
2202                 return -ENOMEM;
2203         }
2204         memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2205         qdev->tx_ring_shadow_reg_area =
2206             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2207                                  &qdev->tx_ring_shadow_reg_dma);
2208         if (qdev->tx_ring_shadow_reg_area == NULL) {
2209                 QPRINTK(qdev, IFUP, ERR,
2210                         "Allocation of TX shadow space failed.\n");
2211                 goto err_wqp_sh_area;
2212         }
2213         memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2214         return 0;
2215
2216 err_wqp_sh_area:
2217         pci_free_consistent(qdev->pdev,
2218                             PAGE_SIZE,
2219                             qdev->rx_ring_shadow_reg_area,
2220                             qdev->rx_ring_shadow_reg_dma);
2221         return -ENOMEM;
2222 }
2223
2224 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2225 {
2226         struct tx_ring_desc *tx_ring_desc;
2227         int i;
2228         struct ob_mac_iocb_req *mac_iocb_ptr;
2229
2230         mac_iocb_ptr = tx_ring->wq_base;
2231         tx_ring_desc = tx_ring->q;
2232         for (i = 0; i < tx_ring->wq_len; i++) {
2233                 tx_ring_desc->index = i;
2234                 tx_ring_desc->skb = NULL;
2235                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2236                 mac_iocb_ptr++;
2237                 tx_ring_desc++;
2238         }
2239         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2240         atomic_set(&tx_ring->queue_stopped, 0);
2241 }
2242
2243 static void ql_free_tx_resources(struct ql_adapter *qdev,
2244                                  struct tx_ring *tx_ring)
2245 {
2246         if (tx_ring->wq_base) {
2247                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2248                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2249                 tx_ring->wq_base = NULL;
2250         }
2251         kfree(tx_ring->q);
2252         tx_ring->q = NULL;
2253 }
2254
2255 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2256                                  struct tx_ring *tx_ring)
2257 {
2258         tx_ring->wq_base =
2259             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2260                                  &tx_ring->wq_base_dma);
2261
2262         if ((tx_ring->wq_base == NULL)
2263                 || tx_ring->wq_base_dma & WQ_ADDR_ALIGN) {
2264                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2265                 return -ENOMEM;
2266         }
2267         tx_ring->q =
2268             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2269         if (tx_ring->q == NULL)
2270                 goto err;
2271
2272         return 0;
2273 err:
2274         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2275                             tx_ring->wq_base, tx_ring->wq_base_dma);
2276         return -ENOMEM;
2277 }
2278
2279 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2280 {
2281         int i;
2282         struct bq_desc *lbq_desc;
2283
2284         for (i = 0; i < rx_ring->lbq_len; i++) {
2285                 lbq_desc = &rx_ring->lbq[i];
2286                 if (lbq_desc->p.lbq_page) {
2287                         pci_unmap_page(qdev->pdev,
2288                                        pci_unmap_addr(lbq_desc, mapaddr),
2289                                        pci_unmap_len(lbq_desc, maplen),
2290                                        PCI_DMA_FROMDEVICE);
2291
2292                         put_page(lbq_desc->p.lbq_page);
2293                         lbq_desc->p.lbq_page = NULL;
2294                 }
2295         }
2296 }
2297
2298 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2299 {
2300         int i;
2301         struct bq_desc *sbq_desc;
2302
2303         for (i = 0; i < rx_ring->sbq_len; i++) {
2304                 sbq_desc = &rx_ring->sbq[i];
2305                 if (sbq_desc == NULL) {
2306                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2307                         return;
2308                 }
2309                 if (sbq_desc->p.skb) {
2310                         pci_unmap_single(qdev->pdev,
2311                                          pci_unmap_addr(sbq_desc, mapaddr),
2312                                          pci_unmap_len(sbq_desc, maplen),
2313                                          PCI_DMA_FROMDEVICE);
2314                         dev_kfree_skb(sbq_desc->p.skb);
2315                         sbq_desc->p.skb = NULL;
2316                 }
2317         }
2318 }
2319
2320 /* Free all large and small rx buffers associated
2321  * with the completion queues for this device.
2322  */
2323 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2324 {
2325         int i;
2326         struct rx_ring *rx_ring;
2327
2328         for (i = 0; i < qdev->rx_ring_count; i++) {
2329                 rx_ring = &qdev->rx_ring[i];
2330                 if (rx_ring->lbq)
2331                         ql_free_lbq_buffers(qdev, rx_ring);
2332                 if (rx_ring->sbq)
2333                         ql_free_sbq_buffers(qdev, rx_ring);
2334         }
2335 }
2336
2337 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2338 {
2339         struct rx_ring *rx_ring;
2340         int i;
2341
2342         for (i = 0; i < qdev->rx_ring_count; i++) {
2343                 rx_ring = &qdev->rx_ring[i];
2344                 if (rx_ring->type != TX_Q)
2345                         ql_update_buffer_queues(qdev, rx_ring);
2346         }
2347 }
2348
2349 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2350                                 struct rx_ring *rx_ring)
2351 {
2352         int i;
2353         struct bq_desc *lbq_desc;
2354         __le64 *bq = rx_ring->lbq_base;
2355
2356         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2357         for (i = 0; i < rx_ring->lbq_len; i++) {
2358                 lbq_desc = &rx_ring->lbq[i];
2359                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2360                 lbq_desc->index = i;
2361                 lbq_desc->addr = bq;
2362                 bq++;
2363         }
2364 }
2365
2366 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2367                                 struct rx_ring *rx_ring)
2368 {
2369         int i;
2370         struct bq_desc *sbq_desc;
2371         __le64 *bq = rx_ring->sbq_base;
2372
2373         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2374         for (i = 0; i < rx_ring->sbq_len; i++) {
2375                 sbq_desc = &rx_ring->sbq[i];
2376                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2377                 sbq_desc->index = i;
2378                 sbq_desc->addr = bq;
2379                 bq++;
2380         }
2381 }
2382
2383 static void ql_free_rx_resources(struct ql_adapter *qdev,
2384                                  struct rx_ring *rx_ring)
2385 {
2386         /* Free the small buffer queue. */
2387         if (rx_ring->sbq_base) {
2388                 pci_free_consistent(qdev->pdev,
2389                                     rx_ring->sbq_size,
2390                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2391                 rx_ring->sbq_base = NULL;
2392         }
2393
2394         /* Free the small buffer queue control blocks. */
2395         kfree(rx_ring->sbq);
2396         rx_ring->sbq = NULL;
2397
2398         /* Free the large buffer queue. */
2399         if (rx_ring->lbq_base) {
2400                 pci_free_consistent(qdev->pdev,
2401                                     rx_ring->lbq_size,
2402                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2403                 rx_ring->lbq_base = NULL;
2404         }
2405
2406         /* Free the large buffer queue control blocks. */
2407         kfree(rx_ring->lbq);
2408         rx_ring->lbq = NULL;
2409
2410         /* Free the rx queue. */
2411         if (rx_ring->cq_base) {
2412                 pci_free_consistent(qdev->pdev,
2413                                     rx_ring->cq_size,
2414                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2415                 rx_ring->cq_base = NULL;
2416         }
2417 }
2418
2419 /* Allocate queues and buffers for this completions queue based
2420  * on the values in the parameter structure. */
2421 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2422                                  struct rx_ring *rx_ring)
2423 {
2424
2425         /*
2426          * Allocate the completion queue for this rx_ring.
2427          */
2428         rx_ring->cq_base =
2429             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2430                                  &rx_ring->cq_base_dma);
2431
2432         if (rx_ring->cq_base == NULL) {
2433                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2434                 return -ENOMEM;
2435         }
2436
2437         if (rx_ring->sbq_len) {
2438                 /*
2439                  * Allocate small buffer queue.
2440                  */
2441                 rx_ring->sbq_base =
2442                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2443                                          &rx_ring->sbq_base_dma);
2444
2445                 if (rx_ring->sbq_base == NULL) {
2446                         QPRINTK(qdev, IFUP, ERR,
2447                                 "Small buffer queue allocation failed.\n");
2448                         goto err_mem;
2449                 }
2450
2451                 /*
2452                  * Allocate small buffer queue control blocks.
2453                  */
2454                 rx_ring->sbq =
2455                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2456                             GFP_KERNEL);
2457                 if (rx_ring->sbq == NULL) {
2458                         QPRINTK(qdev, IFUP, ERR,
2459                                 "Small buffer queue control block allocation failed.\n");
2460                         goto err_mem;
2461                 }
2462
2463                 ql_init_sbq_ring(qdev, rx_ring);
2464         }
2465
2466         if (rx_ring->lbq_len) {
2467                 /*
2468                  * Allocate large buffer queue.
2469                  */
2470                 rx_ring->lbq_base =
2471                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2472                                          &rx_ring->lbq_base_dma);
2473
2474                 if (rx_ring->lbq_base == NULL) {
2475                         QPRINTK(qdev, IFUP, ERR,
2476                                 "Large buffer queue allocation failed.\n");
2477                         goto err_mem;
2478                 }
2479                 /*
2480                  * Allocate large buffer queue control blocks.
2481                  */
2482                 rx_ring->lbq =
2483                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2484                             GFP_KERNEL);
2485                 if (rx_ring->lbq == NULL) {
2486                         QPRINTK(qdev, IFUP, ERR,
2487                                 "Large buffer queue control block allocation failed.\n");
2488                         goto err_mem;
2489                 }
2490
2491                 ql_init_lbq_ring(qdev, rx_ring);
2492         }
2493
2494         return 0;
2495
2496 err_mem:
2497         ql_free_rx_resources(qdev, rx_ring);
2498         return -ENOMEM;
2499 }
2500
2501 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2502 {
2503         struct tx_ring *tx_ring;
2504         struct tx_ring_desc *tx_ring_desc;
2505         int i, j;
2506
2507         /*
2508          * Loop through all queues and free
2509          * any resources.
2510          */
2511         for (j = 0; j < qdev->tx_ring_count; j++) {
2512                 tx_ring = &qdev->tx_ring[j];
2513                 for (i = 0; i < tx_ring->wq_len; i++) {
2514                         tx_ring_desc = &tx_ring->q[i];
2515                         if (tx_ring_desc && tx_ring_desc->skb) {
2516                                 QPRINTK(qdev, IFDOWN, ERR,
2517                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2518                                         tx_ring_desc->skb, j,
2519                                         tx_ring_desc->index);
2520                                 ql_unmap_send(qdev, tx_ring_desc,
2521                                               tx_ring_desc->map_cnt);
2522                                 dev_kfree_skb(tx_ring_desc->skb);
2523                                 tx_ring_desc->skb = NULL;
2524                         }
2525                 }
2526         }
2527 }
2528
2529 static void ql_free_mem_resources(struct ql_adapter *qdev)
2530 {
2531         int i;
2532
2533         for (i = 0; i < qdev->tx_ring_count; i++)
2534                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2535         for (i = 0; i < qdev->rx_ring_count; i++)
2536                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2537         ql_free_shadow_space(qdev);
2538 }
2539
2540 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2541 {
2542         int i;
2543
2544         /* Allocate space for our shadow registers and such. */
2545         if (ql_alloc_shadow_space(qdev))
2546                 return -ENOMEM;
2547
2548         for (i = 0; i < qdev->rx_ring_count; i++) {
2549                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2550                         QPRINTK(qdev, IFUP, ERR,
2551                                 "RX resource allocation failed.\n");
2552                         goto err_mem;
2553                 }
2554         }
2555         /* Allocate tx queue resources */
2556         for (i = 0; i < qdev->tx_ring_count; i++) {
2557                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2558                         QPRINTK(qdev, IFUP, ERR,
2559                                 "TX resource allocation failed.\n");
2560                         goto err_mem;
2561                 }
2562         }
2563         return 0;
2564
2565 err_mem:
2566         ql_free_mem_resources(qdev);
2567         return -ENOMEM;
2568 }
2569
2570 /* Set up the rx ring control block and pass it to the chip.
2571  * The control block is defined as
2572  * "Completion Queue Initialization Control Block", or cqicb.
2573  */
2574 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2575 {
2576         struct cqicb *cqicb = &rx_ring->cqicb;
2577         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2578                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2579         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2580                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2581         void __iomem *doorbell_area =
2582             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2583         int err = 0;
2584         u16 bq_len;
2585         u64 tmp;
2586         __le64 *base_indirect_ptr;
2587         int page_entries;
2588
2589         /* Set up the shadow registers for this ring. */
2590         rx_ring->prod_idx_sh_reg = shadow_reg;
2591         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2592         shadow_reg += sizeof(u64);
2593         shadow_reg_dma += sizeof(u64);
2594         rx_ring->lbq_base_indirect = shadow_reg;
2595         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2596         shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2597         shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2598         rx_ring->sbq_base_indirect = shadow_reg;
2599         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2600
2601         /* PCI doorbell mem area + 0x00 for consumer index register */
2602         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2603         rx_ring->cnsmr_idx = 0;
2604         rx_ring->curr_entry = rx_ring->cq_base;
2605
2606         /* PCI doorbell mem area + 0x04 for valid register */
2607         rx_ring->valid_db_reg = doorbell_area + 0x04;
2608
2609         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2610         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2611
2612         /* PCI doorbell mem area + 0x1c */
2613         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2614
2615         memset((void *)cqicb, 0, sizeof(struct cqicb));
2616         cqicb->msix_vect = rx_ring->irq;
2617
2618         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2619         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2620
2621         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2622
2623         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2624
2625         /*
2626          * Set up the control block load flags.
2627          */
2628         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2629             FLAGS_LV |          /* Load MSI-X vector */
2630             FLAGS_LI;           /* Load irq delay values */
2631         if (rx_ring->lbq_len) {
2632                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2633                 tmp = (u64)rx_ring->lbq_base_dma;;
2634                 base_indirect_ptr = (__le64 *) rx_ring->lbq_base_indirect;
2635                 page_entries = 0;
2636                 do {
2637                         *base_indirect_ptr = cpu_to_le64(tmp);
2638                         tmp += DB_PAGE_SIZE;
2639                         base_indirect_ptr++;
2640                         page_entries++;
2641                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2642                 cqicb->lbq_addr =
2643                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2644                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2645                         (u16) rx_ring->lbq_buf_size;
2646                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2647                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2648                         (u16) rx_ring->lbq_len;
2649                 cqicb->lbq_len = cpu_to_le16(bq_len);
2650                 rx_ring->lbq_prod_idx = 0;
2651                 rx_ring->lbq_curr_idx = 0;
2652                 rx_ring->lbq_clean_idx = 0;
2653                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2654         }
2655         if (rx_ring->sbq_len) {
2656                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2657                 tmp = (u64)rx_ring->sbq_base_dma;;
2658                 base_indirect_ptr = (__le64 *) rx_ring->sbq_base_indirect;
2659                 page_entries = 0;
2660                 do {
2661                         *base_indirect_ptr = cpu_to_le64(tmp);
2662                         tmp += DB_PAGE_SIZE;
2663                         base_indirect_ptr++;
2664                         page_entries++;
2665                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
2666                 cqicb->sbq_addr =
2667                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2668                 cqicb->sbq_buf_size =
2669                     cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2670                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2671                         (u16) rx_ring->sbq_len;
2672                 cqicb->sbq_len = cpu_to_le16(bq_len);
2673                 rx_ring->sbq_prod_idx = 0;
2674                 rx_ring->sbq_curr_idx = 0;
2675                 rx_ring->sbq_clean_idx = 0;
2676                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2677         }
2678         switch (rx_ring->type) {
2679         case TX_Q:
2680                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2681                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2682                 break;
2683         case RX_Q:
2684                 /* Inbound completion handling rx_rings run in
2685                  * separate NAPI contexts.
2686                  */
2687                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2688                                64);
2689                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2690                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2691                 break;
2692         default:
2693                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2694                         rx_ring->type);
2695         }
2696         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2697         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2698                            CFG_LCQ, rx_ring->cq_id);
2699         if (err) {
2700                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2701                 return err;
2702         }
2703         return err;
2704 }
2705
2706 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2707 {
2708         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2709         void __iomem *doorbell_area =
2710             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2711         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2712             (tx_ring->wq_id * sizeof(u64));
2713         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2714             (tx_ring->wq_id * sizeof(u64));
2715         int err = 0;
2716
2717         /*
2718          * Assign doorbell registers for this tx_ring.
2719          */
2720         /* TX PCI doorbell mem area for tx producer index */
2721         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2722         tx_ring->prod_idx = 0;
2723         /* TX PCI doorbell mem area + 0x04 */
2724         tx_ring->valid_db_reg = doorbell_area + 0x04;
2725
2726         /*
2727          * Assign shadow registers for this tx_ring.
2728          */
2729         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2730         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2731
2732         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2733         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2734                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2735         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2736         wqicb->rid = 0;
2737         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2738
2739         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2740
2741         ql_init_tx_ring(qdev, tx_ring);
2742
2743         err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
2744                            (u16) tx_ring->wq_id);
2745         if (err) {
2746                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2747                 return err;
2748         }
2749         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2750         return err;
2751 }
2752
2753 static void ql_disable_msix(struct ql_adapter *qdev)
2754 {
2755         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2756                 pci_disable_msix(qdev->pdev);
2757                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2758                 kfree(qdev->msi_x_entry);
2759                 qdev->msi_x_entry = NULL;
2760         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2761                 pci_disable_msi(qdev->pdev);
2762                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2763         }
2764 }
2765
2766 /* We start by trying to get the number of vectors
2767  * stored in qdev->intr_count. If we don't get that
2768  * many then we reduce the count and try again.
2769  */
2770 static void ql_enable_msix(struct ql_adapter *qdev)
2771 {
2772         int i, err;
2773
2774         /* Get the MSIX vectors. */
2775         if (irq_type == MSIX_IRQ) {
2776                 /* Try to alloc space for the msix struct,
2777                  * if it fails then go to MSI/legacy.
2778                  */
2779                 qdev->msi_x_entry = kcalloc(qdev->intr_count,
2780                                             sizeof(struct msix_entry),
2781                                             GFP_KERNEL);
2782                 if (!qdev->msi_x_entry) {
2783                         irq_type = MSI_IRQ;
2784                         goto msi;
2785                 }
2786
2787                 for (i = 0; i < qdev->intr_count; i++)
2788                         qdev->msi_x_entry[i].entry = i;
2789
2790                 /* Loop to get our vectors.  We start with
2791                  * what we want and settle for what we get.
2792                  */
2793                 do {
2794                         err = pci_enable_msix(qdev->pdev,
2795                                 qdev->msi_x_entry, qdev->intr_count);
2796                         if (err > 0)
2797                                 qdev->intr_count = err;
2798                 } while (err > 0);
2799
2800                 if (err < 0) {
2801                         kfree(qdev->msi_x_entry);
2802                         qdev->msi_x_entry = NULL;
2803                         QPRINTK(qdev, IFUP, WARNING,
2804                                 "MSI-X Enable failed, trying MSI.\n");
2805                         qdev->intr_count = 1;
2806                         irq_type = MSI_IRQ;
2807                 } else if (err == 0) {
2808                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2809                         QPRINTK(qdev, IFUP, INFO,
2810                                 "MSI-X Enabled, got %d vectors.\n",
2811                                 qdev->intr_count);
2812                         return;
2813                 }
2814         }
2815 msi:
2816         qdev->intr_count = 1;
2817         if (irq_type == MSI_IRQ) {
2818                 if (!pci_enable_msi(qdev->pdev)) {
2819                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2820                         QPRINTK(qdev, IFUP, INFO,
2821                                 "Running with MSI interrupts.\n");
2822                         return;
2823                 }
2824         }
2825         irq_type = LEG_IRQ;
2826         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2827 }
2828
2829 /* Each vector services 1 RSS ring and and 1 or more
2830  * TX completion rings.  This function loops through
2831  * the TX completion rings and assigns the vector that
2832  * will service it.  An example would be if there are
2833  * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
2834  * This would mean that vector 0 would service RSS ring 0
2835  * and TX competion rings 0,1,2 and 3.  Vector 1 would
2836  * service RSS ring 1 and TX completion rings 4,5,6 and 7.
2837  */
2838 static void ql_set_tx_vect(struct ql_adapter *qdev)
2839 {
2840         int i, j, vect;
2841         u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
2842
2843         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2844                 /* Assign irq vectors to TX rx_rings.*/
2845                 for (vect = 0, j = 0, i = qdev->rss_ring_count;
2846                                          i < qdev->rx_ring_count; i++) {
2847                         if (j == tx_rings_per_vector) {
2848                                 vect++;
2849                                 j = 0;
2850                         }
2851                         qdev->rx_ring[i].irq = vect;
2852                         j++;
2853                 }
2854         } else {
2855                 /* For single vector all rings have an irq
2856                  * of zero.
2857                  */
2858                 for (i = 0; i < qdev->rx_ring_count; i++)
2859                         qdev->rx_ring[i].irq = 0;
2860         }
2861 }
2862
2863 /* Set the interrupt mask for this vector.  Each vector
2864  * will service 1 RSS ring and 1 or more TX completion
2865  * rings.  This function sets up a bit mask per vector
2866  * that indicates which rings it services.
2867  */
2868 static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
2869 {
2870         int j, vect = ctx->intr;
2871         u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
2872
2873         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2874                 /* Add the RSS ring serviced by this vector
2875                  * to the mask.
2876                  */
2877                 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
2878                 /* Add the TX ring(s) serviced by this vector
2879                  * to the mask. */
2880                 for (j = 0; j < tx_rings_per_vector; j++) {
2881                         ctx->irq_mask |=
2882                         (1 << qdev->rx_ring[qdev->rss_ring_count +
2883                         (vect * tx_rings_per_vector) + j].cq_id);
2884                 }
2885         } else {
2886                 /* For single vector we just shift each queue's
2887                  * ID into the mask.
2888                  */
2889                 for (j = 0; j < qdev->rx_ring_count; j++)
2890                         ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
2891         }
2892 }
2893
2894 /*
2895  * Here we build the intr_context structures based on
2896  * our rx_ring count and intr vector count.
2897  * The intr_context structure is used to hook each vector
2898  * to possibly different handlers.
2899  */
2900 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2901 {
2902         int i = 0;
2903         struct intr_context *intr_context = &qdev->intr_context[0];
2904
2905         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2906                 /* Each rx_ring has it's
2907                  * own intr_context since we have separate
2908                  * vectors for each queue.
2909                  */
2910                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2911                         qdev->rx_ring[i].irq = i;
2912                         intr_context->intr = i;
2913                         intr_context->qdev = qdev;
2914                         /* Set up this vector's bit-mask that indicates
2915                          * which queues it services.
2916                          */
2917                         ql_set_irq_mask(qdev, intr_context);
2918                         /*
2919                          * We set up each vectors enable/disable/read bits so
2920                          * there's no bit/mask calculations in the critical path.
2921                          */
2922                         intr_context->intr_en_mask =
2923                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2924                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2925                             | i;
2926                         intr_context->intr_dis_mask =
2927                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2928                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2929                             INTR_EN_IHD | i;
2930                         intr_context->intr_read_mask =
2931                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2932                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2933                             i;
2934                         if (i == 0) {
2935                                 /* The first vector/queue handles
2936                                  * broadcast/multicast, fatal errors,
2937                                  * and firmware events.  This in addition
2938                                  * to normal inbound NAPI processing.
2939                                  */
2940                                 intr_context->handler = qlge_isr;
2941                                 sprintf(intr_context->name, "%s-rx-%d",
2942                                         qdev->ndev->name, i);
2943                         } else {
2944                                 /*
2945                                  * Inbound queues handle unicast frames only.
2946                                  */
2947                                 intr_context->handler = qlge_msix_rx_isr;
2948                                 sprintf(intr_context->name, "%s-rx-%d",
2949                                         qdev->ndev->name, i);
2950                         }
2951                 }
2952         } else {
2953                 /*
2954                  * All rx_rings use the same intr_context since
2955                  * there is only one vector.
2956                  */
2957                 intr_context->intr = 0;
2958                 intr_context->qdev = qdev;
2959                 /*
2960                  * We set up each vectors enable/disable/read bits so
2961                  * there's no bit/mask calculations in the critical path.
2962                  */
2963                 intr_context->intr_en_mask =
2964                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2965                 intr_context->intr_dis_mask =
2966                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2967                     INTR_EN_TYPE_DISABLE;
2968                 intr_context->intr_read_mask =
2969                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2970                 /*
2971                  * Single interrupt means one handler for all rings.
2972                  */
2973                 intr_context->handler = qlge_isr;
2974                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2975                 /* Set up this vector's bit-mask that indicates
2976                  * which queues it services. In this case there is
2977                  * a single vector so it will service all RSS and
2978                  * TX completion rings.
2979                  */
2980                 ql_set_irq_mask(qdev, intr_context);
2981         }
2982         /* Tell the TX completion rings which MSIx vector
2983          * they will be using.
2984          */
2985         ql_set_tx_vect(qdev);
2986 }
2987
2988 static void ql_free_irq(struct ql_adapter *qdev)
2989 {
2990         int i;
2991         struct intr_context *intr_context = &qdev->intr_context[0];
2992
2993         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2994                 if (intr_context->hooked) {
2995                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2996                                 free_irq(qdev->msi_x_entry[i].vector,
2997                                          &qdev->rx_ring[i]);
2998                                 QPRINTK(qdev, IFDOWN, DEBUG,
2999                                         "freeing msix interrupt %d.\n", i);
3000                         } else {
3001                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
3002                                 QPRINTK(qdev, IFDOWN, DEBUG,
3003                                         "freeing msi interrupt %d.\n", i);
3004                         }
3005                 }
3006         }
3007         ql_disable_msix(qdev);
3008 }
3009
3010 static int ql_request_irq(struct ql_adapter *qdev)
3011 {
3012         int i;
3013         int status = 0;
3014         struct pci_dev *pdev = qdev->pdev;
3015         struct intr_context *intr_context = &qdev->intr_context[0];
3016
3017         ql_resolve_queues_to_irqs(qdev);
3018
3019         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3020                 atomic_set(&intr_context->irq_cnt, 0);
3021                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3022                         status = request_irq(qdev->msi_x_entry[i].vector,
3023                                              intr_context->handler,
3024                                              0,
3025                                              intr_context->name,
3026                                              &qdev->rx_ring[i]);
3027                         if (status) {
3028                                 QPRINTK(qdev, IFUP, ERR,
3029                                         "Failed request for MSIX interrupt %d.\n",
3030                                         i);
3031                                 goto err_irq;
3032                         } else {
3033                                 QPRINTK(qdev, IFUP, DEBUG,
3034                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
3035                                         i,
3036                                         qdev->rx_ring[i].type ==
3037                                         DEFAULT_Q ? "DEFAULT_Q" : "",
3038                                         qdev->rx_ring[i].type ==
3039                                         TX_Q ? "TX_Q" : "",
3040                                         qdev->rx_ring[i].type ==
3041                                         RX_Q ? "RX_Q" : "", intr_context->name);
3042                         }
3043                 } else {
3044                         QPRINTK(qdev, IFUP, DEBUG,
3045                                 "trying msi or legacy interrupts.\n");
3046                         QPRINTK(qdev, IFUP, DEBUG,
3047                                 "%s: irq = %d.\n", __func__, pdev->irq);
3048                         QPRINTK(qdev, IFUP, DEBUG,
3049                                 "%s: context->name = %s.\n", __func__,
3050                                intr_context->name);
3051                         QPRINTK(qdev, IFUP, DEBUG,
3052                                 "%s: dev_id = 0x%p.\n", __func__,
3053                                &qdev->rx_ring[0]);
3054                         status =
3055                             request_irq(pdev->irq, qlge_isr,
3056                                         test_bit(QL_MSI_ENABLED,
3057                                                  &qdev->
3058                                                  flags) ? 0 : IRQF_SHARED,
3059                                         intr_context->name, &qdev->rx_ring[0]);
3060                         if (status)
3061                                 goto err_irq;
3062
3063                         QPRINTK(qdev, IFUP, ERR,
3064                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
3065                                 i,
3066                                 qdev->rx_ring[0].type ==
3067                                 DEFAULT_Q ? "DEFAULT_Q" : "",
3068                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
3069                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3070                                 intr_context->name);
3071                 }
3072                 intr_context->hooked = 1;
3073         }
3074         return status;
3075 err_irq:
3076         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
3077         ql_free_irq(qdev);
3078         return status;
3079 }
3080
3081 static int ql_start_rss(struct ql_adapter *qdev)
3082 {
3083         struct ricb *ricb = &qdev->ricb;
3084         int status = 0;
3085         int i;
3086         u8 *hash_id = (u8 *) ricb->hash_cq_id;
3087
3088         memset((void *)ricb, 0, sizeof(*ricb));
3089
3090         ricb->base_cq = RSS_L4K;
3091         ricb->flags =
3092             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
3093              RSS_RT6);
3094         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
3095
3096         /*
3097          * Fill out the Indirection Table.
3098          */
3099         for (i = 0; i < 256; i++)
3100                 hash_id[i] = i & (qdev->rss_ring_count - 1);
3101
3102         /*
3103          * Random values for the IPv6 and IPv4 Hash Keys.
3104          */
3105         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
3106         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
3107
3108         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
3109
3110         status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3111         if (status) {
3112                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
3113                 return status;
3114         }
3115         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
3116         return status;
3117 }
3118
3119 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3120 {
3121         int i, status = 0;
3122
3123         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3124         if (status)
3125                 return status;
3126         /* Clear all the entries in the routing table. */
3127         for (i = 0; i < 16; i++) {
3128                 status = ql_set_routing_reg(qdev, i, 0, 0);
3129                 if (status) {
3130                         QPRINTK(qdev, IFUP, ERR,
3131                                 "Failed to init routing register for CAM "
3132                                 "packets.\n");
3133                         break;
3134                 }
3135         }
3136         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3137         return status;
3138 }
3139
3140 /* Initialize the frame-to-queue routing. */
3141 static int ql_route_initialize(struct ql_adapter *qdev)
3142 {
3143         int status = 0;
3144
3145         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3146         if (status)
3147                 return status;
3148
3149         /* Clear all the entries in the routing table. */
3150         status = ql_clear_routing_entries(qdev);
3151         if (status)
3152                 goto exit;
3153
3154         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3155         if (status) {
3156                 QPRINTK(qdev, IFUP, ERR,
3157                         "Failed to init routing register for error packets.\n");
3158                 goto exit;
3159         }
3160         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3161         if (status) {
3162                 QPRINTK(qdev, IFUP, ERR,
3163                         "Failed to init routing register for broadcast packets.\n");
3164                 goto exit;
3165         }
3166         /* If we have more than one inbound queue, then turn on RSS in the
3167          * routing block.
3168          */
3169         if (qdev->rss_ring_count > 1) {
3170                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3171                                         RT_IDX_RSS_MATCH, 1);
3172                 if (status) {
3173                         QPRINTK(qdev, IFUP, ERR,
3174                                 "Failed to init routing register for MATCH RSS packets.\n");
3175                         goto exit;
3176                 }
3177         }
3178
3179         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3180                                     RT_IDX_CAM_HIT, 1);
3181         if (status)
3182                 QPRINTK(qdev, IFUP, ERR,
3183                         "Failed to init routing register for CAM packets.\n");
3184 exit:
3185         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3186         return status;
3187 }
3188
3189 int ql_cam_route_initialize(struct ql_adapter *qdev)
3190 {
3191         int status, set;
3192
3193         /* If check if the link is up and use to
3194          * determine if we are setting or clearing
3195          * the MAC address in the CAM.
3196          */
3197         set = ql_read32(qdev, STS);
3198         set &= qdev->port_link_up;
3199         status = ql_set_mac_addr(qdev, set);
3200         if (status) {
3201                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3202                 return status;
3203         }
3204
3205         status = ql_route_initialize(qdev);
3206         if (status)
3207                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3208
3209         return status;
3210 }
3211
3212 static int ql_adapter_initialize(struct ql_adapter *qdev)
3213 {
3214         u32 value, mask;
3215         int i;
3216         int status = 0;
3217
3218         /*
3219          * Set up the System register to halt on errors.
3220          */
3221         value = SYS_EFE | SYS_FAE;
3222         mask = value << 16;
3223         ql_write32(qdev, SYS, mask | value);
3224
3225         /* Set the default queue, and VLAN behavior. */
3226         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3227         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3228         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3229
3230         /* Set the MPI interrupt to enabled. */
3231         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3232
3233         /* Enable the function, set pagesize, enable error checking. */
3234         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3235             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3236
3237         /* Set/clear header splitting. */
3238         mask = FSC_VM_PAGESIZE_MASK |
3239             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3240         ql_write32(qdev, FSC, mask | value);
3241
3242         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3243                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3244
3245         /* Start up the rx queues. */
3246         for (i = 0; i < qdev->rx_ring_count; i++) {
3247                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3248                 if (status) {
3249                         QPRINTK(qdev, IFUP, ERR,
3250                                 "Failed to start rx ring[%d].\n", i);
3251                         return status;
3252                 }
3253         }
3254
3255         /* If there is more than one inbound completion queue
3256          * then download a RICB to configure RSS.
3257          */
3258         if (qdev->rss_ring_count > 1) {
3259                 status = ql_start_rss(qdev);
3260                 if (status) {
3261                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3262                         return status;
3263                 }
3264         }
3265
3266         /* Start up the tx queues. */
3267         for (i = 0; i < qdev->tx_ring_count; i++) {
3268                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3269                 if (status) {
3270                         QPRINTK(qdev, IFUP, ERR,
3271                                 "Failed to start tx ring[%d].\n", i);
3272                         return status;
3273                 }
3274         }
3275
3276         /* Initialize the port and set the max framesize. */
3277         status = qdev->nic_ops->port_initialize(qdev);
3278        if (status) {
3279               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3280               return status;
3281        }
3282
3283         /* Set up the MAC address and frame routing filter. */
3284         status = ql_cam_route_initialize(qdev);
3285         if (status) {
3286                 QPRINTK(qdev, IFUP, ERR,
3287                                 "Failed to init CAM/Routing tables.\n");
3288                 return status;
3289         }
3290
3291         /* Start NAPI for the RSS queues. */
3292         for (i = 0; i < qdev->rss_ring_count; i++) {
3293                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3294                         i);
3295                 napi_enable(&qdev->rx_ring[i].napi);
3296         }
3297
3298         return status;
3299 }
3300
3301 /* Issue soft reset to chip. */
3302 static int ql_adapter_reset(struct ql_adapter *qdev)
3303 {
3304         u32 value;
3305         int status = 0;
3306         unsigned long end_jiffies;
3307
3308         /* Clear all the entries in the routing table. */
3309         status = ql_clear_routing_entries(qdev);
3310         if (status) {
3311                 QPRINTK(qdev, IFUP, ERR, "Failed to clear routing bits.\n");
3312                 return status;
3313         }
3314
3315         end_jiffies = jiffies +
3316                 max((unsigned long)1, usecs_to_jiffies(30));
3317         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3318
3319         do {
3320                 value = ql_read32(qdev, RST_FO);
3321                 if ((value & RST_FO_FR) == 0)
3322                         break;
3323                 cpu_relax();
3324         } while (time_before(jiffies, end_jiffies));
3325
3326         if (value & RST_FO_FR) {
3327                 QPRINTK(qdev, IFDOWN, ERR,
3328                         "ETIMEDOUT!!! errored out of resetting the chip!\n");
3329                 status = -ETIMEDOUT;
3330         }
3331
3332         return status;
3333 }
3334
3335 static void ql_display_dev_info(struct net_device *ndev)
3336 {
3337         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3338
3339         QPRINTK(qdev, PROBE, INFO,
3340                 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3341                 "XG Roll = %d, XG Rev = %d.\n",
3342                 qdev->func,
3343                 qdev->port,
3344                 qdev->chip_rev_id & 0x0000000f,
3345                 qdev->chip_rev_id >> 4 & 0x0000000f,
3346                 qdev->chip_rev_id >> 8 & 0x0000000f,
3347                 qdev->chip_rev_id >> 12 & 0x0000000f);
3348         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3349 }
3350
3351 static int ql_adapter_down(struct ql_adapter *qdev)
3352 {
3353         int i, status = 0;
3354
3355         ql_link_off(qdev);
3356
3357         /* Don't kill the reset worker thread if we
3358          * are in the process of recovery.
3359          */
3360         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3361                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3362         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3363         cancel_delayed_work_sync(&qdev->mpi_work);
3364         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3365         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3366
3367         for (i = 0; i < qdev->rss_ring_count; i++)
3368                 napi_disable(&qdev->rx_ring[i].napi);
3369
3370         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3371
3372         ql_disable_interrupts(qdev);
3373
3374         ql_tx_ring_clean(qdev);
3375
3376         /* Call netif_napi_del() from common point.
3377          */
3378         for (i = 0; i < qdev->rss_ring_count; i++)
3379                 netif_napi_del(&qdev->rx_ring[i].napi);
3380
3381         ql_free_rx_buffers(qdev);
3382
3383         spin_lock(&qdev->hw_lock);
3384         status = ql_adapter_reset(qdev);
3385         if (status)
3386                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3387                         qdev->func);
3388         spin_unlock(&qdev->hw_lock);
3389         return status;
3390 }
3391
3392 static int ql_adapter_up(struct ql_adapter *qdev)
3393 {
3394         int err = 0;
3395
3396         err = ql_adapter_initialize(qdev);
3397         if (err) {
3398                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3399                 goto err_init;
3400         }
3401         set_bit(QL_ADAPTER_UP, &qdev->flags);
3402         ql_alloc_rx_buffers(qdev);
3403         /* If the port is initialized and the
3404          * link is up the turn on the carrier.
3405          */
3406         if ((ql_read32(qdev, STS) & qdev->port_init) &&
3407                         (ql_read32(qdev, STS) & qdev->port_link_up))
3408                 ql_link_on(qdev);
3409         ql_enable_interrupts(qdev);
3410         ql_enable_all_completion_interrupts(qdev);
3411         netif_tx_start_all_queues(qdev->ndev);
3412
3413         return 0;
3414 err_init:
3415         ql_adapter_reset(qdev);
3416         return err;
3417 }
3418
3419 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3420 {
3421         ql_free_mem_resources(qdev);
3422         ql_free_irq(qdev);
3423 }
3424
3425 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3426 {
3427         int status = 0;
3428
3429         if (ql_alloc_mem_resources(qdev)) {
3430                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3431                 return -ENOMEM;
3432         }
3433         status = ql_request_irq(qdev);
3434         return status;
3435 }
3436
3437 static int qlge_close(struct net_device *ndev)
3438 {
3439         struct ql_adapter *qdev = netdev_priv(ndev);
3440
3441         /*
3442          * Wait for device to recover from a reset.
3443          * (Rarely happens, but possible.)
3444          */
3445         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3446                 msleep(1);
3447         ql_adapter_down(qdev);
3448         ql_release_adapter_resources(qdev);
3449         return 0;
3450 }
3451
3452 static int ql_configure_rings(struct ql_adapter *qdev)
3453 {
3454         int i;
3455         struct rx_ring *rx_ring;
3456         struct tx_ring *tx_ring;
3457         int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
3458
3459         /* In a perfect world we have one RSS ring for each CPU
3460          * and each has it's own vector.  To do that we ask for
3461          * cpu_cnt vectors.  ql_enable_msix() will adjust the
3462          * vector count to what we actually get.  We then
3463          * allocate an RSS ring for each.
3464          * Essentially, we are doing min(cpu_count, msix_vector_count).
3465          */
3466         qdev->intr_count = cpu_cnt;
3467         ql_enable_msix(qdev);
3468         /* Adjust the RSS ring count to the actual vector count. */
3469         qdev->rss_ring_count = qdev->intr_count;
3470         qdev->tx_ring_count = cpu_cnt;
3471         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
3472
3473         for (i = 0; i < qdev->tx_ring_count; i++) {
3474                 tx_ring = &qdev->tx_ring[i];
3475                 memset((void *)tx_ring, 0, sizeof(*tx_ring));
3476                 tx_ring->qdev = qdev;
3477                 tx_ring->wq_id = i;
3478                 tx_ring->wq_len = qdev->tx_ring_size;
3479                 tx_ring->wq_size =
3480                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3481
3482                 /*
3483                  * The completion queue ID for the tx rings start
3484                  * immediately after the rss rings.
3485                  */
3486                 tx_ring->cq_id = qdev->rss_ring_count + i;
3487         }
3488
3489         for (i = 0; i < qdev->rx_ring_count; i++) {
3490                 rx_ring = &qdev->rx_ring[i];
3491                 memset((void *)rx_ring, 0, sizeof(*rx_ring));
3492                 rx_ring->qdev = qdev;
3493                 rx_ring->cq_id = i;
3494                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3495                 if (i < qdev->rss_ring_count) {
3496                         /*
3497                          * Inbound (RSS) queues.
3498                          */
3499                         rx_ring->cq_len = qdev->rx_ring_size;
3500                         rx_ring->cq_size =
3501                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3502                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3503                         rx_ring->lbq_size =
3504                             rx_ring->lbq_len * sizeof(__le64);
3505                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3506                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3507                         rx_ring->sbq_size =
3508                             rx_ring->sbq_len * sizeof(__le64);
3509                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3510                         rx_ring->type = RX_Q;
3511                 } else {
3512                         /*
3513                          * Outbound queue handles outbound completions only.
3514                          */
3515                         /* outbound cq is same size as tx_ring it services. */
3516                         rx_ring->cq_len = qdev->tx_ring_size;
3517                         rx_ring->cq_size =
3518                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3519                         rx_ring->lbq_len = 0;
3520                         rx_ring->lbq_size = 0;
3521                         rx_ring->lbq_buf_size = 0;
3522                         rx_ring->sbq_len = 0;
3523                         rx_ring->sbq_size = 0;
3524                         rx_ring->sbq_buf_size = 0;
3525                         rx_ring->type = TX_Q;
3526                 }
3527         }
3528         return 0;
3529 }
3530
3531 static int qlge_open(struct net_device *ndev)
3532 {
3533         int err = 0;
3534         struct ql_adapter *qdev = netdev_priv(ndev);
3535
3536         err = ql_configure_rings(qdev);
3537         if (err)
3538                 return err;
3539
3540         err = ql_get_adapter_resources(qdev);
3541         if (err)
3542                 goto error_up;
3543
3544         err = ql_adapter_up(qdev);
3545         if (err)
3546                 goto error_up;
3547
3548         return err;
3549
3550 error_up:
3551         ql_release_adapter_resources(qdev);
3552         return err;
3553 }
3554
3555 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3556 {
3557         struct ql_adapter *qdev = netdev_priv(ndev);
3558
3559         if (ndev->mtu == 1500 && new_mtu == 9000) {
3560                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3561                 queue_delayed_work(qdev->workqueue,
3562                                 &qdev->mpi_port_cfg_work, 0);
3563         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3564                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3565         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3566                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3567                 return 0;
3568         } else
3569                 return -EINVAL;
3570         ndev->mtu = new_mtu;
3571         return 0;
3572 }
3573
3574 static struct net_device_stats *qlge_get_stats(struct net_device
3575                                                *ndev)
3576 {
3577         struct ql_adapter *qdev = netdev_priv(ndev);
3578         return &qdev->stats;
3579 }
3580
3581 static void qlge_set_multicast_list(struct net_device *ndev)
3582 {
3583         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3584         struct dev_mc_list *mc_ptr;
3585         int i, status;
3586
3587         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3588         if (status)
3589                 return;
3590         spin_lock(&qdev->hw_lock);
3591         /*
3592          * Set or clear promiscuous mode if a
3593          * transition is taking place.
3594          */
3595         if (ndev->flags & IFF_PROMISC) {
3596                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3597                         if (ql_set_routing_reg
3598                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3599                                 QPRINTK(qdev, HW, ERR,
3600                                         "Failed to set promiscous mode.\n");
3601                         } else {
3602                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3603                         }
3604                 }
3605         } else {
3606                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3607                         if (ql_set_routing_reg
3608                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3609                                 QPRINTK(qdev, HW, ERR,
3610                                         "Failed to clear promiscous mode.\n");
3611                         } else {
3612                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3613                         }
3614                 }
3615         }
3616
3617         /*
3618          * Set or clear all multicast mode if a
3619          * transition is taking place.
3620          */
3621         if ((ndev->flags & IFF_ALLMULTI) ||
3622             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3623                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3624                         if (ql_set_routing_reg
3625                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3626                                 QPRINTK(qdev, HW, ERR,
3627                                         "Failed to set all-multi mode.\n");
3628                         } else {
3629                                 set_bit(QL_ALLMULTI, &qdev->flags);
3630                         }
3631                 }
3632         } else {
3633                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3634                         if (ql_set_routing_reg
3635                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3636                                 QPRINTK(qdev, HW, ERR,
3637                                         "Failed to clear all-multi mode.\n");
3638                         } else {
3639                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3640                         }
3641                 }
3642         }
3643
3644         if (ndev->mc_count) {
3645                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3646                 if (status)
3647                         goto exit;
3648                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3649                      i++, mc_ptr = mc_ptr->next)
3650                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3651                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3652                                 QPRINTK(qdev, HW, ERR,
3653                                         "Failed to loadmulticast address.\n");
3654                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3655                                 goto exit;
3656                         }
3657                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3658                 if (ql_set_routing_reg
3659                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3660                         QPRINTK(qdev, HW, ERR,
3661                                 "Failed to set multicast match mode.\n");
3662                 } else {
3663                         set_bit(QL_ALLMULTI, &qdev->flags);
3664                 }
3665         }
3666 exit:
3667         spin_unlock(&qdev->hw_lock);
3668         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3669 }
3670
3671 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3672 {
3673         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3674         struct sockaddr *addr = p;
3675         int status;
3676
3677         if (netif_running(ndev))
3678                 return -EBUSY;
3679
3680         if (!is_valid_ether_addr(addr->sa_data))
3681                 return -EADDRNOTAVAIL;
3682         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3683
3684         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3685         if (status)
3686                 return status;
3687         spin_lock(&qdev->hw_lock);
3688         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3689                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3690         spin_unlock(&qdev->hw_lock);
3691         if (status)
3692                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3693         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3694         return status;
3695 }
3696
3697 static void qlge_tx_timeout(struct net_device *ndev)
3698 {
3699         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3700         ql_queue_asic_error(qdev);
3701 }
3702
3703 static void ql_asic_reset_work(struct work_struct *work)
3704 {
3705         struct ql_adapter *qdev =
3706             container_of(work, struct ql_adapter, asic_reset_work.work);
3707         int status;
3708
3709         status = ql_adapter_down(qdev);
3710         if (status)
3711                 goto error;
3712
3713         status = ql_adapter_up(qdev);
3714         if (status)
3715                 goto error;
3716
3717         return;
3718 error:
3719         QPRINTK(qdev, IFUP, ALERT,
3720                 "Driver up/down cycle failed, closing device\n");
3721         rtnl_lock();
3722         set_bit(QL_ADAPTER_UP, &qdev->flags);
3723         dev_close(qdev->ndev);
3724         rtnl_unlock();
3725 }
3726
3727 static struct nic_operations qla8012_nic_ops = {
3728         .get_flash              = ql_get_8012_flash_params,
3729         .port_initialize        = ql_8012_port_initialize,
3730 };
3731
3732 static struct nic_operations qla8000_nic_ops = {
3733         .get_flash              = ql_get_8000_flash_params,
3734         .port_initialize        = ql_8000_port_initialize,
3735 };
3736
3737 /* Find the pcie function number for the other NIC
3738  * on this chip.  Since both NIC functions share a
3739  * common firmware we have the lowest enabled function
3740  * do any common work.  Examples would be resetting
3741  * after a fatal firmware error, or doing a firmware
3742  * coredump.
3743  */
3744 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
3745 {
3746         int status = 0;
3747         u32 temp;
3748         u32 nic_func1, nic_func2;
3749
3750         status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
3751                         &temp);
3752         if (status)
3753                 return status;
3754
3755         nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
3756                         MPI_TEST_NIC_FUNC_MASK);
3757         nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
3758                         MPI_TEST_NIC_FUNC_MASK);
3759
3760         if (qdev->func == nic_func1)
3761                 qdev->alt_func = nic_func2;
3762         else if (qdev->func == nic_func2)
3763                 qdev->alt_func = nic_func1;
3764         else
3765                 status = -EIO;
3766
3767         return status;
3768 }
3769
3770 static int ql_get_board_info(struct ql_adapter *qdev)
3771 {
3772         int status;
3773         qdev->func =
3774             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3775         if (qdev->func > 3)
3776                 return -EIO;
3777
3778         status = ql_get_alt_pcie_func(qdev);
3779         if (status)
3780                 return status;
3781
3782         qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
3783         if (qdev->port) {
3784                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3785                 qdev->port_link_up = STS_PL1;
3786                 qdev->port_init = STS_PI1;
3787                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3788                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3789         } else {
3790                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3791                 qdev->port_link_up = STS_PL0;
3792                 qdev->port_init = STS_PI0;
3793                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3794                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3795         }
3796         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3797         qdev->device_id = qdev->pdev->device;
3798         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3799                 qdev->nic_ops = &qla8012_nic_ops;
3800         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3801                 qdev->nic_ops = &qla8000_nic_ops;
3802         return status;
3803 }
3804
3805 static void ql_release_all(struct pci_dev *pdev)
3806 {
3807         struct net_device *ndev = pci_get_drvdata(pdev);
3808         struct ql_adapter *qdev = netdev_priv(ndev);
3809
3810         if (qdev->workqueue) {
3811                 destroy_workqueue(qdev->workqueue);
3812                 qdev->workqueue = NULL;
3813         }
3814
3815         if (qdev->reg_base)
3816                 iounmap(qdev->reg_base);
3817         if (qdev->doorbell_area)
3818                 iounmap(qdev->doorbell_area);
3819         pci_release_regions(pdev);
3820         pci_set_drvdata(pdev, NULL);
3821 }
3822
3823 static int __devinit ql_init_device(struct pci_dev *pdev,
3824                                     struct net_device *ndev, int cards_found)
3825 {
3826         struct ql_adapter *qdev = netdev_priv(ndev);
3827         int pos, err = 0;
3828         u16 val16;
3829
3830         memset((void *)qdev, 0, sizeof(*qdev));
3831         err = pci_enable_device(pdev);
3832         if (err) {
3833                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3834                 return err;
3835         }
3836
3837         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3838         if (pos <= 0) {
3839                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3840                         "aborting.\n");
3841                 goto err_out;
3842         } else {
3843                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3844                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3845                 val16 |= (PCI_EXP_DEVCTL_CERE |
3846                           PCI_EXP_DEVCTL_NFERE |
3847                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3848                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3849         }
3850
3851         err = pci_request_regions(pdev, DRV_NAME);
3852         if (err) {
3853                 dev_err(&pdev->dev, "PCI region request failed.\n");
3854                 goto err_out;
3855         }
3856
3857         pci_set_master(pdev);
3858         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3859                 set_bit(QL_DMA64, &qdev->flags);
3860                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3861         } else {
3862                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3863                 if (!err)
3864                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3865         }
3866
3867         if (err) {
3868                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3869                 goto err_out;
3870         }
3871
3872         pci_set_drvdata(pdev, ndev);
3873         qdev->reg_base =
3874             ioremap_nocache(pci_resource_start(pdev, 1),
3875                             pci_resource_len(pdev, 1));
3876         if (!qdev->reg_base) {
3877                 dev_err(&pdev->dev, "Register mapping failed.\n");
3878                 err = -ENOMEM;
3879                 goto err_out;
3880         }
3881
3882         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3883         qdev->doorbell_area =
3884             ioremap_nocache(pci_resource_start(pdev, 3),
3885                             pci_resource_len(pdev, 3));
3886         if (!qdev->doorbell_area) {
3887                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3888                 err = -ENOMEM;
3889                 goto err_out;
3890         }
3891
3892         qdev->ndev = ndev;
3893         qdev->pdev = pdev;
3894         err = ql_get_board_info(qdev);
3895         if (err) {
3896                 dev_err(&pdev->dev, "Register access failed.\n");
3897                 err = -EIO;
3898                 goto err_out;
3899         }
3900         qdev->msg_enable = netif_msg_init(debug, default_msg);
3901         spin_lock_init(&qdev->hw_lock);
3902         spin_lock_init(&qdev->stats_lock);
3903
3904         /* make sure the EEPROM is good */
3905         err = qdev->nic_ops->get_flash(qdev);
3906         if (err) {
3907                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3908                 goto err_out;
3909         }
3910
3911         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3912
3913         /* Set up the default ring sizes. */
3914         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3915         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3916
3917         /* Set up the coalescing parameters. */
3918         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3919         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3920         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3921         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3922
3923         /*
3924          * Set up the operating parameters.
3925          */
3926         qdev->rx_csum = 1;
3927         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3928         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3929         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3930         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3931         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3932         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3933         mutex_init(&qdev->mpi_mutex);
3934         init_completion(&qdev->ide_completion);
3935
3936         if (!cards_found) {
3937                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3938                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3939                          DRV_NAME, DRV_VERSION);
3940         }
3941         return 0;
3942 err_out:
3943         ql_release_all(pdev);
3944         pci_disable_device(pdev);
3945         return err;
3946 }
3947
3948
3949 static const struct net_device_ops qlge_netdev_ops = {
3950         .ndo_open               = qlge_open,
3951         .ndo_stop               = qlge_close,
3952         .ndo_start_xmit         = qlge_send,
3953         .ndo_change_mtu         = qlge_change_mtu,
3954         .ndo_get_stats          = qlge_get_stats,
3955         .ndo_set_multicast_list = qlge_set_multicast_list,
3956         .ndo_set_mac_address    = qlge_set_mac_address,
3957         .ndo_validate_addr      = eth_validate_addr,
3958         .ndo_tx_timeout         = qlge_tx_timeout,
3959         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3960         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3961         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3962 };
3963
3964 static int __devinit qlge_probe(struct pci_dev *pdev,
3965                                 const struct pci_device_id *pci_entry)
3966 {
3967         struct net_device *ndev = NULL;
3968         struct ql_adapter *qdev = NULL;
3969         static int cards_found = 0;
3970         int err = 0;
3971
3972         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3973                         min(MAX_CPUS, (int)num_online_cpus()));
3974         if (!ndev)
3975                 return -ENOMEM;
3976
3977         err = ql_init_device(pdev, ndev, cards_found);
3978         if (err < 0) {
3979                 free_netdev(ndev);
3980                 return err;
3981         }
3982
3983         qdev = netdev_priv(ndev);
3984         SET_NETDEV_DEV(ndev, &pdev->dev);
3985         ndev->features = (0
3986                           | NETIF_F_IP_CSUM
3987                           | NETIF_F_SG
3988                           | NETIF_F_TSO
3989                           | NETIF_F_TSO6
3990                           | NETIF_F_TSO_ECN
3991                           | NETIF_F_HW_VLAN_TX
3992                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3993         ndev->features |= NETIF_F_GRO;
3994
3995         if (test_bit(QL_DMA64, &qdev->flags))
3996                 ndev->features |= NETIF_F_HIGHDMA;
3997
3998         /*
3999          * Set up net_device structure.
4000          */
4001         ndev->tx_queue_len = qdev->tx_ring_size;
4002         ndev->irq = pdev->irq;
4003
4004         ndev->netdev_ops = &qlge_netdev_ops;
4005         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
4006         ndev->watchdog_timeo = 10 * HZ;
4007
4008         err = register_netdev(ndev);
4009         if (err) {
4010                 dev_err(&pdev->dev, "net device registration failed.\n");
4011                 ql_release_all(pdev);
4012                 pci_disable_device(pdev);
4013                 return err;
4014         }
4015         ql_link_off(qdev);
4016         ql_display_dev_info(ndev);
4017         cards_found++;
4018         return 0;
4019 }
4020
4021 static void __devexit qlge_remove(struct pci_dev *pdev)
4022 {
4023         struct net_device *ndev = pci_get_drvdata(pdev);
4024         unregister_netdev(ndev);
4025         ql_release_all(pdev);
4026         pci_disable_device(pdev);
4027         free_netdev(ndev);
4028 }
4029
4030 /*
4031  * This callback is called by the PCI subsystem whenever
4032  * a PCI bus error is detected.
4033  */
4034 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4035                                                enum pci_channel_state state)
4036 {
4037         struct net_device *ndev = pci_get_drvdata(pdev);
4038         struct ql_adapter *qdev = netdev_priv(ndev);
4039
4040         netif_device_detach(ndev);
4041
4042         if (state == pci_channel_io_perm_failure)
4043                 return PCI_ERS_RESULT_DISCONNECT;
4044
4045         if (netif_running(ndev))
4046                 ql_adapter_down(qdev);
4047
4048         pci_disable_device(pdev);
4049
4050         /* Request a slot reset. */
4051         return PCI_ERS_RESULT_NEED_RESET;
4052 }
4053
4054 /*
4055  * This callback is called after the PCI buss has been reset.
4056  * Basically, this tries to restart the card from scratch.
4057  * This is a shortened version of the device probe/discovery code,
4058  * it resembles the first-half of the () routine.
4059  */
4060 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4061 {
4062         struct net_device *ndev = pci_get_drvdata(pdev);
4063         struct ql_adapter *qdev = netdev_priv(ndev);
4064
4065         if (pci_enable_device(pdev)) {
4066                 QPRINTK(qdev, IFUP, ERR,
4067                         "Cannot re-enable PCI device after reset.\n");
4068                 return PCI_ERS_RESULT_DISCONNECT;
4069         }
4070
4071         pci_set_master(pdev);
4072
4073         netif_carrier_off(ndev);
4074         ql_adapter_reset(qdev);
4075
4076         /* Make sure the EEPROM is good */
4077         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4078
4079         if (!is_valid_ether_addr(ndev->perm_addr)) {
4080                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
4081                 return PCI_ERS_RESULT_DISCONNECT;
4082         }
4083
4084         return PCI_ERS_RESULT_RECOVERED;
4085 }
4086
4087 static void qlge_io_resume(struct pci_dev *pdev)
4088 {
4089         struct net_device *ndev = pci_get_drvdata(pdev);
4090         struct ql_adapter *qdev = netdev_priv(ndev);
4091
4092         pci_set_master(pdev);
4093
4094         if (netif_running(ndev)) {
4095                 if (ql_adapter_up(qdev)) {
4096                         QPRINTK(qdev, IFUP, ERR,
4097                                 "Device initialization failed after reset.\n");
4098                         return;
4099                 }
4100         }
4101
4102         netif_device_attach(ndev);
4103 }
4104
4105 static struct pci_error_handlers qlge_err_handler = {
4106         .error_detected = qlge_io_error_detected,
4107         .slot_reset = qlge_io_slot_reset,
4108         .resume = qlge_io_resume,
4109 };
4110
4111 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4112 {
4113         struct net_device *ndev = pci_get_drvdata(pdev);
4114         struct ql_adapter *qdev = netdev_priv(ndev);
4115         int err;
4116
4117         netif_device_detach(ndev);
4118
4119         if (netif_running(ndev)) {
4120                 err = ql_adapter_down(qdev);
4121                 if (!err)
4122                         return err;
4123         }
4124
4125         err = pci_save_state(pdev);
4126         if (err)
4127                 return err;
4128
4129         pci_disable_device(pdev);
4130
4131         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4132
4133         return 0;
4134 }
4135
4136 #ifdef CONFIG_PM
4137 static int qlge_resume(struct pci_dev *pdev)
4138 {
4139         struct net_device *ndev = pci_get_drvdata(pdev);
4140         struct ql_adapter *qdev = netdev_priv(ndev);
4141         int err;
4142
4143         pci_set_power_state(pdev, PCI_D0);
4144         pci_restore_state(pdev);
4145         err = pci_enable_device(pdev);
4146         if (err) {
4147                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4148                 return err;
4149         }
4150         pci_set_master(pdev);
4151
4152         pci_enable_wake(pdev, PCI_D3hot, 0);
4153         pci_enable_wake(pdev, PCI_D3cold, 0);
4154
4155         if (netif_running(ndev)) {
4156                 err = ql_adapter_up(qdev);
4157                 if (err)
4158                         return err;
4159         }
4160
4161         netif_device_attach(ndev);
4162
4163         return 0;
4164 }
4165 #endif /* CONFIG_PM */
4166
4167 static void qlge_shutdown(struct pci_dev *pdev)
4168 {
4169         qlge_suspend(pdev, PMSG_SUSPEND);
4170 }
4171
4172 static struct pci_driver qlge_driver = {
4173         .name = DRV_NAME,
4174         .id_table = qlge_pci_tbl,
4175         .probe = qlge_probe,
4176         .remove = __devexit_p(qlge_remove),
4177 #ifdef CONFIG_PM
4178         .suspend = qlge_suspend,
4179         .resume = qlge_resume,
4180 #endif
4181         .shutdown = qlge_shutdown,
4182         .err_handler = &qlge_err_handler
4183 };
4184
4185 static int __init qlge_init_module(void)
4186 {
4187         return pci_register_driver(&qlge_driver);
4188 }
4189
4190 static void __exit qlge_exit(void)
4191 {
4192         pci_unregister_driver(&qlge_driver);
4193 }
4194
4195 module_init(qlge_init_module);
4196 module_exit(qlge_exit);