drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define DRV_NAME        "pcnet32"
  25 #define DRV_VERSION     "1.35"
  26 #define DRV_RELDATE     "21.Apr.2008"
  27 #define PFX             DRV_NAME ": "
  28
  29 static const char *const version =
  30     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/sched.h>
  35 #include <linux/string.h>
  36 #include <linux/errno.h>
  37 #include <linux/ioport.h>
  38 #include <linux/slab.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/pci.h>
  41 #include <linux/delay.h>
  42 #include <linux/init.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/crc32.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/etherdevice.h>
  48 #include <linux/if_ether.h>
  49 #include <linux/skbuff.h>
  50 #include <linux/spinlock.h>
  51 #include <linux/moduleparam.h>
  52 #include <linux/bitops.h>
  53
  54 #include <asm/dma.h>
  55 #include <asm/io.h>
  56 #include <asm/uaccess.h>
  57 #include <asm/irq.h>
  58
  59 /*
  60  * PCI device identifiers for "new style" Linux PCI Device Drivers
  61  */
  62 static struct pci_device_id pcnet32_pci_tbl[] = {
  63         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  64         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  65
  66         /*
  67          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  68          * the incorrect vendor id.
  69          */
  70         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  71           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  72
  73         { }     /* terminate list */
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  77
  78 static int cards_found;
  79
  80 /*
  81  * VLB I/O addresses
  82  */
  83 static unsigned int pcnet32_portlist[] __initdata =
  84     { 0x300, 0x320, 0x340, 0x360, 0 };
  85
  86 static int pcnet32_debug = 0;
  87 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  88 static int pcnet32vlb;          /* check for VLB cards ? */
  89
  90 static struct net_device *pcnet32_dev;
  91
  92 static int max_interrupt_work = 2;
  93 static int rx_copybreak = 200;
  94
  95 #define PCNET32_PORT_AUI      0x00
  96 #define PCNET32_PORT_10BT     0x01
  97 #define PCNET32_PORT_GPSI     0x02
  98 #define PCNET32_PORT_MII      0x03
  99
 100 #define PCNET32_PORT_PORTSEL  0x03
 101 #define PCNET32_PORT_ASEL     0x04
 102 #define PCNET32_PORT_100      0x40
 103 #define PCNET32_PORT_FD       0x80
 104
 105 #define PCNET32_DMA_MASK 0xffffffff
 106
 107 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 108 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 109
 110 /*
 111  * table to translate option values from tulip
 112  * to internal options
 113  */
 114 static const unsigned char options_mapping[] = {
 115         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 116         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 117         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 118         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 119         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 120         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 121         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 122         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 124         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 125         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 126         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 127         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 128         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 129                                                 /* 14 MII 100BaseTx-FD */
 130         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 131         PCNET32_PORT_ASEL                       /* 15 not supported    */
 132 };
 133
 134 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 135         "Loopback test  (offline)"
 136 };
 137
 138 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 139
 140 #define PCNET32_NUM_REGS 136
 141
 142 #define MAX_UNITS 8             /* More are supported, limit only on options */
 143 static int options[MAX_UNITS];
 144 static int full_duplex[MAX_UNITS];
 145 static int homepna[MAX_UNITS];
 146
 147 /*
 148  *                              Theory of Operation
 149  *
 150  * This driver uses the same software structure as the normal lance
 151  * driver. So look for a verbose description in lance.c. The differences
 152  * to the normal lance driver is the use of the 32bit mode of PCnet32
 153  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 154  * 16MB limitation and we don't need bounce buffers.
 155  */
 156
 157 /*
 158  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 159  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 160  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 161  */
 162 #ifndef PCNET32_LOG_TX_BUFFERS
 163 #define PCNET32_LOG_TX_BUFFERS          4
 164 #define PCNET32_LOG_RX_BUFFERS          5
 165 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 166 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 167 #endif
 168
 169 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 170 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 171
 172 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 173 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 174
 175 #define PKT_BUF_SKB             1544
 176 /* actual buffer length after being aligned */
 177 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 178 /* chip wants twos complement of the (aligned) buffer length */
 179 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 180
 181 /* Offsets from base I/O address. */
 182 #define PCNET32_WIO_RDP         0x10
 183 #define PCNET32_WIO_RAP         0x12
 184 #define PCNET32_WIO_RESET       0x14
 185 #define PCNET32_WIO_BDP         0x16
 186
 187 #define PCNET32_DWIO_RDP        0x10
 188 #define PCNET32_DWIO_RAP        0x14
 189 #define PCNET32_DWIO_RESET      0x18
 190 #define PCNET32_DWIO_BDP        0x1C
 191
 192 #define PCNET32_TOTAL_SIZE      0x20
 193
 194 #define CSR0            0
 195 #define CSR0_INIT       0x1
 196 #define CSR0_START      0x2
 197 #define CSR0_STOP       0x4
 198 #define CSR0_TXPOLL     0x8
 199 #define CSR0_INTEN      0x40
 200 #define CSR0_IDON       0x0100
 201 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 202 #define PCNET32_INIT_LOW        1
 203 #define PCNET32_INIT_HIGH       2
 204 #define CSR3            3
 205 #define CSR4            4
 206 #define CSR5            5
 207 #define CSR5_SUSPEND    0x0001
 208 #define CSR15           15
 209 #define PCNET32_MC_FILTER       8
 210
 211 #define PCNET32_79C970A 0x2621
 212
 213 /* The PCNET32 Rx and Tx ring descriptors. */
 214 struct pcnet32_rx_head {
 215         __le32  base;
 216         __le16  buf_length;     /* two`s complement of length */
 217         __le16  status;
 218         __le32  msg_length;
 219         __le32  reserved;
 220 };
 221
 222 struct pcnet32_tx_head {
 223         __le32  base;
 224         __le16  length;         /* two`s complement of length */
 225         __le16  status;
 226         __le32  misc;
 227         __le32  reserved;
 228 };
 229
 230 /* The PCNET32 32-Bit initialization block, described in databook. */
 231 struct pcnet32_init_block {
 232         __le16  mode;
 233         __le16  tlen_rlen;
 234         u8      phys_addr[6];
 235         __le16  reserved;
 236         __le32  filter[2];
 237         /* Receive and transmit ring base, along with extra bits. */
 238         __le32  rx_ring;
 239         __le32  tx_ring;
 240 };
 241
 242 /* PCnet32 access functions */
 243 struct pcnet32_access {
 244         u16     (*read_csr) (unsigned long, int);
 245         void    (*write_csr) (unsigned long, int, u16);
 246         u16     (*read_bcr) (unsigned long, int);
 247         void    (*write_bcr) (unsigned long, int, u16);
 248         u16     (*read_rap) (unsigned long);
 249         void    (*write_rap) (unsigned long, u16);
 250         void    (*reset) (unsigned long);
 251 };
 252
 253 /*
 254  * The first field of pcnet32_private is read by the ethernet device
 255  * so the structure should be allocated using pci_alloc_consistent().
 256  */
 257 struct pcnet32_private {
 258         struct pcnet32_init_block *init_block;
 259         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 260         struct pcnet32_rx_head  *rx_ring;
 261         struct pcnet32_tx_head  *tx_ring;
 262         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 263                                    returned by pci_alloc_consistent */
 264         struct pci_dev          *pci_dev;
 265         const char              *name;
 266         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 267         struct sk_buff          **tx_skbuff;
 268         struct sk_buff          **rx_skbuff;
 269         dma_addr_t              *tx_dma_addr;
 270         dma_addr_t              *rx_dma_addr;
 271         struct pcnet32_access   a;
 272         spinlock_t              lock;           /* Guard lock */
 273         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 274         unsigned int            rx_ring_size;   /* current rx ring size */
 275         unsigned int            tx_ring_size;   /* current tx ring size */
 276         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 277         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 278         unsigned short          rx_len_bits;
 279         unsigned short          tx_len_bits;
 280         dma_addr_t              rx_ring_dma_addr;
 281         dma_addr_t              tx_ring_dma_addr;
 282         unsigned int            dirty_rx,       /* ring entries to be freed. */
 283                                 dirty_tx;
 284
 285         struct net_device       *dev;
 286         struct napi_struct      napi;
 287         char                    tx_full;
 288         char                    phycount;       /* number of phys found */
 289         int                     options;
 290         unsigned int            shared_irq:1,   /* shared irq possible */
 291                                 dxsuflo:1,   /* disable transmit stop on uflo */
 292                                 mii:1;          /* mii port available */
 293         struct net_device       *next;
 294         struct mii_if_info      mii_if;
 295         struct timer_list       watchdog_timer;
 296         struct timer_list       blink_timer;
 297         u32                     msg_enable;     /* debug message level */
 298
 299         /* each bit indicates an available PHY */
 300         u32                     phymask;
 301         unsigned short          chip_version;   /* which variant this is */
 302 };
 303
 304 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 305 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 306 static int pcnet32_open(struct net_device *);
 307 static int pcnet32_init_ring(struct net_device *);
 308 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 309                                       struct net_device *);
 310 static void pcnet32_tx_timeout(struct net_device *dev);
 311 static irqreturn_t pcnet32_interrupt(int, void *);
 312 static int pcnet32_close(struct net_device *);
 313 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 314 static void pcnet32_load_multicast(struct net_device *dev);
 315 static void pcnet32_set_multicast_list(struct net_device *);
 316 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 317 static void pcnet32_watchdog(struct net_device *);
 318 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 319 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 320                        int val);
 321 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 322 static void pcnet32_ethtool_test(struct net_device *dev,
 323                                  struct ethtool_test *eth_test, u64 * data);
 324 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 325 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 326 static void pcnet32_led_blink_callback(struct net_device *dev);
 327 static int pcnet32_get_regs_len(struct net_device *dev);
 328 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 329                              void *ptr);
 330 static void pcnet32_purge_tx_ring(struct net_device *dev);
 331 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 332 static void pcnet32_free_ring(struct net_device *dev);
 333 static void pcnet32_check_media(struct net_device *dev, int verbose);
 334
 335 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 336 {
 337         outw(index, addr + PCNET32_WIO_RAP);
 338         return inw(addr + PCNET32_WIO_RDP);
 339 }
 340
 341 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 342 {
 343         outw(index, addr + PCNET32_WIO_RAP);
 344         outw(val, addr + PCNET32_WIO_RDP);
 345 }
 346
 347 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 348 {
 349         outw(index, addr + PCNET32_WIO_RAP);
 350         return inw(addr + PCNET32_WIO_BDP);
 351 }
 352
 353 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 354 {
 355         outw(index, addr + PCNET32_WIO_RAP);
 356         outw(val, addr + PCNET32_WIO_BDP);
 357 }
 358
 359 static u16 pcnet32_wio_read_rap(unsigned long addr)
 360 {
 361         return inw(addr + PCNET32_WIO_RAP);
 362 }
 363
 364 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 365 {
 366         outw(val, addr + PCNET32_WIO_RAP);
 367 }
 368
 369 static void pcnet32_wio_reset(unsigned long addr)
 370 {
 371         inw(addr + PCNET32_WIO_RESET);
 372 }
 373
 374 static int pcnet32_wio_check(unsigned long addr)
 375 {
 376         outw(88, addr + PCNET32_WIO_RAP);
 377         return (inw(addr + PCNET32_WIO_RAP) == 88);
 378 }
 379
 380 static struct pcnet32_access pcnet32_wio = {
 381         .read_csr = pcnet32_wio_read_csr,
 382         .write_csr = pcnet32_wio_write_csr,
 383         .read_bcr = pcnet32_wio_read_bcr,
 384         .write_bcr = pcnet32_wio_write_bcr,
 385         .read_rap = pcnet32_wio_read_rap,
 386         .write_rap = pcnet32_wio_write_rap,
 387         .reset = pcnet32_wio_reset
 388 };
 389
 390 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 391 {
 392         outl(index, addr + PCNET32_DWIO_RAP);
 393         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 394 }
 395
 396 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 397 {
 398         outl(index, addr + PCNET32_DWIO_RAP);
 399         outl(val, addr + PCNET32_DWIO_RDP);
 400 }
 401
 402 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 403 {
 404         outl(index, addr + PCNET32_DWIO_RAP);
 405         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 406 }
 407
 408 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 409 {
 410         outl(index, addr + PCNET32_DWIO_RAP);
 411         outl(val, addr + PCNET32_DWIO_BDP);
 412 }
 413
 414 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 415 {
 416         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 417 }
 418
 419 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 420 {
 421         outl(val, addr + PCNET32_DWIO_RAP);
 422 }
 423
 424 static void pcnet32_dwio_reset(unsigned long addr)
 425 {
 426         inl(addr + PCNET32_DWIO_RESET);
 427 }
 428
 429 static int pcnet32_dwio_check(unsigned long addr)
 430 {
 431         outl(88, addr + PCNET32_DWIO_RAP);
 432         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 433 }
 434
 435 static struct pcnet32_access pcnet32_dwio = {
 436         .read_csr = pcnet32_dwio_read_csr,
 437         .write_csr = pcnet32_dwio_write_csr,
 438         .read_bcr = pcnet32_dwio_read_bcr,
 439         .write_bcr = pcnet32_dwio_write_bcr,
 440         .read_rap = pcnet32_dwio_read_rap,
 441         .write_rap = pcnet32_dwio_write_rap,
 442         .reset = pcnet32_dwio_reset
 443 };
 444
 445 static void pcnet32_netif_stop(struct net_device *dev)
 446 {
 447         struct pcnet32_private *lp = netdev_priv(dev);
 448
 449         dev->trans_start = jiffies;
 450         napi_disable(&lp->napi);
 451         netif_tx_disable(dev);
 452 }
 453
 454 static void pcnet32_netif_start(struct net_device *dev)
 455 {
 456         struct pcnet32_private *lp = netdev_priv(dev);
 457         ulong ioaddr = dev->base_addr;
 458         u16 val;
 459
 460         netif_wake_queue(dev);
 461         val = lp->a.read_csr(ioaddr, CSR3);
 462         val &= 0x00ff;
 463         lp->a.write_csr(ioaddr, CSR3, val);
 464         napi_enable(&lp->napi);
 465 }
 466
 467 /*
 468  * Allocate space for the new sized tx ring.
 469  * Free old resources
 470  * Save new resources.
 471  * Any failure keeps old resources.
 472  * Must be called with lp->lock held.
 473  */
 474 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 475                                     struct pcnet32_private *lp,
 476                                     unsigned int size)
 477 {
 478         dma_addr_t new_ring_dma_addr;
 479         dma_addr_t *new_dma_addr_list;
 480         struct pcnet32_tx_head *new_tx_ring;
 481         struct sk_buff **new_skb_list;
 482
 483         pcnet32_purge_tx_ring(dev);
 484
 485         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 486                                            sizeof(struct pcnet32_tx_head) *
 487                                            (1 << size),
 488                                            &new_ring_dma_addr);
 489         if (new_tx_ring == NULL) {
 490                 if (netif_msg_drv(lp))
 491                         printk(KERN_ERR
 492                                "%s: Consistent memory allocation failed.\n",
 493                                dev->name);
 494                 return;
 495         }
 496         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 497
 498         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 499                                 GFP_ATOMIC);
 500         if (!new_dma_addr_list) {
 501                 if (netif_msg_drv(lp))
 502                         printk(KERN_ERR
 503                                "%s: Memory allocation failed.\n", dev->name);
 504                 goto free_new_tx_ring;
 505         }
 506
 507         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 508                                 GFP_ATOMIC);
 509         if (!new_skb_list) {
 510                 if (netif_msg_drv(lp))
 511                         printk(KERN_ERR
 512                                "%s: Memory allocation failed.\n", dev->name);
 513                 goto free_new_lists;
 514         }
 515
 516         kfree(lp->tx_skbuff);
 517         kfree(lp->tx_dma_addr);
 518         pci_free_consistent(lp->pci_dev,
 519                             sizeof(struct pcnet32_tx_head) *
 520                             lp->tx_ring_size, lp->tx_ring,
 521                             lp->tx_ring_dma_addr);
 522
 523         lp->tx_ring_size = (1 << size);
 524         lp->tx_mod_mask = lp->tx_ring_size - 1;
 525         lp->tx_len_bits = (size << 12);
 526         lp->tx_ring = new_tx_ring;
 527         lp->tx_ring_dma_addr = new_ring_dma_addr;
 528         lp->tx_dma_addr = new_dma_addr_list;
 529         lp->tx_skbuff = new_skb_list;
 530         return;
 531
 532     free_new_lists:
 533         kfree(new_dma_addr_list);
 534     free_new_tx_ring:
 535         pci_free_consistent(lp->pci_dev,
 536                             sizeof(struct pcnet32_tx_head) *
 537                             (1 << size),
 538                             new_tx_ring,
 539                             new_ring_dma_addr);
 540         return;
 541 }
 542
 543 /*
 544  * Allocate space for the new sized rx ring.
 545  * Re-use old receive buffers.
 546  *   alloc extra buffers
 547  *   free unneeded buffers
 548  *   free unneeded buffers
 549  * Save new resources.
 550  * Any failure keeps old resources.
 551  * Must be called with lp->lock held.
 552  */
 553 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 554                                     struct pcnet32_private *lp,
 555                                     unsigned int size)
 556 {
 557         dma_addr_t new_ring_dma_addr;
 558         dma_addr_t *new_dma_addr_list;
 559         struct pcnet32_rx_head *new_rx_ring;
 560         struct sk_buff **new_skb_list;
 561         int new, overlap;
 562
 563         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 564                                            sizeof(struct pcnet32_rx_head) *
 565                                            (1 << size),
 566                                            &new_ring_dma_addr);
 567         if (new_rx_ring == NULL) {
 568                 if (netif_msg_drv(lp))
 569                         printk(KERN_ERR
 570                                "%s: Consistent memory allocation failed.\n",
 571                                dev->name);
 572                 return;
 573         }
 574         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 575
 576         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 577                                 GFP_ATOMIC);
 578         if (!new_dma_addr_list) {
 579                 if (netif_msg_drv(lp))
 580                         printk(KERN_ERR
 581                                "%s: Memory allocation failed.\n", dev->name);
 582                 goto free_new_rx_ring;
 583         }
 584
 585         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 586                                 GFP_ATOMIC);
 587         if (!new_skb_list) {
 588                 if (netif_msg_drv(lp))
 589                         printk(KERN_ERR
 590                                "%s: Memory allocation failed.\n", dev->name);
 591                 goto free_new_lists;
 592         }
 593
 594         /* first copy the current receive buffers */
 595         overlap = min(size, lp->rx_ring_size);
 596         for (new = 0; new < overlap; new++) {
 597                 new_rx_ring[new] = lp->rx_ring[new];
 598                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 599                 new_skb_list[new] = lp->rx_skbuff[new];
 600         }
 601         /* now allocate any new buffers needed */
 602         for (; new < size; new++ ) {
 603                 struct sk_buff *rx_skbuff;
 604                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
 605                 if (!(rx_skbuff = new_skb_list[new])) {
 606                         /* keep the original lists and buffers */
 607                         if (netif_msg_drv(lp))
 608                                 printk(KERN_ERR
 609                                        "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
 610                                        dev->name);
 611                         goto free_all_new;
 612                 }
 613                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 614
 615                 new_dma_addr_list[new] =
 616                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 617                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 618                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 619                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 620                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 621         }
 622         /* and free any unneeded buffers */
 623         for (; new < lp->rx_ring_size; new++) {
 624                 if (lp->rx_skbuff[new]) {
 625                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 626                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 627                         dev_kfree_skb(lp->rx_skbuff[new]);
 628                 }
 629         }
 630
 631         kfree(lp->rx_skbuff);
 632         kfree(lp->rx_dma_addr);
 633         pci_free_consistent(lp->pci_dev,
 634                             sizeof(struct pcnet32_rx_head) *
 635                             lp->rx_ring_size, lp->rx_ring,
 636                             lp->rx_ring_dma_addr);
 637
 638         lp->rx_ring_size = (1 << size);
 639         lp->rx_mod_mask = lp->rx_ring_size - 1;
 640         lp->rx_len_bits = (size << 4);
 641         lp->rx_ring = new_rx_ring;
 642         lp->rx_ring_dma_addr = new_ring_dma_addr;
 643         lp->rx_dma_addr = new_dma_addr_list;
 644         lp->rx_skbuff = new_skb_list;
 645         return;
 646
 647     free_all_new:
 648         for (; --new >= lp->rx_ring_size; ) {
 649                 if (new_skb_list[new]) {
 650                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 651                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 652                         dev_kfree_skb(new_skb_list[new]);
 653                 }
 654         }
 655         kfree(new_skb_list);
 656     free_new_lists:
 657         kfree(new_dma_addr_list);
 658     free_new_rx_ring:
 659         pci_free_consistent(lp->pci_dev,
 660                             sizeof(struct pcnet32_rx_head) *
 661                             (1 << size),
 662                             new_rx_ring,
 663                             new_ring_dma_addr);
 664         return;
 665 }
 666
 667 static void pcnet32_purge_rx_ring(struct net_device *dev)
 668 {
 669         struct pcnet32_private *lp = netdev_priv(dev);
 670         int i;
 671
 672         /* free all allocated skbuffs */
 673         for (i = 0; i < lp->rx_ring_size; i++) {
 674                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 675                 wmb();          /* Make sure adapter sees owner change */
 676                 if (lp->rx_skbuff[i]) {
 677                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 678                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 679                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 680                 }
 681                 lp->rx_skbuff[i] = NULL;
 682                 lp->rx_dma_addr[i] = 0;
 683         }
 684 }
 685
 686 #ifdef CONFIG_NET_POLL_CONTROLLER
 687 static void pcnet32_poll_controller(struct net_device *dev)
 688 {
 689         disable_irq(dev->irq);
 690         pcnet32_interrupt(0, dev);
 691         enable_irq(dev->irq);
 692 }
 693 #endif
 694
 695 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 696 {
 697         struct pcnet32_private *lp = netdev_priv(dev);
 698         unsigned long flags;
 699         int r = -EOPNOTSUPP;
 700
 701         if (lp->mii) {
 702                 spin_lock_irqsave(&lp->lock, flags);
 703                 mii_ethtool_gset(&lp->mii_if, cmd);
 704                 spin_unlock_irqrestore(&lp->lock, flags);
 705                 r = 0;
 706         }
 707         return r;
 708 }
 709
 710 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 711 {
 712         struct pcnet32_private *lp = netdev_priv(dev);
 713         unsigned long flags;
 714         int r = -EOPNOTSUPP;
 715
 716         if (lp->mii) {
 717                 spin_lock_irqsave(&lp->lock, flags);
 718                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 719                 spin_unlock_irqrestore(&lp->lock, flags);
 720         }
 721         return r;
 722 }
 723
 724 static void pcnet32_get_drvinfo(struct net_device *dev,
 725                                 struct ethtool_drvinfo *info)
 726 {
 727         struct pcnet32_private *lp = netdev_priv(dev);
 728
 729         strcpy(info->driver, DRV_NAME);
 730         strcpy(info->version, DRV_VERSION);
 731         if (lp->pci_dev)
 732                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 733         else
 734                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 735 }
 736
 737 static u32 pcnet32_get_link(struct net_device *dev)
 738 {
 739         struct pcnet32_private *lp = netdev_priv(dev);
 740         unsigned long flags;
 741         int r;
 742
 743         spin_lock_irqsave(&lp->lock, flags);
 744         if (lp->mii) {
 745                 r = mii_link_ok(&lp->mii_if);
 746         } else if (lp->chip_version >= PCNET32_79C970A) {
 747                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 748                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 749         } else {        /* can not detect link on really old chips */
 750                 r = 1;
 751         }
 752         spin_unlock_irqrestore(&lp->lock, flags);
 753
 754         return r;
 755 }
 756
 757 static u32 pcnet32_get_msglevel(struct net_device *dev)
 758 {
 759         struct pcnet32_private *lp = netdev_priv(dev);
 760         return lp->msg_enable;
 761 }
 762
 763 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 764 {
 765         struct pcnet32_private *lp = netdev_priv(dev);
 766         lp->msg_enable = value;
 767 }
 768
 769 static int pcnet32_nway_reset(struct net_device *dev)
 770 {
 771         struct pcnet32_private *lp = netdev_priv(dev);
 772         unsigned long flags;
 773         int r = -EOPNOTSUPP;
 774
 775         if (lp->mii) {
 776                 spin_lock_irqsave(&lp->lock, flags);
 777                 r = mii_nway_restart(&lp->mii_if);
 778                 spin_unlock_irqrestore(&lp->lock, flags);
 779         }
 780         return r;
 781 }
 782
 783 static void pcnet32_get_ringparam(struct net_device *dev,
 784                                   struct ethtool_ringparam *ering)
 785 {
 786         struct pcnet32_private *lp = netdev_priv(dev);
 787
 788         ering->tx_max_pending = TX_MAX_RING_SIZE;
 789         ering->tx_pending = lp->tx_ring_size;
 790         ering->rx_max_pending = RX_MAX_RING_SIZE;
 791         ering->rx_pending = lp->rx_ring_size;
 792 }
 793
 794 static int pcnet32_set_ringparam(struct net_device *dev,
 795                                  struct ethtool_ringparam *ering)
 796 {
 797         struct pcnet32_private *lp = netdev_priv(dev);
 798         unsigned long flags;
 799         unsigned int size;
 800         ulong ioaddr = dev->base_addr;
 801         int i;
 802
 803         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 804                 return -EINVAL;
 805
 806         if (netif_running(dev))
 807                 pcnet32_netif_stop(dev);
 808
 809         spin_lock_irqsave(&lp->lock, flags);
 810         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 811
 812         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 813
 814         /* set the minimum ring size to 4, to allow the loopback test to work
 815          * unchanged.
 816          */
 817         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 818                 if (size <= (1 << i))
 819                         break;
 820         }
 821         if ((1 << i) != lp->tx_ring_size)
 822                 pcnet32_realloc_tx_ring(dev, lp, i);
 823
 824         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 825         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 826                 if (size <= (1 << i))
 827                         break;
 828         }
 829         if ((1 << i) != lp->rx_ring_size)
 830                 pcnet32_realloc_rx_ring(dev, lp, i);
 831
 832         lp->napi.weight = lp->rx_ring_size / 2;
 833
 834         if (netif_running(dev)) {
 835                 pcnet32_netif_start(dev);
 836                 pcnet32_restart(dev, CSR0_NORMAL);
 837         }
 838
 839         spin_unlock_irqrestore(&lp->lock, flags);
 840
 841         if (netif_msg_drv(lp))
 842                 printk(KERN_INFO
 843                        "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
 844                        lp->rx_ring_size, lp->tx_ring_size);
 845
 846         return 0;
 847 }
 848
 849 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 850                                 u8 * data)
 851 {
 852         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 853 }
 854
 855 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 856 {
 857         switch (sset) {
 858         case ETH_SS_TEST:
 859                 return PCNET32_TEST_LEN;
 860         default:
 861                 return -EOPNOTSUPP;
 862         }
 863 }
 864
 865 static void pcnet32_ethtool_test(struct net_device *dev,
 866                                  struct ethtool_test *test, u64 * data)
 867 {
 868         struct pcnet32_private *lp = netdev_priv(dev);
 869         int rc;
 870
 871         if (test->flags == ETH_TEST_FL_OFFLINE) {
 872                 rc = pcnet32_loopback_test(dev, data);
 873                 if (rc) {
 874                         if (netif_msg_hw(lp))
 875                                 printk(KERN_DEBUG "%s: Loopback test failed.\n",
 876                                        dev->name);
 877                         test->flags |= ETH_TEST_FL_FAILED;
 878                 } else if (netif_msg_hw(lp))
 879                         printk(KERN_DEBUG "%s: Loopback test passed.\n",
 880                                dev->name);
 881         } else if (netif_msg_hw(lp))
 882                 printk(KERN_DEBUG
 883                        "%s: No tests to run (specify 'Offline' on ethtool).",
 884                        dev->name);
 885 }                               /* end pcnet32_ethtool_test */
 886
 887 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 888 {
 889         struct pcnet32_private *lp = netdev_priv(dev);
 890         struct pcnet32_access *a = &lp->a;      /* access to registers */
 891         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 892         struct sk_buff *skb;    /* sk buff */
 893         int x, i;               /* counters */
 894         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 895         u16 status = 0x8300;    /* TX ring status */
 896         __le16 teststatus;      /* test of ring status */
 897         int rc;                 /* return code */
 898         int size;               /* size of packets */
 899         unsigned char *packet;  /* source packet data */
 900         static const int data_len = 60; /* length of source packets */
 901         unsigned long flags;
 902         unsigned long ticks;
 903
 904         rc = 1;                 /* default to fail */
 905
 906         if (netif_running(dev))
 907                 pcnet32_netif_stop(dev);
 908
 909         spin_lock_irqsave(&lp->lock, flags);
 910         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 911
 912         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 913
 914         /* Reset the PCNET32 */
 915         lp->a.reset(ioaddr);
 916         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
 917
 918         /* switch pcnet32 to 32bit mode */
 919         lp->a.write_bcr(ioaddr, 20, 2);
 920
 921         /* purge & init rings but don't actually restart */
 922         pcnet32_restart(dev, 0x0000);
 923
 924         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 925
 926         /* Initialize Transmit buffers. */
 927         size = data_len + 15;
 928         for (x = 0; x < numbuffs; x++) {
 929                 if (!(skb = dev_alloc_skb(size))) {
 930                         if (netif_msg_hw(lp))
 931                                 printk(KERN_DEBUG
 932                                        "%s: Cannot allocate skb at line: %d!\n",
 933                                        dev->name, __LINE__);
 934                         goto clean_up;
 935                 } else {
 936                         packet = skb->data;
 937                         skb_put(skb, size);     /* create space for data */
 938                         lp->tx_skbuff[x] = skb;
 939                         lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 940                         lp->tx_ring[x].misc = 0;
 941
 942                         /* put DA and SA into the skb */
 943                         for (i = 0; i < 6; i++)
 944                                 *packet++ = dev->dev_addr[i];
 945                         for (i = 0; i < 6; i++)
 946                                 *packet++ = dev->dev_addr[i];
 947                         /* type */
 948                         *packet++ = 0x08;
 949                         *packet++ = 0x06;
 950                         /* packet number */
 951                         *packet++ = x;
 952                         /* fill packet with data */
 953                         for (i = 0; i < data_len; i++)
 954                                 *packet++ = i;
 955
 956                         lp->tx_dma_addr[x] =
 957                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 958                                            PCI_DMA_TODEVICE);
 959                         lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 960                         wmb();  /* Make sure owner changes after all others are visible */
 961                         lp->tx_ring[x].status = cpu_to_le16(status);
 962                 }
 963         }
 964
 965         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 966         a->write_bcr(ioaddr, 32, x | 0x0002);
 967
 968         /* set int loopback in CSR15 */
 969         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 970         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 971
 972         teststatus = cpu_to_le16(0x8000);
 973         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 974
 975         /* Check status of descriptors */
 976         for (x = 0; x < numbuffs; x++) {
 977                 ticks = 0;
 978                 rmb();
 979                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 980                         spin_unlock_irqrestore(&lp->lock, flags);
 981                         msleep(1);
 982                         spin_lock_irqsave(&lp->lock, flags);
 983                         rmb();
 984                         ticks++;
 985                 }
 986                 if (ticks == 200) {
 987                         if (netif_msg_hw(lp))
 988                                 printk("%s: Desc %d failed to reset!\n",
 989                                        dev->name, x);
 990                         break;
 991                 }
 992         }
 993
 994         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 995         wmb();
 996         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 997                 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
 998
 999                 for (x = 0; x < numbuffs; x++) {
1000                         printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1001                         skb = lp->rx_skbuff[x];
1002                         for (i = 0; i < size; i++) {
1003                                 printk("%02x ", *(skb->data + i));
1004                         }
1005                         printk("\n");
1006                 }
1007         }
1008
1009         x = 0;
1010         rc = 0;
1011         while (x < numbuffs && !rc) {
1012                 skb = lp->rx_skbuff[x];
1013                 packet = lp->tx_skbuff[x]->data;
1014                 for (i = 0; i < size; i++) {
1015                         if (*(skb->data + i) != packet[i]) {
1016                                 if (netif_msg_hw(lp))
1017                                         printk(KERN_DEBUG
1018                                                "%s: Error in compare! %2x - %02x %02x\n",
1019                                                dev->name, i, *(skb->data + i),
1020                                                packet[i]);
1021                                 rc = 1;
1022                                 break;
1023                         }
1024                 }
1025                 x++;
1026         }
1027
1028       clean_up:
1029         *data1 = rc;
1030         pcnet32_purge_tx_ring(dev);
1031
1032         x = a->read_csr(ioaddr, CSR15);
1033         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1034
1035         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1036         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1037
1038         if (netif_running(dev)) {
1039                 pcnet32_netif_start(dev);
1040                 pcnet32_restart(dev, CSR0_NORMAL);
1041         } else {
1042                 pcnet32_purge_rx_ring(dev);
1043                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1044         }
1045         spin_unlock_irqrestore(&lp->lock, flags);
1046
1047         return (rc);
1048 }                               /* end pcnet32_loopback_test  */
1049
1050 static void pcnet32_led_blink_callback(struct net_device *dev)
1051 {
1052         struct pcnet32_private *lp = netdev_priv(dev);
1053         struct pcnet32_access *a = &lp->a;
1054         ulong ioaddr = dev->base_addr;
1055         unsigned long flags;
1056         int i;
1057
1058         spin_lock_irqsave(&lp->lock, flags);
1059         for (i = 4; i < 8; i++) {
1060                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1061         }
1062         spin_unlock_irqrestore(&lp->lock, flags);
1063
1064         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1065 }
1066
1067 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1068 {
1069         struct pcnet32_private *lp = netdev_priv(dev);
1070         struct pcnet32_access *a = &lp->a;
1071         ulong ioaddr = dev->base_addr;
1072         unsigned long flags;
1073         int i, regs[4];
1074
1075         if (!lp->blink_timer.function) {
1076                 init_timer(&lp->blink_timer);
1077                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1078                 lp->blink_timer.data = (unsigned long)dev;
1079         }
1080
1081         /* Save the current value of the bcrs */
1082         spin_lock_irqsave(&lp->lock, flags);
1083         for (i = 4; i < 8; i++) {
1084                 regs[i - 4] = a->read_bcr(ioaddr, i);
1085         }
1086         spin_unlock_irqrestore(&lp->lock, flags);
1087
1088         mod_timer(&lp->blink_timer, jiffies);
1089         set_current_state(TASK_INTERRUPTIBLE);
1090
1091         /* AV: the limit here makes no sense whatsoever */
1092         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1093                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1094
1095         msleep_interruptible(data * 1000);
1096         del_timer_sync(&lp->blink_timer);
1097
1098         /* Restore the original value of the bcrs */
1099         spin_lock_irqsave(&lp->lock, flags);
1100         for (i = 4; i < 8; i++) {
1101                 a->write_bcr(ioaddr, i, regs[i - 4]);
1102         }
1103         spin_unlock_irqrestore(&lp->lock, flags);
1104
1105         return 0;
1106 }
1107
1108 /*
1109  * lp->lock must be held.
1110  */
1111 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1112                 int can_sleep)
1113 {
1114         int csr5;
1115         struct pcnet32_private *lp = netdev_priv(dev);
1116         struct pcnet32_access *a = &lp->a;
1117         ulong ioaddr = dev->base_addr;
1118         int ticks;
1119
1120         /* really old chips have to be stopped. */
1121         if (lp->chip_version < PCNET32_79C970A)
1122                 return 0;
1123
1124         /* set SUSPEND (SPND) - CSR5 bit 0 */
1125         csr5 = a->read_csr(ioaddr, CSR5);
1126         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1127
1128         /* poll waiting for bit to be set */
1129         ticks = 0;
1130         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1131                 spin_unlock_irqrestore(&lp->lock, *flags);
1132                 if (can_sleep)
1133                         msleep(1);
1134                 else
1135                         mdelay(1);
1136                 spin_lock_irqsave(&lp->lock, *flags);
1137                 ticks++;
1138                 if (ticks > 200) {
1139                         if (netif_msg_hw(lp))
1140                                 printk(KERN_DEBUG
1141                                        "%s: Error getting into suspend!\n",
1142                                        dev->name);
1143                         return 0;
1144                 }
1145         }
1146         return 1;
1147 }
1148
1149 /*
1150  * process one receive descriptor entry
1151  */
1152
1153 static void pcnet32_rx_entry(struct net_device *dev,
1154                              struct pcnet32_private *lp,
1155                              struct pcnet32_rx_head *rxp,
1156                              int entry)
1157 {
1158         int status = (short)le16_to_cpu(rxp->status) >> 8;
1159         int rx_in_place = 0;
1160         struct sk_buff *skb;
1161         short pkt_len;
1162
1163         if (status != 0x03) {   /* There was an error. */
1164                 /*
1165                  * There is a tricky error noted by John Murphy,
1166                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1167                  * buffers it's possible for a jabber packet to use two
1168                  * buffers, with only the last correctly noting the error.
1169                  */
1170                 if (status & 0x01)      /* Only count a general error at the */
1171                         dev->stats.rx_errors++; /* end of a packet. */
1172                 if (status & 0x20)
1173                         dev->stats.rx_frame_errors++;
1174                 if (status & 0x10)
1175                         dev->stats.rx_over_errors++;
1176                 if (status & 0x08)
1177                         dev->stats.rx_crc_errors++;
1178                 if (status & 0x04)
1179                         dev->stats.rx_fifo_errors++;
1180                 return;
1181         }
1182
1183         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1184
1185         /* Discard oversize frames. */
1186         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1187                 if (netif_msg_drv(lp))
1188                         printk(KERN_ERR "%s: Impossible packet size %d!\n",
1189                                dev->name, pkt_len);
1190                 dev->stats.rx_errors++;
1191                 return;
1192         }
1193         if (pkt_len < 60) {
1194                 if (netif_msg_rx_err(lp))
1195                         printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1196                 dev->stats.rx_errors++;
1197                 return;
1198         }
1199
1200         if (pkt_len > rx_copybreak) {
1201                 struct sk_buff *newskb;
1202
1203                 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1204                         skb_reserve(newskb, NET_IP_ALIGN);
1205                         skb = lp->rx_skbuff[entry];
1206                         pci_unmap_single(lp->pci_dev,
1207                                          lp->rx_dma_addr[entry],
1208                                          PKT_BUF_SIZE,
1209                                          PCI_DMA_FROMDEVICE);
1210                         skb_put(skb, pkt_len);
1211                         lp->rx_skbuff[entry] = newskb;
1212                         lp->rx_dma_addr[entry] =
1213                                             pci_map_single(lp->pci_dev,
1214                                                            newskb->data,
1215                                                            PKT_BUF_SIZE,
1216                                                            PCI_DMA_FROMDEVICE);
1217                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1218                         rx_in_place = 1;
1219                 } else
1220                         skb = NULL;
1221         } else {
1222                 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1223         }
1224
1225         if (skb == NULL) {
1226                 if (netif_msg_drv(lp))
1227                         printk(KERN_ERR
1228                                "%s: Memory squeeze, dropping packet.\n",
1229                                dev->name);
1230                 dev->stats.rx_dropped++;
1231                 return;
1232         }
1233         if (!rx_in_place) {
1234                 skb_reserve(skb, NET_IP_ALIGN);
1235                 skb_put(skb, pkt_len);  /* Make room */
1236                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1237                                             lp->rx_dma_addr[entry],
1238                                             pkt_len,
1239                                             PCI_DMA_FROMDEVICE);
1240                 skb_copy_to_linear_data(skb,
1241                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1242                                  pkt_len);
1243                 pci_dma_sync_single_for_device(lp->pci_dev,
1244                                                lp->rx_dma_addr[entry],
1245                                                pkt_len,
1246                                                PCI_DMA_FROMDEVICE);
1247         }
1248         dev->stats.rx_bytes += skb->len;
1249         skb->protocol = eth_type_trans(skb, dev);
1250         netif_receive_skb(skb);
1251         dev->stats.rx_packets++;
1252         return;
1253 }
1254
1255 static int pcnet32_rx(struct net_device *dev, int budget)
1256 {
1257         struct pcnet32_private *lp = netdev_priv(dev);
1258         int entry = lp->cur_rx & lp->rx_mod_mask;
1259         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1260         int npackets = 0;
1261
1262         /* If we own the next entry, it's a new packet. Send it up. */
1263         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1264                 pcnet32_rx_entry(dev, lp, rxp, entry);
1265                 npackets += 1;
1266                 /*
1267                  * The docs say that the buffer length isn't touched, but Andrew
1268                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1269                  */
1270                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1271                 wmb();  /* Make sure owner changes after others are visible */
1272                 rxp->status = cpu_to_le16(0x8000);
1273                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1274                 rxp = &lp->rx_ring[entry];
1275         }
1276
1277         return npackets;
1278 }
1279
1280 static int pcnet32_tx(struct net_device *dev)
1281 {
1282         struct pcnet32_private *lp = netdev_priv(dev);
1283         unsigned int dirty_tx = lp->dirty_tx;
1284         int delta;
1285         int must_restart = 0;
1286
1287         while (dirty_tx != lp->cur_tx) {
1288                 int entry = dirty_tx & lp->tx_mod_mask;
1289                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1290
1291                 if (status < 0)
1292                         break;  /* It still hasn't been Txed */
1293
1294                 lp->tx_ring[entry].base = 0;
1295
1296                 if (status & 0x4000) {
1297                         /* There was a major error, log it. */
1298                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1299                         dev->stats.tx_errors++;
1300                         if (netif_msg_tx_err(lp))
1301                                 printk(KERN_ERR
1302                                        "%s: Tx error status=%04x err_status=%08x\n",
1303                                        dev->name, status,
1304                                        err_status);
1305                         if (err_status & 0x04000000)
1306                                 dev->stats.tx_aborted_errors++;
1307                         if (err_status & 0x08000000)
1308                                 dev->stats.tx_carrier_errors++;
1309                         if (err_status & 0x10000000)
1310                                 dev->stats.tx_window_errors++;
1311 #ifndef DO_DXSUFLO
1312                         if (err_status & 0x40000000) {
1313                                 dev->stats.tx_fifo_errors++;
1314                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1315                                 /* Remove this verbosity later! */
1316                                 if (netif_msg_tx_err(lp))
1317                                         printk(KERN_ERR
1318                                                "%s: Tx FIFO error!\n",
1319                                                dev->name);
1320                                 must_restart = 1;
1321                         }
1322 #else
1323                         if (err_status & 0x40000000) {
1324                                 dev->stats.tx_fifo_errors++;
1325                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1326                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1327                                         /* Remove this verbosity later! */
1328                                         if (netif_msg_tx_err(lp))
1329                                                 printk(KERN_ERR
1330                                                        "%s: Tx FIFO error!\n",
1331                                                        dev->name);
1332                                         must_restart = 1;
1333                                 }
1334                         }
1335 #endif
1336                 } else {
1337                         if (status & 0x1800)
1338                                 dev->stats.collisions++;
1339                         dev->stats.tx_packets++;
1340                 }
1341
1342                 /* We must free the original skb */
1343                 if (lp->tx_skbuff[entry]) {
1344                         pci_unmap_single(lp->pci_dev,
1345                                          lp->tx_dma_addr[entry],
1346                                          lp->tx_skbuff[entry]->
1347                                          len, PCI_DMA_TODEVICE);
1348                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1349                         lp->tx_skbuff[entry] = NULL;
1350                         lp->tx_dma_addr[entry] = 0;
1351                 }
1352                 dirty_tx++;
1353         }
1354
1355         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1356         if (delta > lp->tx_ring_size) {
1357                 if (netif_msg_drv(lp))
1358                         printk(KERN_ERR
1359                                "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1360                                dev->name, dirty_tx, lp->cur_tx,
1361                                lp->tx_full);
1362                 dirty_tx += lp->tx_ring_size;
1363                 delta -= lp->tx_ring_size;
1364         }
1365
1366         if (lp->tx_full &&
1367             netif_queue_stopped(dev) &&
1368             delta < lp->tx_ring_size - 2) {
1369                 /* The ring is no longer full, clear tbusy. */
1370                 lp->tx_full = 0;
1371                 netif_wake_queue(dev);
1372         }
1373         lp->dirty_tx = dirty_tx;
1374
1375         return must_restart;
1376 }
1377
1378 static int pcnet32_poll(struct napi_struct *napi, int budget)
1379 {
1380         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1381         struct net_device *dev = lp->dev;
1382         unsigned long ioaddr = dev->base_addr;
1383         unsigned long flags;
1384         int work_done;
1385         u16 val;
1386
1387         work_done = pcnet32_rx(dev, budget);
1388
1389         spin_lock_irqsave(&lp->lock, flags);
1390         if (pcnet32_tx(dev)) {
1391                 /* reset the chip to clear the error condition, then restart */
1392                 lp->a.reset(ioaddr);
1393                 lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
1394                 pcnet32_restart(dev, CSR0_START);
1395                 netif_wake_queue(dev);
1396         }
1397         spin_unlock_irqrestore(&lp->lock, flags);
1398
1399         if (work_done < budget) {
1400                 spin_lock_irqsave(&lp->lock, flags);
1401
1402                 __napi_complete(napi);
1403
1404                 /* clear interrupt masks */
1405                 val = lp->a.read_csr(ioaddr, CSR3);
1406                 val &= 0x00ff;
1407                 lp->a.write_csr(ioaddr, CSR3, val);
1408
1409                 /* Set interrupt enable. */
1410                 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1411
1412                 spin_unlock_irqrestore(&lp->lock, flags);
1413         }
1414         return work_done;
1415 }
1416
1417 #define PCNET32_REGS_PER_PHY    32
1418 #define PCNET32_MAX_PHYS        32
1419 static int pcnet32_get_regs_len(struct net_device *dev)
1420 {
1421         struct pcnet32_private *lp = netdev_priv(dev);
1422         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1423
1424         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1425 }
1426
1427 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1428                              void *ptr)
1429 {
1430         int i, csr0;
1431         u16 *buff = ptr;
1432         struct pcnet32_private *lp = netdev_priv(dev);
1433         struct pcnet32_access *a = &lp->a;
1434         ulong ioaddr = dev->base_addr;
1435         unsigned long flags;
1436
1437         spin_lock_irqsave(&lp->lock, flags);
1438
1439         csr0 = a->read_csr(ioaddr, CSR0);
1440         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1441                 pcnet32_suspend(dev, &flags, 1);
1442
1443         /* read address PROM */
1444         for (i = 0; i < 16; i += 2)
1445                 *buff++ = inw(ioaddr + i);
1446
1447         /* read control and status registers */
1448         for (i = 0; i < 90; i++) {
1449                 *buff++ = a->read_csr(ioaddr, i);
1450         }
1451
1452         *buff++ = a->read_csr(ioaddr, 112);
1453         *buff++ = a->read_csr(ioaddr, 114);
1454
1455         /* read bus configuration registers */
1456         for (i = 0; i < 30; i++) {
1457                 *buff++ = a->read_bcr(ioaddr, i);
1458         }
1459         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1460         for (i = 31; i < 36; i++) {
1461                 *buff++ = a->read_bcr(ioaddr, i);
1462         }
1463
1464         /* read mii phy registers */
1465         if (lp->mii) {
1466                 int j;
1467                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1468                         if (lp->phymask & (1 << j)) {
1469                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1470                                         lp->a.write_bcr(ioaddr, 33,
1471                                                         (j << 5) | i);
1472                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1473                                 }
1474                         }
1475                 }
1476         }
1477
1478         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1479                 int csr5;
1480
1481                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1482                 csr5 = a->read_csr(ioaddr, CSR5);
1483                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1484         }
1485
1486         spin_unlock_irqrestore(&lp->lock, flags);
1487 }
1488
1489 static const struct ethtool_ops pcnet32_ethtool_ops = {
1490         .get_settings           = pcnet32_get_settings,
1491         .set_settings           = pcnet32_set_settings,
1492         .get_drvinfo            = pcnet32_get_drvinfo,
1493         .get_msglevel           = pcnet32_get_msglevel,
1494         .set_msglevel           = pcnet32_set_msglevel,
1495         .nway_reset             = pcnet32_nway_reset,
1496         .get_link               = pcnet32_get_link,
1497         .get_ringparam          = pcnet32_get_ringparam,
1498         .set_ringparam          = pcnet32_set_ringparam,
1499         .get_strings            = pcnet32_get_strings,
1500         .self_test              = pcnet32_ethtool_test,
1501         .phys_id                = pcnet32_phys_id,
1502         .get_regs_len           = pcnet32_get_regs_len,
1503         .get_regs               = pcnet32_get_regs,
1504         .get_sset_count         = pcnet32_get_sset_count,
1505 };
1506
1507 /* only probes for non-PCI devices, the rest are handled by
1508  * pci_register_driver via pcnet32_probe_pci */
1509
1510 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1511 {
1512         unsigned int *port, ioaddr;
1513
1514         /* search for PCnet32 VLB cards at known addresses */
1515         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1516                 if (request_region
1517                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1518                         /* check if there is really a pcnet chip on that ioaddr */
1519                         if ((inb(ioaddr + 14) == 0x57) &&
1520                             (inb(ioaddr + 15) == 0x57)) {
1521                                 pcnet32_probe1(ioaddr, 0, NULL);
1522                         } else {
1523                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1524                         }
1525                 }
1526         }
1527 }
1528
1529 static int __devinit
1530 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1531 {
1532         unsigned long ioaddr;
1533         int err;
1534
1535         err = pci_enable_device(pdev);
1536         if (err < 0) {
1537                 if (pcnet32_debug & NETIF_MSG_PROBE)
1538                         printk(KERN_ERR PFX
1539                                "failed to enable device -- err=%d\n", err);
1540                 return err;
1541         }
1542         pci_set_master(pdev);
1543
1544         ioaddr = pci_resource_start(pdev, 0);
1545         if (!ioaddr) {
1546                 if (pcnet32_debug & NETIF_MSG_PROBE)
1547                         printk(KERN_ERR PFX
1548                                "card has no PCI IO resources, aborting\n");
1549                 return -ENODEV;
1550         }
1551
1552         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1553                 if (pcnet32_debug & NETIF_MSG_PROBE)
1554                         printk(KERN_ERR PFX
1555                                "architecture does not support 32bit PCI busmaster DMA\n");
1556                 return -ENODEV;
1557         }
1558         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1559             NULL) {
1560                 if (pcnet32_debug & NETIF_MSG_PROBE)
1561                         printk(KERN_ERR PFX
1562                                "io address range already allocated\n");
1563                 return -EBUSY;
1564         }
1565
1566         err = pcnet32_probe1(ioaddr, 1, pdev);
1567         if (err < 0) {
1568                 pci_disable_device(pdev);
1569         }
1570         return err;
1571 }
1572
1573 static const struct net_device_ops pcnet32_netdev_ops = {
1574         .ndo_open               = pcnet32_open,
1575         .ndo_stop               = pcnet32_close,
1576         .ndo_start_xmit         = pcnet32_start_xmit,
1577         .ndo_tx_timeout         = pcnet32_tx_timeout,
1578         .ndo_get_stats          = pcnet32_get_stats,
1579         .ndo_set_multicast_list = pcnet32_set_multicast_list,
1580         .ndo_do_ioctl           = pcnet32_ioctl,
1581         .ndo_change_mtu         = eth_change_mtu,
1582         .ndo_set_mac_address    = eth_mac_addr,
1583         .ndo_validate_addr      = eth_validate_addr,
1584 #ifdef CONFIG_NET_POLL_CONTROLLER
1585         .ndo_poll_controller    = pcnet32_poll_controller,
1586 #endif
1587 };
1588
1589 /* pcnet32_probe1
1590  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1591  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1592  */
1593 static int __devinit
1594 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1595 {
1596         struct pcnet32_private *lp;
1597         int i, media;
1598         int fdx, mii, fset, dxsuflo;
1599         int chip_version;
1600         char *chipname;
1601         struct net_device *dev;
1602         struct pcnet32_access *a = NULL;
1603         u8 promaddr[6];
1604         int ret = -ENODEV;
1605
1606         /* reset the chip */
1607         pcnet32_wio_reset(ioaddr);
1608
1609         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1610         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1611                 a = &pcnet32_wio;
1612         } else {
1613                 pcnet32_dwio_reset(ioaddr);
1614                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1615                     pcnet32_dwio_check(ioaddr)) {
1616                         a = &pcnet32_dwio;
1617                 } else {
1618                         if (pcnet32_debug & NETIF_MSG_PROBE)
1619                                 printk(KERN_ERR PFX "No access methods\n");
1620                         goto err_release_region;
1621                 }
1622         }
1623
1624         chip_version =
1625             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1626         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1627                 printk(KERN_INFO "  PCnet chip version is %#x.\n",
1628                        chip_version);
1629         if ((chip_version & 0xfff) != 0x003) {
1630                 if (pcnet32_debug & NETIF_MSG_PROBE)
1631                         printk(KERN_INFO PFX "Unsupported chip version.\n");
1632                 goto err_release_region;
1633         }
1634
1635         /* initialize variables */
1636         fdx = mii = fset = dxsuflo = 0;
1637         chip_version = (chip_version >> 12) & 0xffff;
1638
1639         switch (chip_version) {
1640         case 0x2420:
1641                 chipname = "PCnet/PCI 79C970";  /* PCI */
1642                 break;
1643         case 0x2430:
1644                 if (shared)
1645                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1646                 else
1647                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1648                 break;
1649         case 0x2621:
1650                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1651                 fdx = 1;
1652                 break;
1653         case 0x2623:
1654                 chipname = "PCnet/FAST 79C971"; /* PCI */
1655                 fdx = 1;
1656                 mii = 1;
1657                 fset = 1;
1658                 break;
1659         case 0x2624:
1660                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1661                 fdx = 1;
1662                 mii = 1;
1663                 fset = 1;
1664                 break;
1665         case 0x2625:
1666                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1667                 fdx = 1;
1668                 mii = 1;
1669                 break;
1670         case 0x2626:
1671                 chipname = "PCnet/Home 79C978"; /* PCI */
1672                 fdx = 1;
1673                 /*
1674                  * This is based on specs published at www.amd.com.  This section
1675                  * assumes that a card with a 79C978 wants to go into standard
1676                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1677                  * and the module option homepna=1 can select this instead.
1678                  */
1679                 media = a->read_bcr(ioaddr, 49);
1680                 media &= ~3;    /* default to 10Mb ethernet */
1681                 if (cards_found < MAX_UNITS && homepna[cards_found])
1682                         media |= 1;     /* switch to home wiring mode */
1683                 if (pcnet32_debug & NETIF_MSG_PROBE)
1684                         printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1685                                (media & 1) ? "1" : "10");
1686                 a->write_bcr(ioaddr, 49, media);
1687                 break;
1688         case 0x2627:
1689                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1690                 fdx = 1;
1691                 mii = 1;
1692                 break;
1693         case 0x2628:
1694                 chipname = "PCnet/PRO 79C976";
1695                 fdx = 1;
1696                 mii = 1;
1697                 break;
1698         default:
1699                 if (pcnet32_debug & NETIF_MSG_PROBE)
1700                         printk(KERN_INFO PFX
1701                                "PCnet version %#x, no PCnet32 chip.\n",
1702                                chip_version);
1703                 goto err_release_region;
1704         }
1705
1706         /*
1707          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1708          *  starting until the packet is loaded. Strike one for reliability, lose
1709          *  one for latency - although on PCI this isnt a big loss. Older chips
1710          *  have FIFO's smaller than a packet, so you can't do this.
1711          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1712          */
1713
1714         if (fset) {
1715                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1716                 a->write_csr(ioaddr, 80,
1717                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1718                 dxsuflo = 1;
1719         }
1720
1721         dev = alloc_etherdev(sizeof(*lp));
1722         if (!dev) {
1723                 if (pcnet32_debug & NETIF_MSG_PROBE)
1724                         printk(KERN_ERR PFX "Memory allocation failed.\n");
1725                 ret = -ENOMEM;
1726                 goto err_release_region;
1727         }
1728
1729         if (pdev)
1730                 SET_NETDEV_DEV(dev, &pdev->dev);
1731
1732         if (pcnet32_debug & NETIF_MSG_PROBE)
1733                 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1734
1735         /* In most chips, after a chip reset, the ethernet address is read from the
1736          * station address PROM at the base address and programmed into the
1737          * "Physical Address Registers" CSR12-14.
1738          * As a precautionary measure, we read the PROM values and complain if
1739          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1740          * is valid, then the PROM addr is used.
1741          */
1742         for (i = 0; i < 3; i++) {
1743                 unsigned int val;
1744                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1745                 /* There may be endianness issues here. */
1746                 dev->dev_addr[2 * i] = val & 0x0ff;
1747                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1748         }
1749
1750         /* read PROM address and compare with CSR address */
1751         for (i = 0; i < 6; i++)
1752                 promaddr[i] = inb(ioaddr + i);
1753
1754         if (memcmp(promaddr, dev->dev_addr, 6) ||
1755             !is_valid_ether_addr(dev->dev_addr)) {
1756                 if (is_valid_ether_addr(promaddr)) {
1757                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1758                                 printk(" warning: CSR address invalid,\n");
1759                                 printk(KERN_INFO
1760                                        "    using instead PROM address of");
1761                         }
1762                         memcpy(dev->dev_addr, promaddr, 6);
1763                 }
1764         }
1765         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1766
1767         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1768         if (!is_valid_ether_addr(dev->perm_addr))
1769                 memset(dev->dev_addr, 0, ETH_ALEN);
1770
1771         if (pcnet32_debug & NETIF_MSG_PROBE) {
1772                 printk(" %pM", dev->dev_addr);
1773
1774                 /* Version 0x2623 and 0x2624 */
1775                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1776                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1777                         printk(KERN_INFO "    tx_start_pt(0x%04x):", i);
1778                         switch (i >> 10) {
1779                         case 0:
1780                                 printk(KERN_CONT "  20 bytes,");
1781                                 break;
1782                         case 1:
1783                                 printk(KERN_CONT "  64 bytes,");
1784                                 break;
1785                         case 2:
1786                                 printk(KERN_CONT " 128 bytes,");
1787                                 break;
1788                         case 3:
1789                                 printk(KERN_CONT "~220 bytes,");
1790                                 break;
1791                         }
1792                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1793                         printk(KERN_CONT " BCR18(%x):", i & 0xffff);
1794                         if (i & (1 << 5))
1795                                 printk(KERN_CONT "BurstWrEn ");
1796                         if (i & (1 << 6))
1797                                 printk(KERN_CONT "BurstRdEn ");
1798                         if (i & (1 << 7))
1799                                 printk(KERN_CONT "DWordIO ");
1800                         if (i & (1 << 11))
1801                                 printk(KERN_CONT "NoUFlow ");
1802                         i = a->read_bcr(ioaddr, 25);
1803                         printk(KERN_INFO "    SRAMSIZE=0x%04x,", i << 8);
1804                         i = a->read_bcr(ioaddr, 26);
1805                         printk(KERN_CONT " SRAM_BND=0x%04x,", i << 8);
1806                         i = a->read_bcr(ioaddr, 27);
1807                         if (i & (1 << 14))
1808                                 printk(KERN_CONT "LowLatRx");
1809                 }
1810         }
1811
1812         dev->base_addr = ioaddr;
1813         lp = netdev_priv(dev);
1814         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1815         if ((lp->init_block =
1816              pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1817                 if (pcnet32_debug & NETIF_MSG_PROBE)
1818                         printk(KERN_ERR PFX
1819                                "Consistent memory allocation failed.\n");
1820                 ret = -ENOMEM;
1821                 goto err_free_netdev;
1822         }
1823         lp->pci_dev = pdev;
1824
1825         lp->dev = dev;
1826
1827         spin_lock_init(&lp->lock);
1828
1829         lp->name = chipname;
1830         lp->shared_irq = shared;
1831         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1832         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1833         lp->tx_mod_mask = lp->tx_ring_size - 1;
1834         lp->rx_mod_mask = lp->rx_ring_size - 1;
1835         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1836         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1837         lp->mii_if.full_duplex = fdx;
1838         lp->mii_if.phy_id_mask = 0x1f;
1839         lp->mii_if.reg_num_mask = 0x1f;
1840         lp->dxsuflo = dxsuflo;
1841         lp->mii = mii;
1842         lp->chip_version = chip_version;
1843         lp->msg_enable = pcnet32_debug;
1844         if ((cards_found >= MAX_UNITS) ||
1845             (options[cards_found] >= sizeof(options_mapping)))
1846                 lp->options = PCNET32_PORT_ASEL;
1847         else
1848                 lp->options = options_mapping[options[cards_found]];
1849         lp->mii_if.dev = dev;
1850         lp->mii_if.mdio_read = mdio_read;
1851         lp->mii_if.mdio_write = mdio_write;
1852
1853         /* napi.weight is used in both the napi and non-napi cases */
1854         lp->napi.weight = lp->rx_ring_size / 2;
1855
1856         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1857
1858         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1859             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1860                 lp->options |= PCNET32_PORT_FD;
1861
1862         lp->a = *a;
1863
1864         /* prior to register_netdev, dev->name is not yet correct */
1865         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1866                 ret = -ENOMEM;
1867                 goto err_free_ring;
1868         }
1869         /* detect special T1/E1 WAN card by checking for MAC address */
1870         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1871             dev->dev_addr[2] == 0x75)
1872                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1873
1874         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1875         lp->init_block->tlen_rlen =
1876             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1877         for (i = 0; i < 6; i++)
1878                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1879         lp->init_block->filter[0] = 0x00000000;
1880         lp->init_block->filter[1] = 0x00000000;
1881         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1882         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1883
1884         /* switch pcnet32 to 32bit mode */
1885         a->write_bcr(ioaddr, 20, 2);
1886
1887         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1888         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1889
1890         if (pdev) {             /* use the IRQ provided by PCI */
1891                 dev->irq = pdev->irq;
1892                 if (pcnet32_debug & NETIF_MSG_PROBE)
1893                         printk(" assigned IRQ %d.\n", dev->irq);
1894         } else {
1895                 unsigned long irq_mask = probe_irq_on();
1896
1897                 /*
1898                  * To auto-IRQ we enable the initialization-done and DMA error
1899                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1900                  * boards will work.
1901                  */
1902                 /* Trigger an initialization just for the interrupt. */
1903                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1904                 mdelay(1);
1905
1906                 dev->irq = probe_irq_off(irq_mask);
1907                 if (!dev->irq) {
1908                         if (pcnet32_debug & NETIF_MSG_PROBE)
1909                                 printk(", failed to detect IRQ line.\n");
1910                         ret = -ENODEV;
1911                         goto err_free_ring;
1912                 }
1913                 if (pcnet32_debug & NETIF_MSG_PROBE)
1914                         printk(", probed IRQ %d.\n", dev->irq);
1915         }
1916
1917         /* Set the mii phy_id so that we can query the link state */
1918         if (lp->mii) {
1919                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1920
1921                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1922                 /* scan for PHYs */
1923                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1924                         unsigned short id1, id2;
1925
1926                         id1 = mdio_read(dev, i, MII_PHYSID1);
1927                         if (id1 == 0xffff)
1928                                 continue;
1929                         id2 = mdio_read(dev, i, MII_PHYSID2);
1930                         if (id2 == 0xffff)
1931                                 continue;
1932                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1933                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1934                         lp->phycount++;
1935                         lp->phymask |= (1 << i);
1936                         lp->mii_if.phy_id = i;
1937                         if (pcnet32_debug & NETIF_MSG_PROBE)
1938                                 printk(KERN_INFO PFX
1939                                        "Found PHY %04x:%04x at address %d.\n",
1940                                        id1, id2, i);
1941                 }
1942                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1943                 if (lp->phycount > 1) {
1944                         lp->options |= PCNET32_PORT_MII;
1945                 }
1946         }
1947
1948         init_timer(&lp->watchdog_timer);
1949         lp->watchdog_timer.data = (unsigned long)dev;
1950         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1951
1952         /* The PCNET32-specific entries in the device structure. */
1953         dev->netdev_ops = &pcnet32_netdev_ops;
1954         dev->ethtool_ops = &pcnet32_ethtool_ops;
1955         dev->watchdog_timeo = (5 * HZ);
1956
1957         /* Fill in the generic fields of the device structure. */
1958         if (register_netdev(dev))
1959                 goto err_free_ring;
1960
1961         if (pdev) {
1962                 pci_set_drvdata(pdev, dev);
1963         } else {
1964                 lp->next = pcnet32_dev;
1965                 pcnet32_dev = dev;
1966         }
1967
1968         if (pcnet32_debug & NETIF_MSG_PROBE)
1969                 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1970         cards_found++;
1971
1972         /* enable LED writes */
1973         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1974
1975         return 0;
1976
1977 err_free_ring:
1978         pcnet32_free_ring(dev);
1979         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1980                             lp->init_block, lp->init_dma_addr);
1981 err_free_netdev:
1982         free_netdev(dev);
1983 err_release_region:
1984         release_region(ioaddr, PCNET32_TOTAL_SIZE);
1985         return ret;
1986 }
1987
1988 /* if any allocation fails, caller must also call pcnet32_free_ring */
1989 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1990 {
1991         struct pcnet32_private *lp = netdev_priv(dev);
1992
1993         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1994                                            sizeof(struct pcnet32_tx_head) *
1995                                            lp->tx_ring_size,
1996                                            &lp->tx_ring_dma_addr);
1997         if (lp->tx_ring == NULL) {
1998                 if (netif_msg_drv(lp))
1999                         printk(KERN_ERR PFX
2000                                "%s: Consistent memory allocation failed.\n",
2001                                name);
2002                 return -ENOMEM;
2003         }
2004
2005         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2006                                            sizeof(struct pcnet32_rx_head) *
2007                                            lp->rx_ring_size,
2008                                            &lp->rx_ring_dma_addr);
2009         if (lp->rx_ring == NULL) {
2010                 if (netif_msg_drv(lp))
2011                         printk(KERN_ERR PFX
2012                                "%s: Consistent memory allocation failed.\n",
2013                                name);
2014                 return -ENOMEM;
2015         }
2016
2017         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2018                                   GFP_ATOMIC);
2019         if (!lp->tx_dma_addr) {
2020                 if (netif_msg_drv(lp))
2021                         printk(KERN_ERR PFX
2022                                "%s: Memory allocation failed.\n", name);
2023                 return -ENOMEM;
2024         }
2025
2026         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2027                                   GFP_ATOMIC);
2028         if (!lp->rx_dma_addr) {
2029                 if (netif_msg_drv(lp))
2030                         printk(KERN_ERR PFX
2031                                "%s: Memory allocation failed.\n", name);
2032                 return -ENOMEM;
2033         }
2034
2035         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2036                                 GFP_ATOMIC);
2037         if (!lp->tx_skbuff) {
2038                 if (netif_msg_drv(lp))
2039                         printk(KERN_ERR PFX
2040                                "%s: Memory allocation failed.\n", name);
2041                 return -ENOMEM;
2042         }
2043
2044         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2045                                 GFP_ATOMIC);
2046         if (!lp->rx_skbuff) {
2047                 if (netif_msg_drv(lp))
2048                         printk(KERN_ERR PFX
2049                                "%s: Memory allocation failed.\n", name);
2050                 return -ENOMEM;
2051         }
2052
2053         return 0;
2054 }
2055
2056 static void pcnet32_free_ring(struct net_device *dev)
2057 {
2058         struct pcnet32_private *lp = netdev_priv(dev);
2059
2060         kfree(lp->tx_skbuff);
2061         lp->tx_skbuff = NULL;
2062
2063         kfree(lp->rx_skbuff);
2064         lp->rx_skbuff = NULL;
2065
2066         kfree(lp->tx_dma_addr);
2067         lp->tx_dma_addr = NULL;
2068
2069         kfree(lp->rx_dma_addr);
2070         lp->rx_dma_addr = NULL;
2071
2072         if (lp->tx_ring) {
2073                 pci_free_consistent(lp->pci_dev,
2074                                     sizeof(struct pcnet32_tx_head) *
2075                                     lp->tx_ring_size, lp->tx_ring,
2076                                     lp->tx_ring_dma_addr);
2077                 lp->tx_ring = NULL;
2078         }
2079
2080         if (lp->rx_ring) {
2081                 pci_free_consistent(lp->pci_dev,
2082                                     sizeof(struct pcnet32_rx_head) *
2083                                     lp->rx_ring_size, lp->rx_ring,
2084                                     lp->rx_ring_dma_addr);
2085                 lp->rx_ring = NULL;
2086         }
2087 }
2088
2089 static int pcnet32_open(struct net_device *dev)
2090 {
2091         struct pcnet32_private *lp = netdev_priv(dev);
2092         struct pci_dev *pdev = lp->pci_dev;
2093         unsigned long ioaddr = dev->base_addr;
2094         u16 val;
2095         int i;
2096         int rc;
2097         unsigned long flags;
2098
2099         if (request_irq(dev->irq, pcnet32_interrupt,
2100                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2101                         (void *)dev)) {
2102                 return -EAGAIN;
2103         }
2104
2105         spin_lock_irqsave(&lp->lock, flags);
2106         /* Check for a valid station address */
2107         if (!is_valid_ether_addr(dev->dev_addr)) {
2108                 rc = -EINVAL;
2109                 goto err_free_irq;
2110         }
2111
2112         /* Reset the PCNET32 */
2113         lp->a.reset(ioaddr);
2114
2115         /* switch pcnet32 to 32bit mode */
2116         lp->a.write_bcr(ioaddr, 20, 2);
2117
2118         if (netif_msg_ifup(lp))
2119                 printk(KERN_DEBUG
2120                        "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2121                        dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2122                        (u32) (lp->rx_ring_dma_addr),
2123                        (u32) (lp->init_dma_addr));
2124
2125         /* set/reset autoselect bit */
2126         val = lp->a.read_bcr(ioaddr, 2) & ~2;
2127         if (lp->options & PCNET32_PORT_ASEL)
2128                 val |= 2;
2129         lp->a.write_bcr(ioaddr, 2, val);
2130
2131         /* handle full duplex setting */
2132         if (lp->mii_if.full_duplex) {
2133                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2134                 if (lp->options & PCNET32_PORT_FD) {
2135                         val |= 1;
2136                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2137                                 val |= 2;
2138                 } else if (lp->options & PCNET32_PORT_ASEL) {
2139                         /* workaround of xSeries250, turn on for 79C975 only */
2140                         if (lp->chip_version == 0x2627)
2141                                 val |= 3;
2142                 }
2143                 lp->a.write_bcr(ioaddr, 9, val);
2144         }
2145
2146         /* set/reset GPSI bit in test register */
2147         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2148         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2149                 val |= 0x10;
2150         lp->a.write_csr(ioaddr, 124, val);
2151
2152         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2153         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2154             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2155              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2156                 if (lp->options & PCNET32_PORT_ASEL) {
2157                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2158                         if (netif_msg_link(lp))
2159                                 printk(KERN_DEBUG
2160                                        "%s: Setting 100Mb-Full Duplex.\n",
2161                                        dev->name);
2162                 }
2163         }
2164         if (lp->phycount < 2) {
2165                 /*
2166                  * 24 Jun 2004 according AMD, in order to change the PHY,
2167                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2168                  * duplex, and/or enable auto negotiation, and clear DANAS
2169                  */
2170                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2171                         lp->a.write_bcr(ioaddr, 32,
2172                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
2173                         /* disable Auto Negotiation, set 10Mpbs, HD */
2174                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2175                         if (lp->options & PCNET32_PORT_FD)
2176                                 val |= 0x10;
2177                         if (lp->options & PCNET32_PORT_100)
2178                                 val |= 0x08;
2179                         lp->a.write_bcr(ioaddr, 32, val);
2180                 } else {
2181                         if (lp->options & PCNET32_PORT_ASEL) {
2182                                 lp->a.write_bcr(ioaddr, 32,
2183                                                 lp->a.read_bcr(ioaddr,
2184                                                                32) | 0x0080);
2185                                 /* enable auto negotiate, setup, disable fd */
2186                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2187                                 val |= 0x20;
2188                                 lp->a.write_bcr(ioaddr, 32, val);
2189                         }
2190                 }
2191         } else {
2192                 int first_phy = -1;
2193                 u16 bmcr;
2194                 u32 bcr9;
2195                 struct ethtool_cmd ecmd;
2196
2197                 /*
2198                  * There is really no good other way to handle multiple PHYs
2199                  * other than turning off all automatics
2200                  */
2201                 val = lp->a.read_bcr(ioaddr, 2);
2202                 lp->a.write_bcr(ioaddr, 2, val & ~2);
2203                 val = lp->a.read_bcr(ioaddr, 32);
2204                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
2205
2206                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2207                         /* setup ecmd */
2208                         ecmd.port = PORT_MII;
2209                         ecmd.transceiver = XCVR_INTERNAL;
2210                         ecmd.autoneg = AUTONEG_DISABLE;
2211                         ecmd.speed =
2212                             lp->
2213                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2214                         bcr9 = lp->a.read_bcr(ioaddr, 9);
2215
2216                         if (lp->options & PCNET32_PORT_FD) {
2217                                 ecmd.duplex = DUPLEX_FULL;
2218                                 bcr9 |= (1 << 0);
2219                         } else {
2220                                 ecmd.duplex = DUPLEX_HALF;
2221                                 bcr9 |= ~(1 << 0);
2222                         }
2223                         lp->a.write_bcr(ioaddr, 9, bcr9);
2224                 }
2225
2226                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2227                         if (lp->phymask & (1 << i)) {
2228                                 /* isolate all but the first PHY */
2229                                 bmcr = mdio_read(dev, i, MII_BMCR);
2230                                 if (first_phy == -1) {
2231                                         first_phy = i;
2232                                         mdio_write(dev, i, MII_BMCR,
2233                                                    bmcr & ~BMCR_ISOLATE);
2234                                 } else {
2235                                         mdio_write(dev, i, MII_BMCR,
2236                                                    bmcr | BMCR_ISOLATE);
2237                                 }
2238                                 /* use mii_ethtool_sset to setup PHY */
2239                                 lp->mii_if.phy_id = i;
2240                                 ecmd.phy_address = i;
2241                                 if (lp->options & PCNET32_PORT_ASEL) {
2242                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2243                                         ecmd.autoneg = AUTONEG_ENABLE;
2244                                 }
2245                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2246                         }
2247                 }
2248                 lp->mii_if.phy_id = first_phy;
2249                 if (netif_msg_link(lp))
2250                         printk(KERN_INFO "%s: Using PHY number %d.\n",
2251                                dev->name, first_phy);
2252         }
2253
2254 #ifdef DO_DXSUFLO
2255         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2256                 val = lp->a.read_csr(ioaddr, CSR3);
2257                 val |= 0x40;
2258                 lp->a.write_csr(ioaddr, CSR3, val);
2259         }
2260 #endif
2261
2262         lp->init_block->mode =
2263             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2264         pcnet32_load_multicast(dev);
2265
2266         if (pcnet32_init_ring(dev)) {
2267                 rc = -ENOMEM;
2268                 goto err_free_ring;
2269         }
2270
2271         napi_enable(&lp->napi);
2272
2273         /* Re-initialize the PCNET32, and start it when done. */
2274         lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2275         lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2276
2277         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
2278         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2279
2280         netif_start_queue(dev);
2281
2282         if (lp->chip_version >= PCNET32_79C970A) {
2283                 /* Print the link status and start the watchdog */
2284                 pcnet32_check_media(dev, 1);
2285                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2286         }
2287
2288         i = 0;
2289         while (i++ < 100)
2290                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2291                         break;
2292         /*
2293          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2294          * reports that doing so triggers a bug in the '974.
2295          */
2296         lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2297
2298         if (netif_msg_ifup(lp))
2299                 printk(KERN_DEBUG
2300                        "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2301                        dev->name, i,
2302                        (u32) (lp->init_dma_addr),
2303                        lp->a.read_csr(ioaddr, CSR0));
2304
2305         spin_unlock_irqrestore(&lp->lock, flags);
2306
2307         return 0;               /* Always succeed */
2308
2309       err_free_ring:
2310         /* free any allocated skbuffs */
2311         pcnet32_purge_rx_ring(dev);
2312
2313         /*
2314          * Switch back to 16bit mode to avoid problems with dumb
2315          * DOS packet driver after a warm reboot
2316          */
2317         lp->a.write_bcr(ioaddr, 20, 4);
2318
2319       err_free_irq:
2320         spin_unlock_irqrestore(&lp->lock, flags);
2321         free_irq(dev->irq, dev);
2322         return rc;
2323 }
2324
2325 /*
2326  * The LANCE has been halted for one reason or another (busmaster memory
2327  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2328  * etc.).  Modern LANCE variants always reload their ring-buffer
2329  * configuration when restarted, so we must reinitialize our ring
2330  * context before restarting.  As part of this reinitialization,
2331  * find all packets still on the Tx ring and pretend that they had been
2332  * sent (in effect, drop the packets on the floor) - the higher-level
2333  * protocols will time out and retransmit.  It'd be better to shuffle
2334  * these skbs to a temp list and then actually re-Tx them after
2335  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2336  */
2337
2338 static void pcnet32_purge_tx_ring(struct net_device *dev)
2339 {
2340         struct pcnet32_private *lp = netdev_priv(dev);
2341         int i;
2342
2343         for (i = 0; i < lp->tx_ring_size; i++) {
2344                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2345                 wmb();          /* Make sure adapter sees owner change */
2346                 if (lp->tx_skbuff[i]) {
2347                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2348                                          lp->tx_skbuff[i]->len,
2349                                          PCI_DMA_TODEVICE);
2350                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2351                 }
2352                 lp->tx_skbuff[i] = NULL;
2353                 lp->tx_dma_addr[i] = 0;
2354         }
2355 }
2356
2357 /* Initialize the PCNET32 Rx and Tx rings. */
2358 static int pcnet32_init_ring(struct net_device *dev)
2359 {
2360         struct pcnet32_private *lp = netdev_priv(dev);
2361         int i;
2362
2363         lp->tx_full = 0;
2364         lp->cur_rx = lp->cur_tx = 0;
2365         lp->dirty_rx = lp->dirty_tx = 0;
2366
2367         for (i = 0; i < lp->rx_ring_size; i++) {
2368                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2369                 if (rx_skbuff == NULL) {
2370                         if (!
2371                             (rx_skbuff = lp->rx_skbuff[i] =
2372                              dev_alloc_skb(PKT_BUF_SKB))) {
2373                                 /* there is not much, we can do at this point */
2374                                 if (netif_msg_drv(lp))
2375                                         printk(KERN_ERR
2376                                                "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2377                                                dev->name);
2378                                 return -1;
2379                         }
2380                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2381                 }
2382
2383                 rmb();
2384                 if (lp->rx_dma_addr[i] == 0)
2385                         lp->rx_dma_addr[i] =
2386                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2387                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2388                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2389                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2390                 wmb();          /* Make sure owner changes after all others are visible */
2391                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2392         }
2393         /* The Tx buffer address is filled in as needed, but we do need to clear
2394          * the upper ownership bit. */
2395         for (i = 0; i < lp->tx_ring_size; i++) {
2396                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2397                 wmb();          /* Make sure adapter sees owner change */
2398                 lp->tx_ring[i].base = 0;
2399                 lp->tx_dma_addr[i] = 0;
2400         }
2401
2402         lp->init_block->tlen_rlen =
2403             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2404         for (i = 0; i < 6; i++)
2405                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2406         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2407         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2408         wmb();                  /* Make sure all changes are visible */
2409         return 0;
2410 }
2411
2412 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2413  * then flush the pending transmit operations, re-initialize the ring,
2414  * and tell the chip to initialize.
2415  */
2416 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2417 {
2418         struct pcnet32_private *lp = netdev_priv(dev);
2419         unsigned long ioaddr = dev->base_addr;
2420         int i;
2421
2422         /* wait for stop */
2423         for (i = 0; i < 100; i++)
2424                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2425                         break;
2426
2427         if (i >= 100 && netif_msg_drv(lp))
2428                 printk(KERN_ERR
2429                        "%s: pcnet32_restart timed out waiting for stop.\n",
2430                        dev->name);
2431
2432         pcnet32_purge_tx_ring(dev);
2433         if (pcnet32_init_ring(dev))
2434                 return;
2435
2436         /* ReInit Ring */
2437         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2438         i = 0;
2439         while (i++ < 1000)
2440                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2441                         break;
2442
2443         lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2444 }
2445
2446 static void pcnet32_tx_timeout(struct net_device *dev)
2447 {
2448         struct pcnet32_private *lp = netdev_priv(dev);
2449         unsigned long ioaddr = dev->base_addr, flags;
2450
2451         spin_lock_irqsave(&lp->lock, flags);
2452         /* Transmitter timeout, serious problems. */
2453         if (pcnet32_debug & NETIF_MSG_DRV)
2454                 printk(KERN_ERR
2455                        "%s: transmit timed out, status %4.4x, resetting.\n",
2456                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2457         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2458         dev->stats.tx_errors++;
2459         if (netif_msg_tx_err(lp)) {
2460                 int i;
2461                 printk(KERN_DEBUG
2462                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2463                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2464                        lp->cur_rx);
2465                 for (i = 0; i < lp->rx_ring_size; i++)
2466                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2467                                le32_to_cpu(lp->rx_ring[i].base),
2468                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2469                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2470                                le16_to_cpu(lp->rx_ring[i].status));
2471                 for (i = 0; i < lp->tx_ring_size; i++)
2472                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2473                                le32_to_cpu(lp->tx_ring[i].base),
2474                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2475                                le32_to_cpu(lp->tx_ring[i].misc),
2476                                le16_to_cpu(lp->tx_ring[i].status));
2477                 printk("\n");
2478         }
2479         pcnet32_restart(dev, CSR0_NORMAL);
2480
2481         dev->trans_start = jiffies;
2482         netif_wake_queue(dev);
2483
2484         spin_unlock_irqrestore(&lp->lock, flags);
2485 }
2486
2487 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2488                                       struct net_device *dev)
2489 {
2490         struct pcnet32_private *lp = netdev_priv(dev);
2491         unsigned long ioaddr = dev->base_addr;
2492         u16 status;
2493         int entry;
2494         unsigned long flags;
2495
2496         spin_lock_irqsave(&lp->lock, flags);
2497
2498         if (netif_msg_tx_queued(lp)) {
2499                 printk(KERN_DEBUG
2500                        "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2501                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2502         }
2503
2504         /* Default status -- will not enable Successful-TxDone
2505          * interrupt when that option is available to us.
2506          */
2507         status = 0x8300;
2508
2509         /* Fill in a Tx ring entry */
2510
2511         /* Mask to ring buffer boundary. */
2512         entry = lp->cur_tx & lp->tx_mod_mask;
2513
2514         /* Caution: the write order is important here, set the status
2515          * with the "ownership" bits last. */
2516
2517         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2518
2519         lp->tx_ring[entry].misc = 0x00000000;
2520
2521         lp->tx_skbuff[entry] = skb;
2522         lp->tx_dma_addr[entry] =
2523             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2524         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2525         wmb();                  /* Make sure owner changes after all others are visible */
2526         lp->tx_ring[entry].status = cpu_to_le16(status);
2527
2528         lp->cur_tx++;
2529         dev->stats.tx_bytes += skb->len;
2530
2531         /* Trigger an immediate send poll. */
2532         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2533
2534         dev->trans_start = jiffies;
2535
2536         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2537                 lp->tx_full = 1;
2538                 netif_stop_queue(dev);
2539         }
2540         spin_unlock_irqrestore(&lp->lock, flags);
2541         return NETDEV_TX_OK;
2542 }
2543
2544 /* The PCNET32 interrupt handler. */
2545 static irqreturn_t
2546 pcnet32_interrupt(int irq, void *dev_id)
2547 {
2548         struct net_device *dev = dev_id;
2549         struct pcnet32_private *lp;
2550         unsigned long ioaddr;
2551         u16 csr0;
2552         int boguscnt = max_interrupt_work;
2553
2554         ioaddr = dev->base_addr;
2555         lp = netdev_priv(dev);
2556
2557         spin_lock(&lp->lock);
2558
2559         csr0 = lp->a.read_csr(ioaddr, CSR0);
2560         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2561                 if (csr0 == 0xffff) {
2562                         break;  /* PCMCIA remove happened */
2563                 }
2564                 /* Acknowledge all of the current interrupt sources ASAP. */
2565                 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2566
2567                 if (netif_msg_intr(lp))
2568                         printk(KERN_DEBUG
2569                                "%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
2570                                dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2571
2572                 /* Log misc errors. */
2573                 if (csr0 & 0x4000)
2574                         dev->stats.tx_errors++; /* Tx babble. */
2575                 if (csr0 & 0x1000) {
2576                         /*
2577                          * This happens when our receive ring is full. This
2578                          * shouldn't be a problem as we will see normal rx
2579                          * interrupts for the frames in the receive ring.  But
2580                          * there are some PCI chipsets (I can reproduce this
2581                          * on SP3G with Intel saturn chipset) which have
2582                          * sometimes problems and will fill up the receive
2583                          * ring with error descriptors.  In this situation we
2584                          * don't get a rx interrupt, but a missed frame
2585                          * interrupt sooner or later.
2586                          */
2587                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2588                 }
2589                 if (csr0 & 0x0800) {
2590                         if (netif_msg_drv(lp))
2591                                 printk(KERN_ERR
2592                                        "%s: Bus master arbitration failure, status %4.4x.\n",
2593                                        dev->name, csr0);
2594                         /* unlike for the lance, there is no restart needed */
2595                 }
2596                 if (napi_schedule_prep(&lp->napi)) {
2597                         u16 val;
2598                         /* set interrupt masks */
2599                         val = lp->a.read_csr(ioaddr, CSR3);
2600                         val |= 0x5f00;
2601                         lp->a.write_csr(ioaddr, CSR3, val);
2602
2603                         __napi_schedule(&lp->napi);
2604                         break;
2605                 }
2606                 csr0 = lp->a.read_csr(ioaddr, CSR0);
2607         }
2608
2609         if (netif_msg_intr(lp))
2610                 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2611                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2612
2613         spin_unlock(&lp->lock);
2614
2615         return IRQ_HANDLED;
2616 }
2617
2618 static int pcnet32_close(struct net_device *dev)
2619 {
2620         unsigned long ioaddr = dev->base_addr;
2621         struct pcnet32_private *lp = netdev_priv(dev);
2622         unsigned long flags;
2623
2624         del_timer_sync(&lp->watchdog_timer);
2625
2626         netif_stop_queue(dev);
2627         napi_disable(&lp->napi);
2628
2629         spin_lock_irqsave(&lp->lock, flags);
2630
2631         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2632
2633         if (netif_msg_ifdown(lp))
2634                 printk(KERN_DEBUG
2635                        "%s: Shutting down ethercard, status was %2.2x.\n",
2636                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2637
2638         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2639         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2640
2641         /*
2642          * Switch back to 16bit mode to avoid problems with dumb
2643          * DOS packet driver after a warm reboot
2644          */
2645         lp->a.write_bcr(ioaddr, 20, 4);
2646
2647         spin_unlock_irqrestore(&lp->lock, flags);
2648
2649         free_irq(dev->irq, dev);
2650
2651         spin_lock_irqsave(&lp->lock, flags);
2652
2653         pcnet32_purge_rx_ring(dev);
2654         pcnet32_purge_tx_ring(dev);
2655
2656         spin_unlock_irqrestore(&lp->lock, flags);
2657
2658         return 0;
2659 }
2660
2661 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2662 {
2663         struct pcnet32_private *lp = netdev_priv(dev);
2664         unsigned long ioaddr = dev->base_addr;
2665         unsigned long flags;
2666
2667         spin_lock_irqsave(&lp->lock, flags);
2668         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2669         spin_unlock_irqrestore(&lp->lock, flags);
2670
2671         return &dev->stats;
2672 }
2673
2674 /* taken from the sunlance driver, which it took from the depca driver */
2675 static void pcnet32_load_multicast(struct net_device *dev)
2676 {
2677         struct pcnet32_private *lp = netdev_priv(dev);
2678         volatile struct pcnet32_init_block *ib = lp->init_block;
2679         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2680         struct dev_mc_list *dmi = dev->mc_list;
2681         unsigned long ioaddr = dev->base_addr;
2682         char *addrs;
2683         int i;
2684         u32 crc;
2685
2686         /* set all multicast bits */
2687         if (dev->flags & IFF_ALLMULTI) {
2688                 ib->filter[0] = cpu_to_le32(~0U);
2689                 ib->filter[1] = cpu_to_le32(~0U);
2690                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2691                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2692                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2693                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2694                 return;
2695         }
2696         /* clear the multicast filter */
2697         ib->filter[0] = 0;
2698         ib->filter[1] = 0;
2699
2700         /* Add addresses */
2701         for (i = 0; i < dev->mc_count; i++) {
2702                 addrs = dmi->dmi_addr;
2703                 dmi = dmi->next;
2704
2705                 /* multicast address? */
2706                 if (!(*addrs & 1))
2707                         continue;
2708
2709                 crc = ether_crc_le(6, addrs);
2710                 crc = crc >> 26;
2711                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2712         }
2713         for (i = 0; i < 4; i++)
2714                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2715                                 le16_to_cpu(mcast_table[i]));
2716         return;
2717 }
2718
2719 /*
2720  * Set or clear the multicast filter for this adaptor.
2721  */
2722 static void pcnet32_set_multicast_list(struct net_device *dev)
2723 {
2724         unsigned long ioaddr = dev->base_addr, flags;
2725         struct pcnet32_private *lp = netdev_priv(dev);
2726         int csr15, suspended;
2727
2728         spin_lock_irqsave(&lp->lock, flags);
2729         suspended = pcnet32_suspend(dev, &flags, 0);
2730         csr15 = lp->a.read_csr(ioaddr, CSR15);
2731         if (dev->flags & IFF_PROMISC) {
2732                 /* Log any net taps. */
2733                 if (netif_msg_hw(lp))
2734                         printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2735                                dev->name);
2736                 lp->init_block->mode =
2737                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2738                                 7);
2739                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2740         } else {
2741                 lp->init_block->mode =
2742                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2743                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2744                 pcnet32_load_multicast(dev);
2745         }
2746
2747         if (suspended) {
2748                 int csr5;
2749                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2750                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2751                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2752         } else {
2753                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2754                 pcnet32_restart(dev, CSR0_NORMAL);
2755                 netif_wake_queue(dev);
2756         }
2757
2758         spin_unlock_irqrestore(&lp->lock, flags);
2759 }
2760
2761 /* This routine assumes that the lp->lock is held */
2762 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2763 {
2764         struct pcnet32_private *lp = netdev_priv(dev);
2765         unsigned long ioaddr = dev->base_addr;
2766         u16 val_out;
2767
2768         if (!lp->mii)
2769                 return 0;
2770
2771         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2772         val_out = lp->a.read_bcr(ioaddr, 34);
2773
2774         return val_out;
2775 }
2776
2777 /* This routine assumes that the lp->lock is held */
2778 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2779 {
2780         struct pcnet32_private *lp = netdev_priv(dev);
2781         unsigned long ioaddr = dev->base_addr;
2782
2783         if (!lp->mii)
2784                 return;
2785
2786         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2787         lp->a.write_bcr(ioaddr, 34, val);
2788 }
2789
2790 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2791 {
2792         struct pcnet32_private *lp = netdev_priv(dev);
2793         int rc;
2794         unsigned long flags;
2795
2796         /* SIOC[GS]MIIxxx ioctls */
2797         if (lp->mii) {
2798                 spin_lock_irqsave(&lp->lock, flags);
2799                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2800                 spin_unlock_irqrestore(&lp->lock, flags);
2801         } else {
2802                 rc = -EOPNOTSUPP;
2803         }
2804
2805         return rc;
2806 }
2807
2808 static int pcnet32_check_otherphy(struct net_device *dev)
2809 {
2810         struct pcnet32_private *lp = netdev_priv(dev);
2811         struct mii_if_info mii = lp->mii_if;
2812         u16 bmcr;
2813         int i;
2814
2815         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2816                 if (i == lp->mii_if.phy_id)
2817                         continue;       /* skip active phy */
2818                 if (lp->phymask & (1 << i)) {
2819                         mii.phy_id = i;
2820                         if (mii_link_ok(&mii)) {
2821                                 /* found PHY with active link */
2822                                 if (netif_msg_link(lp))
2823                                         printk(KERN_INFO
2824                                                "%s: Using PHY number %d.\n",
2825                                                dev->name, i);
2826
2827                                 /* isolate inactive phy */
2828                                 bmcr =
2829                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2830                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2831                                            bmcr | BMCR_ISOLATE);
2832
2833                                 /* de-isolate new phy */
2834                                 bmcr = mdio_read(dev, i, MII_BMCR);
2835                                 mdio_write(dev, i, MII_BMCR,
2836                                            bmcr & ~BMCR_ISOLATE);
2837
2838                                 /* set new phy address */
2839                                 lp->mii_if.phy_id = i;
2840                                 return 1;
2841                         }
2842                 }
2843         }
2844         return 0;
2845 }
2846
2847 /*
2848  * Show the status of the media.  Similar to mii_check_media however it
2849  * correctly shows the link speed for all (tested) pcnet32 variants.
2850  * Devices with no mii just report link state without speed.
2851  *
2852  * Caller is assumed to hold and release the lp->lock.
2853  */
2854
2855 static void pcnet32_check_media(struct net_device *dev, int verbose)
2856 {
2857         struct pcnet32_private *lp = netdev_priv(dev);
2858         int curr_link;
2859         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2860         u32 bcr9;
2861
2862         if (lp->mii) {
2863                 curr_link = mii_link_ok(&lp->mii_if);
2864         } else {
2865                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2866                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2867         }
2868         if (!curr_link) {
2869                 if (prev_link || verbose) {
2870                         netif_carrier_off(dev);
2871                         if (netif_msg_link(lp))
2872                                 printk(KERN_INFO "%s: link down\n", dev->name);
2873                 }
2874                 if (lp->phycount > 1) {
2875                         curr_link = pcnet32_check_otherphy(dev);
2876                         prev_link = 0;
2877                 }
2878         } else if (verbose || !prev_link) {
2879                 netif_carrier_on(dev);
2880                 if (lp->mii) {
2881                         if (netif_msg_link(lp)) {
2882                                 struct ethtool_cmd ecmd;
2883                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2884                                 printk(KERN_INFO
2885                                        "%s: link up, %sMbps, %s-duplex\n",
2886                                        dev->name,
2887                                        (ecmd.speed == SPEED_100) ? "100" : "10",
2888                                        (ecmd.duplex ==
2889                                         DUPLEX_FULL) ? "full" : "half");
2890                         }
2891                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2892                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2893                                 if (lp->mii_if.full_duplex)
2894                                         bcr9 |= (1 << 0);
2895                                 else
2896                                         bcr9 &= ~(1 << 0);
2897                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2898                         }
2899                 } else {
2900                         if (netif_msg_link(lp))
2901                                 printk(KERN_INFO "%s: link up\n", dev->name);
2902                 }
2903         }
2904 }
2905
2906 /*
2907  * Check for loss of link and link establishment.
2908  * Can not use mii_check_media because it does nothing if mode is forced.
2909  */
2910
2911 static void pcnet32_watchdog(struct net_device *dev)
2912 {
2913         struct pcnet32_private *lp = netdev_priv(dev);
2914         unsigned long flags;
2915
2916         /* Print the link status if it has changed */
2917         spin_lock_irqsave(&lp->lock, flags);
2918         pcnet32_check_media(dev, 0);
2919         spin_unlock_irqrestore(&lp->lock, flags);
2920
2921         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2922 }
2923
2924 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2925 {
2926         struct net_device *dev = pci_get_drvdata(pdev);
2927
2928         if (netif_running(dev)) {
2929                 netif_device_detach(dev);
2930                 pcnet32_close(dev);
2931         }
2932         pci_save_state(pdev);
2933         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2934         return 0;
2935 }
2936
2937 static int pcnet32_pm_resume(struct pci_dev *pdev)
2938 {
2939         struct net_device *dev = pci_get_drvdata(pdev);
2940
2941         pci_set_power_state(pdev, PCI_D0);
2942         pci_restore_state(pdev);
2943
2944         if (netif_running(dev)) {
2945                 pcnet32_open(dev);
2946                 netif_device_attach(dev);
2947         }
2948         return 0;
2949 }
2950
2951 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2952 {
2953         struct net_device *dev = pci_get_drvdata(pdev);
2954
2955         if (dev) {
2956                 struct pcnet32_private *lp = netdev_priv(dev);
2957
2958                 unregister_netdev(dev);
2959                 pcnet32_free_ring(dev);
2960                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2961                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2962                                     lp->init_block, lp->init_dma_addr);
2963                 free_netdev(dev);
2964                 pci_disable_device(pdev);
2965                 pci_set_drvdata(pdev, NULL);
2966         }
2967 }
2968
2969 static struct pci_driver pcnet32_driver = {
2970         .name = DRV_NAME,
2971         .probe = pcnet32_probe_pci,
2972         .remove = __devexit_p(pcnet32_remove_one),
2973         .id_table = pcnet32_pci_tbl,
2974         .suspend = pcnet32_pm_suspend,
2975         .resume = pcnet32_pm_resume,
2976 };
2977
2978 /* An additional parameter that may be passed in... */
2979 static int debug = -1;
2980 static int tx_start_pt = -1;
2981 static int pcnet32_have_pci;
2982
2983 module_param(debug, int, 0);
2984 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2985 module_param(max_interrupt_work, int, 0);
2986 MODULE_PARM_DESC(max_interrupt_work,
2987                  DRV_NAME " maximum events handled per interrupt");
2988 module_param(rx_copybreak, int, 0);
2989 MODULE_PARM_DESC(rx_copybreak,
2990                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2991 module_param(tx_start_pt, int, 0);
2992 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2993 module_param(pcnet32vlb, int, 0);
2994 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2995 module_param_array(options, int, NULL, 0);
2996 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2997 module_param_array(full_duplex, int, NULL, 0);
2998 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2999 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3000 module_param_array(homepna, int, NULL, 0);
3001 MODULE_PARM_DESC(homepna,
3002                  DRV_NAME
3003                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3004
3005 MODULE_AUTHOR("Thomas Bogendoerfer");
3006 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3007 MODULE_LICENSE("GPL");
3008
3009 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3010
3011 static int __init pcnet32_init_module(void)
3012 {
3013         printk(KERN_INFO "%s", version);
3014
3015         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3016
3017         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3018                 tx_start = tx_start_pt;
3019
3020         /* find the PCI devices */
3021         if (!pci_register_driver(&pcnet32_driver))
3022                 pcnet32_have_pci = 1;
3023
3024         /* should we find any remaining VLbus devices ? */
3025         if (pcnet32vlb)
3026                 pcnet32_probe_vlbus(pcnet32_portlist);
3027
3028         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3029                 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3030
3031         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3032 }
3033
3034 static void __exit pcnet32_cleanup_module(void)
3035 {
3036         struct net_device *next_dev;
3037
3038         while (pcnet32_dev) {
3039                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3040                 next_dev = lp->next;
3041                 unregister_netdev(pcnet32_dev);
3042                 pcnet32_free_ring(pcnet32_dev);
3043                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3044                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3045                                     lp->init_block, lp->init_dma_addr);
3046                 free_netdev(pcnet32_dev);
3047                 pcnet32_dev = next_dev;
3048         }
3049
3050         if (pcnet32_have_pci)
3051                 pci_unregister_driver(&pcnet32_driver);
3052 }
3053
3054 module_init(pcnet32_init_module);
3055 module_exit(pcnet32_cleanup_module);
3056
3057 /*
3058  * Local variables:
3059  *  c-indent-level: 4
3060  *  tab-width: 8
3061  * End:
3062  */