1 #ifndef __MV643XX_ETH_H__
2 #define __MV643XX_ETH_H__
4 #include <linux/module.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/workqueue.h>
10 #include <linux/mv643xx_eth.h>
12 #include <asm/dma-mapping.h>
14 /* Checksum offload for Tx works for most packets, but
15 * fails if previous packet sent did not use hw csum
17 #define MV643XX_CHECKSUM_OFFLOAD_TX
19 #define MV643XX_TX_FAST_REFILL
23 * Number of RX / TX descriptors on RX / TX rings.
24 * Note that allocating RX descriptors is done by allocating the RX
25 * ring AND a preallocated RX buffers (skb's) for each descriptor.
26 * The TX descriptors only allocates the TX descriptors ring,
27 * with no pre allocated TX buffers (skb's are allocated by higher layers.
30 /* Default TX ring size is 1000 descriptors */
31 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
33 /* Default RX ring size is 400 descriptors */
34 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
36 #define MV643XX_TX_COAL 100
38 #define MV643XX_RX_COAL 100
41 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
42 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
44 #define MAX_DESCS_PER_SKB 1
47 #define ETH_VLAN_HLEN 4
49 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
50 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
51 ETH_VLAN_HLEN + ETH_FCS_LEN)
52 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
53 dma_get_cache_alignment())
56 * Registers shared between all ports.
58 #define PHY_ADDR_REG 0x0000
59 #define SMI_REG 0x0004
60 #define UNIT_DEFAULT_ADDR_REG 0x0008
61 #define UNIT_DEFAULTID_REG 0x000c
62 #define UNIT_INTERRUPT_CAUSE_REG 0x0080
63 #define UNIT_INTERRUPT_MASK_REG 0x0084
64 #define UNIT_INTERNAL_USE_REG 0x04fc
65 #define UNIT_ERROR_ADDR_REG 0x0094
72 #define SIZE_REG_0 0x0204
73 #define SIZE_REG_1 0x020c
74 #define SIZE_REG_2 0x0214
75 #define SIZE_REG_3 0x021c
76 #define SIZE_REG_4 0x0224
77 #define SIZE_REG_5 0x022c
78 #define HEADERS_RETARGET_BASE_REG 0x0230
79 #define HEADERS_RETARGET_CONTROL_REG 0x0234
80 #define HIGH_ADDR_REMAP_REG_0 0x0280
81 #define HIGH_ADDR_REMAP_REG_1 0x0284
82 #define HIGH_ADDR_REMAP_REG_2 0x0288
83 #define HIGH_ADDR_REMAP_REG_3 0x028c
84 #define BASE_ADDR_ENABLE_REG 0x0290
90 #define ACCESS_PROTECTION_REG(p) (0x0294 + ((p) << 2))
91 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
92 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
93 #define MII_SERIAL_PARAMETRS_REG(p) (0x0408 + ((p) << 10))
94 #define GMII_SERIAL_PARAMETRS_REG(p) (0x040c + ((p) << 10))
95 #define VLAN_ETHERTYPE_REG(p) (0x0410 + ((p) << 10))
96 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
97 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
98 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
99 #define DSCP_0(p) (0x0420 + ((p) << 10))
100 #define DSCP_1(p) (0x0424 + ((p) << 10))
101 #define DSCP_2(p) (0x0428 + ((p) << 10))
102 #define DSCP_3(p) (0x042c + ((p) << 10))
103 #define DSCP_4(p) (0x0430 + ((p) << 10))
104 #define DSCP_5(p) (0x0434 + ((p) << 10))
105 #define DSCP_6(p) (0x0438 + ((p) << 10))
106 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
107 #define VLAN_PRIORITY_TAG_TO_PRIORITY(p) (0x0440 + ((p) << 10))
108 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
109 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
110 #define TX_QUEUE_FIXED_PRIORITY(p) (0x044c + ((p) << 10))
111 #define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(p) (0x0450 + ((p) << 10))
112 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
113 #define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(p) (0x045c + ((p) << 10))
114 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
115 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
116 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
117 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
118 #define RX_FIFO_URGENT_THRESHOLD_REG(p) (0x0470 + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
120 #define RX_MINIMAL_FRAME_SIZE_REG(p) (0x047c + ((p) << 10))
121 #define RX_DISCARDED_FRAMES_COUNTER(p) (0x0484 + ((p) << 10))
122 #define PORT_DEBUG_0_REG(p) (0x048c + ((p) << 10))
123 #define PORT_DEBUG_1_REG(p) (0x0490 + ((p) << 10))
124 #define PORT_INTERNAL_ADDR_ERROR_REG(p) (0x0494 + ((p) << 10))
125 #define INTERNAL_USE_REG(p) (0x04fc + ((p) << 10))
126 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
127 #define RX_CURRENT_QUEUE_DESC_PTR_1(p) (0x061c + ((p) << 10))
128 #define RX_CURRENT_QUEUE_DESC_PTR_2(p) (0x062c + ((p) << 10))
129 #define RX_CURRENT_QUEUE_DESC_PTR_3(p) (0x063c + ((p) << 10))
130 #define RX_CURRENT_QUEUE_DESC_PTR_4(p) (0x064c + ((p) << 10))
131 #define RX_CURRENT_QUEUE_DESC_PTR_5(p) (0x065c + ((p) << 10))
132 #define RX_CURRENT_QUEUE_DESC_PTR_6(p) (0x066c + ((p) << 10))
133 #define RX_CURRENT_QUEUE_DESC_PTR_7(p) (0x067c + ((p) << 10))
134 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
135 #define CURRENT_SERVED_TX_DESC_PTR(p) (0x0684 + ((p) << 10))
136 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
137 #define TX_CURRENT_QUEUE_DESC_PTR_1(p) (0x06c4 + ((p) << 10))
138 #define TX_CURRENT_QUEUE_DESC_PTR_2(p) (0x06c8 + ((p) << 10))
139 #define TX_CURRENT_QUEUE_DESC_PTR_3(p) (0x06cc + ((p) << 10))
140 #define TX_CURRENT_QUEUE_DESC_PTR_4(p) (0x06d0 + ((p) << 10))
141 #define TX_CURRENT_QUEUE_DESC_PTR_5(p) (0x06d4 + ((p) << 10))
142 #define TX_CURRENT_QUEUE_DESC_PTR_6(p) (0x06d8 + ((p) << 10))
143 #define TX_CURRENT_QUEUE_DESC_PTR_7(p) (0x06dc + ((p) << 10))
144 #define TX_QUEUE_0_TOKEN_BUCKET_COUNT(p) (0x0700 + ((p) << 10))
145 #define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(p) (0x0704 + ((p) << 10))
146 #define TX_QUEUE_0_ARBITER_CONFIG(p) (0x0708 + ((p) << 10))
147 #define TX_QUEUE_1_TOKEN_BUCKET_COUNT(p) (0x0710 + ((p) << 10))
148 #define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(p) (0x0714 + ((p) << 10))
149 #define TX_QUEUE_1_ARBITER_CONFIG(p) (0x0718 + ((p) << 10))
150 #define TX_QUEUE_2_TOKEN_BUCKET_COUNT(p) (0x0720 + ((p) << 10))
151 #define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(p) (0x0724 + ((p) << 10))
152 #define TX_QUEUE_2_ARBITER_CONFIG(p) (0x0728 + ((p) << 10))
153 #define TX_QUEUE_3_TOKEN_BUCKET_COUNT(p) (0x0730 + ((p) << 10))
154 #define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(p) (0x0734 + ((p) << 10))
155 #define TX_QUEUE_3_ARBITER_CONFIG(p) (0x0738 + ((p) << 10))
156 #define TX_QUEUE_4_TOKEN_BUCKET_COUNT(p) (0x0740 + ((p) << 10))
157 #define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(p) (0x0744 + ((p) << 10))
158 #define TX_QUEUE_4_ARBITER_CONFIG(p) (0x0748 + ((p) << 10))
159 #define TX_QUEUE_5_TOKEN_BUCKET_COUNT(p) (0x0750 + ((p) << 10))
160 #define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(p) (0x0754 + ((p) << 10))
161 #define TX_QUEUE_5_ARBITER_CONFIG(p) (0x0758 + ((p) << 10))
162 #define TX_QUEUE_6_TOKEN_BUCKET_COUNT(p) (0x0760 + ((p) << 10))
163 #define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(p) (0x0764 + ((p) << 10))
164 #define TX_QUEUE_6_ARBITER_CONFIG(p) (0x0768 + ((p) << 10))
165 #define TX_QUEUE_7_TOKEN_BUCKET_COUNT(p) (0x0770 + ((p) << 10))
166 #define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(p) (0x0774 + ((p) << 10))
167 #define TX_QUEUE_7_ARBITER_CONFIG(p) (0x0778 + ((p) << 10))
168 #define PORT_TX_TOKEN_BUCKET_COUNT(p) (0x0780 + ((p) << 10))
169 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
170 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
171 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
172 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
174 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
175 #define UNICAST_NORMAL_MODE (0 << 0)
176 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
177 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
178 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
179 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
180 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
181 #define RECEIVE_BC_IF_IP (0 << 8)
182 #define REJECT_BC_IF_IP (1 << 8)
183 #define RECEIVE_BC_IF_ARP (0 << 9)
184 #define REJECT_BC_IF_ARP (1 << 9)
185 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
186 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
187 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
188 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
189 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
190 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
191 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
192 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
194 #define PORT_CONFIG_DEFAULT_VALUE \
195 UNICAST_NORMAL_MODE | \
196 DEFAULT_RX_QUEUE(0) | \
197 DEFAULT_RX_ARP_QUEUE(0) | \
198 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
200 RECEIVE_BC_IF_ARP | \
201 CAPTURE_TCP_FRAMES_DIS | \
202 CAPTURE_UDP_FRAMES_DIS | \
203 DEFAULT_RX_TCP_QUEUE(0) | \
204 DEFAULT_RX_UDP_QUEUE(0) | \
205 DEFAULT_RX_BPDU_QUEUE(0)
207 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
208 #define CLASSIFY_EN (1 << 0)
209 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
210 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
211 #define PARTITION_DISABLE (0 << 2)
212 #define PARTITION_ENABLE (1 << 2)
214 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
215 SPAN_BPDU_PACKETS_AS_NORMAL | \
218 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
219 #define RIFB (1 << 0)
220 #define RX_BURST_SIZE_1_64BIT (0 << 1)
221 #define RX_BURST_SIZE_2_64BIT (1 << 1)
222 #define RX_BURST_SIZE_4_64BIT (2 << 1)
223 #define RX_BURST_SIZE_8_64BIT (3 << 1)
224 #define RX_BURST_SIZE_16_64BIT (4 << 1)
225 #define BLM_RX_NO_SWAP (1 << 4)
226 #define BLM_RX_BYTE_SWAP (0 << 4)
227 #define BLM_TX_NO_SWAP (1 << 5)
228 #define BLM_TX_BYTE_SWAP (0 << 5)
229 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
230 #define DESCRIPTORS_NO_SWAP (0 << 6)
231 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
232 #define TX_BURST_SIZE_1_64BIT (0 << 22)
233 #define TX_BURST_SIZE_2_64BIT (1 << 22)
234 #define TX_BURST_SIZE_4_64BIT (2 << 22)
235 #define TX_BURST_SIZE_8_64BIT (3 << 22)
236 #define TX_BURST_SIZE_16_64BIT (4 << 22)
238 #if defined(__BIG_ENDIAN)
239 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
240 RX_BURST_SIZE_4_64BIT | \
242 TX_BURST_SIZE_4_64BIT
243 #elif defined(__LITTLE_ENDIAN)
244 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
245 RX_BURST_SIZE_4_64BIT | \
249 TX_BURST_SIZE_4_64BIT
251 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
254 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
255 #define SERIAL_PORT_DISABLE (0 << 0)
256 #define SERIAL_PORT_ENABLE (1 << 0)
257 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
258 #define FORCE_LINK_PASS (1 << 1)
259 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
260 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
261 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
262 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
263 #define ADV_NO_FLOW_CTRL (0 << 4)
264 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
265 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
266 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
267 #define FORCE_BP_MODE_NO_JAM (0 << 7)
268 #define FORCE_BP_MODE_JAM_TX (1 << 7)
269 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
270 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
271 #define FORCE_LINK_FAIL (0 << 10)
272 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
273 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
274 #define RETRANSMIT_FOREVER (1 << 11)
275 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
276 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
277 #define DTE_ADV_0 (0 << 14)
278 #define DTE_ADV_1 (1 << 14)
279 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
280 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
281 #define AUTO_NEG_NO_CHANGE (0 << 16)
282 #define RESTART_AUTO_NEG (1 << 16)
283 #define MAX_RX_PACKET_1518BYTE (0 << 17)
284 #define MAX_RX_PACKET_1522BYTE (1 << 17)
285 #define MAX_RX_PACKET_1552BYTE (2 << 17)
286 #define MAX_RX_PACKET_9022BYTE (3 << 17)
287 #define MAX_RX_PACKET_9192BYTE (4 << 17)
288 #define MAX_RX_PACKET_9700BYTE (5 << 17)
289 #define MAX_RX_PACKET_MASK (7 << 17)
290 #define CLR_EXT_LOOPBACK (0 << 20)
291 #define SET_EXT_LOOPBACK (1 << 20)
292 #define SET_HALF_DUPLEX_MODE (0 << 21)
293 #define SET_FULL_DUPLEX_MODE (1 << 21)
294 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
295 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
296 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
297 #define SET_GMII_SPEED_TO_1000 (1 << 23)
298 #define SET_MII_SPEED_TO_10 (0 << 24)
299 #define SET_MII_SPEED_TO_100 (1 << 24)
301 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
302 DO_NOT_FORCE_LINK_PASS | \
303 ENABLE_AUTO_NEG_FOR_DUPLX | \
304 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
305 ADV_SYMMETRIC_FLOW_CTRL | \
306 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
307 FORCE_BP_MODE_NO_JAM | \
308 (1 << 9) /* reserved */ | \
309 DO_NOT_FORCE_LINK_FAIL | \
310 RETRANSMIT_16_ATTEMPTS | \
311 ENABLE_AUTO_NEG_SPEED_GMII | \
313 DISABLE_AUTO_NEG_BYPASS | \
314 AUTO_NEG_NO_CHANGE | \
315 MAX_RX_PACKET_9700BYTE | \
317 SET_FULL_DUPLEX_MODE | \
318 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
320 /* These macros describe Ethernet Serial Status reg (PSR) bits */
321 #define PORT_STATUS_MODE_10_BIT (1 << 0)
322 #define PORT_STATUS_LINK_UP (1 << 1)
323 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
324 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
325 #define PORT_STATUS_GMII_1000 (1 << 4)
326 #define PORT_STATUS_MII_100 (1 << 5)
327 /* PSR bit 6 is undocumented */
328 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
329 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
330 #define PORT_STATUS_PARTITION (1 << 9)
331 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
332 /* PSR bits 11-31 are reserved */
334 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
335 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
339 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
340 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
342 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
343 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
344 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
345 #define ETH_INT_CAUSE_EXT 0x00000002
346 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
348 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
349 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
350 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
351 #define ETH_INT_CAUSE_PHY 0x00010000
352 #define ETH_INT_CAUSE_STATE 0x00100000
353 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
356 #define ETH_INT_MASK_ALL 0x00000000
357 #define ETH_INT_MASK_ALL_EXT 0x00000000
359 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
360 #define PHY_WAIT_MICRO_SECONDS 10
362 /* Buffer offset from buffer pointer */
363 #define RX_BUF_OFFSET 0x2
365 /* Gigabit Ethernet Unit Global Registers */
367 /* MIB Counters register definitions */
368 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
369 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
370 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
371 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
372 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
373 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
374 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
375 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
376 #define ETH_MIB_FRAMES_64_OCTETS 0x20
377 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
378 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
379 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
380 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
381 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
382 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
383 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
384 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
385 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
386 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
387 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
388 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
389 #define ETH_MIB_FC_SENT 0x54
390 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
391 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
392 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
393 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
394 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
395 #define ETH_MIB_JABBER_RECEIVED 0x6c
396 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
397 #define ETH_MIB_BAD_CRC_EVENT 0x74
398 #define ETH_MIB_COLLISION 0x78
399 #define ETH_MIB_LATE_COLLISION 0x7c
401 /* Port serial status reg (PSR) */
402 #define ETH_INTERFACE_PCM 0x00000001
403 #define ETH_LINK_IS_UP 0x00000002
404 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
405 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
406 #define ETH_GMII_SPEED_1000 0x00000010
407 #define ETH_MII_SPEED_100 0x00000020
408 #define ETH_TX_IN_PROGRESS 0x00000080
409 #define ETH_BYPASS_ACTIVE 0x00000100
410 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
411 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
414 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
415 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
416 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
417 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
419 /* Interrupt Cause Register Bit Definitions */
421 /* SDMA command status fields macros */
423 /* Tx & Rx descriptors status */
424 #define ETH_ERROR_SUMMARY 0x00000001
426 /* Tx & Rx descriptors command */
427 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
429 /* Tx descriptors status */
430 #define ETH_LC_ERROR 0
431 #define ETH_UR_ERROR 0x00000002
432 #define ETH_RL_ERROR 0x00000004
433 #define ETH_LLC_SNAP_FORMAT 0x00000200
435 /* Rx descriptors status */
436 #define ETH_OVERRUN_ERROR 0x00000002
437 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
438 #define ETH_RESOURCE_ERROR 0x00000006
439 #define ETH_VLAN_TAGGED 0x00080000
440 #define ETH_BPDU_FRAME 0x00100000
441 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
442 #define ETH_OTHER_FRAME_TYPE 0x00400000
443 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
444 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
445 #define ETH_FRAME_HEADER_OK 0x02000000
446 #define ETH_RX_LAST_DESC 0x04000000
447 #define ETH_RX_FIRST_DESC 0x08000000
448 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
449 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
450 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
452 /* Rx descriptors byte count */
453 #define ETH_FRAME_FRAGMENTED 0x00000004
455 /* Tx descriptors command */
456 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
457 #define ETH_FRAME_SET_TO_VLAN 0x00008000
458 #define ETH_UDP_FRAME 0x00010000
459 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
460 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
461 #define ETH_ZERO_PADDING 0x00080000
462 #define ETH_TX_LAST_DESC 0x00100000
463 #define ETH_TX_FIRST_DESC 0x00200000
464 #define ETH_GEN_CRC 0x00400000
465 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
466 #define ETH_AUTO_MODE 0x40000000
468 #define ETH_TX_IHL_SHIFT 11
472 typedef enum _eth_func_ret_status {
473 ETH_OK, /* Returned as expected. */
474 ETH_ERROR, /* Fundamental error. */
475 ETH_RETRY, /* Could not process request. Try later.*/
476 ETH_END_OF_JOB, /* Ring has nothing to process. */
477 ETH_QUEUE_FULL, /* Ring resource error. */
478 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
479 } ETH_FUNC_RET_STATUS;
481 typedef enum _eth_target {
489 /* These are for big-endian machines. Little endian needs different
492 #if defined(__BIG_ENDIAN)
494 u16 byte_cnt; /* Descriptor buffer byte count */
495 u16 buf_size; /* Buffer size */
496 u32 cmd_sts; /* Descriptor command status */
497 u32 next_desc_ptr; /* Next descriptor pointer */
498 u32 buf_ptr; /* Descriptor buffer pointer */
502 u16 byte_cnt; /* buffer byte count */
503 u16 l4i_chk; /* CPU provided TCP checksum */
504 u32 cmd_sts; /* Command/status field */
505 u32 next_desc_ptr; /* Pointer to next descriptor */
506 u32 buf_ptr; /* pointer to buffer for this descriptor*/
508 #elif defined(__LITTLE_ENDIAN)
510 u32 cmd_sts; /* Descriptor command status */
511 u16 buf_size; /* Buffer size */
512 u16 byte_cnt; /* Descriptor buffer byte count */
513 u32 buf_ptr; /* Descriptor buffer pointer */
514 u32 next_desc_ptr; /* Next descriptor pointer */
518 u32 cmd_sts; /* Command/status field */
519 u16 l4i_chk; /* CPU provided TCP checksum */
520 u16 byte_cnt; /* buffer byte count */
521 u32 buf_ptr; /* pointer to buffer for this descriptor*/
522 u32 next_desc_ptr; /* Pointer to next descriptor */
525 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
528 /* Unified struct for Rx and Tx operations. The user is not required to */
529 /* be familier with neither Tx nor Rx descriptors. */
531 unsigned short byte_cnt; /* Descriptor buffer byte count */
532 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
533 unsigned int cmd_sts; /* Descriptor command status */
534 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
535 struct sk_buff *return_info; /* User resource return information */
538 /* Ethernet port specific information */
539 struct mv643xx_mib_counters {
540 u64 good_octets_received;
541 u32 bad_octets_received;
542 u32 internal_mac_transmit_err;
543 u32 good_frames_received;
544 u32 bad_frames_received;
545 u32 broadcast_frames_received;
546 u32 multicast_frames_received;
547 u32 frames_64_octets;
548 u32 frames_65_to_127_octets;
549 u32 frames_128_to_255_octets;
550 u32 frames_256_to_511_octets;
551 u32 frames_512_to_1023_octets;
552 u32 frames_1024_to_max_octets;
553 u64 good_octets_sent;
554 u32 good_frames_sent;
555 u32 excessive_collision;
556 u32 multicast_frames_sent;
557 u32 broadcast_frames_sent;
558 u32 unrec_mac_control_received;
560 u32 good_fc_received;
562 u32 undersize_received;
563 u32 fragments_received;
564 u32 oversize_received;
566 u32 mac_receive_error;
572 struct mv643xx_private {
573 int port_num; /* User Ethernet port number */
575 u32 rx_sram_addr; /* Base address of rx sram area */
576 u32 rx_sram_size; /* Size of rx sram area */
577 u32 tx_sram_addr; /* Base address of tx sram area */
578 u32 tx_sram_size; /* Size of tx sram area */
580 int rx_resource_err; /* Rx ring resource error flag */
582 /* Tx/Rx rings managment indexes fields. For driver use */
584 /* Next available and first returning Rx resource */
585 int rx_curr_desc_q, rx_used_desc_q;
587 /* Next available and first returning Tx resource */
588 int tx_curr_desc_q, tx_used_desc_q;
590 #ifdef MV643XX_TX_FAST_REFILL
591 u32 tx_clean_threshold;
594 struct eth_rx_desc *p_rx_desc_area;
595 dma_addr_t rx_desc_dma;
596 int rx_desc_area_size;
597 struct sk_buff **rx_skb;
599 struct eth_tx_desc *p_tx_desc_area;
600 dma_addr_t tx_desc_dma;
601 int tx_desc_area_size;
602 struct sk_buff **tx_skb;
604 struct work_struct tx_timeout_task;
606 struct net_device *dev;
607 struct napi_struct napi;
608 struct net_device_stats stats;
609 struct mv643xx_mib_counters mib_counters;
611 /* Size of Tx Ring per queue */
613 /* Number of tx descriptors in use */
615 /* Size of Rx Ring per queue */
617 /* Number of rx descriptors in use */
621 * Used in case RX Ring is empty, which can be caused when
622 * system does not have resources (skb's)
624 struct timer_list timeout;
628 struct mii_if_info mii;
631 /* Port operation control routines */
632 static void eth_port_init(struct mv643xx_private *mp);
633 static void eth_port_reset(unsigned int eth_port_num);
634 static void eth_port_start(struct net_device *dev);
636 /* PHY and MIB routines */
637 static void ethernet_phy_reset(unsigned int eth_port_num);
639 static void eth_port_write_smi_reg(unsigned int eth_port_num,
640 unsigned int phy_reg, unsigned int value);
642 static void eth_port_read_smi_reg(unsigned int eth_port_num,
643 unsigned int phy_reg, unsigned int *value);
645 static void eth_clear_mib_counters(unsigned int eth_port_num);
647 /* Port data flow control routines */
648 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
649 struct pkt_info *p_pkt_info);
650 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
651 struct pkt_info *p_pkt_info);
Code Review / linux-2.6.git / blob