1 #ifndef __MV643XX_ETH_H__
2 #define __MV643XX_ETH_H__
4 #include <linux/module.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/workqueue.h>
10 #include <linux/mv643xx_eth.h>
12 #include <asm/dma-mapping.h>
14 /* Checksum offload for Tx works for most packets, but
15 * fails if previous packet sent did not use hw csum
17 #define MV643XX_CHECKSUM_OFFLOAD_TX
19 #define MV643XX_TX_FAST_REFILL
23 * Number of RX / TX descriptors on RX / TX rings.
24 * Note that allocating RX descriptors is done by allocating the RX
25 * ring AND a preallocated RX buffers (skb's) for each descriptor.
26 * The TX descriptors only allocates the TX descriptors ring,
27 * with no pre allocated TX buffers (skb's are allocated by higher layers.
30 /* Default TX ring size is 1000 descriptors */
31 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
33 /* Default RX ring size is 400 descriptors */
34 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
36 #define MV643XX_TX_COAL 100
38 #define MV643XX_RX_COAL 100
41 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
42 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
44 #define MAX_DESCS_PER_SKB 1
47 #define ETH_VLAN_HLEN 4
49 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
50 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
51 ETH_VLAN_HLEN + ETH_FCS_LEN)
52 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())
54 /****************************************/
55 /* Ethernet Unit Registers */
56 /****************************************/
58 #define MV643XX_ETH_PHY_ADDR_REG 0x2000
59 #define MV643XX_ETH_SMI_REG 0x2004
60 #define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
61 #define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
62 #define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
63 #define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
64 #define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
65 #define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
66 #define MV643XX_ETH_BAR_0 0x2200
67 #define MV643XX_ETH_BAR_1 0x2208
68 #define MV643XX_ETH_BAR_2 0x2210
69 #define MV643XX_ETH_BAR_3 0x2218
70 #define MV643XX_ETH_BAR_4 0x2220
71 #define MV643XX_ETH_BAR_5 0x2228
72 #define MV643XX_ETH_SIZE_REG_0 0x2204
73 #define MV643XX_ETH_SIZE_REG_1 0x220c
74 #define MV643XX_ETH_SIZE_REG_2 0x2214
75 #define MV643XX_ETH_SIZE_REG_3 0x221c
76 #define MV643XX_ETH_SIZE_REG_4 0x2224
77 #define MV643XX_ETH_SIZE_REG_5 0x222c
78 #define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
79 #define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
80 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
81 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
82 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
83 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
84 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
85 #define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
86 #define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
87 #define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
88 #define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
89 #define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
90 #define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
91 #define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
92 #define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
93 #define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
94 #define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
95 #define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
96 #define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
97 #define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
98 #define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
99 #define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
100 #define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
101 #define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
102 #define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
103 #define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
104 #define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
105 #define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
106 #define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
107 #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
108 #define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
109 #define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
110 #define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
111 #define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
112 #define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
113 #define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
114 #define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
115 #define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
116 #define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
117 #define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
118 #define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
119 #define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
120 #define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
121 #define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
122 #define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
123 #define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
124 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
125 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
126 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
127 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
128 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
129 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
130 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
131 #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
132 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
133 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
134 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
135 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
136 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
137 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
138 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
139 #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
140 #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
141 #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
142 #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
143 #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
144 #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
145 #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
146 #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
147 #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
148 #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
149 #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
150 #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
151 #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
152 #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
153 #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
154 #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
155 #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
156 #define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
157 #define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
158 #define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
159 #define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
160 #define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
161 #define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
162 #define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
163 #define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
164 #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
165 #define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
166 #define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
167 #define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
169 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
170 #define MV643XX_ETH_UNICAST_NORMAL_MODE 0
171 #define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
172 #define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
173 #define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
174 #define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
175 #define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
176 #define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
177 #define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
178 #define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
179 #define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
180 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
181 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
182 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
183 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
184 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
185 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
186 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
187 #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
188 #define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
189 #define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
190 #define MV643XX_ETH_RECEIVE_BC_IF_IP 0
191 #define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
192 #define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
193 #define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
194 #define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
195 #define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
196 #define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
197 #define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
198 #define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
199 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
200 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
201 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
202 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
203 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
204 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
205 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
206 #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
207 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
208 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
209 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
210 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
211 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
212 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
213 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
214 #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
215 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
216 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
217 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
218 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
219 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
220 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
221 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
222 #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
224 #define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
225 MV643XX_ETH_UNICAST_NORMAL_MODE | \
226 MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
227 MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
228 MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
229 MV643XX_ETH_RECEIVE_BC_IF_IP | \
230 MV643XX_ETH_RECEIVE_BC_IF_ARP | \
231 MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
232 MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
233 MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
234 MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
235 MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
237 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
238 #define MV643XX_ETH_CLASSIFY_EN (1<<0)
239 #define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
240 #define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
241 #define MV643XX_ETH_PARTITION_DISABLE 0
242 #define MV643XX_ETH_PARTITION_ENABLE (1<<2)
244 #define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
245 MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
246 MV643XX_ETH_PARTITION_DISABLE
248 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
249 #define MV643XX_ETH_RIFB (1<<0)
250 #define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
251 #define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
252 #define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
253 #define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
254 #define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
255 #define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
256 #define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
257 #define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
258 #define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
259 #define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
260 #define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
261 #define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
262 #define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
263 #define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
264 #define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
265 #define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
267 #define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
269 #define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
270 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
271 MV643XX_ETH_IPG_INT_RX(0) | \
272 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
274 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
275 #define MV643XX_ETH_SERIAL_PORT_DISABLE 0
276 #define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
277 #define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
278 #define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
279 #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
280 #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
281 #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
282 #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
283 #define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
284 #define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
285 #define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
286 #define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
287 #define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
288 #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
289 #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
290 #define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
291 #define MV643XX_ETH_FORCE_LINK_FAIL 0
292 #define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
293 #define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
294 #define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
295 #define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
296 #define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
297 #define MV643XX_ETH_DTE_ADV_0 0
298 #define MV643XX_ETH_DTE_ADV_1 (1<<14)
299 #define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
300 #define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
301 #define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
302 #define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
303 #define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
304 #define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
305 #define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
306 #define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
307 #define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
308 #define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
309 #define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
310 #define MV643XX_ETH_CLR_EXT_LOOPBACK 0
311 #define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
312 #define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
313 #define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
314 #define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
315 #define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
316 #define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
317 #define MV643XX_ETH_SET_MII_SPEED_TO_10 0
318 #define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
320 #define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
322 #define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
323 MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
324 MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
325 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
326 MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
327 MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
328 MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
329 (1<<9) /* reserved */ | \
330 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
331 MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
332 MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
333 MV643XX_ETH_DTE_ADV_0 | \
334 MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
335 MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
336 MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
337 MV643XX_ETH_CLR_EXT_LOOPBACK | \
338 MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
339 MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
341 /* These macros describe Ethernet Serial Status reg (PSR) bits */
342 #define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
343 #define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
344 #define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
345 #define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
346 #define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
347 #define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
348 /* PSR bit 6 is undocumented */
349 #define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
350 #define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
351 #define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
352 #define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
353 /* PSR bits 11-31 are reserved */
355 #define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
356 #define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
358 #define MV643XX_ETH_DESC_SIZE 64
360 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
361 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
363 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
364 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
365 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
366 #define ETH_INT_CAUSE_EXT 0x00000002
367 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
369 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
370 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
371 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
372 #define ETH_INT_CAUSE_PHY 0x00010000
373 #define ETH_INT_CAUSE_STATE 0x00100000
374 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
377 #define ETH_INT_MASK_ALL 0x00000000
378 #define ETH_INT_MASK_ALL_EXT 0x00000000
380 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
381 #define PHY_WAIT_MICRO_SECONDS 10
383 /* Buffer offset from buffer pointer */
384 #define RX_BUF_OFFSET 0x2
386 /* Gigabit Ethernet Unit Global Registers */
388 /* MIB Counters register definitions */
389 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
390 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
391 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
392 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
393 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
394 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
395 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
396 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
397 #define ETH_MIB_FRAMES_64_OCTETS 0x20
398 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
399 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
400 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
401 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
402 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
403 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
404 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
405 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
406 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
407 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
408 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
409 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
410 #define ETH_MIB_FC_SENT 0x54
411 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
412 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
413 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
414 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
415 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
416 #define ETH_MIB_JABBER_RECEIVED 0x6c
417 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
418 #define ETH_MIB_BAD_CRC_EVENT 0x74
419 #define ETH_MIB_COLLISION 0x78
420 #define ETH_MIB_LATE_COLLISION 0x7c
422 /* Port serial status reg (PSR) */
423 #define ETH_INTERFACE_PCM 0x00000001
424 #define ETH_LINK_IS_UP 0x00000002
425 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
426 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
427 #define ETH_GMII_SPEED_1000 0x00000010
428 #define ETH_MII_SPEED_100 0x00000020
429 #define ETH_TX_IN_PROGRESS 0x00000080
430 #define ETH_BYPASS_ACTIVE 0x00000100
431 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
432 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
435 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
436 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
437 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
438 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
440 /* Interrupt Cause Register Bit Definitions */
442 /* SDMA command status fields macros */
444 /* Tx & Rx descriptors status */
445 #define ETH_ERROR_SUMMARY 0x00000001
447 /* Tx & Rx descriptors command */
448 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
450 /* Tx descriptors status */
451 #define ETH_LC_ERROR 0
452 #define ETH_UR_ERROR 0x00000002
453 #define ETH_RL_ERROR 0x00000004
454 #define ETH_LLC_SNAP_FORMAT 0x00000200
456 /* Rx descriptors status */
457 #define ETH_OVERRUN_ERROR 0x00000002
458 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
459 #define ETH_RESOURCE_ERROR 0x00000006
460 #define ETH_VLAN_TAGGED 0x00080000
461 #define ETH_BPDU_FRAME 0x00100000
462 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
463 #define ETH_OTHER_FRAME_TYPE 0x00400000
464 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
465 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
466 #define ETH_FRAME_HEADER_OK 0x02000000
467 #define ETH_RX_LAST_DESC 0x04000000
468 #define ETH_RX_FIRST_DESC 0x08000000
469 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
470 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
471 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
473 /* Rx descriptors byte count */
474 #define ETH_FRAME_FRAGMENTED 0x00000004
476 /* Tx descriptors command */
477 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
478 #define ETH_FRAME_SET_TO_VLAN 0x00008000
479 #define ETH_UDP_FRAME 0x00010000
480 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
481 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
482 #define ETH_ZERO_PADDING 0x00080000
483 #define ETH_TX_LAST_DESC 0x00100000
484 #define ETH_TX_FIRST_DESC 0x00200000
485 #define ETH_GEN_CRC 0x00400000
486 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
487 #define ETH_AUTO_MODE 0x40000000
489 #define ETH_TX_IHL_SHIFT 11
493 typedef enum _eth_func_ret_status {
494 ETH_OK, /* Returned as expected. */
495 ETH_ERROR, /* Fundamental error. */
496 ETH_RETRY, /* Could not process request. Try later.*/
497 ETH_END_OF_JOB, /* Ring has nothing to process. */
498 ETH_QUEUE_FULL, /* Ring resource error. */
499 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
500 } ETH_FUNC_RET_STATUS;
502 typedef enum _eth_target {
510 /* These are for big-endian machines. Little endian needs different
513 #if defined(__BIG_ENDIAN)
515 u16 byte_cnt; /* Descriptor buffer byte count */
516 u16 buf_size; /* Buffer size */
517 u32 cmd_sts; /* Descriptor command status */
518 u32 next_desc_ptr; /* Next descriptor pointer */
519 u32 buf_ptr; /* Descriptor buffer pointer */
523 u16 byte_cnt; /* buffer byte count */
524 u16 l4i_chk; /* CPU provided TCP checksum */
525 u32 cmd_sts; /* Command/status field */
526 u32 next_desc_ptr; /* Pointer to next descriptor */
527 u32 buf_ptr; /* pointer to buffer for this descriptor*/
530 #elif defined(__LITTLE_ENDIAN)
532 u32 cmd_sts; /* Descriptor command status */
533 u16 buf_size; /* Buffer size */
534 u16 byte_cnt; /* Descriptor buffer byte count */
535 u32 buf_ptr; /* Descriptor buffer pointer */
536 u32 next_desc_ptr; /* Next descriptor pointer */
540 u32 cmd_sts; /* Command/status field */
541 u16 l4i_chk; /* CPU provided TCP checksum */
542 u16 byte_cnt; /* buffer byte count */
543 u32 buf_ptr; /* pointer to buffer for this descriptor*/
544 u32 next_desc_ptr; /* Pointer to next descriptor */
547 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
550 /* Unified struct for Rx and Tx operations. The user is not required to */
551 /* be familier with neither Tx nor Rx descriptors. */
553 unsigned short byte_cnt; /* Descriptor buffer byte count */
554 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
555 unsigned int cmd_sts; /* Descriptor command status */
556 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
557 struct sk_buff *return_info; /* User resource return information */
560 /* Ethernet port specific information */
562 struct mv643xx_mib_counters {
563 u64 good_octets_received;
564 u32 bad_octets_received;
565 u32 internal_mac_transmit_err;
566 u32 good_frames_received;
567 u32 bad_frames_received;
568 u32 broadcast_frames_received;
569 u32 multicast_frames_received;
570 u32 frames_64_octets;
571 u32 frames_65_to_127_octets;
572 u32 frames_128_to_255_octets;
573 u32 frames_256_to_511_octets;
574 u32 frames_512_to_1023_octets;
575 u32 frames_1024_to_max_octets;
576 u64 good_octets_sent;
577 u32 good_frames_sent;
578 u32 excessive_collision;
579 u32 multicast_frames_sent;
580 u32 broadcast_frames_sent;
581 u32 unrec_mac_control_received;
583 u32 good_fc_received;
585 u32 undersize_received;
586 u32 fragments_received;
587 u32 oversize_received;
589 u32 mac_receive_error;
595 struct mv643xx_private {
596 int port_num; /* User Ethernet port number */
598 u32 rx_sram_addr; /* Base address of rx sram area */
599 u32 rx_sram_size; /* Size of rx sram area */
600 u32 tx_sram_addr; /* Base address of tx sram area */
601 u32 tx_sram_size; /* Size of tx sram area */
603 int rx_resource_err; /* Rx ring resource error flag */
605 /* Tx/Rx rings managment indexes fields. For driver use */
607 /* Next available and first returning Rx resource */
608 int rx_curr_desc_q, rx_used_desc_q;
610 /* Next available and first returning Tx resource */
611 int tx_curr_desc_q, tx_used_desc_q;
613 #ifdef MV643XX_TX_FAST_REFILL
614 u32 tx_clean_threshold;
617 struct eth_rx_desc *p_rx_desc_area;
618 dma_addr_t rx_desc_dma;
619 int rx_desc_area_size;
620 struct sk_buff **rx_skb;
622 struct eth_tx_desc *p_tx_desc_area;
623 dma_addr_t tx_desc_dma;
624 int tx_desc_area_size;
625 struct sk_buff **tx_skb;
627 struct work_struct tx_timeout_task;
629 struct net_device *dev;
630 struct napi_struct napi;
631 struct net_device_stats stats;
632 struct mv643xx_mib_counters mib_counters;
634 /* Size of Tx Ring per queue */
636 /* Number of tx descriptors in use */
638 /* Size of Rx Ring per queue */
640 /* Number of rx descriptors in use */
644 * Used in case RX Ring is empty, which can be caused when
645 * system does not have resources (skb's)
647 struct timer_list timeout;
651 struct mii_if_info mii;
654 /* Port operation control routines */
655 static void eth_port_init(struct mv643xx_private *mp);
656 static void eth_port_reset(unsigned int eth_port_num);
657 static void eth_port_start(struct net_device *dev);
659 /* PHY and MIB routines */
660 static void ethernet_phy_reset(unsigned int eth_port_num);
662 static void eth_port_write_smi_reg(unsigned int eth_port_num,
663 unsigned int phy_reg, unsigned int value);
665 static void eth_port_read_smi_reg(unsigned int eth_port_num,
666 unsigned int phy_reg, unsigned int *value);
668 static void eth_clear_mib_counters(unsigned int eth_port_num);
670 /* Port data flow control routines */
671 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
672 struct pkt_info *p_pkt_info);
673 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
674 struct pkt_info *p_pkt_info);
676 #endif /* __MV643XX_ETH_H__ */
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