drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.44-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 101          board_82599 },
 102
 103         /* required last entry */
 104         {0, }
 105 };
 106 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 107
 108 #ifdef CONFIG_IXGBE_DCA
 109 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 110                             void *p);
 111 static struct notifier_block dca_notifier = {
 112         .notifier_call = ixgbe_notify_dca,
 113         .next          = NULL,
 114         .priority      = 0
 115 };
 116 #endif
 117
 118 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 119 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 120 MODULE_LICENSE("GPL");
 121 MODULE_VERSION(DRV_VERSION);
 122
 123 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 124
 125 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 126 {
 127         u32 ctrl_ext;
 128
 129         /* Let firmware take over control of h/w */
 130         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 131         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 132                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 133 }
 134
 135 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 136 {
 137         u32 ctrl_ext;
 138
 139         /* Let firmware know the driver has taken over */
 140         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 141         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 142                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 143 }
 144
 145 /*
 146  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 147  * @adapter: pointer to adapter struct
 148  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 149  * @queue: queue to map the corresponding interrupt to
 150  * @msix_vector: the vector to map to the corresponding queue
 151  *
 152  */
 153 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 154                            u8 queue, u8 msix_vector)
 155 {
 156         u32 ivar, index;
 157         struct ixgbe_hw *hw = &adapter->hw;
 158         switch (hw->mac.type) {
 159         case ixgbe_mac_82598EB:
 160                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 161                 if (direction == -1)
 162                         direction = 0;
 163                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 164                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 165                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 166                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 167                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 168                 break;
 169         case ixgbe_mac_82599EB:
 170                 if (direction == -1) {
 171                         /* other causes */
 172                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 173                         index = ((queue & 1) * 8);
 174                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 175                         ivar &= ~(0xFF << index);
 176                         ivar |= (msix_vector << index);
 177                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 178                         break;
 179                 } else {
 180                         /* tx or rx causes */
 181                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 182                         index = ((16 * (queue & 1)) + (8 * direction));
 183                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 184                         ivar &= ~(0xFF << index);
 185                         ivar |= (msix_vector << index);
 186                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 187                         break;
 188                 }
 189         default:
 190                 break;
 191         }
 192 }
 193
 194 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 195                                           u64 qmask)
 196 {
 197         u32 mask;
 198
 199         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 200                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 202         } else {
 203                 mask = (qmask & 0xFFFFFFFF);
 204                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 205                 mask = (qmask >> 32);
 206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 207         }
 208 }
 209
 210 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 211                                              struct ixgbe_tx_buffer
 212                                              *tx_buffer_info)
 213 {
 214         tx_buffer_info->dma = 0;
 215         if (tx_buffer_info->skb) {
 216                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 217                               DMA_TO_DEVICE);
 218                 dev_kfree_skb_any(tx_buffer_info->skb);
 219                 tx_buffer_info->skb = NULL;
 220         }
 221         tx_buffer_info->time_stamp = 0;
 222         /* tx_buffer_info must be completely set up in the transmit path */
 223 }
 224
 225 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 226                                        struct ixgbe_ring *tx_ring,
 227                                        unsigned int eop)
 228 {
 229         struct ixgbe_hw *hw = &adapter->hw;
 230
 231         /* Detect a transmit hang in hardware, this serializes the
 232          * check with the clearing of time_stamp and movement of eop */
 233         adapter->detect_tx_hung = false;
 234         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 235             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 236             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 237                 /* detected Tx unit hang */
 238                 union ixgbe_adv_tx_desc *tx_desc;
 239                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 240                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 241                         "  Tx Queue             <%d>\n"
 242                         "  TDH, TDT             <%x>, <%x>\n"
 243                         "  next_to_use          <%x>\n"
 244                         "  next_to_clean        <%x>\n"
 245                         "tx_buffer_info[next_to_clean]\n"
 246                         "  time_stamp           <%lx>\n"
 247                         "  jiffies              <%lx>\n",
 248                         tx_ring->queue_index,
 249                         IXGBE_READ_REG(hw, tx_ring->head),
 250                         IXGBE_READ_REG(hw, tx_ring->tail),
 251                         tx_ring->next_to_use, eop,
 252                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 253                 return true;
 254         }
 255
 256         return false;
 257 }
 258
 259 #define IXGBE_MAX_TXD_PWR       14
 260 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 261
 262 /* Tx Descriptors needed, worst case */
 263 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 264                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 265 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 266         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 267
 268 static void ixgbe_tx_timeout(struct net_device *netdev);
 269
 270 /**
 271  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 272  * @q_vector: structure containing interrupt and ring information
 273  * @tx_ring: tx ring to clean
 274  **/
 275 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 276                                struct ixgbe_ring *tx_ring)
 277 {
 278         struct ixgbe_adapter *adapter = q_vector->adapter;
 279         struct net_device *netdev = adapter->netdev;
 280         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 281         struct ixgbe_tx_buffer *tx_buffer_info;
 282         unsigned int i, eop, count = 0;
 283         unsigned int total_bytes = 0, total_packets = 0;
 284
 285         i = tx_ring->next_to_clean;
 286         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 287         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 288
 289         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 290                (count < tx_ring->work_limit)) {
 291                 bool cleaned = false;
 292                 for ( ; !cleaned; count++) {
 293                         struct sk_buff *skb;
 294                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 295                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 296                         cleaned = (i == eop);
 297                         skb = tx_buffer_info->skb;
 298
 299                         if (cleaned && skb) {
 300                                 unsigned int segs, bytecount;
 301                                 unsigned int hlen = skb_headlen(skb);
 302
 303                                 /* gso_segs is currently only valid for tcp */
 304                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 305 #ifdef IXGBE_FCOE
 306                                 /* adjust for FCoE Sequence Offload */
 307                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 308                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 309                                     skb_is_gso(skb)) {
 310                                         hlen = skb_transport_offset(skb) +
 311                                                 sizeof(struct fc_frame_header) +
 312                                                 sizeof(struct fcoe_crc_eof);
 313                                         segs = DIV_ROUND_UP(skb->len - hlen,
 314                                                 skb_shinfo(skb)->gso_size);
 315                                 }
 316 #endif /* IXGBE_FCOE */
 317                                 /* multiply data chunks by size of headers */
 318                                 bytecount = ((segs - 1) * hlen) + skb->len;
 319                                 total_packets += segs;
 320                                 total_bytes += bytecount;
 321                         }
 322
 323                         ixgbe_unmap_and_free_tx_resource(adapter,
 324                                                          tx_buffer_info);
 325
 326                         tx_desc->wb.status = 0;
 327
 328                         i++;
 329                         if (i == tx_ring->count)
 330                                 i = 0;
 331                 }
 332
 333                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 334                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 335         }
 336
 337         tx_ring->next_to_clean = i;
 338
 339 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 340         if (unlikely(count && netif_carrier_ok(netdev) &&
 341                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 342                 /* Make sure that anybody stopping the queue after this
 343                  * sees the new next_to_clean.
 344                  */
 345                 smp_mb();
 346                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 347                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 348                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 349                         ++adapter->restart_queue;
 350                 }
 351         }
 352
 353         if (adapter->detect_tx_hung) {
 354                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 355                         /* schedule immediate reset if we believe we hung */
 356                         DPRINTK(PROBE, INFO,
 357                                 "tx hang %d detected, resetting adapter\n",
 358                                 adapter->tx_timeout_count + 1);
 359                         ixgbe_tx_timeout(adapter->netdev);
 360                 }
 361         }
 362
 363         /* re-arm the interrupt */
 364         if (count >= tx_ring->work_limit)
 365                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 366
 367         tx_ring->total_bytes += total_bytes;
 368         tx_ring->total_packets += total_packets;
 369         tx_ring->stats.packets += total_packets;
 370         tx_ring->stats.bytes += total_bytes;
 371         adapter->net_stats.tx_bytes += total_bytes;
 372         adapter->net_stats.tx_packets += total_packets;
 373         return (count < tx_ring->work_limit);
 374 }
 375
 376 #ifdef CONFIG_IXGBE_DCA
 377 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 378                                 struct ixgbe_ring *rx_ring)
 379 {
 380         u32 rxctrl;
 381         int cpu = get_cpu();
 382         int q = rx_ring - adapter->rx_ring;
 383
 384         if (rx_ring->cpu != cpu) {
 385                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 386                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 387                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 388                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 389                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 390                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 391                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 392                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 393                 }
 394                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 395                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 396                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 397                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 398                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 399                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 400                 rx_ring->cpu = cpu;
 401         }
 402         put_cpu();
 403 }
 404
 405 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 406                                 struct ixgbe_ring *tx_ring)
 407 {
 408         u32 txctrl;
 409         int cpu = get_cpu();
 410         int q = tx_ring - adapter->tx_ring;
 411
 412         if (tx_ring->cpu != cpu) {
 413                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 414                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 415                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 416                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 417                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 418                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 419                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 420                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 421                 }
 422                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 423                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 424                 tx_ring->cpu = cpu;
 425         }
 426         put_cpu();
 427 }
 428
 429 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 430 {
 431         int i;
 432
 433         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 434                 return;
 435
 436         /* always use CB2 mode, difference is masked in the CB driver */
 437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 438
 439         for (i = 0; i < adapter->num_tx_queues; i++) {
 440                 adapter->tx_ring[i].cpu = -1;
 441                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 442         }
 443         for (i = 0; i < adapter->num_rx_queues; i++) {
 444                 adapter->rx_ring[i].cpu = -1;
 445                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 446         }
 447 }
 448
 449 static int __ixgbe_notify_dca(struct device *dev, void *data)
 450 {
 451         struct net_device *netdev = dev_get_drvdata(dev);
 452         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 453         unsigned long event = *(unsigned long *)data;
 454
 455         switch (event) {
 456         case DCA_PROVIDER_ADD:
 457                 /* if we're already enabled, don't do it again */
 458                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 459                         break;
 460                 if (dca_add_requester(dev) == 0) {
 461                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 462                         ixgbe_setup_dca(adapter);
 463                         break;
 464                 }
 465                 /* Fall Through since DCA is disabled. */
 466         case DCA_PROVIDER_REMOVE:
 467                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 468                         dca_remove_requester(dev);
 469                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 470                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 471                 }
 472                 break;
 473         }
 474
 475         return 0;
 476 }
 477
 478 #endif /* CONFIG_IXGBE_DCA */
 479 /**
 480  * ixgbe_receive_skb - Send a completed packet up the stack
 481  * @adapter: board private structure
 482  * @skb: packet to send up
 483  * @status: hardware indication of status of receive
 484  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 485  * @rx_desc: rx descriptor
 486  **/
 487 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 488                               struct sk_buff *skb, u8 status,
 489                               struct ixgbe_ring *ring,
 490                               union ixgbe_adv_rx_desc *rx_desc)
 491 {
 492         struct ixgbe_adapter *adapter = q_vector->adapter;
 493         struct napi_struct *napi = &q_vector->napi;
 494         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 495         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 496
 497         skb_record_rx_queue(skb, ring->queue_index);
 498         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 499                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 500                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 501                 else
 502                         napi_gro_receive(napi, skb);
 503         } else {
 504                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 505                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 506                 else
 507                         netif_rx(skb);
 508         }
 509 }
 510
 511 /**
 512  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 513  * @adapter: address of board private structure
 514  * @status_err: hardware indication of status of receive
 515  * @skb: skb currently being received and modified
 516  **/
 517 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 518                                      union ixgbe_adv_rx_desc *rx_desc,
 519                                      struct sk_buff *skb)
 520 {
 521         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 522
 523         skb->ip_summed = CHECKSUM_NONE;
 524
 525         /* Rx csum disabled */
 526         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 527                 return;
 528
 529         /* if IP and error */
 530         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 531             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 532                 adapter->hw_csum_rx_error++;
 533                 return;
 534         }
 535
 536         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 537                 return;
 538
 539         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 540                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 541
 542                 /*
 543                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 544                  * checksum errors.
 545                  */
 546                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 547                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 548                         return;
 549
 550                 adapter->hw_csum_rx_error++;
 551                 return;
 552         }
 553
 554         /* It must be a TCP or UDP packet with a valid checksum */
 555         skb->ip_summed = CHECKSUM_UNNECESSARY;
 556         adapter->hw_csum_rx_good++;
 557 }
 558
 559 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 560                                          struct ixgbe_ring *rx_ring, u32 val)
 561 {
 562         /*
 563          * Force memory writes to complete before letting h/w
 564          * know there are new descriptors to fetch.  (Only
 565          * applicable for weak-ordered memory model archs,
 566          * such as IA-64).
 567          */
 568         wmb();
 569         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 570 }
 571
 572 /**
 573  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 574  * @adapter: address of board private structure
 575  **/
 576 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 577                                    struct ixgbe_ring *rx_ring,
 578                                    int cleaned_count)
 579 {
 580         struct pci_dev *pdev = adapter->pdev;
 581         union ixgbe_adv_rx_desc *rx_desc;
 582         struct ixgbe_rx_buffer *bi;
 583         unsigned int i;
 584
 585         i = rx_ring->next_to_use;
 586         bi = &rx_ring->rx_buffer_info[i];
 587
 588         while (cleaned_count--) {
 589                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 590
 591                 if (!bi->page_dma &&
 592                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 593                         if (!bi->page) {
 594                                 bi->page = alloc_page(GFP_ATOMIC);
 595                                 if (!bi->page) {
 596                                         adapter->alloc_rx_page_failed++;
 597                                         goto no_buffers;
 598                                 }
 599                                 bi->page_offset = 0;
 600                         } else {
 601                                 /* use a half page if we're re-using */
 602                                 bi->page_offset ^= (PAGE_SIZE / 2);
 603                         }
 604
 605                         bi->page_dma = pci_map_page(pdev, bi->page,
 606                                                     bi->page_offset,
 607                                                     (PAGE_SIZE / 2),
 608                                                     PCI_DMA_FROMDEVICE);
 609                 }
 610
 611                 if (!bi->skb) {
 612                         struct sk_buff *skb;
 613                         skb = netdev_alloc_skb(adapter->netdev,
 614                                                (rx_ring->rx_buf_len +
 615                                                 NET_IP_ALIGN));
 616
 617                         if (!skb) {
 618                                 adapter->alloc_rx_buff_failed++;
 619                                 goto no_buffers;
 620                         }
 621
 622                         /*
 623                          * Make buffer alignment 2 beyond a 16 byte boundary
 624                          * this will result in a 16 byte aligned IP header after
 625                          * the 14 byte MAC header is removed
 626                          */
 627                         skb_reserve(skb, NET_IP_ALIGN);
 628
 629                         bi->skb = skb;
 630                         bi->dma = pci_map_single(pdev, skb->data,
 631                                                  rx_ring->rx_buf_len,
 632                                                  PCI_DMA_FROMDEVICE);
 633                 }
 634                 /* Refresh the desc even if buffer_addrs didn't change because
 635                  * each write-back erases this info. */
 636                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 637                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 638                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 639                 } else {
 640                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 641                 }
 642
 643                 i++;
 644                 if (i == rx_ring->count)
 645                         i = 0;
 646                 bi = &rx_ring->rx_buffer_info[i];
 647         }
 648
 649 no_buffers:
 650         if (rx_ring->next_to_use != i) {
 651                 rx_ring->next_to_use = i;
 652                 if (i-- == 0)
 653                         i = (rx_ring->count - 1);
 654
 655                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 656         }
 657 }
 658
 659 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 660 {
 661         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 662 }
 663
 664 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 665 {
 666         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 667 }
 668
 669 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 670 {
 671         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 672                 IXGBE_RXDADV_RSCCNT_MASK) >>
 673                 IXGBE_RXDADV_RSCCNT_SHIFT;
 674 }
 675
 676 /**
 677  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 678  * @skb: pointer to the last skb in the rsc queue
 679  *
 680  * This function changes a queue full of hw rsc buffers into a completed
 681  * packet.  It uses the ->prev pointers to find the first packet and then
 682  * turns it into the frag list owner.
 683  **/
 684 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 685 {
 686         unsigned int frag_list_size = 0;
 687
 688         while (skb->prev) {
 689                 struct sk_buff *prev = skb->prev;
 690                 frag_list_size += skb->len;
 691                 skb->prev = NULL;
 692                 skb = prev;
 693         }
 694
 695         skb_shinfo(skb)->frag_list = skb->next;
 696         skb->next = NULL;
 697         skb->len += frag_list_size;
 698         skb->data_len += frag_list_size;
 699         skb->truesize += frag_list_size;
 700         return skb;
 701 }
 702
 703 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 704                                struct ixgbe_ring *rx_ring,
 705                                int *work_done, int work_to_do)
 706 {
 707         struct ixgbe_adapter *adapter = q_vector->adapter;
 708         struct pci_dev *pdev = adapter->pdev;
 709         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 710         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 711         struct sk_buff *skb;
 712         unsigned int i, rsc_count = 0;
 713         u32 len, staterr;
 714         u16 hdr_info;
 715         bool cleaned = false;
 716         int cleaned_count = 0;
 717         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 718 #ifdef IXGBE_FCOE
 719         int ddp_bytes = 0;
 720 #endif /* IXGBE_FCOE */
 721
 722         i = rx_ring->next_to_clean;
 723         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 724         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 725         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 726
 727         while (staterr & IXGBE_RXD_STAT_DD) {
 728                 u32 upper_len = 0;
 729                 if (*work_done >= work_to_do)
 730                         break;
 731                 (*work_done)++;
 732
 733                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 734                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 735                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 736                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 737                         if (hdr_info & IXGBE_RXDADV_SPH)
 738                                 adapter->rx_hdr_split++;
 739                         if (len > IXGBE_RX_HDR_SIZE)
 740                                 len = IXGBE_RX_HDR_SIZE;
 741                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 742                 } else {
 743                         len = le16_to_cpu(rx_desc->wb.upper.length);
 744                 }
 745
 746                 cleaned = true;
 747                 skb = rx_buffer_info->skb;
 748                 prefetch(skb->data - NET_IP_ALIGN);
 749                 rx_buffer_info->skb = NULL;
 750
 751                 if (rx_buffer_info->dma) {
 752                         pci_unmap_single(pdev, rx_buffer_info->dma,
 753                                          rx_ring->rx_buf_len,
 754                                          PCI_DMA_FROMDEVICE);
 755                         rx_buffer_info->dma = 0;
 756                         skb_put(skb, len);
 757                 }
 758
 759                 if (upper_len) {
 760                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 761                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 762                         rx_buffer_info->page_dma = 0;
 763                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 764                                            rx_buffer_info->page,
 765                                            rx_buffer_info->page_offset,
 766                                            upper_len);
 767
 768                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 769                             (page_count(rx_buffer_info->page) != 1))
 770                                 rx_buffer_info->page = NULL;
 771                         else
 772                                 get_page(rx_buffer_info->page);
 773
 774                         skb->len += upper_len;
 775                         skb->data_len += upper_len;
 776                         skb->truesize += upper_len;
 777                 }
 778
 779                 i++;
 780                 if (i == rx_ring->count)
 781                         i = 0;
 782
 783                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 784                 prefetch(next_rxd);
 785                 cleaned_count++;
 786
 787                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 788                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 789
 790                 if (rsc_count) {
 791                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 792                                      IXGBE_RXDADV_NEXTP_SHIFT;
 793                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 794                         rx_ring->rsc_count += (rsc_count - 1);
 795                 } else {
 796                         next_buffer = &rx_ring->rx_buffer_info[i];
 797                 }
 798
 799                 if (staterr & IXGBE_RXD_STAT_EOP) {
 800                         if (skb->prev)
 801                                 skb = ixgbe_transform_rsc_queue(skb);
 802                         rx_ring->stats.packets++;
 803                         rx_ring->stats.bytes += skb->len;
 804                 } else {
 805                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 806                                 rx_buffer_info->skb = next_buffer->skb;
 807                                 rx_buffer_info->dma = next_buffer->dma;
 808                                 next_buffer->skb = skb;
 809                                 next_buffer->dma = 0;
 810                         } else {
 811                                 skb->next = next_buffer->skb;
 812                                 skb->next->prev = skb;
 813                         }
 814                         adapter->non_eop_descs++;
 815                         goto next_desc;
 816                 }
 817
 818                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 819                         dev_kfree_skb_irq(skb);
 820                         goto next_desc;
 821                 }
 822
 823                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 824
 825                 /* probably a little skewed due to removing CRC */
 826                 total_rx_bytes += skb->len;
 827                 total_rx_packets++;
 828
 829                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 830 #ifdef IXGBE_FCOE
 831                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 832                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 833                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 834                         if (!ddp_bytes)
 835                                 goto next_desc;
 836                 }
 837 #endif /* IXGBE_FCOE */
 838                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 839
 840 next_desc:
 841                 rx_desc->wb.upper.status_error = 0;
 842
 843                 /* return some buffers to hardware, one at a time is too slow */
 844                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 845                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 846                         cleaned_count = 0;
 847                 }
 848
 849                 /* use prefetched values */
 850                 rx_desc = next_rxd;
 851                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 852
 853                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 854         }
 855
 856         rx_ring->next_to_clean = i;
 857         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 858
 859         if (cleaned_count)
 860                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 861
 862 #ifdef IXGBE_FCOE
 863         /* include DDPed FCoE data */
 864         if (ddp_bytes > 0) {
 865                 unsigned int mss;
 866
 867                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 868                         sizeof(struct fc_frame_header) -
 869                         sizeof(struct fcoe_crc_eof);
 870                 if (mss > 512)
 871                         mss &= ~511;
 872                 total_rx_bytes += ddp_bytes;
 873                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 874         }
 875 #endif /* IXGBE_FCOE */
 876
 877         rx_ring->total_packets += total_rx_packets;
 878         rx_ring->total_bytes += total_rx_bytes;
 879         adapter->net_stats.rx_bytes += total_rx_bytes;
 880         adapter->net_stats.rx_packets += total_rx_packets;
 881
 882         return cleaned;
 883 }
 884
 885 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 886 /**
 887  * ixgbe_configure_msix - Configure MSI-X hardware
 888  * @adapter: board private structure
 889  *
 890  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 891  * interrupts.
 892  **/
 893 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 894 {
 895         struct ixgbe_q_vector *q_vector;
 896         int i, j, q_vectors, v_idx, r_idx;
 897         u32 mask;
 898
 899         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 900
 901         /*
 902          * Populate the IVAR table and set the ITR values to the
 903          * corresponding register.
 904          */
 905         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 906                 q_vector = adapter->q_vector[v_idx];
 907                 /* XXX for_each_bit(...) */
 908                 r_idx = find_first_bit(q_vector->rxr_idx,
 909                                        adapter->num_rx_queues);
 910
 911                 for (i = 0; i < q_vector->rxr_count; i++) {
 912                         j = adapter->rx_ring[r_idx].reg_idx;
 913                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 914                         r_idx = find_next_bit(q_vector->rxr_idx,
 915                                               adapter->num_rx_queues,
 916                                               r_idx + 1);
 917                 }
 918                 r_idx = find_first_bit(q_vector->txr_idx,
 919                                        adapter->num_tx_queues);
 920
 921                 for (i = 0; i < q_vector->txr_count; i++) {
 922                         j = adapter->tx_ring[r_idx].reg_idx;
 923                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 924                         r_idx = find_next_bit(q_vector->txr_idx,
 925                                               adapter->num_tx_queues,
 926                                               r_idx + 1);
 927                 }
 928
 929                 if (q_vector->txr_count && !q_vector->rxr_count)
 930                         /* tx only */
 931                         q_vector->eitr = adapter->tx_eitr_param;
 932                 else if (q_vector->rxr_count)
 933                         /* rx or mixed */
 934                         q_vector->eitr = adapter->rx_eitr_param;
 935
 936                 ixgbe_write_eitr(q_vector);
 937         }
 938
 939         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 940                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 941                                v_idx);
 942         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 943                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 944         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 945
 946         /* set up to autoclear timer, and the vectors */
 947         mask = IXGBE_EIMS_ENABLE_MASK;
 948         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 949         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 950 }
 951
 952 enum latency_range {
 953         lowest_latency = 0,
 954         low_latency = 1,
 955         bulk_latency = 2,
 956         latency_invalid = 255
 957 };
 958
 959 /**
 960  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 961  * @adapter: pointer to adapter
 962  * @eitr: eitr setting (ints per sec) to give last timeslice
 963  * @itr_setting: current throttle rate in ints/second
 964  * @packets: the number of packets during this measurement interval
 965  * @bytes: the number of bytes during this measurement interval
 966  *
 967  *      Stores a new ITR value based on packets and byte
 968  *      counts during the last interrupt.  The advantage of per interrupt
 969  *      computation is faster updates and more accurate ITR for the current
 970  *      traffic pattern.  Constants in this function were computed
 971  *      based on theoretical maximum wire speed and thresholds were set based
 972  *      on testing data as well as attempting to minimize response time
 973  *      while increasing bulk throughput.
 974  *      this functionality is controlled by the InterruptThrottleRate module
 975  *      parameter (see ixgbe_param.c)
 976  **/
 977 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 978                            u32 eitr, u8 itr_setting,
 979                            int packets, int bytes)
 980 {
 981         unsigned int retval = itr_setting;
 982         u32 timepassed_us;
 983         u64 bytes_perint;
 984
 985         if (packets == 0)
 986                 goto update_itr_done;
 987
 988
 989         /* simple throttlerate management
 990          *    0-20MB/s lowest (100000 ints/s)
 991          *   20-100MB/s low   (20000 ints/s)
 992          *  100-1249MB/s bulk (8000 ints/s)
 993          */
 994         /* what was last interrupt timeslice? */
 995         timepassed_us = 1000000/eitr;
 996         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 997
 998         switch (itr_setting) {
 999         case lowest_latency:
1000                 if (bytes_perint > adapter->eitr_low)
1001                         retval = low_latency;
1002                 break;
1003         case low_latency:
1004                 if (bytes_perint > adapter->eitr_high)
1005                         retval = bulk_latency;
1006                 else if (bytes_perint <= adapter->eitr_low)
1007                         retval = lowest_latency;
1008                 break;
1009         case bulk_latency:
1010                 if (bytes_perint <= adapter->eitr_high)
1011                         retval = low_latency;
1012                 break;
1013         }
1014
1015 update_itr_done:
1016         return retval;
1017 }
1018
1019 /**
1020  * ixgbe_write_eitr - write EITR register in hardware specific way
1021  * @q_vector: structure containing interrupt and ring information
1022  *
1023  * This function is made to be called by ethtool and by the driver
1024  * when it needs to update EITR registers at runtime.  Hardware
1025  * specific quirks/differences are taken care of here.
1026  */
1027 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1028 {
1029         struct ixgbe_adapter *adapter = q_vector->adapter;
1030         struct ixgbe_hw *hw = &adapter->hw;
1031         int v_idx = q_vector->v_idx;
1032         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1033
1034         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1035                 /* must write high and low 16 bits to reset counter */
1036                 itr_reg |= (itr_reg << 16);
1037         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1038                 /*
1039                  * set the WDIS bit to not clear the timer bits and cause an
1040                  * immediate assertion of the interrupt
1041                  */
1042                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1043         }
1044         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1045 }
1046
1047 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1048 {
1049         struct ixgbe_adapter *adapter = q_vector->adapter;
1050         u32 new_itr;
1051         u8 current_itr, ret_itr;
1052         int i, r_idx;
1053         struct ixgbe_ring *rx_ring, *tx_ring;
1054
1055         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1056         for (i = 0; i < q_vector->txr_count; i++) {
1057                 tx_ring = &(adapter->tx_ring[r_idx]);
1058                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1059                                            q_vector->tx_itr,
1060                                            tx_ring->total_packets,
1061                                            tx_ring->total_bytes);
1062                 /* if the result for this queue would decrease interrupt
1063                  * rate for this vector then use that result */
1064                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1065                                     q_vector->tx_itr - 1 : ret_itr);
1066                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1067                                       r_idx + 1);
1068         }
1069
1070         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1071         for (i = 0; i < q_vector->rxr_count; i++) {
1072                 rx_ring = &(adapter->rx_ring[r_idx]);
1073                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1074                                            q_vector->rx_itr,
1075                                            rx_ring->total_packets,
1076                                            rx_ring->total_bytes);
1077                 /* if the result for this queue would decrease interrupt
1078                  * rate for this vector then use that result */
1079                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1080                                     q_vector->rx_itr - 1 : ret_itr);
1081                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1082                                       r_idx + 1);
1083         }
1084
1085         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1086
1087         switch (current_itr) {
1088         /* counts and packets in update_itr are dependent on these numbers */
1089         case lowest_latency:
1090                 new_itr = 100000;
1091                 break;
1092         case low_latency:
1093                 new_itr = 20000; /* aka hwitr = ~200 */
1094                 break;
1095         case bulk_latency:
1096         default:
1097                 new_itr = 8000;
1098                 break;
1099         }
1100
1101         if (new_itr != q_vector->eitr) {
1102                 /* do an exponential smoothing */
1103                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1104
1105                 /* save the algorithm value here, not the smoothed one */
1106                 q_vector->eitr = new_itr;
1107
1108                 ixgbe_write_eitr(q_vector);
1109         }
1110
1111         return;
1112 }
1113
1114 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1115 {
1116         struct ixgbe_hw *hw = &adapter->hw;
1117
1118         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1119             (eicr & IXGBE_EICR_GPI_SDP1)) {
1120                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1121                 /* write to clear the interrupt */
1122                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1123         }
1124 }
1125
1126 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1127 {
1128         struct ixgbe_hw *hw = &adapter->hw;
1129
1130         if (eicr & IXGBE_EICR_GPI_SDP1) {
1131                 /* Clear the interrupt */
1132                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1133                 schedule_work(&adapter->multispeed_fiber_task);
1134         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1135                 /* Clear the interrupt */
1136                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1137                 schedule_work(&adapter->sfp_config_module_task);
1138         } else {
1139                 /* Interrupt isn't for us... */
1140                 return;
1141         }
1142 }
1143
1144 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1145 {
1146         struct ixgbe_hw *hw = &adapter->hw;
1147
1148         adapter->lsc_int++;
1149         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1150         adapter->link_check_timeout = jiffies;
1151         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1152                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1153                 schedule_work(&adapter->watchdog_task);
1154         }
1155 }
1156
1157 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1158 {
1159         struct net_device *netdev = data;
1160         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1161         struct ixgbe_hw *hw = &adapter->hw;
1162         u32 eicr;
1163
1164         /*
1165          * Workaround for Silicon errata.  Use clear-by-write instead
1166          * of clear-by-read.  Reading with EICS will return the
1167          * interrupt causes without clearing, which later be done
1168          * with the write to EICR.
1169          */
1170         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1171         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1172
1173         if (eicr & IXGBE_EICR_LSC)
1174                 ixgbe_check_lsc(adapter);
1175
1176         if (hw->mac.type == ixgbe_mac_82598EB)
1177                 ixgbe_check_fan_failure(adapter, eicr);
1178
1179         if (hw->mac.type == ixgbe_mac_82599EB) {
1180                 ixgbe_check_sfp_event(adapter, eicr);
1181
1182                 /* Handle Flow Director Full threshold interrupt */
1183                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1184                         int i;
1185                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1186                         /* Disable transmits before FDIR Re-initialization */
1187                         netif_tx_stop_all_queues(netdev);
1188                         for (i = 0; i < adapter->num_tx_queues; i++) {
1189                                 struct ixgbe_ring *tx_ring =
1190                                                            &adapter->tx_ring[i];
1191                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1192                                                        &tx_ring->reinit_state))
1193                                         schedule_work(&adapter->fdir_reinit_task);
1194                         }
1195                 }
1196         }
1197         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1198                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1204                                            u64 qmask)
1205 {
1206         u32 mask;
1207
1208         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1209                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1211         } else {
1212                 mask = (qmask & 0xFFFFFFFF);
1213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1214                 mask = (qmask >> 32);
1215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1216         }
1217         /* skip the flush */
1218 }
1219
1220 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1221                                             u64 qmask)
1222 {
1223         u32 mask;
1224
1225         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1226                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1227                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1228         } else {
1229                 mask = (qmask & 0xFFFFFFFF);
1230                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1231                 mask = (qmask >> 32);
1232                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1233         }
1234         /* skip the flush */
1235 }
1236
1237 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1238 {
1239         struct ixgbe_q_vector *q_vector = data;
1240         struct ixgbe_adapter  *adapter = q_vector->adapter;
1241         struct ixgbe_ring     *tx_ring;
1242         int i, r_idx;
1243
1244         if (!q_vector->txr_count)
1245                 return IRQ_HANDLED;
1246
1247         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1248         for (i = 0; i < q_vector->txr_count; i++) {
1249                 tx_ring = &(adapter->tx_ring[r_idx]);
1250                 tx_ring->total_bytes = 0;
1251                 tx_ring->total_packets = 0;
1252                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1253                                       r_idx + 1);
1254         }
1255
1256         /* disable interrupts on this vector only */
1257         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1258         napi_schedule(&q_vector->napi);
1259
1260         return IRQ_HANDLED;
1261 }
1262
1263 /**
1264  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1265  * @irq: unused
1266  * @data: pointer to our q_vector struct for this interrupt vector
1267  **/
1268 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1269 {
1270         struct ixgbe_q_vector *q_vector = data;
1271         struct ixgbe_adapter  *adapter = q_vector->adapter;
1272         struct ixgbe_ring  *rx_ring;
1273         int r_idx;
1274         int i;
1275
1276         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277         for (i = 0;  i < q_vector->rxr_count; i++) {
1278                 rx_ring = &(adapter->rx_ring[r_idx]);
1279                 rx_ring->total_bytes = 0;
1280                 rx_ring->total_packets = 0;
1281                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1282                                       r_idx + 1);
1283         }
1284
1285         if (!q_vector->rxr_count)
1286                 return IRQ_HANDLED;
1287
1288         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1289         rx_ring = &(adapter->rx_ring[r_idx]);
1290         /* disable interrupts on this vector only */
1291         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1292         napi_schedule(&q_vector->napi);
1293
1294         return IRQ_HANDLED;
1295 }
1296
1297 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1298 {
1299         struct ixgbe_q_vector *q_vector = data;
1300         struct ixgbe_adapter  *adapter = q_vector->adapter;
1301         struct ixgbe_ring  *ring;
1302         int r_idx;
1303         int i;
1304
1305         if (!q_vector->txr_count && !q_vector->rxr_count)
1306                 return IRQ_HANDLED;
1307
1308         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1309         for (i = 0; i < q_vector->txr_count; i++) {
1310                 ring = &(adapter->tx_ring[r_idx]);
1311                 ring->total_bytes = 0;
1312                 ring->total_packets = 0;
1313                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1314                                       r_idx + 1);
1315         }
1316
1317         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1318         for (i = 0; i < q_vector->rxr_count; i++) {
1319                 ring = &(adapter->rx_ring[r_idx]);
1320                 ring->total_bytes = 0;
1321                 ring->total_packets = 0;
1322                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1323                                       r_idx + 1);
1324         }
1325
1326         /* disable interrupts on this vector only */
1327         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1328         napi_schedule(&q_vector->napi);
1329
1330         return IRQ_HANDLED;
1331 }
1332
1333 /**
1334  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1335  * @napi: napi struct with our devices info in it
1336  * @budget: amount of work driver is allowed to do this pass, in packets
1337  *
1338  * This function is optimized for cleaning one queue only on a single
1339  * q_vector!!!
1340  **/
1341 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1342 {
1343         struct ixgbe_q_vector *q_vector =
1344                                container_of(napi, struct ixgbe_q_vector, napi);
1345         struct ixgbe_adapter *adapter = q_vector->adapter;
1346         struct ixgbe_ring *rx_ring = NULL;
1347         int work_done = 0;
1348         long r_idx;
1349
1350         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1351         rx_ring = &(adapter->rx_ring[r_idx]);
1352 #ifdef CONFIG_IXGBE_DCA
1353         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1354                 ixgbe_update_rx_dca(adapter, rx_ring);
1355 #endif
1356
1357         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1358
1359         /* If all Rx work done, exit the polling mode */
1360         if (work_done < budget) {
1361                 napi_complete(napi);
1362                 if (adapter->rx_itr_setting & 1)
1363                         ixgbe_set_itr_msix(q_vector);
1364                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1365                         ixgbe_irq_enable_queues(adapter,
1366                                                 ((u64)1 << q_vector->v_idx));
1367         }
1368
1369         return work_done;
1370 }
1371
1372 /**
1373  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1374  * @napi: napi struct with our devices info in it
1375  * @budget: amount of work driver is allowed to do this pass, in packets
1376  *
1377  * This function will clean more than one rx queue associated with a
1378  * q_vector.
1379  **/
1380 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1381 {
1382         struct ixgbe_q_vector *q_vector =
1383                                container_of(napi, struct ixgbe_q_vector, napi);
1384         struct ixgbe_adapter *adapter = q_vector->adapter;
1385         struct ixgbe_ring *ring = NULL;
1386         int work_done = 0, i;
1387         long r_idx;
1388         bool tx_clean_complete = true;
1389
1390         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1391         for (i = 0; i < q_vector->txr_count; i++) {
1392                 ring = &(adapter->tx_ring[r_idx]);
1393 #ifdef CONFIG_IXGBE_DCA
1394                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395                         ixgbe_update_tx_dca(adapter, ring);
1396 #endif
1397                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1398                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1399                                       r_idx + 1);
1400         }
1401
1402         /* attempt to distribute budget to each queue fairly, but don't allow
1403          * the budget to go below 1 because we'll exit polling */
1404         budget /= (q_vector->rxr_count ?: 1);
1405         budget = max(budget, 1);
1406         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1407         for (i = 0; i < q_vector->rxr_count; i++) {
1408                 ring = &(adapter->rx_ring[r_idx]);
1409 #ifdef CONFIG_IXGBE_DCA
1410                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1411                         ixgbe_update_rx_dca(adapter, ring);
1412 #endif
1413                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1414                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1415                                       r_idx + 1);
1416         }
1417
1418         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1419         ring = &(adapter->rx_ring[r_idx]);
1420         /* If all Rx work done, exit the polling mode */
1421         if (work_done < budget) {
1422                 napi_complete(napi);
1423                 if (adapter->rx_itr_setting & 1)
1424                         ixgbe_set_itr_msix(q_vector);
1425                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1426                         ixgbe_irq_enable_queues(adapter,
1427                                                 ((u64)1 << q_vector->v_idx));
1428                 return 0;
1429         }
1430
1431         return work_done;
1432 }
1433
1434 /**
1435  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1436  * @napi: napi struct with our devices info in it
1437  * @budget: amount of work driver is allowed to do this pass, in packets
1438  *
1439  * This function is optimized for cleaning one queue only on a single
1440  * q_vector!!!
1441  **/
1442 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1443 {
1444         struct ixgbe_q_vector *q_vector =
1445                                container_of(napi, struct ixgbe_q_vector, napi);
1446         struct ixgbe_adapter *adapter = q_vector->adapter;
1447         struct ixgbe_ring *tx_ring = NULL;
1448         int work_done = 0;
1449         long r_idx;
1450
1451         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1452         tx_ring = &(adapter->tx_ring[r_idx]);
1453 #ifdef CONFIG_IXGBE_DCA
1454         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1455                 ixgbe_update_tx_dca(adapter, tx_ring);
1456 #endif
1457
1458         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1459                 work_done = budget;
1460
1461         /* If all Tx work done, exit the polling mode */
1462         if (work_done < budget) {
1463                 napi_complete(napi);
1464                 if (adapter->tx_itr_setting & 1)
1465                         ixgbe_set_itr_msix(q_vector);
1466                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1467                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1468         }
1469
1470         return work_done;
1471 }
1472
1473 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1474                                      int r_idx)
1475 {
1476         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1477
1478         set_bit(r_idx, q_vector->rxr_idx);
1479         q_vector->rxr_count++;
1480 }
1481
1482 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1483                                      int t_idx)
1484 {
1485         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1486
1487         set_bit(t_idx, q_vector->txr_idx);
1488         q_vector->txr_count++;
1489 }
1490
1491 /**
1492  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1493  * @adapter: board private structure to initialize
1494  * @vectors: allotted vector count for descriptor rings
1495  *
1496  * This function maps descriptor rings to the queue-specific vectors
1497  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1498  * one vector per ring/queue, but on a constrained vector budget, we
1499  * group the rings as "efficiently" as possible.  You would add new
1500  * mapping configurations in here.
1501  **/
1502 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1503                                       int vectors)
1504 {
1505         int v_start = 0;
1506         int rxr_idx = 0, txr_idx = 0;
1507         int rxr_remaining = adapter->num_rx_queues;
1508         int txr_remaining = adapter->num_tx_queues;
1509         int i, j;
1510         int rqpv, tqpv;
1511         int err = 0;
1512
1513         /* No mapping required if MSI-X is disabled. */
1514         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1515                 goto out;
1516
1517         /*
1518          * The ideal configuration...
1519          * We have enough vectors to map one per queue.
1520          */
1521         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1522                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1523                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1524
1525                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1526                         map_vector_to_txq(adapter, v_start, txr_idx);
1527
1528                 goto out;
1529         }
1530
1531         /*
1532          * If we don't have enough vectors for a 1-to-1
1533          * mapping, we'll have to group them so there are
1534          * multiple queues per vector.
1535          */
1536         /* Re-adjusting *qpv takes care of the remainder. */
1537         for (i = v_start; i < vectors; i++) {
1538                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1539                 for (j = 0; j < rqpv; j++) {
1540                         map_vector_to_rxq(adapter, i, rxr_idx);
1541                         rxr_idx++;
1542                         rxr_remaining--;
1543                 }
1544         }
1545         for (i = v_start; i < vectors; i++) {
1546                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1547                 for (j = 0; j < tqpv; j++) {
1548                         map_vector_to_txq(adapter, i, txr_idx);
1549                         txr_idx++;
1550                         txr_remaining--;
1551                 }
1552         }
1553
1554 out:
1555         return err;
1556 }
1557
1558 /**
1559  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1560  * @adapter: board private structure
1561  *
1562  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1563  * interrupts from the kernel.
1564  **/
1565 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1566 {
1567         struct net_device *netdev = adapter->netdev;
1568         irqreturn_t (*handler)(int, void *);
1569         int i, vector, q_vectors, err;
1570         int ri=0, ti=0;
1571
1572         /* Decrement for Other and TCP Timer vectors */
1573         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1574
1575         /* Map the Tx/Rx rings to the vectors we were allotted. */
1576         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1577         if (err)
1578                 goto out;
1579
1580 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1581                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1582                          &ixgbe_msix_clean_many)
1583         for (vector = 0; vector < q_vectors; vector++) {
1584                 handler = SET_HANDLER(adapter->q_vector[vector]);
1585
1586                 if(handler == &ixgbe_msix_clean_rx) {
1587                         sprintf(adapter->name[vector], "%s-%s-%d",
1588                                 netdev->name, "rx", ri++);
1589                 }
1590                 else if(handler == &ixgbe_msix_clean_tx) {
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "tx", ti++);
1593                 }
1594                 else
1595                         sprintf(adapter->name[vector], "%s-%s-%d",
1596                                 netdev->name, "TxRx", vector);
1597
1598                 err = request_irq(adapter->msix_entries[vector].vector,
1599                                   handler, 0, adapter->name[vector],
1600                                   adapter->q_vector[vector]);
1601                 if (err) {
1602                         DPRINTK(PROBE, ERR,
1603                                 "request_irq failed for MSIX interrupt "
1604                                 "Error: %d\n", err);
1605                         goto free_queue_irqs;
1606                 }
1607         }
1608
1609         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1610         err = request_irq(adapter->msix_entries[vector].vector,
1611                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1612         if (err) {
1613                 DPRINTK(PROBE, ERR,
1614                         "request_irq for msix_lsc failed: %d\n", err);
1615                 goto free_queue_irqs;
1616         }
1617
1618         return 0;
1619
1620 free_queue_irqs:
1621         for (i = vector - 1; i >= 0; i--)
1622                 free_irq(adapter->msix_entries[--vector].vector,
1623                          adapter->q_vector[i]);
1624         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1625         pci_disable_msix(adapter->pdev);
1626         kfree(adapter->msix_entries);
1627         adapter->msix_entries = NULL;
1628 out:
1629         return err;
1630 }
1631
1632 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1633 {
1634         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1635         u8 current_itr;
1636         u32 new_itr = q_vector->eitr;
1637         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1638         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1639
1640         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1641                                             q_vector->tx_itr,
1642                                             tx_ring->total_packets,
1643                                             tx_ring->total_bytes);
1644         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1645                                             q_vector->rx_itr,
1646                                             rx_ring->total_packets,
1647                                             rx_ring->total_bytes);
1648
1649         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1650
1651         switch (current_itr) {
1652         /* counts and packets in update_itr are dependent on these numbers */
1653         case lowest_latency:
1654                 new_itr = 100000;
1655                 break;
1656         case low_latency:
1657                 new_itr = 20000; /* aka hwitr = ~200 */
1658                 break;
1659         case bulk_latency:
1660                 new_itr = 8000;
1661                 break;
1662         default:
1663                 break;
1664         }
1665
1666         if (new_itr != q_vector->eitr) {
1667                 /* do an exponential smoothing */
1668                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1669
1670                 /* save the algorithm value here, not the smoothed one */
1671                 q_vector->eitr = new_itr;
1672
1673                 ixgbe_write_eitr(q_vector);
1674         }
1675
1676         return;
1677 }
1678
1679 /**
1680  * ixgbe_irq_enable - Enable default interrupt generation settings
1681  * @adapter: board private structure
1682  **/
1683 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1684 {
1685         u32 mask;
1686
1687         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1688         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1689                 mask |= IXGBE_EIMS_GPI_SDP1;
1690         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1691                 mask |= IXGBE_EIMS_ECC;
1692                 mask |= IXGBE_EIMS_GPI_SDP1;
1693                 mask |= IXGBE_EIMS_GPI_SDP2;
1694         }
1695         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1696             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1697                 mask |= IXGBE_EIMS_FLOW_DIR;
1698
1699         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1700         ixgbe_irq_enable_queues(adapter, ~0);
1701         IXGBE_WRITE_FLUSH(&adapter->hw);
1702 }
1703
1704 /**
1705  * ixgbe_intr - legacy mode Interrupt Handler
1706  * @irq: interrupt number
1707  * @data: pointer to a network interface device structure
1708  **/
1709 static irqreturn_t ixgbe_intr(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1715         u32 eicr;
1716
1717         /*
1718          * Workaround for silicon errata.  Mask the interrupts
1719          * before the read of EICR.
1720          */
1721         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1722
1723         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1724          * therefore no explict interrupt disable is necessary */
1725         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1726         if (!eicr) {
1727                 /* shared interrupt alert!
1728                  * make sure interrupts are enabled because the read will
1729                  * have disabled interrupts due to EIAM */
1730                 ixgbe_irq_enable(adapter);
1731                 return IRQ_NONE;        /* Not our interrupt */
1732         }
1733
1734         if (eicr & IXGBE_EICR_LSC)
1735                 ixgbe_check_lsc(adapter);
1736
1737         if (hw->mac.type == ixgbe_mac_82599EB)
1738                 ixgbe_check_sfp_event(adapter, eicr);
1739
1740         ixgbe_check_fan_failure(adapter, eicr);
1741
1742         if (napi_schedule_prep(&(q_vector->napi))) {
1743                 adapter->tx_ring[0].total_packets = 0;
1744                 adapter->tx_ring[0].total_bytes = 0;
1745                 adapter->rx_ring[0].total_packets = 0;
1746                 adapter->rx_ring[0].total_bytes = 0;
1747                 /* would disable interrupts here but EIAM disabled it */
1748                 __napi_schedule(&(q_vector->napi));
1749         }
1750
1751         return IRQ_HANDLED;
1752 }
1753
1754 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1755 {
1756         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1757
1758         for (i = 0; i < q_vectors; i++) {
1759                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1760                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1761                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1762                 q_vector->rxr_count = 0;
1763                 q_vector->txr_count = 0;
1764         }
1765 }
1766
1767 /**
1768  * ixgbe_request_irq - initialize interrupts
1769  * @adapter: board private structure
1770  *
1771  * Attempts to configure interrupts using the best available
1772  * capabilities of the hardware and kernel.
1773  **/
1774 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1775 {
1776         struct net_device *netdev = adapter->netdev;
1777         int err;
1778
1779         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1780                 err = ixgbe_request_msix_irqs(adapter);
1781         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1782                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1783                                   netdev->name, netdev);
1784         } else {
1785                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1786                                   netdev->name, netdev);
1787         }
1788
1789         if (err)
1790                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1791
1792         return err;
1793 }
1794
1795 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1796 {
1797         struct net_device *netdev = adapter->netdev;
1798
1799         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1800                 int i, q_vectors;
1801
1802                 q_vectors = adapter->num_msix_vectors;
1803
1804                 i = q_vectors - 1;
1805                 free_irq(adapter->msix_entries[i].vector, netdev);
1806
1807                 i--;
1808                 for (; i >= 0; i--) {
1809                         free_irq(adapter->msix_entries[i].vector,
1810                                  adapter->q_vector[i]);
1811                 }
1812
1813                 ixgbe_reset_q_vectors(adapter);
1814         } else {
1815                 free_irq(adapter->pdev->irq, netdev);
1816         }
1817 }
1818
1819 /**
1820  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1821  * @adapter: board private structure
1822  **/
1823 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1824 {
1825         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1827         } else {
1828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1829                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1831         }
1832         IXGBE_WRITE_FLUSH(&adapter->hw);
1833         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1834                 int i;
1835                 for (i = 0; i < adapter->num_msix_vectors; i++)
1836                         synchronize_irq(adapter->msix_entries[i].vector);
1837         } else {
1838                 synchronize_irq(adapter->pdev->irq);
1839         }
1840 }
1841
1842 /**
1843  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1844  *
1845  **/
1846 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1847 {
1848         struct ixgbe_hw *hw = &adapter->hw;
1849
1850         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1851                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1852
1853         ixgbe_set_ivar(adapter, 0, 0, 0);
1854         ixgbe_set_ivar(adapter, 1, 0, 0);
1855
1856         map_vector_to_rxq(adapter, 0, 0);
1857         map_vector_to_txq(adapter, 0, 0);
1858
1859         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1860 }
1861
1862 /**
1863  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1864  * @adapter: board private structure
1865  *
1866  * Configure the Tx unit of the MAC after a reset.
1867  **/
1868 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1869 {
1870         u64 tdba;
1871         struct ixgbe_hw *hw = &adapter->hw;
1872         u32 i, j, tdlen, txctrl;
1873
1874         /* Setup the HW Tx Head and Tail descriptor pointers */
1875         for (i = 0; i < adapter->num_tx_queues; i++) {
1876                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1877                 j = ring->reg_idx;
1878                 tdba = ring->dma;
1879                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1880                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1881                                 (tdba & DMA_BIT_MASK(32)));
1882                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1883                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1885                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1886                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1887                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1888                 /*
1889                  * Disable Tx Head Writeback RO bit, since this hoses
1890                  * bookkeeping if things aren't delivered in order.
1891                  */
1892                 switch (hw->mac.type) {
1893                 case ixgbe_mac_82598EB:
1894                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1895                         break;
1896                 case ixgbe_mac_82599EB:
1897                 default:
1898                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1899                         break;
1900                 }
1901                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1902                 switch (hw->mac.type) {
1903                 case ixgbe_mac_82598EB:
1904                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1905                         break;
1906                 case ixgbe_mac_82599EB:
1907                 default:
1908                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1909                         break;
1910                 }
1911         }
1912         if (hw->mac.type == ixgbe_mac_82599EB) {
1913                 /* We enable 8 traffic classes, DCB only */
1914                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1915                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1916                                         IXGBE_MTQC_8TC_8TQ));
1917         }
1918 }
1919
1920 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1921
1922 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1923                                    struct ixgbe_ring *rx_ring)
1924 {
1925         u32 srrctl;
1926         int index;
1927         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1928
1929         index = rx_ring->reg_idx;
1930         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1931                 unsigned long mask;
1932                 mask = (unsigned long) feature[RING_F_RSS].mask;
1933                 index = index & mask;
1934         }
1935         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1936
1937         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1938         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1939
1940         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1941                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1942
1943         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1944 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1945                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1946 #else
1947                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1948 #endif
1949                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1950         } else {
1951                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1952                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1953                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1954         }
1955
1956         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1957 }
1958
1959 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1960 {
1961         u32 mrqc = 0;
1962         int mask;
1963
1964         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1965                 return mrqc;
1966
1967         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1968 #ifdef CONFIG_IXGBE_DCB
1969                                  | IXGBE_FLAG_DCB_ENABLED
1970 #endif
1971                                 );
1972
1973         switch (mask) {
1974         case (IXGBE_FLAG_RSS_ENABLED):
1975                 mrqc = IXGBE_MRQC_RSSEN;
1976                 break;
1977 #ifdef CONFIG_IXGBE_DCB
1978         case (IXGBE_FLAG_DCB_ENABLED):
1979                 mrqc = IXGBE_MRQC_RT8TCEN;
1980                 break;
1981 #endif /* CONFIG_IXGBE_DCB */
1982         default:
1983                 break;
1984         }
1985
1986         return mrqc;
1987 }
1988
1989 /**
1990  * ixgbe_configure_rscctl - enable RSC for the indicated ring
1991  * @adapter:    address of board private structure
1992  * @index:      index of ring to set
1993  * @rx_buf_len: rx buffer length
1994  **/
1995 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
1996                                    int rx_buf_len)
1997 {
1998         struct ixgbe_ring *rx_ring;
1999         struct ixgbe_hw *hw = &adapter->hw;
2000         int j;
2001         u32 rscctrl;
2002
2003         rx_ring = &adapter->rx_ring[index];
2004         j = rx_ring->reg_idx;
2005         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2006         rscctrl |= IXGBE_RSCCTL_RSCEN;
2007         /*
2008          * we must limit the number of descriptors so that the
2009          * total size of max desc * buf_len is not greater
2010          * than 65535
2011          */
2012         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2013 #if (MAX_SKB_FRAGS > 16)
2014                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2015 #elif (MAX_SKB_FRAGS > 8)
2016                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2017 #elif (MAX_SKB_FRAGS > 4)
2018                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2019 #else
2020                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2021 #endif
2022         } else {
2023                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2024                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2025                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2026                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2027                 else
2028                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2029         }
2030         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2031 }
2032
2033 /**
2034  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2035  * @adapter: board private structure
2036  *
2037  * Configure the Rx unit of the MAC after a reset.
2038  **/
2039 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2040 {
2041         u64 rdba;
2042         struct ixgbe_hw *hw = &adapter->hw;
2043         struct ixgbe_ring *rx_ring;
2044         struct net_device *netdev = adapter->netdev;
2045         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2046         int i, j;
2047         u32 rdlen, rxctrl, rxcsum;
2048         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2049                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2050                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2051         u32 fctrl, hlreg0;
2052         u32 reta = 0, mrqc = 0;
2053         u32 rdrxctl;
2054         int rx_buf_len;
2055
2056         /* Decide whether to use packet split mode or not */
2057         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2058
2059         /* Set the RX buffer length according to the mode */
2060         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2061                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2062                 if (hw->mac.type == ixgbe_mac_82599EB) {
2063                         /* PSRTYPE must be initialized in 82599 */
2064                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2065                                       IXGBE_PSRTYPE_UDPHDR |
2066                                       IXGBE_PSRTYPE_IPV4HDR |
2067                                       IXGBE_PSRTYPE_IPV6HDR |
2068                                       IXGBE_PSRTYPE_L2HDR;
2069                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2070                 }
2071         } else {
2072                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2073                     (netdev->mtu <= ETH_DATA_LEN))
2074                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2075                 else
2076                         rx_buf_len = ALIGN(max_frame, 1024);
2077         }
2078
2079         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2080         fctrl |= IXGBE_FCTRL_BAM;
2081         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2082         fctrl |= IXGBE_FCTRL_PMCF;
2083         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2084
2085         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2086         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2087                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2088         else
2089                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2090 #ifdef IXGBE_FCOE
2091         if (netdev->features & NETIF_F_FCOE_MTU)
2092                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2093 #endif
2094         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2095
2096         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2097         /* disable receives while setting up the descriptors */
2098         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2099         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2100
2101         /*
2102          * Setup the HW Rx Head and Tail Descriptor Pointers and
2103          * the Base and Length of the Rx Descriptor Ring
2104          */
2105         for (i = 0; i < adapter->num_rx_queues; i++) {
2106                 rx_ring = &adapter->rx_ring[i];
2107                 rdba = rx_ring->dma;
2108                 j = rx_ring->reg_idx;
2109                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2110                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2111                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2112                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2113                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2114                 rx_ring->head = IXGBE_RDH(j);
2115                 rx_ring->tail = IXGBE_RDT(j);
2116                 rx_ring->rx_buf_len = rx_buf_len;
2117
2118                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2119                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2120                 else
2121                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2122
2123 #ifdef IXGBE_FCOE
2124                 if (netdev->features & NETIF_F_FCOE_MTU) {
2125                         struct ixgbe_ring_feature *f;
2126                         f = &adapter->ring_feature[RING_F_FCOE];
2127                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2128                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2129                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2130                                         rx_ring->rx_buf_len =
2131                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2132                         }
2133                 }
2134
2135 #endif /* IXGBE_FCOE */
2136                 ixgbe_configure_srrctl(adapter, rx_ring);
2137         }
2138
2139         if (hw->mac.type == ixgbe_mac_82598EB) {
2140                 /*
2141                  * For VMDq support of different descriptor types or
2142                  * buffer sizes through the use of multiple SRRCTL
2143                  * registers, RDRXCTL.MVMEN must be set to 1
2144                  *
2145                  * also, the manual doesn't mention it clearly but DCA hints
2146                  * will only use queue 0's tags unless this bit is set.  Side
2147                  * effects of setting this bit are only that SRRCTL must be
2148                  * fully programmed [0..15]
2149                  */
2150                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2151                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2152                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2153         }
2154
2155         /* Program MRQC for the distribution of queues */
2156         mrqc = ixgbe_setup_mrqc(adapter);
2157
2158         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2159                 /* Fill out redirection table */
2160                 for (i = 0, j = 0; i < 128; i++, j++) {
2161                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2162                                 j = 0;
2163                         /* reta = 4-byte sliding window of
2164                          * 0x00..(indices-1)(indices-1)00..etc. */
2165                         reta = (reta << 8) | (j * 0x11);
2166                         if ((i & 3) == 3)
2167                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2168                 }
2169
2170                 /* Fill out hash function seeds */
2171                 for (i = 0; i < 10; i++)
2172                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2173
2174                 if (hw->mac.type == ixgbe_mac_82598EB)
2175                         mrqc |= IXGBE_MRQC_RSSEN;
2176                     /* Perform hash on these packet types */
2177                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2178                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2179                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2180                       | IXGBE_MRQC_RSS_FIELD_IPV6
2181                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2182                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2183         }
2184         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2185
2186         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2187
2188         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2189             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2190                 /* Disable indicating checksum in descriptor, enables
2191                  * RSS hash */
2192                 rxcsum |= IXGBE_RXCSUM_PCSD;
2193         }
2194         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2195                 /* Enable IPv4 payload checksum for UDP fragments
2196                  * if PCSD is not set */
2197                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2198         }
2199
2200         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2201
2202         if (hw->mac.type == ixgbe_mac_82599EB) {
2203                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2204                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2205                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2206                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2207         }
2208
2209         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2210                 /* Enable 82599 HW-RSC */
2211                 for (i = 0; i < adapter->num_rx_queues; i++)
2212                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2213
2214                 /* Disable RSC for ACK packets */
2215                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2216                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2217         }
2218 }
2219
2220 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2221 {
2222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2223         struct ixgbe_hw *hw = &adapter->hw;
2224
2225         /* add VID to filter table */
2226         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2227 }
2228
2229 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2230 {
2231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2232         struct ixgbe_hw *hw = &adapter->hw;
2233
2234         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2235                 ixgbe_irq_disable(adapter);
2236
2237         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2238
2239         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2240                 ixgbe_irq_enable(adapter);
2241
2242         /* remove VID from filter table */
2243         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2244 }
2245
2246 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2247                                    struct vlan_group *grp)
2248 {
2249         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2250         u32 ctrl;
2251         int i, j;
2252
2253         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2254                 ixgbe_irq_disable(adapter);
2255         adapter->vlgrp = grp;
2256
2257         /*
2258          * For a DCB driver, always enable VLAN tag stripping so we can
2259          * still receive traffic from a DCB-enabled host even if we're
2260          * not in DCB mode.
2261          */
2262         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2263         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2264                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2265                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2266                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2267         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2268                 ctrl |= IXGBE_VLNCTRL_VFE;
2269                 /* enable VLAN tag insert/strip */
2270                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2271                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2272                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2273                 for (i = 0; i < adapter->num_rx_queues; i++) {
2274                         j = adapter->rx_ring[i].reg_idx;
2275                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2276                         ctrl |= IXGBE_RXDCTL_VME;
2277                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2278                 }
2279         }
2280         ixgbe_vlan_rx_add_vid(netdev, 0);
2281
2282         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2283                 ixgbe_irq_enable(adapter);
2284 }
2285
2286 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2287 {
2288         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2289
2290         if (adapter->vlgrp) {
2291                 u16 vid;
2292                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2293                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2294                                 continue;
2295                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2296                 }
2297         }
2298 }
2299
2300 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2301 {
2302         struct dev_mc_list *mc_ptr;
2303         u8 *addr = *mc_addr_ptr;
2304         *vmdq = 0;
2305
2306         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2307         if (mc_ptr->next)
2308                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2309         else
2310                 *mc_addr_ptr = NULL;
2311
2312         return addr;
2313 }
2314
2315 /**
2316  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2317  * @netdev: network interface device structure
2318  *
2319  * The set_rx_method entry point is called whenever the unicast/multicast
2320  * address list or the network interface flags are updated.  This routine is
2321  * responsible for configuring the hardware for proper unicast, multicast and
2322  * promiscuous mode.
2323  **/
2324 static void ixgbe_set_rx_mode(struct net_device *netdev)
2325 {
2326         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2327         struct ixgbe_hw *hw = &adapter->hw;
2328         u32 fctrl, vlnctrl;
2329         u8 *addr_list = NULL;
2330         int addr_count = 0;
2331
2332         /* Check for Promiscuous and All Multicast modes */
2333
2334         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2335         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2336
2337         if (netdev->flags & IFF_PROMISC) {
2338                 hw->addr_ctrl.user_set_promisc = 1;
2339                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2340                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2341         } else {
2342                 if (netdev->flags & IFF_ALLMULTI) {
2343                         fctrl |= IXGBE_FCTRL_MPE;
2344                         fctrl &= ~IXGBE_FCTRL_UPE;
2345                 } else {
2346                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2347                 }
2348                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2349                 hw->addr_ctrl.user_set_promisc = 0;
2350         }
2351
2352         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2353         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2354
2355         /* reprogram secondary unicast list */
2356         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2357
2358         /* reprogram multicast list */
2359         addr_count = netdev->mc_count;
2360         if (addr_count)
2361                 addr_list = netdev->mc_list->dmi_addr;
2362         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2363                                         ixgbe_addr_list_itr);
2364 }
2365
2366 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2367 {
2368         int q_idx;
2369         struct ixgbe_q_vector *q_vector;
2370         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2371
2372         /* legacy and MSI only use one vector */
2373         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2374                 q_vectors = 1;
2375
2376         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2377                 struct napi_struct *napi;
2378                 q_vector = adapter->q_vector[q_idx];
2379                 napi = &q_vector->napi;
2380                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2381                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2382                                 if (q_vector->txr_count == 1)
2383                                         napi->poll = &ixgbe_clean_txonly;
2384                                 else if (q_vector->rxr_count == 1)
2385                                         napi->poll = &ixgbe_clean_rxonly;
2386                         }
2387                 }
2388
2389                 napi_enable(napi);
2390         }
2391 }
2392
2393 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2394 {
2395         int q_idx;
2396         struct ixgbe_q_vector *q_vector;
2397         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2398
2399         /* legacy and MSI only use one vector */
2400         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2401                 q_vectors = 1;
2402
2403         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2404                 q_vector = adapter->q_vector[q_idx];
2405                 napi_disable(&q_vector->napi);
2406         }
2407 }
2408
2409 #ifdef CONFIG_IXGBE_DCB
2410 /*
2411  * ixgbe_configure_dcb - Configure DCB hardware
2412  * @adapter: ixgbe adapter struct
2413  *
2414  * This is called by the driver on open to configure the DCB hardware.
2415  * This is also called by the gennetlink interface when reconfiguring
2416  * the DCB state.
2417  */
2418 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2419 {
2420         struct ixgbe_hw *hw = &adapter->hw;
2421         u32 txdctl, vlnctrl;
2422         int i, j;
2423
2424         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2425         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2426         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2427
2428         /* reconfigure the hardware */
2429         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2430
2431         for (i = 0; i < adapter->num_tx_queues; i++) {
2432                 j = adapter->tx_ring[i].reg_idx;
2433                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2434                 /* PThresh workaround for Tx hang with DFP enabled. */
2435                 txdctl |= 32;
2436                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2437         }
2438         /* Enable VLAN tag insert/strip */
2439         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2440         if (hw->mac.type == ixgbe_mac_82598EB) {
2441                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2442                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2443                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2444         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2445                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2446                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2447                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2448                 for (i = 0; i < adapter->num_rx_queues; i++) {
2449                         j = adapter->rx_ring[i].reg_idx;
2450                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2451                         vlnctrl |= IXGBE_RXDCTL_VME;
2452                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2453                 }
2454         }
2455         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2456 }
2457
2458 #endif
2459 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2460 {
2461         struct net_device *netdev = adapter->netdev;
2462         struct ixgbe_hw *hw = &adapter->hw;
2463         int i;
2464
2465         ixgbe_set_rx_mode(netdev);
2466
2467         ixgbe_restore_vlan(adapter);
2468 #ifdef CONFIG_IXGBE_DCB
2469         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2470                 netif_set_gso_max_size(netdev, 32768);
2471                 ixgbe_configure_dcb(adapter);
2472         } else {
2473                 netif_set_gso_max_size(netdev, 65536);
2474         }
2475 #else
2476         netif_set_gso_max_size(netdev, 65536);
2477 #endif
2478
2479 #ifdef IXGBE_FCOE
2480         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2481                 ixgbe_configure_fcoe(adapter);
2482
2483 #endif /* IXGBE_FCOE */
2484         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2485                 for (i = 0; i < adapter->num_tx_queues; i++)
2486                         adapter->tx_ring[i].atr_sample_rate =
2487                                                        adapter->atr_sample_rate;
2488                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2489         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2490                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2491         }
2492
2493         ixgbe_configure_tx(adapter);
2494         ixgbe_configure_rx(adapter);
2495         for (i = 0; i < adapter->num_rx_queues; i++)
2496                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2497                                        (adapter->rx_ring[i].count - 1));
2498 }
2499
2500 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2501 {
2502         switch (hw->phy.type) {
2503         case ixgbe_phy_sfp_avago:
2504         case ixgbe_phy_sfp_ftl:
2505         case ixgbe_phy_sfp_intel:
2506         case ixgbe_phy_sfp_unknown:
2507         case ixgbe_phy_tw_tyco:
2508         case ixgbe_phy_tw_unknown:
2509                 return true;
2510         default:
2511                 return false;
2512         }
2513 }
2514
2515 /**
2516  * ixgbe_sfp_link_config - set up SFP+ link
2517  * @adapter: pointer to private adapter struct
2518  **/
2519 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2520 {
2521         struct ixgbe_hw *hw = &adapter->hw;
2522
2523                 if (hw->phy.multispeed_fiber) {
2524                         /*
2525                          * In multispeed fiber setups, the device may not have
2526                          * had a physical connection when the driver loaded.
2527                          * If that's the case, the initial link configuration
2528                          * couldn't get the MAC into 10G or 1G mode, so we'll
2529                          * never have a link status change interrupt fire.
2530                          * We need to try and force an autonegotiation
2531                          * session, then bring up link.
2532                          */
2533                         hw->mac.ops.setup_sfp(hw);
2534                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2535                                 schedule_work(&adapter->multispeed_fiber_task);
2536                 } else {
2537                         /*
2538                          * Direct Attach Cu and non-multispeed fiber modules
2539                          * still need to be configured properly prior to
2540                          * attempting link.
2541                          */
2542                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2543                                 schedule_work(&adapter->sfp_config_module_task);
2544                 }
2545 }
2546
2547 /**
2548  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2549  * @hw: pointer to private hardware struct
2550  *
2551  * Returns 0 on success, negative on failure
2552  **/
2553 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2554 {
2555         u32 autoneg;
2556         bool negotiation, link_up = false;
2557         u32 ret = IXGBE_ERR_LINK_SETUP;
2558
2559         if (hw->mac.ops.check_link)
2560                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2561
2562         if (ret)
2563                 goto link_cfg_out;
2564
2565         if (hw->mac.ops.get_link_capabilities)
2566                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2567         if (ret)
2568                 goto link_cfg_out;
2569
2570         if (hw->mac.ops.setup_link)
2571                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2572 link_cfg_out:
2573         return ret;
2574 }
2575
2576 #define IXGBE_MAX_RX_DESC_POLL 10
2577 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2578                                               int rxr)
2579 {
2580         int j = adapter->rx_ring[rxr].reg_idx;
2581         int k;
2582
2583         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2584                 if (IXGBE_READ_REG(&adapter->hw,
2585                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2586                         break;
2587                 else
2588                         msleep(1);
2589         }
2590         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2591                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2592                         "not set within the polling period\n", rxr);
2593         }
2594         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2595                               (adapter->rx_ring[rxr].count - 1));
2596 }
2597
2598 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2599 {
2600         struct net_device *netdev = adapter->netdev;
2601         struct ixgbe_hw *hw = &adapter->hw;
2602         int i, j = 0;
2603         int num_rx_rings = adapter->num_rx_queues;
2604         int err;
2605         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2606         u32 txdctl, rxdctl, mhadd;
2607         u32 dmatxctl;
2608         u32 gpie;
2609
2610         ixgbe_get_hw_control(adapter);
2611
2612         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2613             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2614                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2615                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2616                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2617                 } else {
2618                         /* MSI only */
2619                         gpie = 0;
2620                 }
2621                 /* XXX: to interrupt immediately for EICS writes, enable this */
2622                 /* gpie |= IXGBE_GPIE_EIMEN; */
2623                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2624         }
2625
2626         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2627                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2628                  * specifically only auto mask tx and rx interrupts */
2629                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2630         }
2631
2632         /* Enable fan failure interrupt if media type is copper */
2633         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2634                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2635                 gpie |= IXGBE_SDP1_GPIEN;
2636                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2637         }
2638
2639         if (hw->mac.type == ixgbe_mac_82599EB) {
2640                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2641                 gpie |= IXGBE_SDP1_GPIEN;
2642                 gpie |= IXGBE_SDP2_GPIEN;
2643                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2644         }
2645
2646 #ifdef IXGBE_FCOE
2647         /* adjust max frame to be able to do baby jumbo for FCoE */
2648         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2649             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2650                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2651
2652 #endif /* IXGBE_FCOE */
2653         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2654         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2655                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2656                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2657
2658                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2659         }
2660
2661         for (i = 0; i < adapter->num_tx_queues; i++) {
2662                 j = adapter->tx_ring[i].reg_idx;
2663                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2664                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2665                 txdctl |= (8 << 16);
2666                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2667         }
2668
2669         if (hw->mac.type == ixgbe_mac_82599EB) {
2670                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2671                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2672                 dmatxctl |= IXGBE_DMATXCTL_TE;
2673                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2674         }
2675         for (i = 0; i < adapter->num_tx_queues; i++) {
2676                 j = adapter->tx_ring[i].reg_idx;
2677                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2678                 txdctl |= IXGBE_TXDCTL_ENABLE;
2679                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2680         }
2681
2682         for (i = 0; i < num_rx_rings; i++) {
2683                 j = adapter->rx_ring[i].reg_idx;
2684                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2685                 /* enable PTHRESH=32 descriptors (half the internal cache)
2686                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2687                  * this also removes a pesky rx_no_buffer_count increment */
2688                 rxdctl |= 0x0020;
2689                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2691                 if (hw->mac.type == ixgbe_mac_82599EB)
2692                         ixgbe_rx_desc_queue_enable(adapter, i);
2693         }
2694         /* enable all receives */
2695         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2696         if (hw->mac.type == ixgbe_mac_82598EB)
2697                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2698         else
2699                 rxdctl |= IXGBE_RXCTRL_RXEN;
2700         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2701
2702         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2703                 ixgbe_configure_msix(adapter);
2704         else
2705                 ixgbe_configure_msi_and_legacy(adapter);
2706
2707         clear_bit(__IXGBE_DOWN, &adapter->state);
2708         ixgbe_napi_enable_all(adapter);
2709
2710         /* clear any pending interrupts, may auto mask */
2711         IXGBE_READ_REG(hw, IXGBE_EICR);
2712
2713         ixgbe_irq_enable(adapter);
2714
2715         /*
2716          * If this adapter has a fan, check to see if we had a failure
2717          * before we enabled the interrupt.
2718          */
2719         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2720                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2721                 if (esdp & IXGBE_ESDP_SDP1)
2722                         DPRINTK(DRV, CRIT,
2723                                 "Fan has stopped, replace the adapter\n");
2724         }
2725
2726         /*
2727          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2728          * arrived before interrupts were enabled but after probe.  Such
2729          * devices wouldn't have their type identified yet. We need to
2730          * kick off the SFP+ module setup first, then try to bring up link.
2731          * If we're not hot-pluggable SFP+, we just need to configure link
2732          * and bring it up.
2733          */
2734         if (hw->phy.type == ixgbe_phy_unknown) {
2735                 err = hw->phy.ops.identify(hw);
2736                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2737                         /*
2738                          * Take the device down and schedule the sfp tasklet
2739                          * which will unregister_netdev and log it.
2740                          */
2741                         ixgbe_down(adapter);
2742                         schedule_work(&adapter->sfp_config_module_task);
2743                         return err;
2744                 }
2745         }
2746
2747         if (ixgbe_is_sfp(hw)) {
2748                 ixgbe_sfp_link_config(adapter);
2749         } else {
2750                 err = ixgbe_non_sfp_link_config(hw);
2751                 if (err)
2752                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2753         }
2754
2755         for (i = 0; i < adapter->num_tx_queues; i++)
2756                 set_bit(__IXGBE_FDIR_INIT_DONE,
2757                         &(adapter->tx_ring[i].reinit_state));
2758
2759         /* enable transmits */
2760         netif_tx_start_all_queues(netdev);
2761
2762         /* bring the link up in the watchdog, this could race with our first
2763          * link up interrupt but shouldn't be a problem */
2764         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2765         adapter->link_check_timeout = jiffies;
2766         mod_timer(&adapter->watchdog_timer, jiffies);
2767         return 0;
2768 }
2769
2770 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2771 {
2772         WARN_ON(in_interrupt());
2773         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2774                 msleep(1);
2775         ixgbe_down(adapter);
2776         ixgbe_up(adapter);
2777         clear_bit(__IXGBE_RESETTING, &adapter->state);
2778 }
2779
2780 int ixgbe_up(struct ixgbe_adapter *adapter)
2781 {
2782         /* hardware has been reset, we need to reload some things */
2783         ixgbe_configure(adapter);
2784
2785         return ixgbe_up_complete(adapter);
2786 }
2787
2788 void ixgbe_reset(struct ixgbe_adapter *adapter)
2789 {
2790         struct ixgbe_hw *hw = &adapter->hw;
2791         int err;
2792
2793         err = hw->mac.ops.init_hw(hw);
2794         switch (err) {
2795         case 0:
2796         case IXGBE_ERR_SFP_NOT_PRESENT:
2797                 break;
2798         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2799                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2800                 break;
2801         case IXGBE_ERR_EEPROM_VERSION:
2802                 /* We are running on a pre-production device, log a warning */
2803                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2804                          "adapter/LOM.  Please be aware there may be issues "
2805                          "associated with your hardware.  If you are "
2806                          "experiencing problems please contact your Intel or "
2807                          "hardware representative who provided you with this "
2808                          "hardware.\n");
2809                 break;
2810         default:
2811                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2812         }
2813
2814         /* reprogram the RAR[0] in case user changed it. */
2815         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2816 }
2817
2818 /**
2819  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2820  * @adapter: board private structure
2821  * @rx_ring: ring to free buffers from
2822  **/
2823 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2824                                 struct ixgbe_ring *rx_ring)
2825 {
2826         struct pci_dev *pdev = adapter->pdev;
2827         unsigned long size;
2828         unsigned int i;
2829
2830         /* Free all the Rx ring sk_buffs */
2831
2832         for (i = 0; i < rx_ring->count; i++) {
2833                 struct ixgbe_rx_buffer *rx_buffer_info;
2834
2835                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2836                 if (rx_buffer_info->dma) {
2837                         pci_unmap_single(pdev, rx_buffer_info->dma,
2838                                          rx_ring->rx_buf_len,
2839                                          PCI_DMA_FROMDEVICE);
2840                         rx_buffer_info->dma = 0;
2841                 }
2842                 if (rx_buffer_info->skb) {
2843                         struct sk_buff *skb = rx_buffer_info->skb;
2844                         rx_buffer_info->skb = NULL;
2845                         do {
2846                                 struct sk_buff *this = skb;
2847                                 skb = skb->prev;
2848                                 dev_kfree_skb(this);
2849                         } while (skb);
2850                 }
2851                 if (!rx_buffer_info->page)
2852                         continue;
2853                 if (rx_buffer_info->page_dma) {
2854                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2855                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2856                         rx_buffer_info->page_dma = 0;
2857                 }
2858                 put_page(rx_buffer_info->page);
2859                 rx_buffer_info->page = NULL;
2860                 rx_buffer_info->page_offset = 0;
2861         }
2862
2863         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2864         memset(rx_ring->rx_buffer_info, 0, size);
2865
2866         /* Zero out the descriptor ring */
2867         memset(rx_ring->desc, 0, rx_ring->size);
2868
2869         rx_ring->next_to_clean = 0;
2870         rx_ring->next_to_use = 0;
2871
2872         if (rx_ring->head)
2873                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2874         if (rx_ring->tail)
2875                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2876 }
2877
2878 /**
2879  * ixgbe_clean_tx_ring - Free Tx Buffers
2880  * @adapter: board private structure
2881  * @tx_ring: ring to be cleaned
2882  **/
2883 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2884                                 struct ixgbe_ring *tx_ring)
2885 {
2886         struct ixgbe_tx_buffer *tx_buffer_info;
2887         unsigned long size;
2888         unsigned int i;
2889
2890         /* Free all the Tx ring sk_buffs */
2891
2892         for (i = 0; i < tx_ring->count; i++) {
2893                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2894                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2895         }
2896
2897         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2898         memset(tx_ring->tx_buffer_info, 0, size);
2899
2900         /* Zero out the descriptor ring */
2901         memset(tx_ring->desc, 0, tx_ring->size);
2902
2903         tx_ring->next_to_use = 0;
2904         tx_ring->next_to_clean = 0;
2905
2906         if (tx_ring->head)
2907                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2908         if (tx_ring->tail)
2909                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2910 }
2911
2912 /**
2913  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2914  * @adapter: board private structure
2915  **/
2916 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2917 {
2918         int i;
2919
2920         for (i = 0; i < adapter->num_rx_queues; i++)
2921                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2922 }
2923
2924 /**
2925  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2926  * @adapter: board private structure
2927  **/
2928 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2929 {
2930         int i;
2931
2932         for (i = 0; i < adapter->num_tx_queues; i++)
2933                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2934 }
2935
2936 void ixgbe_down(struct ixgbe_adapter *adapter)
2937 {
2938         struct net_device *netdev = adapter->netdev;
2939         struct ixgbe_hw *hw = &adapter->hw;
2940         u32 rxctrl;
2941         u32 txdctl;
2942         int i, j;
2943
2944         /* signal that we are down to the interrupt handler */
2945         set_bit(__IXGBE_DOWN, &adapter->state);
2946
2947         /* disable receives */
2948         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2949         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2950
2951         netif_tx_disable(netdev);
2952
2953         IXGBE_WRITE_FLUSH(hw);
2954         msleep(10);
2955
2956         netif_tx_stop_all_queues(netdev);
2957
2958         ixgbe_irq_disable(adapter);
2959
2960         ixgbe_napi_disable_all(adapter);
2961
2962         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2963         del_timer_sync(&adapter->sfp_timer);
2964         del_timer_sync(&adapter->watchdog_timer);
2965         cancel_work_sync(&adapter->watchdog_task);
2966
2967         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2968             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2969                 cancel_work_sync(&adapter->fdir_reinit_task);
2970
2971         /* disable transmits in the hardware now that interrupts are off */
2972         for (i = 0; i < adapter->num_tx_queues; i++) {
2973                 j = adapter->tx_ring[i].reg_idx;
2974                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2975                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2976                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2977         }
2978         /* Disable the Tx DMA engine on 82599 */
2979         if (hw->mac.type == ixgbe_mac_82599EB)
2980                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2981                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2982                                  ~IXGBE_DMATXCTL_TE));
2983
2984         netif_carrier_off(netdev);
2985
2986         if (!pci_channel_offline(adapter->pdev))
2987                 ixgbe_reset(adapter);
2988         ixgbe_clean_all_tx_rings(adapter);
2989         ixgbe_clean_all_rx_rings(adapter);
2990
2991 #ifdef CONFIG_IXGBE_DCA
2992         /* since we reset the hardware DCA settings were cleared */
2993         ixgbe_setup_dca(adapter);
2994 #endif
2995 }
2996
2997 /**
2998  * ixgbe_poll - NAPI Rx polling callback
2999  * @napi: structure for representing this polling device
3000  * @budget: how many packets driver is allowed to clean
3001  *
3002  * This function is used for legacy and MSI, NAPI mode
3003  **/
3004 static int ixgbe_poll(struct napi_struct *napi, int budget)
3005 {
3006         struct ixgbe_q_vector *q_vector =
3007                                 container_of(napi, struct ixgbe_q_vector, napi);
3008         struct ixgbe_adapter *adapter = q_vector->adapter;
3009         int tx_clean_complete, work_done = 0;
3010
3011 #ifdef CONFIG_IXGBE_DCA
3012         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3013                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3014                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3015         }
3016 #endif
3017
3018         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3019         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3020
3021         if (!tx_clean_complete)
3022                 work_done = budget;
3023
3024         /* If budget not fully consumed, exit the polling mode */
3025         if (work_done < budget) {
3026                 napi_complete(napi);
3027                 if (adapter->rx_itr_setting & 1)
3028                         ixgbe_set_itr(adapter);
3029                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3030                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3031         }
3032         return work_done;
3033 }
3034
3035 /**
3036  * ixgbe_tx_timeout - Respond to a Tx Hang
3037  * @netdev: network interface device structure
3038  **/
3039 static void ixgbe_tx_timeout(struct net_device *netdev)
3040 {
3041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042
3043         /* Do the reset outside of interrupt context */
3044         schedule_work(&adapter->reset_task);
3045 }
3046
3047 static void ixgbe_reset_task(struct work_struct *work)
3048 {
3049         struct ixgbe_adapter *adapter;
3050         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3051
3052         /* If we're already down or resetting, just bail */
3053         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3054             test_bit(__IXGBE_RESETTING, &adapter->state))
3055                 return;
3056
3057         adapter->tx_timeout_count++;
3058
3059         ixgbe_reinit_locked(adapter);
3060 }
3061
3062 #ifdef CONFIG_IXGBE_DCB
3063 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3064 {
3065         bool ret = false;
3066         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3067
3068         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3069                 return ret;
3070
3071         f->mask = 0x7 << 3;
3072         adapter->num_rx_queues = f->indices;
3073         adapter->num_tx_queues = f->indices;
3074         ret = true;
3075
3076         return ret;
3077 }
3078 #endif
3079
3080 /**
3081  * ixgbe_set_rss_queues: Allocate queues for RSS
3082  * @adapter: board private structure to initialize
3083  *
3084  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3085  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3086  *
3087  **/
3088 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3089 {
3090         bool ret = false;
3091         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3092
3093         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3094                 f->mask = 0xF;
3095                 adapter->num_rx_queues = f->indices;
3096                 adapter->num_tx_queues = f->indices;
3097                 ret = true;
3098         } else {
3099                 ret = false;
3100         }
3101
3102         return ret;
3103 }
3104
3105 /**
3106  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3107  * @adapter: board private structure to initialize
3108  *
3109  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3110  * to the original CPU that initiated the Tx session.  This runs in addition
3111  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3112  * Rx load across CPUs using RSS.
3113  *
3114  **/
3115 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3116 {
3117         bool ret = false;
3118         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3119
3120         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3121         f_fdir->mask = 0;
3122
3123         /* Flow Director must have RSS enabled */
3124         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3125             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3126              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3127                 adapter->num_tx_queues = f_fdir->indices;
3128                 adapter->num_rx_queues = f_fdir->indices;
3129                 ret = true;
3130         } else {
3131                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3132                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3133         }
3134         return ret;
3135 }
3136
3137 #ifdef IXGBE_FCOE
3138 /**
3139  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3140  * @adapter: board private structure to initialize
3141  *
3142  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3143  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3144  * rx queues out of the max number of rx queues, instead, it is used as the
3145  * index of the first rx queue used by FCoE.
3146  *
3147  **/
3148 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3149 {
3150         bool ret = false;
3151         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3152
3153         f->indices = min((int)num_online_cpus(), f->indices);
3154         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3155                 adapter->num_rx_queues = 1;
3156                 adapter->num_tx_queues = 1;
3157 #ifdef CONFIG_IXGBE_DCB
3158                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3159                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3160                         ixgbe_set_dcb_queues(adapter);
3161                 }
3162 #endif
3163                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3164                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3165                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3166                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3167                                 ixgbe_set_fdir_queues(adapter);
3168                         else
3169                                 ixgbe_set_rss_queues(adapter);
3170