drivers/net/ixgbe/ixgbe_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/uaccess.h>
  37
  38 #include "ixgbe.h"
  39
  40
  41 #define IXGBE_ALL_RAR_ENTRIES 16
  42
  43 struct ixgbe_stats {
  44         char stat_string[ETH_GSTRING_LEN];
  45         int sizeof_stat;
  46         int stat_offset;
  47 };
  48
  49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
  50                              offsetof(struct ixgbe_adapter, m)
  51 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
  52         {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
  53         {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
  54         {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
  55         {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
  56         {"lsc_int", IXGBE_STAT(lsc_int)},
  57         {"tx_busy", IXGBE_STAT(tx_busy)},
  58         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  59         {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
  60         {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
  61         {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
  62         {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
  63         {"multicast", IXGBE_STAT(net_stats.multicast)},
  64         {"broadcast", IXGBE_STAT(stats.bprc)},
  65         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  66         {"collisions", IXGBE_STAT(net_stats.collisions)},
  67         {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
  68         {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
  69         {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
  70         {"hw_rsc_count", IXGBE_STAT(rsc_count)},
  71         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  72         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  73         {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
  74         {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
  75         {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
  76         {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
  77         {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
  78         {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
  79         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  80         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  81         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
  82         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
  83         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
  84         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
  85         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
  86         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
  87         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
  88         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
  89         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
  90         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
  91         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
  92         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
  93         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
  94         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
  95         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
  96 #ifdef IXGBE_FCOE
  97         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
  98         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
  99         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 100         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 101         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 102         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 103 #endif /* IXGBE_FCOE */
 104 };
 105
 106 #define IXGBE_QUEUE_STATS_LEN \
 107         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
 108         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
 109         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 110 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 111 #define IXGBE_PB_STATS_LEN ( \
 112                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
 113                  IXGBE_FLAG_DCB_ENABLED) ? \
 114                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 115                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 116                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 117                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 118                   / sizeof(u64) : 0)
 119 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 120                          IXGBE_PB_STATS_LEN + \
 121                          IXGBE_QUEUE_STATS_LEN)
 122
 123 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 124         "Register test  (offline)", "Eeprom test    (offline)",
 125         "Interrupt test (offline)", "Loopback test  (offline)",
 126         "Link test   (on/offline)"
 127 };
 128 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 129
 130 static int ixgbe_get_settings(struct net_device *netdev,
 131                               struct ethtool_cmd *ecmd)
 132 {
 133         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 134         struct ixgbe_hw *hw = &adapter->hw;
 135         u32 link_speed = 0;
 136         bool link_up;
 137
 138         ecmd->supported = SUPPORTED_10000baseT_Full;
 139         ecmd->autoneg = AUTONEG_ENABLE;
 140         ecmd->transceiver = XCVR_EXTERNAL;
 141         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 142             (hw->phy.multispeed_fiber)) {
 143                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
 144                                     SUPPORTED_Autoneg);
 145
 146                 ecmd->advertising = ADVERTISED_Autoneg;
 147                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 148                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 149                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 150                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 151                 /*
 152                  * It's possible that phy.autoneg_advertised may not be
 153                  * set yet.  If so display what the default would be -
 154                  * both 1G and 10G supported.
 155                  */
 156                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
 157                                            ADVERTISED_10000baseT_Full)))
 158                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
 159                                               ADVERTISED_1000baseT_Full);
 160
 161                 if (hw->phy.media_type == ixgbe_media_type_copper) {
 162                         ecmd->supported |= SUPPORTED_TP;
 163                         ecmd->advertising |= ADVERTISED_TP;
 164                         ecmd->port = PORT_TP;
 165                 } else {
 166                         ecmd->supported |= SUPPORTED_FIBRE;
 167                         ecmd->advertising |= ADVERTISED_FIBRE;
 168                         ecmd->port = PORT_FIBRE;
 169                 }
 170         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
 171                 /* Set as FIBRE until SERDES defined in kernel */
 172                 switch (hw->device_id) {
 173                 case IXGBE_DEV_ID_82598:
 174                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 175                                 SUPPORTED_FIBRE);
 176                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
 177                                 ADVERTISED_1000baseT_Full |
 178                                 ADVERTISED_FIBRE);
 179                         ecmd->port = PORT_FIBRE;
 180                         break;
 181                 case IXGBE_DEV_ID_82598_BX:
 182                         ecmd->supported = (SUPPORTED_1000baseT_Full |
 183                                            SUPPORTED_FIBRE);
 184                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
 185                                              ADVERTISED_FIBRE);
 186                         ecmd->port = PORT_FIBRE;
 187                         ecmd->autoneg = AUTONEG_DISABLE;
 188                         break;
 189                 }
 190         } else {
 191                 ecmd->supported |= SUPPORTED_FIBRE;
 192                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
 193                                      ADVERTISED_FIBRE);
 194                 ecmd->port = PORT_FIBRE;
 195                 ecmd->autoneg = AUTONEG_DISABLE;
 196         }
 197
 198         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 199         if (link_up) {
 200                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
 201                                SPEED_10000 : SPEED_1000;
 202                 ecmd->duplex = DUPLEX_FULL;
 203         } else {
 204                 ecmd->speed = -1;
 205                 ecmd->duplex = -1;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int ixgbe_set_settings(struct net_device *netdev,
 212                               struct ethtool_cmd *ecmd)
 213 {
 214         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 215         struct ixgbe_hw *hw = &adapter->hw;
 216         u32 advertised, old;
 217         s32 err = 0;
 218
 219         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 220             (hw->phy.multispeed_fiber)) {
 221                 /* 10000/copper and 1000/copper must autoneg
 222                  * this function does not support any duplex forcing, but can
 223                  * limit the advertising of the adapter to only 10000 or 1000 */
 224                 if (ecmd->autoneg == AUTONEG_DISABLE)
 225                         return -EINVAL;
 226
 227                 old = hw->phy.autoneg_advertised;
 228                 advertised = 0;
 229                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 230                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 231
 232                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 233                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 234
 235                 if (old == advertised)
 236                         return err;
 237                 /* this sets the link speed and restarts auto-neg */
 238                 hw->mac.autotry_restart = true;
 239                 err = hw->mac.ops.setup_link_speed(hw, advertised, true, true);
 240                 if (err) {
 241                         DPRINTK(PROBE, INFO,
 242                                 "setup link failed with code %d\n", err);
 243                         hw->mac.ops.setup_link_speed(hw, old, true, true);
 244                 }
 245         } else {
 246                 /* in this case we currently only support 10Gb/FULL */
 247                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 248                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 249                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 250                         return -EINVAL;
 251         }
 252
 253         return err;
 254 }
 255
 256 static void ixgbe_get_pauseparam(struct net_device *netdev,
 257                                  struct ethtool_pauseparam *pause)
 258 {
 259         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 260         struct ixgbe_hw *hw = &adapter->hw;
 261
 262         /*
 263          * Flow Control Autoneg isn't on if
 264          *  - we didn't ask for it OR
 265          *  - it failed, we know this by tx & rx being off
 266          */
 267         if (hw->fc.disable_fc_autoneg ||
 268             (hw->fc.current_mode == ixgbe_fc_none))
 269                 pause->autoneg = 0;
 270         else
 271                 pause->autoneg = 1;
 272
 273 #ifdef CONFIG_DCB
 274         if (hw->fc.current_mode == ixgbe_fc_pfc) {
 275                 pause->rx_pause = 0;
 276                 pause->tx_pause = 0;
 277         }
 278
 279 #endif
 280         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 281                 pause->rx_pause = 1;
 282         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 283                 pause->tx_pause = 1;
 284         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 285                 pause->rx_pause = 1;
 286                 pause->tx_pause = 1;
 287         }
 288 }
 289
 290 static int ixgbe_set_pauseparam(struct net_device *netdev,
 291                                 struct ethtool_pauseparam *pause)
 292 {
 293         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 294         struct ixgbe_hw *hw = &adapter->hw;
 295         struct ixgbe_fc_info fc;
 296
 297 #ifdef CONFIG_DCB
 298         if (adapter->dcb_cfg.pfc_mode_enable ||
 299                 ((hw->mac.type == ixgbe_mac_82598EB) &&
 300                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
 301                 return -EINVAL;
 302
 303 #endif
 304
 305         fc = hw->fc;
 306
 307         if (pause->autoneg != AUTONEG_ENABLE)
 308                 fc.disable_fc_autoneg = true;
 309         else
 310                 fc.disable_fc_autoneg = false;
 311
 312         if (pause->rx_pause && pause->tx_pause)
 313                 fc.requested_mode = ixgbe_fc_full;
 314         else if (pause->rx_pause && !pause->tx_pause)
 315                 fc.requested_mode = ixgbe_fc_rx_pause;
 316         else if (!pause->rx_pause && pause->tx_pause)
 317                 fc.requested_mode = ixgbe_fc_tx_pause;
 318         else if (!pause->rx_pause && !pause->tx_pause)
 319                 fc.requested_mode = ixgbe_fc_none;
 320         else
 321                 return -EINVAL;
 322
 323 #ifdef CONFIG_DCB
 324         adapter->last_lfc_mode = fc.requested_mode;
 325 #endif
 326
 327         /* if the thing changed then we'll update and use new autoneg */
 328         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 329                 hw->fc = fc;
 330                 if (netif_running(netdev))
 331                         ixgbe_reinit_locked(adapter);
 332                 else
 333                         ixgbe_reset(adapter);
 334         }
 335
 336         return 0;
 337 }
 338
 339 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
 340 {
 341         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 342         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
 343 }
 344
 345 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
 346 {
 347         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 348         if (data)
 349                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
 350         else
 351                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 352
 353         if (netif_running(netdev))
 354                 ixgbe_reinit_locked(adapter);
 355         else
 356                 ixgbe_reset(adapter);
 357
 358         return 0;
 359 }
 360
 361 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 362 {
 363         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 364 }
 365
 366 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 367 {
 368         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 369
 370         if (data) {
 371                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 372                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 373                         netdev->features |= NETIF_F_SCTP_CSUM;
 374         } else {
 375                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 376                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 377                         netdev->features &= ~NETIF_F_SCTP_CSUM;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
 384 {
 385         if (data) {
 386                 netdev->features |= NETIF_F_TSO;
 387                 netdev->features |= NETIF_F_TSO6;
 388         } else {
 389                 netif_tx_stop_all_queues(netdev);
 390                 netdev->features &= ~NETIF_F_TSO;
 391                 netdev->features &= ~NETIF_F_TSO6;
 392                 netif_tx_start_all_queues(netdev);
 393         }
 394         return 0;
 395 }
 396
 397 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 398 {
 399         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 400         return adapter->msg_enable;
 401 }
 402
 403 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 404 {
 405         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 406         adapter->msg_enable = data;
 407 }
 408
 409 static int ixgbe_get_regs_len(struct net_device *netdev)
 410 {
 411 #define IXGBE_REGS_LEN  1128
 412         return IXGBE_REGS_LEN * sizeof(u32);
 413 }
 414
 415 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 416
 417 static void ixgbe_get_regs(struct net_device *netdev,
 418                            struct ethtool_regs *regs, void *p)
 419 {
 420         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 421         struct ixgbe_hw *hw = &adapter->hw;
 422         u32 *regs_buff = p;
 423         u8 i;
 424
 425         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 426
 427         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
 428
 429         /* General Registers */
 430         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 431         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 432         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 433         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 434         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 435         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 436         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 437         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 438
 439         /* NVM Register */
 440         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 441         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 442         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 443         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 444         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 445         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 446         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 447         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 448         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 449         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 450
 451         /* Interrupt */
 452         /* don't read EICR because it can clear interrupt causes, instead
 453          * read EICS which is a shadow but doesn't clear EICR */
 454         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 455         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 456         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 457         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 458         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 459         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 460         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 461         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 462         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 463         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 464         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 465         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 466
 467         /* Flow Control */
 468         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 469         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 470         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 471         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 472         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 473         for (i = 0; i < 8; i++)
 474                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 475         for (i = 0; i < 8; i++)
 476                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 477         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 478         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 479
 480         /* Receive DMA */
 481         for (i = 0; i < 64; i++)
 482                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 483         for (i = 0; i < 64; i++)
 484                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 485         for (i = 0; i < 64; i++)
 486                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 487         for (i = 0; i < 64; i++)
 488                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 489         for (i = 0; i < 64; i++)
 490                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 491         for (i = 0; i < 64; i++)
 492                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 493         for (i = 0; i < 16; i++)
 494                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 495         for (i = 0; i < 16; i++)
 496                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 497         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 498         for (i = 0; i < 8; i++)
 499                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 500         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 501         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 502
 503         /* Receive */
 504         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 505         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 506         for (i = 0; i < 16; i++)
 507                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 508         for (i = 0; i < 16; i++)
 509                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 510         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 511         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 512         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 513         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 514         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 515         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 516         for (i = 0; i < 8; i++)
 517                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 518         for (i = 0; i < 8; i++)
 519                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 520         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 521
 522         /* Transmit */
 523         for (i = 0; i < 32; i++)
 524                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 525         for (i = 0; i < 32; i++)
 526                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 527         for (i = 0; i < 32; i++)
 528                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 529         for (i = 0; i < 32; i++)
 530                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 531         for (i = 0; i < 32; i++)
 532                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 533         for (i = 0; i < 32; i++)
 534                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 535         for (i = 0; i < 32; i++)
 536                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 537         for (i = 0; i < 32; i++)
 538                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 539         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 540         for (i = 0; i < 16; i++)
 541                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 542         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 543         for (i = 0; i < 8; i++)
 544                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 545         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 546
 547         /* Wake Up */
 548         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 549         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 550         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 551         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 552         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 553         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 554         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 555         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 556         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 557
 558         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 559         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 560         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 561         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 562         for (i = 0; i < 8; i++)
 563                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 564         for (i = 0; i < 8; i++)
 565                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 566         for (i = 0; i < 8; i++)
 567                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 568         for (i = 0; i < 8; i++)
 569                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 570         for (i = 0; i < 8; i++)
 571                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 572         for (i = 0; i < 8; i++)
 573                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 574
 575         /* Statistics */
 576         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 577         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 578         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 579         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 580         for (i = 0; i < 8; i++)
 581                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 582         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 583         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 584         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 585         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 586         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 587         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 588         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 589         for (i = 0; i < 8; i++)
 590                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 591         for (i = 0; i < 8; i++)
 592                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 593         for (i = 0; i < 8; i++)
 594                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 595         for (i = 0; i < 8; i++)
 596                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 597         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 598         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 599         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 600         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 601         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 602         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 603         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 604         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 605         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 606         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 607         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 608         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 609         for (i = 0; i < 8; i++)
 610                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 611         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 612         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 613         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 614         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 615         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 616         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 617         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 618         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 619         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 620         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 621         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 622         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 623         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 624         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 625         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 626         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 627         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 628         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 629         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 630         for (i = 0; i < 16; i++)
 631                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 632         for (i = 0; i < 16; i++)
 633                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 634         for (i = 0; i < 16; i++)
 635                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 636         for (i = 0; i < 16; i++)
 637                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 638
 639         /* MAC */
 640         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 641         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 642         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 643         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 644         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 645         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 646         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 647         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 648         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 649         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 650         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 651         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 652         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 653         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 654         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 655         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 656         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 657         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 658         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 659         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 660         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 661         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 662         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 663         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 664         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 665         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 666         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 667         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 668         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 669         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 670         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 671         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 672         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 673
 674         /* Diagnostic */
 675         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 676         for (i = 0; i < 8; i++)
 677                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 678         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 679         for (i = 0; i < 4; i++)
 680                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 681         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 682         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 683         for (i = 0; i < 8; i++)
 684                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 685         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 686         for (i = 0; i < 4; i++)
 687                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 688         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 689         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 690         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 691         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 692         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 693         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 694         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 695         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 696         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 697         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 698         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 699         for (i = 0; i < 8; i++)
 700                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 701         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 702         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 703         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 704         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 705         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 706         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 707         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 708         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 709         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 710 }
 711
 712 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 713 {
 714         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 715         return adapter->hw.eeprom.word_size * 2;
 716 }
 717
 718 static int ixgbe_get_eeprom(struct net_device *netdev,
 719                             struct ethtool_eeprom *eeprom, u8 *bytes)
 720 {
 721         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 722         struct ixgbe_hw *hw = &adapter->hw;
 723         u16 *eeprom_buff;
 724         int first_word, last_word, eeprom_len;
 725         int ret_val = 0;
 726         u16 i;
 727
 728         if (eeprom->len == 0)
 729                 return -EINVAL;
 730
 731         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 732
 733         first_word = eeprom->offset >> 1;
 734         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 735         eeprom_len = last_word - first_word + 1;
 736
 737         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 738         if (!eeprom_buff)
 739                 return -ENOMEM;
 740
 741         for (i = 0; i < eeprom_len; i++) {
 742                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
 743                     &eeprom_buff[i])))
 744                         break;
 745         }
 746
 747         /* Device's eeprom is always little-endian, word addressable */
 748         for (i = 0; i < eeprom_len; i++)
 749                 le16_to_cpus(&eeprom_buff[i]);
 750
 751         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 752         kfree(eeprom_buff);
 753
 754         return ret_val;
 755 }
 756
 757 static void ixgbe_get_drvinfo(struct net_device *netdev,
 758                               struct ethtool_drvinfo *drvinfo)
 759 {
 760         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 761         char firmware_version[32];
 762
 763         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
 764         strncpy(drvinfo->version, ixgbe_driver_version, 32);
 765
 766         sprintf(firmware_version, "%d.%d-%d",
 767                 (adapter->eeprom_version & 0xF000) >> 12,
 768                 (adapter->eeprom_version & 0x0FF0) >> 4,
 769                 adapter->eeprom_version & 0x000F);
 770
 771         strncpy(drvinfo->fw_version, firmware_version, 32);
 772         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 773         drvinfo->n_stats = IXGBE_STATS_LEN;
 774         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 775         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 776 }
 777
 778 static void ixgbe_get_ringparam(struct net_device *netdev,
 779                                 struct ethtool_ringparam *ring)
 780 {
 781         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 782         struct ixgbe_ring *tx_ring = adapter->tx_ring;
 783         struct ixgbe_ring *rx_ring = adapter->rx_ring;
 784
 785         ring->rx_max_pending = IXGBE_MAX_RXD;
 786         ring->tx_max_pending = IXGBE_MAX_TXD;
 787         ring->rx_mini_max_pending = 0;
 788         ring->rx_jumbo_max_pending = 0;
 789         ring->rx_pending = rx_ring->count;
 790         ring->tx_pending = tx_ring->count;
 791         ring->rx_mini_pending = 0;
 792         ring->rx_jumbo_pending = 0;
 793 }
 794
 795 static int ixgbe_set_ringparam(struct net_device *netdev,
 796                                struct ethtool_ringparam *ring)
 797 {
 798         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 799         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
 800         int i, err;
 801         u32 new_rx_count, new_tx_count;
 802         bool need_update = false;
 803
 804         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 805                 return -EINVAL;
 806
 807         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
 808         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
 809         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 810
 811         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
 812         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
 813         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 814
 815         if ((new_tx_count == adapter->tx_ring->count) &&
 816             (new_rx_count == adapter->rx_ring->count)) {
 817                 /* nothing to do */
 818                 return 0;
 819         }
 820
 821         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 822                 msleep(1);
 823
 824         temp_tx_ring = kcalloc(adapter->num_tx_queues,
 825                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 826         if (!temp_tx_ring) {
 827                 err = -ENOMEM;
 828                 goto err_setup;
 829         }
 830
 831         if (new_tx_count != adapter->tx_ring_count) {
 832                 memcpy(temp_tx_ring, adapter->tx_ring,
 833                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
 834                 for (i = 0; i < adapter->num_tx_queues; i++) {
 835                         temp_tx_ring[i].count = new_tx_count;
 836                         err = ixgbe_setup_tx_resources(adapter,
 837                                                        &temp_tx_ring[i]);
 838                         if (err) {
 839                                 while (i) {
 840                                         i--;
 841                                         ixgbe_free_tx_resources(adapter,
 842                                                                 &temp_tx_ring[i]);
 843                                 }
 844                                 goto err_setup;
 845                         }
 846                 }
 847                 need_update = true;
 848         }
 849
 850         temp_rx_ring = kcalloc(adapter->num_rx_queues,
 851                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 852         if ((!temp_rx_ring) && (need_update)) {
 853                 for (i = 0; i < adapter->num_tx_queues; i++)
 854                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
 855                 kfree(temp_tx_ring);
 856                 err = -ENOMEM;
 857                 goto err_setup;
 858         }
 859
 860         if (new_rx_count != adapter->rx_ring_count) {
 861                 memcpy(temp_rx_ring, adapter->rx_ring,
 862                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
 863                 for (i = 0; i < adapter->num_rx_queues; i++) {
 864                         temp_rx_ring[i].count = new_rx_count;
 865                         err = ixgbe_setup_rx_resources(adapter,
 866                                                        &temp_rx_ring[i]);
 867                         if (err) {
 868                                 while (i) {
 869                                         i--;
 870                                         ixgbe_free_rx_resources(adapter,
 871                                                               &temp_rx_ring[i]);
 872                                 }
 873                                 goto err_setup;
 874                         }
 875                 }
 876                 need_update = true;
 877         }
 878
 879         /* if rings need to be updated, here's the place to do it in one shot */
 880         if (need_update) {
 881                 if (netif_running(netdev))
 882                         ixgbe_down(adapter);
 883
 884                 /* tx */
 885                 if (new_tx_count != adapter->tx_ring_count) {
 886                         kfree(adapter->tx_ring);
 887                         adapter->tx_ring = temp_tx_ring;
 888                         temp_tx_ring = NULL;
 889                         adapter->tx_ring_count = new_tx_count;
 890                 }
 891
 892                 /* rx */
 893                 if (new_rx_count != adapter->rx_ring_count) {
 894                         kfree(adapter->rx_ring);
 895                         adapter->rx_ring = temp_rx_ring;
 896                         temp_rx_ring = NULL;
 897                         adapter->rx_ring_count = new_rx_count;
 898                 }
 899         }
 900
 901         /* success! */
 902         err = 0;
 903         if (netif_running(netdev))
 904                 ixgbe_up(adapter);
 905
 906 err_setup:
 907         clear_bit(__IXGBE_RESETTING, &adapter->state);
 908         return err;
 909 }
 910
 911 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
 912 {
 913         switch (sset) {
 914         case ETH_SS_TEST:
 915                 return IXGBE_TEST_LEN;
 916         case ETH_SS_STATS:
 917                 return IXGBE_STATS_LEN;
 918         default:
 919                 return -EOPNOTSUPP;
 920         }
 921 }
 922
 923 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
 924                                     struct ethtool_stats *stats, u64 *data)
 925 {
 926         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 927         u64 *queue_stat;
 928         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
 929         int j, k;
 930         int i;
 931
 932         ixgbe_update_stats(adapter);
 933         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 934                 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
 935                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
 936                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
 937         }
 938         for (j = 0; j < adapter->num_tx_queues; j++) {
 939                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
 940                 for (k = 0; k < stat_count; k++)
 941                         data[i + k] = queue_stat[k];
 942                 i += k;
 943         }
 944         for (j = 0; j < adapter->num_rx_queues; j++) {
 945                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
 946                 for (k = 0; k < stat_count; k++)
 947                         data[i + k] = queue_stat[k];
 948                 i += k;
 949         }
 950         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 951                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
 952                         data[i++] = adapter->stats.pxontxc[j];
 953                         data[i++] = adapter->stats.pxofftxc[j];
 954                 }
 955                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
 956                         data[i++] = adapter->stats.pxonrxc[j];
 957                         data[i++] = adapter->stats.pxoffrxc[j];
 958                 }
 959         }
 960 }
 961
 962 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
 963                               u8 *data)
 964 {
 965         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 966         char *p = (char *)data;
 967         int i;
 968
 969         switch (stringset) {
 970         case ETH_SS_TEST:
 971                 memcpy(data, *ixgbe_gstrings_test,
 972                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
 973                 break;
 974         case ETH_SS_STATS:
 975                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 976                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
 977                                ETH_GSTRING_LEN);
 978                         p += ETH_GSTRING_LEN;
 979                 }
 980                 for (i = 0; i < adapter->num_tx_queues; i++) {
 981                         sprintf(p, "tx_queue_%u_packets", i);
 982                         p += ETH_GSTRING_LEN;
 983                         sprintf(p, "tx_queue_%u_bytes", i);
 984                         p += ETH_GSTRING_LEN;
 985                 }
 986                 for (i = 0; i < adapter->num_rx_queues; i++) {
 987                         sprintf(p, "rx_queue_%u_packets", i);
 988                         p += ETH_GSTRING_LEN;
 989                         sprintf(p, "rx_queue_%u_bytes", i);
 990                         p += ETH_GSTRING_LEN;
 991                 }
 992                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 993                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 994                                 sprintf(p, "tx_pb_%u_pxon", i);
 995                                 p += ETH_GSTRING_LEN;
 996                                 sprintf(p, "tx_pb_%u_pxoff", i);
 997                                 p += ETH_GSTRING_LEN;
 998                         }
 999                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1000                                 sprintf(p, "rx_pb_%u_pxon", i);
1001                                 p += ETH_GSTRING_LEN;
1002                                 sprintf(p, "rx_pb_%u_pxoff", i);
1003                                 p += ETH_GSTRING_LEN;
1004                         }
1005                 }
1006                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1007                 break;
1008         }
1009 }
1010
1011 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1012 {
1013         struct ixgbe_hw *hw = &adapter->hw;
1014         bool link_up;
1015         u32 link_speed = 0;
1016         *data = 0;
1017
1018         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1019         if (link_up)
1020                 return *data;
1021         else
1022                 *data = 1;
1023         return *data;
1024 }
1025
1026 /* ethtool register test data */
1027 struct ixgbe_reg_test {
1028         u16 reg;
1029         u8  array_len;
1030         u8  test_type;
1031         u32 mask;
1032         u32 write;
1033 };
1034
1035 /* In the hardware, registers are laid out either singly, in arrays
1036  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1037  * most tests take place on arrays or single registers (handled
1038  * as a single-element array) and special-case the tables.
1039  * Table tests are always pattern tests.
1040  *
1041  * We also make provision for some required setup steps by specifying
1042  * registers to be written without any read-back testing.
1043  */
1044
1045 #define PATTERN_TEST    1
1046 #define SET_READ_TEST   2
1047 #define WRITE_NO_TEST   3
1048 #define TABLE32_TEST    4
1049 #define TABLE64_TEST_LO 5
1050 #define TABLE64_TEST_HI 6
1051
1052 /* default 82599 register test */
1053 static struct ixgbe_reg_test reg_test_82599[] = {
1054         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1055         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1056         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1058         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1059         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1060         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1061         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1062         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1063         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1064         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1065         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1066         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1067         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1068         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1069         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1070         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1071         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1072         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1073         { 0, 0, 0, 0 }
1074 };
1075
1076 /* default 82598 register test */
1077 static struct ixgbe_reg_test reg_test_82598[] = {
1078         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1079         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1080         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1082         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1083         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1085         /* Enable all four RX queues before testing. */
1086         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1087         /* RDH is read-only for 82598, only test RDT. */
1088         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1089         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1090         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1091         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1092         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1093         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1094         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1096         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1097         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1098         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1099         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1100         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1101         { 0, 0, 0, 0 }
1102 };
1103
1104 #define REG_PATTERN_TEST(R, M, W)                                             \
1105 {                                                                             \
1106         u32 pat, val, before;                                                 \
1107         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1108         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1109                 before = readl(adapter->hw.hw_addr + R);                      \
1110                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1111                 val = readl(adapter->hw.hw_addr + R);                         \
1112                 if (val != (_test[pat] & W & M)) {                            \
1113                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1114                                           "0x%08X expected 0x%08X\n",         \
1115                                 R, val, (_test[pat] & W & M));                \
1116                         *data = R;                                            \
1117                         writel(before, adapter->hw.hw_addr + R);              \
1118                         return 1;                                             \
1119                 }                                                             \
1120                 writel(before, adapter->hw.hw_addr + R);                      \
1121         }                                                                     \
1122 }
1123
1124 #define REG_SET_AND_CHECK(R, M, W)                                            \
1125 {                                                                             \
1126         u32 val, before;                                                      \
1127         before = readl(adapter->hw.hw_addr + R);                              \
1128         writel((W & M), (adapter->hw.hw_addr + R));                           \
1129         val = readl(adapter->hw.hw_addr + R);                                 \
1130         if ((W & M) != (val & M)) {                                           \
1131                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1132                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1133                 *data = R;                                                    \
1134                 writel(before, (adapter->hw.hw_addr + R));                    \
1135                 return 1;                                                     \
1136         }                                                                     \
1137         writel(before, (adapter->hw.hw_addr + R));                            \
1138 }
1139
1140 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1141 {
1142         struct ixgbe_reg_test *test;
1143         u32 value, before, after;
1144         u32 i, toggle;
1145
1146         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1147                 toggle = 0x7FFFF30F;
1148                 test = reg_test_82599;
1149         } else {
1150                 toggle = 0x7FFFF3FF;
1151                 test = reg_test_82598;
1152         }
1153
1154         /*
1155          * Because the status register is such a special case,
1156          * we handle it separately from the rest of the register
1157          * tests.  Some bits are read-only, some toggle, and some
1158          * are writeable on newer MACs.
1159          */
1160         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1161         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1162         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1163         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1164         if (value != after) {
1165                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1166                         "0x%08X expected: 0x%08X\n", after, value);
1167                 *data = 1;
1168                 return 1;
1169         }
1170         /* restore previous status */
1171         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1172
1173         /*
1174          * Perform the remainder of the register test, looping through
1175          * the test table until we either fail or reach the null entry.
1176          */
1177         while (test->reg) {
1178                 for (i = 0; i < test->array_len; i++) {
1179                         switch (test->test_type) {
1180                         case PATTERN_TEST:
1181                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1182                                                 test->mask,
1183                                                 test->write);
1184                                 break;
1185                         case SET_READ_TEST:
1186                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1187                                                 test->mask,
1188                                                 test->write);
1189                                 break;
1190                         case WRITE_NO_TEST:
1191                                 writel(test->write,
1192                                        (adapter->hw.hw_addr + test->reg)
1193                                        + (i * 0x40));
1194                                 break;
1195                         case TABLE32_TEST:
1196                                 REG_PATTERN_TEST(test->reg + (i * 4),
1197                                                 test->mask,
1198                                                 test->write);
1199                                 break;
1200                         case TABLE64_TEST_LO:
1201                                 REG_PATTERN_TEST(test->reg + (i * 8),
1202                                                 test->mask,
1203                                                 test->write);
1204                                 break;
1205                         case TABLE64_TEST_HI:
1206                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1207                                                 test->mask,
1208                                                 test->write);
1209                                 break;
1210                         }
1211                 }
1212                 test++;
1213         }
1214
1215         *data = 0;
1216         return 0;
1217 }
1218
1219 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1220 {
1221         struct ixgbe_hw *hw = &adapter->hw;
1222         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1223                 *data = 1;
1224         else
1225                 *data = 0;
1226         return *data;
1227 }
1228
1229 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1230 {
1231         struct net_device *netdev = (struct net_device *) data;
1232         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1233
1234         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1235
1236         return IRQ_HANDLED;
1237 }
1238
1239 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1240 {
1241         struct net_device *netdev = adapter->netdev;
1242         u32 mask, i = 0, shared_int = true;
1243         u32 irq = adapter->pdev->irq;
1244
1245         *data = 0;
1246
1247         /* Hook up test interrupt handler just for this test */
1248         if (adapter->msix_entries) {
1249                 /* NOTE: we don't test MSI-X interrupts here, yet */
1250                 return 0;
1251         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1252                 shared_int = false;
1253                 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1254                                 netdev)) {
1255                         *data = 1;
1256                         return -1;
1257                 }
1258         } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1259                                 netdev->name, netdev)) {
1260                 shared_int = false;
1261         } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1262                                netdev->name, netdev)) {
1263                 *data = 1;
1264                 return -1;
1265         }
1266         DPRINTK(HW, INFO, "testing %s interrupt\n",
1267                 (shared_int ? "shared" : "unshared"));
1268
1269         /* Disable all the interrupts */
1270         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1271         msleep(10);
1272
1273         /* Test each interrupt */
1274         for (; i < 10; i++) {
1275                 /* Interrupt to test */
1276                 mask = 1 << i;
1277
1278                 if (!shared_int) {
1279                         /*
1280                          * Disable the interrupts to be reported in
1281                          * the cause register and then force the same
1282                          * interrupt and see if one gets posted.  If
1283                          * an interrupt was posted to the bus, the
1284                          * test failed.
1285                          */
1286                         adapter->test_icr = 0;
1287                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1288                                         ~mask & 0x00007FFF);
1289                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1290                                         ~mask & 0x00007FFF);
1291                         msleep(10);
1292
1293                         if (adapter->test_icr & mask) {
1294                                 *data = 3;
1295                                 break;
1296                         }
1297                 }
1298
1299                 /*
1300                  * Enable the interrupt to be reported in the cause
1301                  * register and then force the same interrupt and see
1302                  * if one gets posted.  If an interrupt was not posted
1303                  * to the bus, the test failed.
1304                  */
1305                 adapter->test_icr = 0;
1306                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1307                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1308                 msleep(10);
1309
1310                 if (!(adapter->test_icr &mask)) {
1311                         *data = 4;
1312                         break;
1313                 }
1314
1315                 if (!shared_int) {
1316                         /*
1317                          * Disable the other interrupts to be reported in
1318                          * the cause register and then force the other
1319                          * interrupts and see if any get posted.  If
1320                          * an interrupt was posted to the bus, the
1321                          * test failed.
1322                          */
1323                         adapter->test_icr = 0;
1324                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1325                                         ~mask & 0x00007FFF);
1326                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1327                                         ~mask & 0x00007FFF);
1328                         msleep(10);
1329
1330                         if (adapter->test_icr) {
1331                                 *data = 5;
1332                                 break;
1333                         }
1334                 }
1335         }
1336
1337         /* Disable all the interrupts */
1338         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1339         msleep(10);
1340
1341         /* Unhook test interrupt handler */
1342         free_irq(irq, netdev);
1343
1344         return *data;
1345 }
1346
1347 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1348 {
1349         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1350         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1351         struct ixgbe_hw *hw = &adapter->hw;
1352         struct pci_dev *pdev = adapter->pdev;
1353         u32 reg_ctl;
1354         int i;
1355
1356         /* shut down the DMA engines now so they can be reinitialized later */
1357
1358         /* first Rx */
1359         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1360         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1361         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1362         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1363         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1364         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1365
1366         /* now Tx */
1367         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1368         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1369         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1370         if (hw->mac.type == ixgbe_mac_82599EB) {
1371                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1372                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1373                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1374         }
1375
1376         ixgbe_reset(adapter);
1377
1378         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1379                 for (i = 0; i < tx_ring->count; i++) {
1380                         struct ixgbe_tx_buffer *buf =
1381                                         &(tx_ring->tx_buffer_info[i]);
1382                         if (buf->dma)
1383                                 pci_unmap_single(pdev, buf->dma, buf->length,
1384                                                  PCI_DMA_TODEVICE);
1385                         if (buf->skb)
1386                                 dev_kfree_skb(buf->skb);
1387                 }
1388         }
1389
1390         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1391                 for (i = 0; i < rx_ring->count; i++) {
1392                         struct ixgbe_rx_buffer *buf =
1393                                         &(rx_ring->rx_buffer_info[i]);
1394                         if (buf->dma)
1395                                 pci_unmap_single(pdev, buf->dma,
1396                                                  IXGBE_RXBUFFER_2048,
1397                                                  PCI_DMA_FROMDEVICE);
1398                         if (buf->skb)
1399                                 dev_kfree_skb(buf->skb);
1400                 }
1401         }
1402
1403         if (tx_ring->desc) {
1404                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1405                                     tx_ring->dma);
1406                 tx_ring->desc = NULL;
1407         }
1408         if (rx_ring->desc) {
1409                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1410                                     rx_ring->dma);
1411                 rx_ring->desc = NULL;
1412         }
1413
1414         kfree(tx_ring->tx_buffer_info);
1415         tx_ring->tx_buffer_info = NULL;
1416         kfree(rx_ring->rx_buffer_info);
1417         rx_ring->rx_buffer_info = NULL;
1418
1419         return;
1420 }
1421
1422 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1423 {
1424         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1425         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1426         struct pci_dev *pdev = adapter->pdev;
1427         u32 rctl, reg_data;
1428         int i, ret_val;
1429
1430         /* Setup Tx descriptor ring and Tx buffers */
1431
1432         if (!tx_ring->count)
1433                 tx_ring->count = IXGBE_DEFAULT_TXD;
1434
1435         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1436                                           sizeof(struct ixgbe_tx_buffer),
1437                                           GFP_KERNEL);
1438         if (!(tx_ring->tx_buffer_info)) {
1439                 ret_val = 1;
1440                 goto err_nomem;
1441         }
1442
1443         tx_ring->size = tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc);
1444         tx_ring->size = ALIGN(tx_ring->size, 4096);
1445         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1446                                                    &tx_ring->dma))) {
1447                 ret_val = 2;
1448                 goto err_nomem;
1449         }
1450         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1451
1452         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1453                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1454         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1455                         ((u64) tx_ring->dma >> 32));
1456         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1457                         tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc));
1458         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1459         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1460
1461         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1462         reg_data |= IXGBE_HLREG0_TXPADEN;
1463         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1464
1465         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1466                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1467                 reg_data |= IXGBE_DMATXCTL_TE;
1468                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1469         }
1470         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1471         reg_data |= IXGBE_TXDCTL_ENABLE;
1472         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1473
1474         for (i = 0; i < tx_ring->count; i++) {
1475                 struct ixgbe_legacy_tx_desc *desc = IXGBE_TX_DESC(*tx_ring, i);
1476                 struct sk_buff *skb;
1477                 unsigned int size = 1024;
1478
1479                 skb = alloc_skb(size, GFP_KERNEL);
1480                 if (!skb) {
1481                         ret_val = 3;
1482                         goto err_nomem;
1483                 }
1484                 skb_put(skb, size);
1485                 tx_ring->tx_buffer_info[i].skb = skb;
1486                 tx_ring->tx_buffer_info[i].length = skb->len;
1487                 tx_ring->tx_buffer_info[i].dma =
1488                         pci_map_single(pdev, skb->data, skb->len,
1489                                         PCI_DMA_TODEVICE);
1490                 desc->buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1491                 desc->lower.data = cpu_to_le32(skb->len);
1492                 desc->lower.data |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1493                                                 IXGBE_TXD_CMD_IFCS |
1494                                                 IXGBE_TXD_CMD_RS);
1495                 desc->upper.data = 0;
1496         }
1497
1498         /* Setup Rx Descriptor ring and Rx buffers */
1499
1500         if (!rx_ring->count)
1501                 rx_ring->count = IXGBE_DEFAULT_RXD;
1502
1503         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1504                                           sizeof(struct ixgbe_rx_buffer),
1505                                           GFP_KERNEL);
1506         if (!(rx_ring->rx_buffer_info)) {
1507                 ret_val = 4;
1508                 goto err_nomem;
1509         }
1510
1511         rx_ring->size = rx_ring->count * sizeof(struct ixgbe_legacy_rx_desc);
1512         rx_ring->size = ALIGN(rx_ring->size, 4096);
1513         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1514                                                    &rx_ring->dma))) {
1515                 ret_val = 5;
1516                 goto err_nomem;
1517         }
1518         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1519
1520         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1521         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1522         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1523                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1525                         ((u64) rx_ring->dma >> 32));
1526         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1528         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1529
1530         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1531         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1532         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1533
1534         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1535         reg_data &= ~IXGBE_HLREG0_LPBK;
1536         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1537
1538         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1539 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1540                                                   Threshold Size mask */
1541         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1542         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1543
1544         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1545 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1546         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1547         reg_data |= adapter->hw.mac.mc_filter_type;
1548         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1549
1550         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1551         reg_data |= IXGBE_RXDCTL_ENABLE;
1552         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1553         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1554                 int j = adapter->rx_ring[0].reg_idx;
1555                 u32 k;
1556                 for (k = 0; k < 10; k++) {
1557                         if (IXGBE_READ_REG(&adapter->hw,
1558                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1559                                 break;
1560                         else
1561                                 msleep(1);
1562                 }
1563         }
1564
1565         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1566         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1567
1568         for (i = 0; i < rx_ring->count; i++) {
1569                 struct ixgbe_legacy_rx_desc *rx_desc =
1570                                         IXGBE_RX_DESC(*rx_ring, i);
1571                 struct sk_buff *skb;
1572
1573                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1574                 if (!skb) {
1575                         ret_val = 6;
1576                         goto err_nomem;
1577                 }
1578                 skb_reserve(skb, NET_IP_ALIGN);
1579                 rx_ring->rx_buffer_info[i].skb = skb;
1580                 rx_ring->rx_buffer_info[i].dma =
1581                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1582                                        PCI_DMA_FROMDEVICE);
1583                 rx_desc->buffer_addr =
1584                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1585                 memset(skb->data, 0x00, skb->len);
1586         }
1587
1588         return 0;
1589
1590 err_nomem:
1591         ixgbe_free_desc_rings(adapter);
1592         return ret_val;
1593 }
1594
1595 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1596 {
1597         struct ixgbe_hw *hw = &adapter->hw;
1598         u32 reg_data;
1599
1600         /* right now we only support MAC loopback in the driver */
1601
1602         /* Setup MAC loopback */
1603         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1604         reg_data |= IXGBE_HLREG0_LPBK;
1605         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1606
1607         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1608         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1609         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1610         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1611
1612         /* Disable Atlas Tx lanes; re-enabled in reset path */
1613         if (hw->mac.type == ixgbe_mac_82598EB) {
1614                 u8 atlas;
1615
1616                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1617                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1618                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1619
1620                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1621                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1622                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1623
1624                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1625                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1626                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1627
1628                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1629                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1630                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1631         }
1632
1633         return 0;
1634 }
1635
1636 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1637 {
1638         u32 reg_data;
1639
1640         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1641         reg_data &= ~IXGBE_HLREG0_LPBK;
1642         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1643 }
1644
1645 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1646                                       unsigned int frame_size)
1647 {
1648         memset(skb->data, 0xFF, frame_size);
1649         frame_size &= ~1;
1650         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1651         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1652         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1653 }
1654
1655 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1656                                     unsigned int frame_size)
1657 {
1658         frame_size &= ~1;
1659         if (*(skb->data + 3) == 0xFF) {
1660                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1661                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1662                         return 0;
1663                 }
1664         }
1665         return 13;
1666 }
1667
1668 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1669 {
1670         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1671         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1672         struct pci_dev *pdev = adapter->pdev;
1673         int i, j, k, l, lc, good_cnt, ret_val = 0;
1674         unsigned long time;
1675
1676         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1677
1678         /*
1679          * Calculate the loop count based on the largest descriptor ring
1680          * The idea is to wrap the largest ring a number of times using 64
1681          * send/receive pairs during each loop
1682          */
1683
1684         if (rx_ring->count <= tx_ring->count)
1685                 lc = ((tx_ring->count / 64) * 2) + 1;
1686         else
1687                 lc = ((rx_ring->count / 64) * 2) + 1;
1688
1689         k = l = 0;
1690         for (j = 0; j <= lc; j++) {
1691                 for (i = 0; i < 64; i++) {
1692                         ixgbe_create_lbtest_frame(
1693                                         tx_ring->tx_buffer_info[k].skb,
1694                                         1024);
1695                         pci_dma_sync_single_for_device(pdev,
1696                                 tx_ring->tx_buffer_info[k].dma,
1697                                 tx_ring->tx_buffer_info[k].length,
1698                                 PCI_DMA_TODEVICE);
1699                         if (unlikely(++k == tx_ring->count))
1700                                 k = 0;
1701                 }
1702                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1703                 msleep(200);
1704                 /* set the start time for the receive */
1705                 time = jiffies;
1706                 good_cnt = 0;
1707                 do {
1708                         /* receive the sent packets */
1709                         pci_dma_sync_single_for_cpu(pdev,
1710                                         rx_ring->rx_buffer_info[l].dma,
1711                                         IXGBE_RXBUFFER_2048,
1712                                         PCI_DMA_FROMDEVICE);
1713                         ret_val = ixgbe_check_lbtest_frame(
1714                                         rx_ring->rx_buffer_info[l].skb, 1024);
1715                         if (!ret_val)
1716                                 good_cnt++;
1717                         if (++l == rx_ring->count)
1718                                 l = 0;
1719                         /*
1720                          * time + 20 msecs (200 msecs on 2.4) is more than
1721                          * enough time to complete the receives, if it's
1722                          * exceeded, break and error off
1723                          */
1724                 } while (good_cnt < 64 && jiffies < (time + 20));
1725                 if (good_cnt != 64) {
1726                         /* ret_val is the same as mis-compare */
1727                         ret_val = 13;
1728                         break;
1729                 }
1730                 if (jiffies >= (time + 20)) {
1731                         /* Error code for time out error */
1732                         ret_val = 14;
1733                         break;
1734                 }
1735         }
1736
1737         return ret_val;
1738 }
1739
1740 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1741 {
1742         *data = ixgbe_setup_desc_rings(adapter);
1743         if (*data)
1744                 goto out;
1745         *data = ixgbe_setup_loopback_test(adapter);
1746         if (*data)
1747                 goto err_loopback;
1748         *data = ixgbe_run_loopback_test(adapter);
1749         ixgbe_loopback_cleanup(adapter);
1750
1751 err_loopback:
1752         ixgbe_free_desc_rings(adapter);
1753 out:
1754         return *data;
1755 }
1756
1757 static void ixgbe_diag_test(struct net_device *netdev,
1758                             struct ethtool_test *eth_test, u64 *data)
1759 {
1760         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1761         bool if_running = netif_running(netdev);
1762
1763         set_bit(__IXGBE_TESTING, &adapter->state);
1764         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1765                 /* Offline tests */
1766
1767                 DPRINTK(HW, INFO, "offline testing starting\n");
1768
1769                 /* Link test performed before hardware reset so autoneg doesn't
1770                  * interfere with test result */
1771                 if (ixgbe_link_test(adapter, &data[4]))
1772                         eth_test->flags |= ETH_TEST_FL_FAILED;
1773
1774                 if (if_running)
1775                         /* indicate we're in test mode */
1776                         dev_close(netdev);
1777                 else
1778                         ixgbe_reset(adapter);
1779
1780                 DPRINTK(HW, INFO, "register testing starting\n");
1781                 if (ixgbe_reg_test(adapter, &data[0]))
1782                         eth_test->flags |= ETH_TEST_FL_FAILED;
1783
1784                 ixgbe_reset(adapter);
1785                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1786                 if (ixgbe_eeprom_test(adapter, &data[1]))
1787                         eth_test->flags |= ETH_TEST_FL_FAILED;
1788
1789                 ixgbe_reset(adapter);
1790                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1791                 if (ixgbe_intr_test(adapter, &data[2]))
1792                         eth_test->flags |= ETH_TEST_FL_FAILED;
1793
1794                 ixgbe_reset(adapter);
1795                 DPRINTK(HW, INFO, "loopback testing starting\n");
1796                 if (ixgbe_loopback_test(adapter, &data[3]))
1797                         eth_test->flags |= ETH_TEST_FL_FAILED;
1798
1799                 ixgbe_reset(adapter);
1800
1801                 clear_bit(__IXGBE_TESTING, &adapter->state);
1802                 if (if_running)
1803                         dev_open(netdev);
1804         } else {
1805                 DPRINTK(HW, INFO, "online testing starting\n");
1806                 /* Online tests */
1807                 if (ixgbe_link_test(adapter, &data[4]))
1808                         eth_test->flags |= ETH_TEST_FL_FAILED;
1809
1810                 /* Online tests aren't run; pass by default */
1811                 data[0] = 0;
1812                 data[1] = 0;
1813                 data[2] = 0;
1814                 data[3] = 0;
1815
1816                 clear_bit(__IXGBE_TESTING, &adapter->state);
1817         }
1818         msleep_interruptible(4 * 1000);
1819 }
1820
1821 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1822                                struct ethtool_wolinfo *wol)
1823 {
1824         struct ixgbe_hw *hw = &adapter->hw;
1825         int retval = 1;
1826
1827         switch(hw->device_id) {
1828         case IXGBE_DEV_ID_82599_KX4:
1829                 retval = 0;
1830                 break;
1831         default:
1832                 wol->supported = 0;
1833         }
1834
1835         return retval;
1836 }
1837
1838 static void ixgbe_get_wol(struct net_device *netdev,
1839                           struct ethtool_wolinfo *wol)
1840 {
1841         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1842
1843         wol->supported = WAKE_UCAST | WAKE_MCAST |
1844                          WAKE_BCAST | WAKE_MAGIC;
1845         wol->wolopts = 0;
1846
1847         if (ixgbe_wol_exclusion(adapter, wol) ||
1848             !device_can_wakeup(&adapter->pdev->dev))
1849                 return;
1850
1851         if (adapter->wol & IXGBE_WUFC_EX)
1852                 wol->wolopts |= WAKE_UCAST;
1853         if (adapter->wol & IXGBE_WUFC_MC)
1854                 wol->wolopts |= WAKE_MCAST;
1855         if (adapter->wol & IXGBE_WUFC_BC)
1856                 wol->wolopts |= WAKE_BCAST;
1857         if (adapter->wol & IXGBE_WUFC_MAG)
1858                 wol->wolopts |= WAKE_MAGIC;
1859
1860         return;
1861 }
1862
1863 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1864 {
1865         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1866
1867         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1868                 return -EOPNOTSUPP;
1869
1870         if (ixgbe_wol_exclusion(adapter, wol))
1871                 return wol->wolopts ? -EOPNOTSUPP : 0;
1872
1873         adapter->wol = 0;
1874
1875         if (wol->wolopts & WAKE_UCAST)
1876                 adapter->wol |= IXGBE_WUFC_EX;
1877         if (wol->wolopts & WAKE_MCAST)
1878                 adapter->wol |= IXGBE_WUFC_MC;
1879         if (wol->wolopts & WAKE_BCAST)
1880                 adapter->wol |= IXGBE_WUFC_BC;
1881         if (wol->wolopts & WAKE_MAGIC)
1882                 adapter->wol |= IXGBE_WUFC_MAG;
1883
1884         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1885
1886         return 0;
1887 }
1888
1889 static int ixgbe_nway_reset(struct net_device *netdev)
1890 {
1891         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1892
1893         if (netif_running(netdev))
1894                 ixgbe_reinit_locked(adapter);
1895
1896         return 0;
1897 }
1898
1899 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1900 {
1901         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1902         struct ixgbe_hw *hw = &adapter->hw;
1903         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1904         u32 i;
1905
1906         if (!data || data > 300)
1907                 data = 300;
1908
1909         for (i = 0; i < (data * 1000); i += 400) {
1910                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1911                 msleep_interruptible(200);
1912                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1913                 msleep_interruptible(200);
1914         }
1915
1916         /* Restore LED settings */
1917         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1918
1919         return 0;
1920 }
1921
1922 static int ixgbe_get_coalesce(struct net_device *netdev,
1923                               struct ethtool_coalesce *ec)
1924 {
1925         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1926
1927         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1928
1929         /* only valid if in constant ITR mode */
1930         switch (adapter->itr_setting) {
1931         case 0:
1932                 /* throttling disabled */
1933                 ec->rx_coalesce_usecs = 0;
1934                 break;
1935         case 1:
1936                 /* dynamic ITR mode */
1937                 ec->rx_coalesce_usecs = 1;
1938                 break;
1939         default:
1940                 /* fixed interrupt rate mode */
1941                 ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
1942                 break;
1943         }
1944         return 0;
1945 }
1946
1947 static int ixgbe_set_coalesce(struct net_device *netdev,
1948                               struct ethtool_coalesce *ec)
1949 {
1950         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1951         struct ixgbe_q_vector *q_vector;
1952         int i;
1953
1954         if (ec->tx_max_coalesced_frames_irq)
1955                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1956
1957         if (ec->rx_coalesce_usecs > 1) {
1958                 /* check the limits */
1959                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1960                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1961                         return -EINVAL;
1962
1963                 /* store the value in ints/second */
1964                 adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
1965
1966                 /* static value of interrupt rate */
1967                 adapter->itr_setting = adapter->eitr_param;
1968                 /* clear the lower bit as its used for dynamic state */
1969                 adapter->itr_setting &= ~1;
1970         } else if (ec->rx_coalesce_usecs == 1) {
1971                 /* 1 means dynamic mode */
1972                 adapter->eitr_param = 20000;
1973                 adapter->itr_setting = 1;
1974         } else {
1975                 /*
1976                  * any other value means disable eitr, which is best
1977                  * served by setting the interrupt rate very high
1978                  */
1979                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
1980                         adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE;
1981                 else
1982                         adapter->eitr_param = IXGBE_MAX_INT_RATE;
1983                 adapter->itr_setting = 0;
1984         }
1985
1986         /* MSI/MSIx Interrupt Mode */
1987         if (adapter->flags &
1988             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
1989                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1990                 for (i = 0; i < num_vectors; i++) {
1991                         q_vector = adapter->q_vector[i];
1992                         if (q_vector->txr_count && !q_vector->rxr_count)
1993                                 /* tx vector gets half the rate */
1994                                 q_vector->eitr = (adapter->eitr_param >> 1);
1995                         else
1996                                 /* rx only or mixed */
1997                                 q_vector->eitr = adapter->eitr_param;
1998                         ixgbe_write_eitr(q_vector);
1999                 }
2000         /* Legacy Interrupt Mode */
2001         } else {
2002                 q_vector = adapter->q_vector[0];
2003                 q_vector->eitr = adapter->eitr_param;
2004                 ixgbe_write_eitr(q_vector);
2005         }
2006
2007         return 0;
2008 }
2009
2010 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2011 {
2012         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2013
2014         ethtool_op_set_flags(netdev, data);
2015
2016         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2017                 return 0;
2018
2019         /* if state changes we need to update adapter->flags and reset */
2020         if ((!!(data & ETH_FLAG_LRO)) !=
2021             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2022                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2023                 if (netif_running(netdev))
2024                         ixgbe_reinit_locked(adapter);
2025                 else
2026                         ixgbe_reset(adapter);
2027         }
2028         return 0;
2029
2030 }
2031
2032 static const struct ethtool_ops ixgbe_ethtool_ops = {
2033         .get_settings           = ixgbe_get_settings,
2034         .set_settings           = ixgbe_set_settings,
2035         .get_drvinfo            = ixgbe_get_drvinfo,
2036         .get_regs_len           = ixgbe_get_regs_len,
2037         .get_regs               = ixgbe_get_regs,
2038         .get_wol                = ixgbe_get_wol,
2039         .set_wol                = ixgbe_set_wol,
2040         .nway_reset             = ixgbe_nway_reset,
2041         .get_link               = ethtool_op_get_link,
2042         .get_eeprom_len         = ixgbe_get_eeprom_len,
2043         .get_eeprom             = ixgbe_get_eeprom,
2044         .get_ringparam          = ixgbe_get_ringparam,
2045         .set_ringparam          = ixgbe_set_ringparam,
2046         .get_pauseparam         = ixgbe_get_pauseparam,
2047         .set_pauseparam         = ixgbe_set_pauseparam,
2048         .get_rx_csum            = ixgbe_get_rx_csum,
2049         .set_rx_csum            = ixgbe_set_rx_csum,
2050         .get_tx_csum            = ixgbe_get_tx_csum,
2051         .set_tx_csum            = ixgbe_set_tx_csum,
2052         .get_sg                 = ethtool_op_get_sg,
2053         .set_sg                 = ethtool_op_set_sg,
2054         .get_msglevel           = ixgbe_get_msglevel,
2055         .set_msglevel           = ixgbe_set_msglevel,
2056         .get_tso                = ethtool_op_get_tso,
2057         .set_tso                = ixgbe_set_tso,
2058         .self_test              = ixgbe_diag_test,
2059         .get_strings            = ixgbe_get_strings,
2060         .phys_id                = ixgbe_phys_id,
2061         .get_sset_count         = ixgbe_get_sset_count,
2062         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2063         .get_coalesce           = ixgbe_get_coalesce,
2064         .set_coalesce           = ixgbe_set_coalesce,
2065         .get_flags              = ethtool_op_get_flags,
2066         .set_flags              = ixgbe_set_flags,
2067 };
2068
2069 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2070 {
2071         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2072 }