drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #include <linux/kernel.h>
  65 #include <linux/string.h>
  66 #include <linux/errno.h>
  67 #include <linux/unistd.h>
  68 #include <linux/slab.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/spinlock.h>
  77 #include <linux/mm.h>
  78 #include <linux/of_mdio.h>
  79 #include <linux/of_platform.h>
  80 #include <linux/ip.h>
  81 #include <linux/tcp.h>
  82 #include <linux/udp.h>
  83 #include <linux/in.h>
  84
  85 #include <asm/io.h>
  86 #include <asm/irq.h>
  87 #include <asm/uaccess.h>
  88 #include <linux/module.h>
  89 #include <linux/dma-mapping.h>
  90 #include <linux/crc32.h>
  91 #include <linux/mii.h>
  92 #include <linux/phy.h>
  93 #include <linux/phy_fixed.h>
  94 #include <linux/of.h>
  95
  96 #include "gianfar.h"
  97 #include "fsl_pq_mdio.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #undef BRIEF_GFAR_ERRORS
 101 #undef VERBOSE_GFAR_ERRORS
 102
 103 const char gfar_driver_name[] = "Gianfar Ethernet";
 104 const char gfar_driver_version[] = "1.3";
 105
 106 static int gfar_enet_open(struct net_device *dev);
 107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 108 static void gfar_reset_task(struct work_struct *work);
 109 static void gfar_timeout(struct net_device *dev);
 110 static int gfar_close(struct net_device *dev);
 111 struct sk_buff *gfar_new_skb(struct net_device *dev);
 112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 113                 struct sk_buff *skb);
 114 static int gfar_set_mac_address(struct net_device *dev);
 115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 116 static irqreturn_t gfar_error(int irq, void *dev_id);
 117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 119 static void adjust_link(struct net_device *dev);
 120 static void init_registers(struct net_device *dev);
 121 static int init_phy(struct net_device *dev);
 122 static int gfar_probe(struct of_device *ofdev,
 123                 const struct of_device_id *match);
 124 static int gfar_remove(struct of_device *ofdev);
 125 static void free_skb_resources(struct gfar_private *priv);
 126 static void gfar_set_multi(struct net_device *dev);
 127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 128 static void gfar_configure_serdes(struct net_device *dev);
 129 static int gfar_poll(struct napi_struct *napi, int budget);
 130 #ifdef CONFIG_NET_POLL_CONTROLLER
 131 static void gfar_netpoll(struct net_device *dev);
 132 #endif
 133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 134 static int gfar_clean_tx_ring(struct net_device *dev);
 135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 136                               int amount_pull);
 137 static void gfar_vlan_rx_register(struct net_device *netdev,
 138                                 struct vlan_group *grp);
 139 void gfar_halt(struct net_device *dev);
 140 static void gfar_halt_nodisable(struct net_device *dev);
 141 void gfar_start(struct net_device *dev);
 142 static void gfar_clear_exact_match(struct net_device *dev);
 143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static const struct net_device_ops gfar_netdev_ops = {
 151         .ndo_open = gfar_enet_open,
 152         .ndo_start_xmit = gfar_start_xmit,
 153         .ndo_stop = gfar_close,
 154         .ndo_change_mtu = gfar_change_mtu,
 155         .ndo_set_multicast_list = gfar_set_multi,
 156         .ndo_tx_timeout = gfar_timeout,
 157         .ndo_do_ioctl = gfar_ioctl,
 158         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 159         .ndo_set_mac_address = eth_mac_addr,
 160         .ndo_validate_addr = eth_validate_addr,
 161 #ifdef CONFIG_NET_POLL_CONTROLLER
 162         .ndo_poll_controller = gfar_netpoll,
 163 #endif
 164 };
 165
 166 /* Returns 1 if incoming frames use an FCB */
 167 static inline int gfar_uses_fcb(struct gfar_private *priv)
 168 {
 169         return priv->vlgrp || priv->rx_csum_enable;
 170 }
 171
 172 static int gfar_of_init(struct net_device *dev)
 173 {
 174         const char *model;
 175         const char *ctype;
 176         const void *mac_addr;
 177         u64 addr, size;
 178         int err = 0;
 179         struct gfar_private *priv = netdev_priv(dev);
 180         struct device_node *np = priv->node;
 181         const u32 *stash;
 182         const u32 *stash_len;
 183         const u32 *stash_idx;
 184
 185         if (!np || !of_device_is_available(np))
 186                 return -ENODEV;
 187
 188         /* get a pointer to the register memory */
 189         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 190         priv->regs = ioremap(addr, size);
 191
 192         if (priv->regs == NULL)
 193                 return -ENOMEM;
 194
 195         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
 196
 197         model = of_get_property(np, "model", NULL);
 198
 199         /* If we aren't the FEC we have multiple interrupts */
 200         if (model && strcasecmp(model, "FEC")) {
 201                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
 202
 203                 priv->interruptError = irq_of_parse_and_map(np, 2);
 204
 205                 if (priv->interruptTransmit < 0 ||
 206                                 priv->interruptReceive < 0 ||
 207                                 priv->interruptError < 0) {
 208                         err = -EINVAL;
 209                         goto err_out;
 210                 }
 211         }
 212
 213         stash = of_get_property(np, "bd-stash", NULL);
 214
 215         if(stash) {
 216                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 217                 priv->bd_stash_en = 1;
 218         }
 219
 220         stash_len = of_get_property(np, "rx-stash-len", NULL);
 221
 222         if (stash_len)
 223                 priv->rx_stash_size = *stash_len;
 224
 225         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 226
 227         if (stash_idx)
 228                 priv->rx_stash_index = *stash_idx;
 229
 230         if (stash_len || stash_idx)
 231                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 232
 233         mac_addr = of_get_mac_address(np);
 234         if (mac_addr)
 235                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 236
 237         if (model && !strcasecmp(model, "TSEC"))
 238                 priv->device_flags =
 239                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 240                         FSL_GIANFAR_DEV_HAS_COALESCE |
 241                         FSL_GIANFAR_DEV_HAS_RMON |
 242                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 243         if (model && !strcasecmp(model, "eTSEC"))
 244                 priv->device_flags =
 245                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 246                         FSL_GIANFAR_DEV_HAS_COALESCE |
 247                         FSL_GIANFAR_DEV_HAS_RMON |
 248                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 249                         FSL_GIANFAR_DEV_HAS_PADDING |
 250                         FSL_GIANFAR_DEV_HAS_CSUM |
 251                         FSL_GIANFAR_DEV_HAS_VLAN |
 252                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 253                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 254
 255         ctype = of_get_property(np, "phy-connection-type", NULL);
 256
 257         /* We only care about rgmii-id.  The rest are autodetected */
 258         if (ctype && !strcmp(ctype, "rgmii-id"))
 259                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 260         else
 261                 priv->interface = PHY_INTERFACE_MODE_MII;
 262
 263         if (of_get_property(np, "fsl,magic-packet", NULL))
 264                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 265
 266         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 267
 268         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 269         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 270
 271         return 0;
 272
 273 err_out:
 274         iounmap(priv->regs);
 275         return err;
 276 }
 277
 278 /* Ioctl MII Interface */
 279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 280 {
 281         struct gfar_private *priv = netdev_priv(dev);
 282
 283         if (!netif_running(dev))
 284                 return -EINVAL;
 285
 286         if (!priv->phydev)
 287                 return -ENODEV;
 288
 289         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 290 }
 291
 292 /* Set up the ethernet device structure, private data,
 293  * and anything else we need before we start */
 294 static int gfar_probe(struct of_device *ofdev,
 295                 const struct of_device_id *match)
 296 {
 297         u32 tempval;
 298         struct net_device *dev = NULL;
 299         struct gfar_private *priv = NULL;
 300         int err = 0;
 301         int len_devname;
 302
 303         /* Create an ethernet device instance */
 304         dev = alloc_etherdev(sizeof (*priv));
 305
 306         if (NULL == dev)
 307                 return -ENOMEM;
 308
 309         priv = netdev_priv(dev);
 310         priv->ndev = dev;
 311         priv->ofdev = ofdev;
 312         priv->node = ofdev->node;
 313         SET_NETDEV_DEV(dev, &ofdev->dev);
 314
 315         err = gfar_of_init(dev);
 316
 317         if (err)
 318                 goto regs_fail;
 319
 320         spin_lock_init(&priv->txlock);
 321         spin_lock_init(&priv->rxlock);
 322         spin_lock_init(&priv->bflock);
 323         INIT_WORK(&priv->reset_task, gfar_reset_task);
 324
 325         dev_set_drvdata(&ofdev->dev, priv);
 326
 327         /* Stop the DMA engine now, in case it was running before */
 328         /* (The firmware could have used it, and left it running). */
 329         gfar_halt(dev);
 330
 331         /* Reset MAC layer */
 332         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 333
 334         /* We need to delay at least 3 TX clocks */
 335         udelay(2);
 336
 337         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 338         gfar_write(&priv->regs->maccfg1, tempval);
 339
 340         /* Initialize MACCFG2. */
 341         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 342
 343         /* Initialize ECNTRL */
 344         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 345
 346         /* Set the dev->base_addr to the gfar reg region */
 347         dev->base_addr = (unsigned long) (priv->regs);
 348
 349         SET_NETDEV_DEV(dev, &ofdev->dev);
 350
 351         /* Fill in the dev structure */
 352         dev->watchdog_timeo = TX_TIMEOUT;
 353         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 354         dev->mtu = 1500;
 355
 356         dev->netdev_ops = &gfar_netdev_ops;
 357         dev->ethtool_ops = &gfar_ethtool_ops;
 358
 359         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 360                 priv->rx_csum_enable = 1;
 361                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 362         } else
 363                 priv->rx_csum_enable = 0;
 364
 365         priv->vlgrp = NULL;
 366
 367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 368                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 369
 370         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 371                 priv->extended_hash = 1;
 372                 priv->hash_width = 9;
 373
 374                 priv->hash_regs[0] = &priv->regs->igaddr0;
 375                 priv->hash_regs[1] = &priv->regs->igaddr1;
 376                 priv->hash_regs[2] = &priv->regs->igaddr2;
 377                 priv->hash_regs[3] = &priv->regs->igaddr3;
 378                 priv->hash_regs[4] = &priv->regs->igaddr4;
 379                 priv->hash_regs[5] = &priv->regs->igaddr5;
 380                 priv->hash_regs[6] = &priv->regs->igaddr6;
 381                 priv->hash_regs[7] = &priv->regs->igaddr7;
 382                 priv->hash_regs[8] = &priv->regs->gaddr0;
 383                 priv->hash_regs[9] = &priv->regs->gaddr1;
 384                 priv->hash_regs[10] = &priv->regs->gaddr2;
 385                 priv->hash_regs[11] = &priv->regs->gaddr3;
 386                 priv->hash_regs[12] = &priv->regs->gaddr4;
 387                 priv->hash_regs[13] = &priv->regs->gaddr5;
 388                 priv->hash_regs[14] = &priv->regs->gaddr6;
 389                 priv->hash_regs[15] = &priv->regs->gaddr7;
 390
 391         } else {
 392                 priv->extended_hash = 0;
 393                 priv->hash_width = 8;
 394
 395                 priv->hash_regs[0] = &priv->regs->gaddr0;
 396                 priv->hash_regs[1] = &priv->regs->gaddr1;
 397                 priv->hash_regs[2] = &priv->regs->gaddr2;
 398                 priv->hash_regs[3] = &priv->regs->gaddr3;
 399                 priv->hash_regs[4] = &priv->regs->gaddr4;
 400                 priv->hash_regs[5] = &priv->regs->gaddr5;
 401                 priv->hash_regs[6] = &priv->regs->gaddr6;
 402                 priv->hash_regs[7] = &priv->regs->gaddr7;
 403         }
 404
 405         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 406                 priv->padding = DEFAULT_PADDING;
 407         else
 408                 priv->padding = 0;
 409
 410         if (dev->features & NETIF_F_IP_CSUM)
 411                 dev->hard_header_len += GMAC_FCB_LEN;
 412
 413         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 414         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 415         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 416         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
 417
 418         priv->txcoalescing = DEFAULT_TX_COALESCE;
 419         priv->txic = DEFAULT_TXIC;
 420         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 421         priv->rxic = DEFAULT_RXIC;
 422
 423         /* Enable most messages by default */
 424         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 425
 426         /* Carrier starts down, phylib will bring it up */
 427         netif_carrier_off(dev);
 428
 429         err = register_netdev(dev);
 430
 431         if (err) {
 432                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 433                                 dev->name);
 434                 goto register_fail;
 435         }
 436
 437         device_init_wakeup(&dev->dev,
 438                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 439
 440         /* fill out IRQ number and name fields */
 441         len_devname = strlen(dev->name);
 442         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
 443         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 444                 strncpy(&priv->int_name_tx[len_devname],
 445                         "_tx", sizeof("_tx") + 1);
 446
 447                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
 448                 strncpy(&priv->int_name_rx[len_devname],
 449                         "_rx", sizeof("_rx") + 1);
 450
 451                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
 452                 strncpy(&priv->int_name_er[len_devname],
 453                         "_er", sizeof("_er") + 1);
 454         } else
 455                 priv->int_name_tx[len_devname] = '\0';
 456
 457         /* Create all the sysfs files */
 458         gfar_init_sysfs(dev);
 459
 460         /* Print out the device info */
 461         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 462
 463         /* Even more device info helps when determining which kernel */
 464         /* provided which set of benchmarks. */
 465         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 466         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 467                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 468
 469         return 0;
 470
 471 register_fail:
 472         iounmap(priv->regs);
 473 regs_fail:
 474         if (priv->phy_node)
 475                 of_node_put(priv->phy_node);
 476         if (priv->tbi_node)
 477                 of_node_put(priv->tbi_node);
 478         free_netdev(dev);
 479         return err;
 480 }
 481
 482 static int gfar_remove(struct of_device *ofdev)
 483 {
 484         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 485
 486         if (priv->phy_node)
 487                 of_node_put(priv->phy_node);
 488         if (priv->tbi_node)
 489                 of_node_put(priv->tbi_node);
 490
 491         dev_set_drvdata(&ofdev->dev, NULL);
 492
 493         unregister_netdev(priv->ndev);
 494         iounmap(priv->regs);
 495         free_netdev(priv->ndev);
 496
 497         return 0;
 498 }
 499
 500 #ifdef CONFIG_PM
 501 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
 502 {
 503         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 504         struct net_device *dev = priv->ndev;
 505         unsigned long flags;
 506         u32 tempval;
 507
 508         int magic_packet = priv->wol_en &&
 509                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 510
 511         netif_device_detach(dev);
 512
 513         if (netif_running(dev)) {
 514                 spin_lock_irqsave(&priv->txlock, flags);
 515                 spin_lock(&priv->rxlock);
 516
 517                 gfar_halt_nodisable(dev);
 518
 519                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 520                 tempval = gfar_read(&priv->regs->maccfg1);
 521
 522                 tempval &= ~MACCFG1_TX_EN;
 523
 524                 if (!magic_packet)
 525                         tempval &= ~MACCFG1_RX_EN;
 526
 527                 gfar_write(&priv->regs->maccfg1, tempval);
 528
 529                 spin_unlock(&priv->rxlock);
 530                 spin_unlock_irqrestore(&priv->txlock, flags);
 531
 532                 napi_disable(&priv->napi);
 533
 534                 if (magic_packet) {
 535                         /* Enable interrupt on Magic Packet */
 536                         gfar_write(&priv->regs->imask, IMASK_MAG);
 537
 538                         /* Enable Magic Packet mode */
 539                         tempval = gfar_read(&priv->regs->maccfg2);
 540                         tempval |= MACCFG2_MPEN;
 541                         gfar_write(&priv->regs->maccfg2, tempval);
 542                 } else {
 543                         phy_stop(priv->phydev);
 544                 }
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int gfar_resume(struct of_device *ofdev)
 551 {
 552         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 553         struct net_device *dev = priv->ndev;
 554         unsigned long flags;
 555         u32 tempval;
 556         int magic_packet = priv->wol_en &&
 557                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 558
 559         if (!netif_running(dev)) {
 560                 netif_device_attach(dev);
 561                 return 0;
 562         }
 563
 564         if (!magic_packet && priv->phydev)
 565                 phy_start(priv->phydev);
 566
 567         /* Disable Magic Packet mode, in case something
 568          * else woke us up.
 569          */
 570
 571         spin_lock_irqsave(&priv->txlock, flags);
 572         spin_lock(&priv->rxlock);
 573
 574         tempval = gfar_read(&priv->regs->maccfg2);
 575         tempval &= ~MACCFG2_MPEN;
 576         gfar_write(&priv->regs->maccfg2, tempval);
 577
 578         gfar_start(dev);
 579
 580         spin_unlock(&priv->rxlock);
 581         spin_unlock_irqrestore(&priv->txlock, flags);
 582
 583         netif_device_attach(dev);
 584
 585         napi_enable(&priv->napi);
 586
 587         return 0;
 588 }
 589 #else
 590 #define gfar_suspend NULL
 591 #define gfar_resume NULL
 592 #endif
 593
 594 /* Reads the controller's registers to determine what interface
 595  * connects it to the PHY.
 596  */
 597 static phy_interface_t gfar_get_interface(struct net_device *dev)
 598 {
 599         struct gfar_private *priv = netdev_priv(dev);
 600         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 601
 602         if (ecntrl & ECNTRL_SGMII_MODE)
 603                 return PHY_INTERFACE_MODE_SGMII;
 604
 605         if (ecntrl & ECNTRL_TBI_MODE) {
 606                 if (ecntrl & ECNTRL_REDUCED_MODE)
 607                         return PHY_INTERFACE_MODE_RTBI;
 608                 else
 609                         return PHY_INTERFACE_MODE_TBI;
 610         }
 611
 612         if (ecntrl & ECNTRL_REDUCED_MODE) {
 613                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 614                         return PHY_INTERFACE_MODE_RMII;
 615                 else {
 616                         phy_interface_t interface = priv->interface;
 617
 618                         /*
 619                          * This isn't autodetected right now, so it must
 620                          * be set by the device tree or platform code.
 621                          */
 622                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 623                                 return PHY_INTERFACE_MODE_RGMII_ID;
 624
 625                         return PHY_INTERFACE_MODE_RGMII;
 626                 }
 627         }
 628
 629         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 630                 return PHY_INTERFACE_MODE_GMII;
 631
 632         return PHY_INTERFACE_MODE_MII;
 633 }
 634
 635
 636 /* Initializes driver's PHY state, and attaches to the PHY.
 637  * Returns 0 on success.
 638  */
 639 static int init_phy(struct net_device *dev)
 640 {
 641         struct gfar_private *priv = netdev_priv(dev);
 642         uint gigabit_support =
 643                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 644                 SUPPORTED_1000baseT_Full : 0;
 645         phy_interface_t interface;
 646
 647         priv->oldlink = 0;
 648         priv->oldspeed = 0;
 649         priv->oldduplex = -1;
 650
 651         interface = gfar_get_interface(dev);
 652
 653         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
 654                                       interface);
 655         if (!priv->phydev)
 656                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
 657                                                          interface);
 658         if (!priv->phydev) {
 659                 dev_err(&dev->dev, "could not attach to PHY\n");
 660                 return -ENODEV;
 661         }
 662
 663         if (interface == PHY_INTERFACE_MODE_SGMII)
 664                 gfar_configure_serdes(dev);
 665
 666         /* Remove any features not supported by the controller */
 667         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 668         priv->phydev->advertising = priv->phydev->supported;
 669
 670         return 0;
 671 }
 672
 673 /*
 674  * Initialize TBI PHY interface for communicating with the
 675  * SERDES lynx PHY on the chip.  We communicate with this PHY
 676  * through the MDIO bus on each controller, treating it as a
 677  * "normal" PHY at the address found in the TBIPA register.  We assume
 678  * that the TBIPA register is valid.  Either the MDIO bus code will set
 679  * it to a value that doesn't conflict with other PHYs on the bus, or the
 680  * value doesn't matter, as there are no other PHYs on the bus.
 681  */
 682 static void gfar_configure_serdes(struct net_device *dev)
 683 {
 684         struct gfar_private *priv = netdev_priv(dev);
 685         struct phy_device *tbiphy;
 686
 687         if (!priv->tbi_node) {
 688                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
 689                                     "device tree specify a tbi-handle\n");
 690                 return;
 691         }
 692
 693         tbiphy = of_phy_find_device(priv->tbi_node);
 694         if (!tbiphy) {
 695                 dev_err(&dev->dev, "error: Could not get TBI device\n");
 696                 return;
 697         }
 698
 699         /*
 700          * If the link is already up, we must already be ok, and don't need to
 701          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 702          * everything for us?  Resetting it takes the link down and requires
 703          * several seconds for it to come back.
 704          */
 705         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
 706                 return;
 707
 708         /* Single clk mode, mii mode off(for serdes communication) */
 709         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 710
 711         phy_write(tbiphy, MII_ADVERTISE,
 712                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 713                         ADVERTISE_1000XPSE_ASYM);
 714
 715         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
 716                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 717 }
 718
 719 static void init_registers(struct net_device *dev)
 720 {
 721         struct gfar_private *priv = netdev_priv(dev);
 722
 723         /* Clear IEVENT */
 724         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 725
 726         /* Initialize IMASK */
 727         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 728
 729         /* Init hash registers to zero */
 730         gfar_write(&priv->regs->igaddr0, 0);
 731         gfar_write(&priv->regs->igaddr1, 0);
 732         gfar_write(&priv->regs->igaddr2, 0);
 733         gfar_write(&priv->regs->igaddr3, 0);
 734         gfar_write(&priv->regs->igaddr4, 0);
 735         gfar_write(&priv->regs->igaddr5, 0);
 736         gfar_write(&priv->regs->igaddr6, 0);
 737         gfar_write(&priv->regs->igaddr7, 0);
 738
 739         gfar_write(&priv->regs->gaddr0, 0);
 740         gfar_write(&priv->regs->gaddr1, 0);
 741         gfar_write(&priv->regs->gaddr2, 0);
 742         gfar_write(&priv->regs->gaddr3, 0);
 743         gfar_write(&priv->regs->gaddr4, 0);
 744         gfar_write(&priv->regs->gaddr5, 0);
 745         gfar_write(&priv->regs->gaddr6, 0);
 746         gfar_write(&priv->regs->gaddr7, 0);
 747
 748         /* Zero out the rmon mib registers if it has them */
 749         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 750                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 751
 752                 /* Mask off the CAM interrupts */
 753                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 754                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 755         }
 756
 757         /* Initialize the max receive buffer length */
 758         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 759
 760         /* Initialize the Minimum Frame Length Register */
 761         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 762 }
 763
 764
 765 /* Halt the receive and transmit queues */
 766 static void gfar_halt_nodisable(struct net_device *dev)
 767 {
 768         struct gfar_private *priv = netdev_priv(dev);
 769         struct gfar __iomem *regs = priv->regs;
 770         u32 tempval;
 771
 772         /* Mask all interrupts */
 773         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 774
 775         /* Clear all interrupts */
 776         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 777
 778         /* Stop the DMA, and wait for it to stop */
 779         tempval = gfar_read(&priv->regs->dmactrl);
 780         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 781             != (DMACTRL_GRS | DMACTRL_GTS)) {
 782                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 783                 gfar_write(&priv->regs->dmactrl, tempval);
 784
 785                 while (!(gfar_read(&priv->regs->ievent) &
 786                          (IEVENT_GRSC | IEVENT_GTSC)))
 787                         cpu_relax();
 788         }
 789 }
 790
 791 /* Halt the receive and transmit queues */
 792 void gfar_halt(struct net_device *dev)
 793 {
 794         struct gfar_private *priv = netdev_priv(dev);
 795         struct gfar __iomem *regs = priv->regs;
 796         u32 tempval;
 797
 798         gfar_halt_nodisable(dev);
 799
 800         /* Disable Rx and Tx */
 801         tempval = gfar_read(&regs->maccfg1);
 802         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 803         gfar_write(&regs->maccfg1, tempval);
 804 }
 805
 806 void stop_gfar(struct net_device *dev)
 807 {
 808         struct gfar_private *priv = netdev_priv(dev);
 809         unsigned long flags;
 810
 811         phy_stop(priv->phydev);
 812
 813         /* Lock it down */
 814         spin_lock_irqsave(&priv->txlock, flags);
 815         spin_lock(&priv->rxlock);
 816
 817         gfar_halt(dev);
 818
 819         spin_unlock(&priv->rxlock);
 820         spin_unlock_irqrestore(&priv->txlock, flags);
 821
 822         /* Free the IRQs */
 823         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 824                 free_irq(priv->interruptError, dev);
 825                 free_irq(priv->interruptTransmit, dev);
 826                 free_irq(priv->interruptReceive, dev);
 827         } else {
 828                 free_irq(priv->interruptTransmit, dev);
 829         }
 830
 831         free_skb_resources(priv);
 832 }
 833
 834 /* If there are any tx skbs or rx skbs still around, free them.
 835  * Then free tx_skbuff and rx_skbuff */
 836 static void free_skb_resources(struct gfar_private *priv)
 837 {
 838         struct device *dev = &priv->ofdev->dev;
 839         struct rxbd8 *rxbdp;
 840         struct txbd8 *txbdp;
 841         int i, j;
 842
 843         /* Go through all the buffer descriptors and free their data buffers */
 844         txbdp = priv->tx_bd_base;
 845
 846         if (!priv->tx_skbuff)
 847                 goto skip_tx_skbuff;
 848
 849         for (i = 0; i < priv->tx_ring_size; i++) {
 850                 if (!priv->tx_skbuff[i])
 851                         continue;
 852
 853                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
 854                                 txbdp->length, DMA_TO_DEVICE);
 855                 txbdp->lstatus = 0;
 856                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
 857                         txbdp++;
 858                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
 859                                         txbdp->length, DMA_TO_DEVICE);
 860                 }
 861                 txbdp++;
 862                 dev_kfree_skb_any(priv->tx_skbuff[i]);
 863                 priv->tx_skbuff[i] = NULL;
 864         }
 865
 866         kfree(priv->tx_skbuff);
 867 skip_tx_skbuff:
 868
 869         rxbdp = priv->rx_bd_base;
 870
 871         if (!priv->rx_skbuff)
 872                 goto skip_rx_skbuff;
 873
 874         for (i = 0; i < priv->rx_ring_size; i++) {
 875                 if (priv->rx_skbuff[i]) {
 876                         dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
 877                                          priv->rx_buffer_size,
 878                                         DMA_FROM_DEVICE);
 879                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 880                         priv->rx_skbuff[i] = NULL;
 881                 }
 882
 883                 rxbdp->lstatus = 0;
 884                 rxbdp->bufPtr = 0;
 885                 rxbdp++;
 886         }
 887
 888         kfree(priv->rx_skbuff);
 889 skip_rx_skbuff:
 890
 891         dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
 892                                sizeof(*rxbdp) * priv->rx_ring_size,
 893                           priv->tx_bd_base, gfar_read(&priv->regs->tbase0));
 894 }
 895
 896 void gfar_start(struct net_device *dev)
 897 {
 898         struct gfar_private *priv = netdev_priv(dev);
 899         struct gfar __iomem *regs = priv->regs;
 900         u32 tempval;
 901
 902         /* Enable Rx and Tx in MACCFG1 */
 903         tempval = gfar_read(&regs->maccfg1);
 904         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 905         gfar_write(&regs->maccfg1, tempval);
 906
 907         /* Initialize DMACTRL to have WWR and WOP */
 908         tempval = gfar_read(&priv->regs->dmactrl);
 909         tempval |= DMACTRL_INIT_SETTINGS;
 910         gfar_write(&priv->regs->dmactrl, tempval);
 911
 912         /* Make sure we aren't stopped */
 913         tempval = gfar_read(&priv->regs->dmactrl);
 914         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 915         gfar_write(&priv->regs->dmactrl, tempval);
 916
 917         /* Clear THLT/RHLT, so that the DMA starts polling now */
 918         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 919         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 920
 921         /* Unmask the interrupts we look for */
 922         gfar_write(&regs->imask, IMASK_DEFAULT);
 923
 924         dev->trans_start = jiffies;
 925 }
 926
 927 /* Bring the controller up and running */
 928 int startup_gfar(struct net_device *ndev)
 929 {
 930         struct txbd8 *txbdp;
 931         struct rxbd8 *rxbdp;
 932         dma_addr_t addr = 0;
 933         void *vaddr;
 934         int i;
 935         struct gfar_private *priv = netdev_priv(ndev);
 936         struct device *dev = &priv->ofdev->dev;
 937         struct gfar __iomem *regs = priv->regs;
 938         int err;
 939         u32 rctrl = 0;
 940         u32 tctrl = 0;
 941         u32 attrs = 0;
 942
 943         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 944
 945         /* Allocate memory for the buffer descriptors */
 946         vaddr = dma_alloc_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
 947                                         sizeof(*rxbdp) * priv->rx_ring_size,
 948                                    &addr, GFP_KERNEL);
 949         if (!vaddr) {
 950                 if (netif_msg_ifup(priv))
 951                         pr_err("%s: Could not allocate buffer descriptors!\n",
 952                                ndev->name);
 953                 return -ENOMEM;
 954         }
 955
 956         priv->tx_bd_base = vaddr;
 957
 958         /* enet DMA only understands physical addresses */
 959         gfar_write(&regs->tbase0, addr);
 960
 961         /* Start the rx descriptor ring where the tx ring leaves off */
 962         addr = addr + sizeof(*txbdp) * priv->tx_ring_size;
 963         vaddr = vaddr + sizeof(*txbdp) * priv->tx_ring_size;
 964         priv->rx_bd_base = vaddr;
 965         gfar_write(&regs->rbase0, addr);
 966
 967         /* Setup the skbuff rings */
 968         priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) *
 969                                   priv->tx_ring_size, GFP_KERNEL);
 970         if (!priv->tx_skbuff) {
 971                 if (netif_msg_ifup(priv))
 972                         pr_err("%s: Could not allocate tx_skbuff\n",
 973                                ndev->name);
 974                 err = -ENOMEM;
 975                 goto tx_skb_fail;
 976         }
 977
 978         for (i = 0; i < priv->tx_ring_size; i++)
 979                 priv->tx_skbuff[i] = NULL;
 980
 981         priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) *
 982                                   priv->rx_ring_size, GFP_KERNEL);
 983         if (!priv->rx_skbuff) {
 984                 if (netif_msg_ifup(priv))
 985                         pr_err("%s: Could not allocate rx_skbuff\n",
 986                                ndev->name);
 987                 err = -ENOMEM;
 988                 goto rx_skb_fail;
 989         }
 990
 991         for (i = 0; i < priv->rx_ring_size; i++)
 992                 priv->rx_skbuff[i] = NULL;
 993
 994         /* Initialize some variables in our dev structure */
 995         priv->num_txbdfree = priv->tx_ring_size;
 996         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 997         priv->cur_rx = priv->rx_bd_base;
 998         priv->skb_curtx = priv->skb_dirtytx = 0;
 999         priv->skb_currx = 0;
1000
1001         /* Initialize Transmit Descriptor Ring */
1002         txbdp = priv->tx_bd_base;
1003         for (i = 0; i < priv->tx_ring_size; i++) {
1004                 txbdp->lstatus = 0;
1005                 txbdp->bufPtr = 0;
1006                 txbdp++;
1007         }
1008
1009         /* Set the last descriptor in the ring to indicate wrap */
1010         txbdp--;
1011         txbdp->status |= TXBD_WRAP;
1012
1013         rxbdp = priv->rx_bd_base;
1014         for (i = 0; i < priv->rx_ring_size; i++) {
1015                 struct sk_buff *skb;
1016
1017                 skb = gfar_new_skb(ndev);
1018                 if (!skb) {
1019                         pr_err("%s: Can't allocate RX buffers\n", ndev->name);
1020                         err = -ENOMEM;
1021                         goto err_rxalloc_fail;
1022                 }
1023
1024                 priv->rx_skbuff[i] = skb;
1025
1026                 gfar_new_rxbdp(ndev, rxbdp, skb);
1027
1028                 rxbdp++;
1029         }
1030
1031         /* Set the last descriptor in the ring to wrap */
1032         rxbdp--;
1033         rxbdp->status |= RXBD_WRAP;
1034
1035         /* If the device has multiple interrupts, register for
1036          * them.  Otherwise, only register for the one */
1037         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1038                 /* Install our interrupt handlers for Error,
1039                  * Transmit, and Receive */
1040                 err = request_irq(priv->interruptError, gfar_error, 0,
1041                                   priv->int_name_er, ndev);
1042                 if (err) {
1043                         if (netif_msg_intr(priv))
1044                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1045                                        priv->interruptError);
1046                         goto err_irq_fail;
1047                 }
1048
1049                 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1050                                   priv->int_name_tx, ndev);
1051                 if (err) {
1052                         if (netif_msg_intr(priv))
1053                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1054                                        priv->interruptTransmit);
1055                         goto tx_irq_fail;
1056                 }
1057
1058                 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1059                                   priv->int_name_rx, ndev);
1060                 if (err) {
1061                         if (netif_msg_intr(priv))
1062                                 pr_err("%s: Can't get IRQ %d (receive0)\n",
1063                                        ndev->name, priv->interruptReceive);
1064                         goto rx_irq_fail;
1065                 }
1066         } else {
1067                 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1068                                 0, priv->int_name_tx, ndev);
1069                 if (err) {
1070                         if (netif_msg_intr(priv))
1071                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1072                                        priv->interruptTransmit);
1073                         goto err_irq_fail;
1074                 }
1075         }
1076
1077         phy_start(priv->phydev);
1078
1079         /* Configure the coalescing support */
1080         gfar_write(&regs->txic, 0);
1081         if (priv->txcoalescing)
1082                 gfar_write(&regs->txic, priv->txic);
1083
1084         gfar_write(&regs->rxic, 0);
1085         if (priv->rxcoalescing)
1086                 gfar_write(&regs->rxic, priv->rxic);
1087
1088         if (priv->rx_csum_enable)
1089                 rctrl |= RCTRL_CHECKSUMMING;
1090
1091         if (priv->extended_hash) {
1092                 rctrl |= RCTRL_EXTHASH;
1093
1094                 gfar_clear_exact_match(ndev);
1095                 rctrl |= RCTRL_EMEN;
1096         }
1097
1098         if (priv->padding) {
1099                 rctrl &= ~RCTRL_PAL_MASK;
1100                 rctrl |= RCTRL_PADDING(priv->padding);
1101         }
1102
1103         /* keep vlan related bits if it's enabled */
1104         if (priv->vlgrp) {
1105                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
1106                 tctrl |= TCTRL_VLINS;
1107         }
1108
1109         /* Init rctrl based on our settings */
1110         gfar_write(&regs->rctrl, rctrl);
1111
1112         if (ndev->features & NETIF_F_IP_CSUM)
1113                 tctrl |= TCTRL_INIT_CSUM;
1114
1115         gfar_write(&regs->tctrl, tctrl);
1116
1117         /* Set the extraction length and index */
1118         attrs = ATTRELI_EL(priv->rx_stash_size) |
1119                 ATTRELI_EI(priv->rx_stash_index);
1120
1121         gfar_write(&regs->attreli, attrs);
1122
1123         /* Start with defaults, and add stashing or locking
1124          * depending on the approprate variables */
1125         attrs = ATTR_INIT_SETTINGS;
1126
1127         if (priv->bd_stash_en)
1128                 attrs |= ATTR_BDSTASH;
1129
1130         if (priv->rx_stash_size != 0)
1131                 attrs |= ATTR_BUFSTASH;
1132
1133         gfar_write(&regs->attr, attrs);
1134
1135         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
1136         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
1137         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1138
1139         /* Start the controller */
1140         gfar_start(ndev);
1141
1142         return 0;
1143
1144 rx_irq_fail:
1145         free_irq(priv->interruptTransmit, ndev);
1146 tx_irq_fail:
1147         free_irq(priv->interruptError, ndev);
1148 err_irq_fail:
1149 err_rxalloc_fail:
1150 rx_skb_fail:
1151 tx_skb_fail:
1152         free_skb_resources(priv);
1153         return err;
1154 }
1155
1156 /* Called when something needs to use the ethernet device */
1157 /* Returns 0 for success. */
1158 static int gfar_enet_open(struct net_device *dev)
1159 {
1160         struct gfar_private *priv = netdev_priv(dev);
1161         int err;
1162
1163         napi_enable(&priv->napi);
1164
1165         skb_queue_head_init(&priv->rx_recycle);
1166
1167         /* Initialize a bunch of registers */
1168         init_registers(dev);
1169
1170         gfar_set_mac_address(dev);
1171
1172         err = init_phy(dev);
1173
1174         if(err) {
1175                 napi_disable(&priv->napi);
1176                 return err;
1177         }
1178
1179         err = startup_gfar(dev);
1180         if (err) {
1181                 napi_disable(&priv->napi);
1182                 return err;
1183         }
1184
1185         netif_start_queue(dev);
1186
1187         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1188
1189         return err;
1190 }
1191
1192 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1193 {
1194         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1195
1196         memset(fcb, 0, GMAC_FCB_LEN);
1197
1198         return fcb;
1199 }
1200
1201 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1202 {
1203         u8 flags = 0;
1204
1205         /* If we're here, it's a IP packet with a TCP or UDP
1206          * payload.  We set it to checksum, using a pseudo-header
1207          * we provide
1208          */
1209         flags = TXFCB_DEFAULT;
1210
1211         /* Tell the controller what the protocol is */
1212         /* And provide the already calculated phcs */
1213         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1214                 flags |= TXFCB_UDP;
1215                 fcb->phcs = udp_hdr(skb)->check;
1216         } else
1217                 fcb->phcs = tcp_hdr(skb)->check;
1218
1219         /* l3os is the distance between the start of the
1220          * frame (skb->data) and the start of the IP hdr.
1221          * l4os is the distance between the start of the
1222          * l3 hdr and the l4 hdr */
1223         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1224         fcb->l4os = skb_network_header_len(skb);
1225
1226         fcb->flags = flags;
1227 }
1228
1229 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1230 {
1231         fcb->flags |= TXFCB_VLN;
1232         fcb->vlctl = vlan_tx_tag_get(skb);
1233 }
1234
1235 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1236                                struct txbd8 *base, int ring_size)
1237 {
1238         struct txbd8 *new_bd = bdp + stride;
1239
1240         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1241 }
1242
1243 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1244                 int ring_size)
1245 {
1246         return skip_txbd(bdp, 1, base, ring_size);
1247 }
1248
1249 /* This is called by the kernel when a frame is ready for transmission. */
1250 /* It is pointed to by the dev->hard_start_xmit function pointer */
1251 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1252 {
1253         struct gfar_private *priv = netdev_priv(dev);
1254         struct txfcb *fcb = NULL;
1255         struct txbd8 *txbdp, *txbdp_start, *base;
1256         u32 lstatus;
1257         int i;
1258         u32 bufaddr;
1259         unsigned long flags;
1260         unsigned int nr_frags, length;
1261
1262         base = priv->tx_bd_base;
1263
1264         /* make space for additional header when fcb is needed */
1265         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1266                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1267                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1268                 struct sk_buff *skb_new;
1269
1270                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1271                 if (!skb_new) {
1272                         dev->stats.tx_errors++;
1273                         kfree_skb(skb);
1274                         return NETDEV_TX_OK;
1275                 }
1276                 kfree_skb(skb);
1277                 skb = skb_new;
1278         }
1279
1280         /* total number of fragments in the SKB */
1281         nr_frags = skb_shinfo(skb)->nr_frags;
1282
1283         spin_lock_irqsave(&priv->txlock, flags);
1284
1285         /* check if there is space to queue this packet */
1286         if ((nr_frags+1) > priv->num_txbdfree) {
1287                 /* no space, stop the queue */
1288                 netif_stop_queue(dev);
1289                 dev->stats.tx_fifo_errors++;
1290                 spin_unlock_irqrestore(&priv->txlock, flags);
1291                 return NETDEV_TX_BUSY;
1292         }
1293
1294         /* Update transmit stats */
1295         dev->stats.tx_bytes += skb->len;
1296
1297         txbdp = txbdp_start = priv->cur_tx;
1298
1299         if (nr_frags == 0) {
1300                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1301         } else {
1302                 /* Place the fragment addresses and lengths into the TxBDs */
1303                 for (i = 0; i < nr_frags; i++) {
1304                         /* Point at the next BD, wrapping as needed */
1305                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1306
1307                         length = skb_shinfo(skb)->frags[i].size;
1308
1309                         lstatus = txbdp->lstatus | length |
1310                                 BD_LFLAG(TXBD_READY);
1311
1312                         /* Handle the last BD specially */
1313                         if (i == nr_frags - 1)
1314                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1315
1316                         bufaddr = dma_map_page(&priv->ofdev->dev,
1317                                         skb_shinfo(skb)->frags[i].page,
1318                                         skb_shinfo(skb)->frags[i].page_offset,
1319                                         length,
1320                                         DMA_TO_DEVICE);
1321
1322                         /* set the TxBD length and buffer pointer */
1323                         txbdp->bufPtr = bufaddr;
1324                         txbdp->lstatus = lstatus;
1325                 }
1326
1327                 lstatus = txbdp_start->lstatus;
1328         }
1329
1330         /* Set up checksumming */
1331         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1332                 fcb = gfar_add_fcb(skb);
1333                 lstatus |= BD_LFLAG(TXBD_TOE);
1334                 gfar_tx_checksum(skb, fcb);
1335         }
1336
1337         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1338                 if (unlikely(NULL == fcb)) {
1339                         fcb = gfar_add_fcb(skb);
1340                         lstatus |= BD_LFLAG(TXBD_TOE);
1341                 }
1342
1343                 gfar_tx_vlan(skb, fcb);
1344         }
1345
1346         /* setup the TxBD length and buffer pointer for the first BD */
1347         priv->tx_skbuff[priv->skb_curtx] = skb;
1348         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1349                         skb_headlen(skb), DMA_TO_DEVICE);
1350
1351         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1352
1353         /*
1354          * The powerpc-specific eieio() is used, as wmb() has too strong
1355          * semantics (it requires synchronization between cacheable and
1356          * uncacheable mappings, which eieio doesn't provide and which we
1357          * don't need), thus requiring a more expensive sync instruction.  At
1358          * some point, the set of architecture-independent barrier functions
1359          * should be expanded to include weaker barriers.
1360          */
1361         eieio();
1362
1363         txbdp_start->lstatus = lstatus;
1364
1365         /* Update the current skb pointer to the next entry we will use
1366          * (wrapping if necessary) */
1367         priv->skb_curtx = (priv->skb_curtx + 1) &
1368                 TX_RING_MOD_MASK(priv->tx_ring_size);
1369
1370         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1371
1372         /* reduce TxBD free count */
1373         priv->num_txbdfree -= (nr_frags + 1);
1374
1375         dev->trans_start = jiffies;
1376
1377         /* If the next BD still needs to be cleaned up, then the bds
1378            are full.  We need to tell the kernel to stop sending us stuff. */
1379         if (!priv->num_txbdfree) {
1380                 netif_stop_queue(dev);
1381
1382                 dev->stats.tx_fifo_errors++;
1383         }
1384
1385         /* Tell the DMA to go go go */
1386         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1387
1388         /* Unlock priv */
1389         spin_unlock_irqrestore(&priv->txlock, flags);
1390
1391         return NETDEV_TX_OK;
1392 }
1393
1394 /* Stops the kernel queue, and halts the controller */
1395 static int gfar_close(struct net_device *dev)
1396 {
1397         struct gfar_private *priv = netdev_priv(dev);
1398
1399         napi_disable(&priv->napi);
1400
1401         skb_queue_purge(&priv->rx_recycle);
1402         cancel_work_sync(&priv->reset_task);
1403         stop_gfar(dev);
1404
1405         /* Disconnect from the PHY */
1406         phy_disconnect(priv->phydev);
1407         priv->phydev = NULL;
1408
1409         netif_stop_queue(dev);
1410
1411         return 0;
1412 }
1413
1414 /* Changes the mac address if the controller is not running. */
1415 static int gfar_set_mac_address(struct net_device *dev)
1416 {
1417         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1418
1419         return 0;
1420 }
1421
1422
1423 /* Enables and disables VLAN insertion/extraction */
1424 static void gfar_vlan_rx_register(struct net_device *dev,
1425                 struct vlan_group *grp)
1426 {
1427         struct gfar_private *priv = netdev_priv(dev);
1428         unsigned long flags;
1429         u32 tempval;
1430
1431         spin_lock_irqsave(&priv->rxlock, flags);
1432
1433         priv->vlgrp = grp;
1434
1435         if (grp) {
1436                 /* Enable VLAN tag insertion */
1437                 tempval = gfar_read(&priv->regs->tctrl);
1438                 tempval |= TCTRL_VLINS;
1439
1440                 gfar_write(&priv->regs->tctrl, tempval);
1441
1442                 /* Enable VLAN tag extraction */
1443                 tempval = gfar_read(&priv->regs->rctrl);
1444                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1445                 gfar_write(&priv->regs->rctrl, tempval);
1446         } else {
1447                 /* Disable VLAN tag insertion */
1448                 tempval = gfar_read(&priv->regs->tctrl);
1449                 tempval &= ~TCTRL_VLINS;
1450                 gfar_write(&priv->regs->tctrl, tempval);
1451
1452                 /* Disable VLAN tag extraction */
1453                 tempval = gfar_read(&priv->regs->rctrl);
1454                 tempval &= ~RCTRL_VLEX;
1455                 /* If parse is no longer required, then disable parser */
1456                 if (tempval & RCTRL_REQ_PARSER)
1457                         tempval |= RCTRL_PRSDEP_INIT;
1458                 else
1459                         tempval &= ~RCTRL_PRSDEP_INIT;
1460                 gfar_write(&priv->regs->rctrl, tempval);
1461         }
1462
1463         gfar_change_mtu(dev, dev->mtu);
1464
1465         spin_unlock_irqrestore(&priv->rxlock, flags);
1466 }
1467
1468 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1469 {
1470         int tempsize, tempval;
1471         struct gfar_private *priv = netdev_priv(dev);
1472         int oldsize = priv->rx_buffer_size;
1473         int frame_size = new_mtu + ETH_HLEN;
1474
1475         if (priv->vlgrp)
1476                 frame_size += VLAN_HLEN;
1477
1478         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1479                 if (netif_msg_drv(priv))
1480                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1481                                         dev->name);
1482                 return -EINVAL;
1483         }
1484
1485         if (gfar_uses_fcb(priv))
1486                 frame_size += GMAC_FCB_LEN;
1487
1488         frame_size += priv->padding;
1489
1490         tempsize =
1491             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1492             INCREMENTAL_BUFFER_SIZE;
1493
1494         /* Only stop and start the controller if it isn't already
1495          * stopped, and we changed something */
1496         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1497                 stop_gfar(dev);
1498
1499         priv->rx_buffer_size = tempsize;
1500
1501         dev->mtu = new_mtu;
1502
1503         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1504         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1505
1506         /* If the mtu is larger than the max size for standard
1507          * ethernet frames (ie, a jumbo frame), then set maccfg2
1508          * to allow huge frames, and to check the length */
1509         tempval = gfar_read(&priv->regs->maccfg2);
1510
1511         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1512                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1513         else
1514                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1515
1516         gfar_write(&priv->regs->maccfg2, tempval);
1517
1518         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1519                 startup_gfar(dev);
1520
1521         return 0;
1522 }
1523
1524 /* gfar_reset_task gets scheduled when a packet has not been
1525  * transmitted after a set amount of time.
1526  * For now, assume that clearing out all the structures, and
1527  * starting over will fix the problem.
1528  */
1529 static void gfar_reset_task(struct work_struct *work)
1530 {
1531         struct gfar_private *priv = container_of(work, struct gfar_private,
1532                         reset_task);
1533         struct net_device *dev = priv->ndev;
1534
1535         if (dev->flags & IFF_UP) {
1536                 netif_stop_queue(dev);
1537                 stop_gfar(dev);
1538                 startup_gfar(dev);
1539                 netif_start_queue(dev);
1540         }
1541
1542         netif_tx_schedule_all(dev);
1543 }
1544
1545 static void gfar_timeout(struct net_device *dev)
1546 {
1547         struct gfar_private *priv = netdev_priv(dev);
1548
1549         dev->stats.tx_errors++;
1550         schedule_work(&priv->reset_task);
1551 }
1552
1553 /* Interrupt Handler for Transmit complete */
1554 static int gfar_clean_tx_ring(struct net_device *dev)
1555 {
1556         struct gfar_private *priv = netdev_priv(dev);
1557         struct txbd8 *bdp;
1558         struct txbd8 *lbdp = NULL;
1559         struct txbd8 *base = priv->tx_bd_base;
1560         struct sk_buff *skb;
1561         int skb_dirtytx;
1562         int tx_ring_size = priv->tx_ring_size;
1563         int frags = 0;
1564         int i;
1565         int howmany = 0;
1566         u32 lstatus;
1567
1568         bdp = priv->dirty_tx;
1569         skb_dirtytx = priv->skb_dirtytx;
1570
1571         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1572                 frags = skb_shinfo(skb)->nr_frags;
1573                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1574
1575                 lstatus = lbdp->lstatus;
1576
1577                 /* Only clean completed frames */
1578                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1579                                 (lstatus & BD_LENGTH_MASK))
1580                         break;
1581
1582                 dma_unmap_single(&priv->ofdev->dev,
1583                                 bdp->bufPtr,
1584                                 bdp->length,
1585                                 DMA_TO_DEVICE);
1586
1587                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1588                 bdp = next_txbd(bdp, base, tx_ring_size);
1589
1590                 for (i = 0; i < frags; i++) {
1591                         dma_unmap_page(&priv->ofdev->dev,
1592                                         bdp->bufPtr,
1593                                         bdp->length,
1594                                         DMA_TO_DEVICE);
1595                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1596                         bdp = next_txbd(bdp, base, tx_ring_size);
1597                 }
1598
1599                 /*
1600                  * If there's room in the queue (limit it to rx_buffer_size)
1601                  * we add this skb back into the pool, if it's the right size
1602                  */
1603                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1604                                 skb_recycle_check(skb, priv->rx_buffer_size +
1605                                         RXBUF_ALIGNMENT))
1606                         __skb_queue_head(&priv->rx_recycle, skb);
1607                 else
1608                         dev_kfree_skb_any(skb);
1609
1610                 priv->tx_skbuff[skb_dirtytx] = NULL;
1611
1612                 skb_dirtytx = (skb_dirtytx + 1) &
1613                         TX_RING_MOD_MASK(tx_ring_size);
1614
1615                 howmany++;
1616                 priv->num_txbdfree += frags + 1;
1617         }
1618
1619         /* If we freed a buffer, we can restart transmission, if necessary */
1620         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1621                 netif_wake_queue(dev);
1622
1623         /* Update dirty indicators */
1624         priv->skb_dirtytx = skb_dirtytx;
1625         priv->dirty_tx = bdp;
1626
1627         dev->stats.tx_packets += howmany;
1628
1629         return howmany;
1630 }
1631
1632 static void gfar_schedule_cleanup(struct net_device *dev)
1633 {
1634         struct gfar_private *priv = netdev_priv(dev);
1635         unsigned long flags;
1636
1637         spin_lock_irqsave(&priv->txlock, flags);
1638         spin_lock(&priv->rxlock);
1639
1640         if (napi_schedule_prep(&priv->napi)) {
1641                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1642                 __napi_schedule(&priv->napi);
1643         } else {
1644                 /*
1645                  * Clear IEVENT, so interrupts aren't called again
1646                  * because of the packets that have already arrived.
1647                  */
1648                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1649         }
1650
1651         spin_unlock(&priv->rxlock);
1652         spin_unlock_irqrestore(&priv->txlock, flags);
1653 }
1654
1655 /* Interrupt Handler for Transmit complete */
1656 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1657 {
1658         gfar_schedule_cleanup((struct net_device *)dev_id);
1659         return IRQ_HANDLED;
1660 }
1661
1662 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1663                 struct sk_buff *skb)
1664 {
1665         struct gfar_private *priv = netdev_priv(dev);
1666         u32 lstatus;
1667
1668         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1669                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1670
1671         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1672
1673         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1674                 lstatus |= BD_LFLAG(RXBD_WRAP);
1675
1676         eieio();
1677
1678         bdp->lstatus = lstatus;
1679 }
1680
1681
1682 struct sk_buff * gfar_new_skb(struct net_device *dev)
1683 {
1684         unsigned int alignamount;
1685         struct gfar_private *priv = netdev_priv(dev);
1686         struct sk_buff *skb = NULL;
1687
1688         skb = __skb_dequeue(&priv->rx_recycle);
1689         if (!skb)
1690                 skb = netdev_alloc_skb(dev,
1691                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1692
1693         if (!skb)
1694                 return NULL;
1695
1696         alignamount = RXBUF_ALIGNMENT -
1697                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1698
1699         /* We need the data buffer to be aligned properly.  We will reserve
1700          * as many bytes as needed to align the data properly
1701          */
1702         skb_reserve(skb, alignamount);
1703
1704         return skb;
1705 }
1706
1707 static inline void count_errors(unsigned short status, struct net_device *dev)
1708 {
1709         struct gfar_private *priv = netdev_priv(dev);
1710         struct net_device_stats *stats = &dev->stats;
1711         struct gfar_extra_stats *estats = &priv->extra_stats;
1712
1713         /* If the packet was truncated, none of the other errors
1714          * matter */
1715         if (status & RXBD_TRUNCATED) {
1716                 stats->rx_length_errors++;
1717
1718                 estats->rx_trunc++;
1719
1720                 return;
1721         }
1722         /* Count the errors, if there were any */
1723         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1724                 stats->rx_length_errors++;
1725
1726                 if (status & RXBD_LARGE)
1727                         estats->rx_large++;
1728                 else
1729                         estats->rx_short++;
1730         }
1731         if (status & RXBD_NONOCTET) {
1732                 stats->rx_frame_errors++;
1733                 estats->rx_nonoctet++;
1734         }
1735         if (status & RXBD_CRCERR) {
1736                 estats->rx_crcerr++;
1737                 stats->rx_crc_errors++;
1738         }
1739         if (status & RXBD_OVERRUN) {
1740                 estats->rx_overrun++;
1741                 stats->rx_crc_errors++;
1742         }
1743 }
1744
1745 irqreturn_t gfar_receive(int irq, void *dev_id)
1746 {
1747         gfar_schedule_cleanup((struct net_device *)dev_id);
1748         return IRQ_HANDLED;
1749 }
1750
1751 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1752 {
1753         /* If valid headers were found, and valid sums
1754          * were verified, then we tell the kernel that no
1755          * checksumming is necessary.  Otherwise, it is */
1756         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1757                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1758         else
1759                 skb->ip_summed = CHECKSUM_NONE;
1760 }
1761
1762
1763 /* gfar_process_frame() -- handle one incoming packet if skb
1764  * isn't NULL.  */
1765 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1766                               int amount_pull)
1767 {
1768         struct gfar_private *priv = netdev_priv(dev);
1769         struct rxfcb *fcb = NULL;
1770
1771         int ret;
1772
1773         /* fcb is at the beginning if exists */
1774         fcb = (struct rxfcb *)skb->data;
1775
1776         /* Remove the FCB from the skb */
1777         /* Remove the padded bytes, if there are any */
1778         if (amount_pull)
1779                 skb_pull(skb, amount_pull);
1780
1781         if (priv->rx_csum_enable)
1782                 gfar_rx_checksum(skb, fcb);
1783
1784         /* Tell the skb what kind of packet this is */
1785         skb->protocol = eth_type_trans(skb, dev);
1786
1787         /* Send the packet up the stack */
1788         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1789                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1790         else
1791                 ret = netif_receive_skb(skb);
1792
1793         if (NET_RX_DROP == ret)
1794                 priv->extra_stats.kernel_dropped++;
1795
1796         return 0;
1797 }
1798
1799 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1800  *   until the budget/quota has been reached. Returns the number
1801  *   of frames handled
1802  */
1803 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1804 {
1805         struct rxbd8 *bdp, *base;
1806         struct sk_buff *skb;
1807         int pkt_len;
1808         int amount_pull;
1809         int howmany = 0;
1810         struct gfar_private *priv = netdev_priv(dev);
1811
1812         /* Get the first full descriptor */
1813         bdp = priv->cur_rx;
1814         base = priv->rx_bd_base;
1815
1816         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1817                 priv->padding;
1818
1819         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1820                 struct sk_buff *newskb;
1821                 rmb();
1822
1823                 /* Add another skb for the future */
1824                 newskb = gfar_new_skb(dev);
1825
1826                 skb = priv->rx_skbuff[priv->skb_currx];
1827
1828                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1829                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1830
1831                 /* We drop the frame if we failed to allocate a new buffer */
1832                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1833                                  bdp->status & RXBD_ERR)) {
1834                         count_errors(bdp->status, dev);
1835
1836                         if (unlikely(!newskb))
1837                                 newskb = skb;
1838                         else if (skb) {
1839                                 /*
1840                                  * We need to reset ->data to what it
1841                                  * was before gfar_new_skb() re-aligned
1842                                  * it to an RXBUF_ALIGNMENT boundary
1843                                  * before we put the skb back on the
1844                                  * recycle list.
1845                                  */
1846                                 skb->data = skb->head + NET_SKB_PAD;
1847                                 __skb_queue_head(&priv->rx_recycle, skb);
1848                         }
1849                 } else {
1850                         /* Increment the number of packets */
1851                         dev->stats.rx_packets++;
1852                         howmany++;
1853
1854                         if (likely(skb)) {
1855                                 pkt_len = bdp->length - ETH_FCS_LEN;
1856                                 /* Remove the FCS from the packet length */
1857                                 skb_put(skb, pkt_len);
1858                                 dev->stats.rx_bytes += pkt_len;
1859
1860                                 if (in_irq() || irqs_disabled())
1861                                         printk("Interrupt problem!\n");
1862                                 gfar_process_frame(dev, skb, amount_pull);
1863
1864                         } else {
1865                                 if (netif_msg_rx_err(priv))
1866                                         printk(KERN_WARNING
1867                                                "%s: Missing skb!\n", dev->name);
1868                                 dev->stats.rx_dropped++;
1869                                 priv->extra_stats.rx_skbmissing++;
1870                         }
1871
1872                 }
1873
1874                 priv->rx_skbuff[priv->skb_currx] = newskb;
1875
1876                 /* Setup the new bdp */
1877                 gfar_new_rxbdp(dev, bdp, newskb);
1878
1879                 /* Update to the next pointer */
1880                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1881
1882                 /* update to point at the next skb */
1883                 priv->skb_currx =
1884                     (priv->skb_currx + 1) &
1885                     RX_RING_MOD_MASK(priv->rx_ring_size);
1886         }
1887
1888         /* Update the current rxbd pointer to be the next one */
1889         priv->cur_rx = bdp;
1890
1891         return howmany;
1892 }
1893
1894 static int gfar_poll(struct napi_struct *napi, int budget)
1895 {
1896         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1897         struct net_device *dev = priv->ndev;
1898         int tx_cleaned = 0;
1899         int rx_cleaned = 0;
1900         unsigned long flags;
1901
1902         /* Clear IEVENT, so interrupts aren't called again
1903          * because of the packets that have already arrived */
1904         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1905
1906         /* If we fail to get the lock, don't bother with the TX BDs */
1907         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1908                 tx_cleaned = gfar_clean_tx_ring(dev);
1909                 spin_unlock_irqrestore(&priv->txlock, flags);
1910         }
1911
1912         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1913
1914         if (tx_cleaned)
1915                 return budget;
1916
1917         if (rx_cleaned < budget) {
1918                 napi_complete(napi);
1919
1920                 /* Clear the halt bit in RSTAT */
1921                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1922
1923                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1924
1925                 /* If we are coalescing interrupts, update the timer */
1926                 /* Otherwise, clear it */
1927                 if (likely(priv->rxcoalescing)) {
1928                         gfar_write(&priv->regs->rxic, 0);
1929                         gfar_write(&priv->regs->rxic, priv->rxic);
1930                 }
1931                 if (likely(priv->txcoalescing)) {
1932                         gfar_write(&priv->regs->txic, 0);
1933                         gfar_write(&priv->regs->txic, priv->txic);
1934                 }
1935         }
1936
1937         return rx_cleaned;
1938 }
1939
1940 #ifdef CONFIG_NET_POLL_CONTROLLER
1941 /*
1942  * Polling 'interrupt' - used by things like netconsole to send skbs
1943  * without having to re-enable interrupts. It's not called while
1944  * the interrupt routine is executing.
1945  */
1946 static void gfar_netpoll(struct net_device *dev)
1947 {
1948         struct gfar_private *priv = netdev_priv(dev);
1949
1950         /* If the device has multiple interrupts, run tx/rx */
1951         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1952                 disable_irq(priv->interruptTransmit);
1953                 disable_irq(priv->interruptReceive);
1954                 disable_irq(priv->interruptError);
1955                 gfar_interrupt(priv->interruptTransmit, dev);
1956                 enable_irq(priv->interruptError);
1957                 enable_irq(priv->interruptReceive);
1958                 enable_irq(priv->interruptTransmit);
1959         } else {
1960                 disable_irq(priv->interruptTransmit);
1961                 gfar_interrupt(priv->interruptTransmit, dev);
1962                 enable_irq(priv->interruptTransmit);
1963         }
1964 }
1965 #endif
1966
1967 /* The interrupt handler for devices with one interrupt */
1968 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1969 {
1970         struct net_device *dev = dev_id;
1971         struct gfar_private *priv = netdev_priv(dev);
1972
1973         /* Save ievent for future reference */
1974         u32 events = gfar_read(&priv->regs->ievent);
1975
1976         /* Check for reception */
1977         if (events & IEVENT_RX_MASK)
1978                 gfar_receive(irq, dev_id);
1979
1980         /* Check for transmit completion */
1981         if (events & IEVENT_TX_MASK)
1982                 gfar_transmit(irq, dev_id);
1983
1984         /* Check for errors */
1985         if (events & IEVENT_ERR_MASK)
1986                 gfar_error(irq, dev_id);
1987
1988         return IRQ_HANDLED;
1989 }
1990
1991 /* Called every time the controller might need to be made
1992  * aware of new link state.  The PHY code conveys this
1993  * information through variables in the phydev structure, and this
1994  * function converts those variables into the appropriate
1995  * register values, and can bring down the device if needed.
1996  */
1997 static void adjust_link(struct net_device *dev)
1998 {
1999         struct gfar_private *priv = netdev_priv(dev);
2000         struct gfar __iomem *regs = priv->regs;
2001         unsigned long flags;
2002         struct phy_device *phydev = priv->phydev;
2003         int new_state = 0;
2004
2005         spin_lock_irqsave(&priv->txlock, flags);
2006         if (phydev->link) {
2007                 u32 tempval = gfar_read(&regs->maccfg2);
2008                 u32 ecntrl = gfar_read(&regs->ecntrl);
2009
2010                 /* Now we make sure that we can be in full duplex mode.
2011                  * If not, we operate in half-duplex mode. */
2012                 if (phydev->duplex != priv->oldduplex) {
2013                         new_state = 1;
2014                         if (!(phydev->duplex))
2015                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2016                         else
2017                                 tempval |= MACCFG2_FULL_DUPLEX;
2018
2019                         priv->oldduplex = phydev->duplex;
2020                 }
2021
2022                 if (phydev->speed != priv->oldspeed) {
2023                         new_state = 1;
2024                         switch (phydev->speed) {
2025                         case 1000:
2026                                 tempval =
2027                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2028
2029                                 ecntrl &= ~(ECNTRL_R100);
2030                                 break;
2031                         case 100:
2032                         case 10:
2033                                 tempval =
2034                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2035
2036                                 /* Reduced mode distinguishes
2037                                  * between 10 and 100 */
2038                                 if (phydev->speed == SPEED_100)
2039                                         ecntrl |= ECNTRL_R100;
2040                                 else
2041                                         ecntrl &= ~(ECNTRL_R100);
2042                                 break;
2043                         default:
2044                                 if (netif_msg_link(priv))
2045                                         printk(KERN_WARNING
2046                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2047                                                 dev->name, phydev->speed);
2048                                 break;
2049                         }
2050
2051                         priv->oldspeed = phydev->speed;
2052                 }
2053
2054                 gfar_write(&regs->maccfg2, tempval);
2055                 gfar_write(&regs->ecntrl, ecntrl);
2056
2057                 if (!priv->oldlink) {
2058                         new_state = 1;
2059                         priv->oldlink = 1;
2060                 }
2061         } else if (priv->oldlink) {
2062                 new_state = 1;
2063                 priv->oldlink = 0;
2064                 priv->oldspeed = 0;
2065                 priv->oldduplex = -1;
2066         }
2067
2068         if (new_state && netif_msg_link(priv))
2069                 phy_print_status(phydev);
2070
2071         spin_unlock_irqrestore(&priv->txlock, flags);
2072 }
2073
2074 /* Update the hash table based on the current list of multicast
2075  * addresses we subscribe to.  Also, change the promiscuity of
2076  * the device based on the flags (this function is called
2077  * whenever dev->flags is changed */
2078 static void gfar_set_multi(struct net_device *dev)
2079 {
2080         struct dev_mc_list *mc_ptr;
2081         struct gfar_private *priv = netdev_priv(dev);
2082         struct gfar __iomem *regs = priv->regs;
2083         u32 tempval;
2084
2085         if(dev->flags & IFF_PROMISC) {
2086                 /* Set RCTRL to PROM */
2087                 tempval = gfar_read(&regs->rctrl);
2088                 tempval |= RCTRL_PROM;
2089                 gfar_write(&regs->rctrl, tempval);
2090         } else {
2091                 /* Set RCTRL to not PROM */
2092                 tempval = gfar_read(&regs->rctrl);
2093                 tempval &= ~(RCTRL_PROM);
2094                 gfar_write(&regs->rctrl, tempval);
2095         }
2096
2097         if(dev->flags & IFF_ALLMULTI) {
2098                 /* Set the hash to rx all multicast frames */
2099                 gfar_write(&regs->igaddr0, 0xffffffff);
2100                 gfar_write(&regs->igaddr1, 0xffffffff);
2101                 gfar_write(&regs->igaddr2, 0xffffffff);
2102                 gfar_write(&regs->igaddr3, 0xffffffff);
2103                 gfar_write(&regs->igaddr4, 0xffffffff);
2104                 gfar_write(&regs->igaddr5, 0xffffffff);
2105                 gfar_write(&regs->igaddr6, 0xffffffff);
2106                 gfar_write(&regs->igaddr7, 0xffffffff);
2107                 gfar_write(&regs->gaddr0, 0xffffffff);
2108                 gfar_write(&regs->gaddr1, 0xffffffff);
2109                 gfar_write(&regs->gaddr2, 0xffffffff);
2110                 gfar_write(&regs->gaddr3, 0xffffffff);
2111                 gfar_write(&regs->gaddr4, 0xffffffff);
2112                 gfar_write(&regs->gaddr5, 0xffffffff);
2113                 gfar_write(&regs->gaddr6, 0xffffffff);
2114                 gfar_write(&regs->gaddr7, 0xffffffff);
2115         } else {
2116                 int em_num;
2117                 int idx;
2118
2119                 /* zero out the hash */
2120                 gfar_write(&regs->igaddr0, 0x0);
2121                 gfar_write(&regs->igaddr1, 0x0);
2122                 gfar_write(&regs->igaddr2, 0x0);
2123                 gfar_write(&regs->igaddr3, 0x0);
2124                 gfar_write(&regs->igaddr4, 0x0);
2125                 gfar_write(&regs->igaddr5, 0x0);
2126                 gfar_write(&regs->igaddr6, 0x0);
2127                 gfar_write(&regs->igaddr7, 0x0);
2128                 gfar_write(&regs->gaddr0, 0x0);
2129                 gfar_write(&regs->gaddr1, 0x0);
2130                 gfar_write(&regs->gaddr2, 0x0);
2131                 gfar_write(&regs->gaddr3, 0x0);
2132                 gfar_write(&regs->gaddr4, 0x0);
2133                 gfar_write(&regs->gaddr5, 0x0);
2134                 gfar_write(&regs->gaddr6, 0x0);
2135                 gfar_write(&regs->gaddr7, 0x0);
2136
2137                 /* If we have extended hash tables, we need to
2138                  * clear the exact match registers to prepare for
2139                  * setting them */
2140                 if (priv->extended_hash) {
2141                         em_num = GFAR_EM_NUM + 1;
2142                         gfar_clear_exact_match(dev);
2143                         idx = 1;
2144                 } else {
2145                         idx = 0;
2146                         em_num = 0;
2147                 }
2148
2149                 if(dev->mc_count == 0)
2150                         return;
2151
2152                 /* Parse the list, and set the appropriate bits */
2153                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2154                         if (idx < em_num) {
2155                                 gfar_set_mac_for_addr(dev, idx,
2156                                                 mc_ptr->dmi_addr);
2157                                 idx++;
2158                         } else
2159                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2160                 }
2161         }
2162
2163         return;
2164 }
2165
2166
2167 /* Clears each of the exact match registers to zero, so they
2168  * don't interfere with normal reception */
2169 static void gfar_clear_exact_match(struct net_device *dev)
2170 {
2171         int idx;
2172         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2173
2174         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2175                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2176 }
2177
2178 /* Set the appropriate hash bit for the given addr */
2179 /* The algorithm works like so:
2180  * 1) Take the Destination Address (ie the multicast address), and
2181  * do a CRC on it (little endian), and reverse the bits of the
2182  * result.
2183  * 2) Use the 8 most significant bits as a hash into a 256-entry
2184  * table.  The table is controlled through 8 32-bit registers:
2185  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2186  * gaddr7.  This means that the 3 most significant bits in the
2187  * hash index which gaddr register to use, and the 5 other bits
2188  * indicate which bit (assuming an IBM numbering scheme, which
2189  * for PowerPC (tm) is usually the case) in the register holds
2190  * the entry. */
2191 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2192 {
2193         u32 tempval;
2194         struct gfar_private *priv = netdev_priv(dev);
2195         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2196         int width = priv->hash_width;
2197         u8 whichbit = (result >> (32 - width)) & 0x1f;
2198         u8 whichreg = result >> (32 - width + 5);
2199         u32 value = (1 << (31-whichbit));
2200
2201         tempval = gfar_read(priv->hash_regs[whichreg]);
2202         tempval |= value;
2203         gfar_write(priv->hash_regs[whichreg], tempval);
2204
2205         return;
2206 }
2207
2208
2209 /* There are multiple MAC Address register pairs on some controllers
2210  * This function sets the numth pair to a given address
2211  */
2212 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2213 {
2214         struct gfar_private *priv = netdev_priv(dev);
2215         int idx;
2216         char tmpbuf[MAC_ADDR_LEN];
2217         u32 tempval;
2218         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2219
2220         macptr += num*2;
2221
2222         /* Now copy it into the mac registers backwards, cuz */
2223         /* little endian is silly */
2224         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2225                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2226
2227         gfar_write(macptr, *((u32 *) (tmpbuf)));
2228
2229         tempval = *((u32 *) (tmpbuf + 4));
2230
2231         gfar_write(macptr+1, tempval);
2232 }
2233
2234 /* GFAR error interrupt handler */
2235 static irqreturn_t gfar_error(int irq, void *dev_id)
2236 {
2237         struct net_device *dev = dev_id;
2238         struct gfar_private *priv = netdev_priv(dev);
2239
2240         /* Save ievent for future reference */
2241         u32 events = gfar_read(&priv->regs->ievent);
2242
2243         /* Clear IEVENT */
2244         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2245
2246         /* Magic Packet is not an error. */
2247         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2248             (events & IEVENT_MAG))
2249                 events &= ~IEVENT_MAG;
2250
2251         /* Hmm... */
2252         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2253                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2254                        dev->name, events, gfar_read(&priv->regs->imask));
2255
2256         /* Update the error counters */
2257         if (events & IEVENT_TXE) {
2258                 dev->stats.tx_errors++;
2259
2260                 if (events & IEVENT_LC)
2261                         dev->stats.tx_window_errors++;
2262                 if (events & IEVENT_CRL)
2263                         dev->stats.tx_aborted_errors++;
2264                 if (events & IEVENT_XFUN) {
2265                         if (netif_msg_tx_err(priv))
2266                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2267                                        "packet dropped.\n", dev->name);
2268                         dev->stats.tx_dropped++;
2269                         priv->extra_stats.tx_underrun++;
2270
2271                         /* Reactivate the Tx Queues */
2272                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2273                 }
2274                 if (netif_msg_tx_err(priv))
2275                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2276         }
2277         if (events & IEVENT_BSY) {
2278                 dev->stats.rx_errors++;
2279                 priv->extra_stats.rx_bsy++;
2280
2281                 gfar_receive(irq, dev_id);
2282
2283                 if (netif_msg_rx_err(priv))
2284                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2285                                dev->name, gfar_read(&priv->regs->rstat));
2286         }
2287         if (events & IEVENT_BABR) {
2288                 dev->stats.rx_errors++;
2289                 priv->extra_stats.rx_babr++;
2290
2291                 if (netif_msg_rx_err(priv))
2292                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2293         }
2294         if (events & IEVENT_EBERR) {
2295                 priv->extra_stats.eberr++;
2296                 if (netif_msg_rx_err(priv))
2297                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2298         }
2299         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2300                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2301
2302         if (events & IEVENT_BABT) {
2303                 priv->extra_stats.tx_babt++;
2304                 if (netif_msg_tx_err(priv))
2305                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2306         }
2307         return IRQ_HANDLED;
2308 }
2309
2310 /* work with hotplug and coldplug */
2311 MODULE_ALIAS("platform:fsl-gianfar");
2312
2313 static struct of_device_id gfar_match[] =
2314 {
2315         {
2316                 .type = "network",
2317                 .compatible = "gianfar",
2318         },
2319         {},
2320 };
2321
2322 /* Structure for a device driver */
2323 static struct of_platform_driver gfar_driver = {
2324         .name = "fsl-gianfar",
2325         .match_table = gfar_match,
2326
2327         .probe = gfar_probe,
2328         .remove = gfar_remove,
2329         .suspend = gfar_suspend,
2330         .resume = gfar_resume,
2331 };
2332
2333 static int __init gfar_init(void)
2334 {
2335         return of_register_platform_driver(&gfar_driver);
2336 }
2337
2338 static void __exit gfar_exit(void)
2339 {
2340         of_unregister_platform_driver(&gfar_driver);
2341 }
2342
2343 module_init(gfar_init);
2344 module_exit(gfar_exit);
2345