netdev: convert non-obvious instances to use ARRAY_SIZE()
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page.
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.
67  */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/slab.h>
75 #include <linux/delay.h>
76 #include <linux/init.h>
77 #include <linux/ioport.h>
78 #include <linux/pci.h>
79 #include <linux/mm.h>
80 #include <linux/highmem.h>
81 #include <linux/list.h>
82 #include <linux/dma-mapping.h>
83
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/crc32.h>
89 #include <linux/random.h>
90 #include <linux/mii.h>
91 #include <linux/ip.h>
92 #include <linux/tcp.h>
93 #include <linux/mutex.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS            num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x)  netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x)  netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB      /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
123 #define USE_RX_BLANK       /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127  * also, we need to make cp->lock finer-grained.
128  */
129 #undef  USE_PCI_INTB
130 #undef  USE_PCI_INTC
131 #undef  USE_PCI_INTD
132 #undef  USE_QOS
133
134 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
140 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
141 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME         "cassini"
144 #define PFX DRV_MODULE_NAME     ": "
145 #define DRV_MODULE_VERSION      "1.4"
146 #define DRV_MODULE_RELDATE      "1 July 2004"
147
148 #define CAS_DEF_MSG_ENABLE        \
149         (NETIF_MSG_DRV          | \
150          NETIF_MSG_PROBE        | \
151          NETIF_MSG_LINK         | \
152          NETIF_MSG_TIMER        | \
153          NETIF_MSG_IFDOWN       | \
154          NETIF_MSG_IFUP         | \
155          NETIF_MSG_RX_ERR       | \
156          NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159  * and dev->tx_timeout() should be called to fix the problem
160  */
161 #define CAS_TX_TIMEOUT                  (HZ)
162 #define CAS_LINK_TIMEOUT                (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT           (1)
164
165 /* timeout values for state changing. these specify the number
166  * of 10us delays to be used before giving up.
167  */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES     5000
170
171 /* specify a minimum frame size to deal with some fifo issues
172  * max mtu == 2 * page size - ethernet header - 64 - swivel =
173  *            2 * page_size - 0x50
174  */
175 #define CAS_MIN_FRAME                   97
176 #define CAS_1000MB_MIN_FRAME            255
177 #define CAS_MIN_MTU                     60
178 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182  * Eliminate these and use separate atomic counters for each, to
183  * avoid a race condition.
184  */
185 #else
186 #define CAS_RESET_MTU                   1
187 #define CAS_RESET_ALL                   2
188 #define CAS_RESET_SPARE                 3
189 #endif
190
191 static char version[] __devinitdata =
192         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
195 static int link_mode;
196
197 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
198 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
199 MODULE_LICENSE("GPL");
200 module_param(cassini_debug, int, 0);
201 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
202 module_param(link_mode, int, 0);
203 MODULE_PARM_DESC(link_mode, "default link mode");
204
205 /*
206  * Work around for a PCS bug in which the link goes down due to the chip
207  * being confused and never showing a link status of "up."
208  */
209 #define DEFAULT_LINKDOWN_TIMEOUT 5
210 /*
211  * Value in seconds, for user input.
212  */
213 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
214 module_param(linkdown_timeout, int, 0);
215 MODULE_PARM_DESC(linkdown_timeout,
216 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
217
218 /*
219  * value in 'ticks' (units used by jiffies). Set when we init the
220  * module because 'HZ' in actually a function call on some flavors of
221  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
222  */
223 static int link_transition_timeout;
224
225
226
227 static u16 link_modes[] __devinitdata = {
228         BMCR_ANENABLE,                   /* 0 : autoneg */
229         0,                               /* 1 : 10bt half duplex */
230         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
231         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
232         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
233         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
234 };
235
236 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
237         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241         { 0, }
242 };
243
244 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245
246 static void cas_set_link_modes(struct cas *cp);
247
248 static inline void cas_lock_tx(struct cas *cp)
249 {
250         int i;
251
252         for (i = 0; i < N_TX_RINGS; i++)
253                 spin_lock(&cp->tx_lock[i]);
254 }
255
256 static inline void cas_lock_all(struct cas *cp)
257 {
258         spin_lock_irq(&cp->lock);
259         cas_lock_tx(cp);
260 }
261
262 /* WTZ: QA was finding deadlock problems with the previous
263  * versions after long test runs with multiple cards per machine.
264  * See if replacing cas_lock_all with safer versions helps. The
265  * symptoms QA is reporting match those we'd expect if interrupts
266  * aren't being properly restored, and we fixed a previous deadlock
267  * with similar symptoms by using save/restore versions in other
268  * places.
269  */
270 #define cas_lock_all_save(cp, flags) \
271 do { \
272         struct cas *xxxcp = (cp); \
273         spin_lock_irqsave(&xxxcp->lock, flags); \
274         cas_lock_tx(xxxcp); \
275 } while (0)
276
277 static inline void cas_unlock_tx(struct cas *cp)
278 {
279         int i;
280
281         for (i = N_TX_RINGS; i > 0; i--)
282                 spin_unlock(&cp->tx_lock[i - 1]);
283 }
284
285 static inline void cas_unlock_all(struct cas *cp)
286 {
287         cas_unlock_tx(cp);
288         spin_unlock_irq(&cp->lock);
289 }
290
291 #define cas_unlock_all_restore(cp, flags) \
292 do { \
293         struct cas *xxxcp = (cp); \
294         cas_unlock_tx(xxxcp); \
295         spin_unlock_irqrestore(&xxxcp->lock, flags); \
296 } while (0)
297
298 static void cas_disable_irq(struct cas *cp, const int ring)
299 {
300         /* Make sure we won't get any more interrupts */
301         if (ring == 0) {
302                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
303                 return;
304         }
305
306         /* disable completion interrupts and selectively mask */
307         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308                 switch (ring) {
309 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
310 #ifdef USE_PCI_INTB
311                 case 1:
312 #endif
313 #ifdef USE_PCI_INTC
314                 case 2:
315 #endif
316 #ifdef USE_PCI_INTD
317                 case 3:
318 #endif
319                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
320                                cp->regs + REG_PLUS_INTRN_MASK(ring));
321                         break;
322 #endif
323                 default:
324                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
325                                REG_PLUS_INTRN_MASK(ring));
326                         break;
327                 }
328         }
329 }
330
331 static inline void cas_mask_intr(struct cas *cp)
332 {
333         int i;
334
335         for (i = 0; i < N_RX_COMP_RINGS; i++)
336                 cas_disable_irq(cp, i);
337 }
338
339 static inline void cas_buffer_init(cas_page_t *cp)
340 {
341         struct page *page = cp->buffer;
342         atomic_set((atomic_t *)&page->lru.next, 1);
343 }
344
345 static inline int cas_buffer_count(cas_page_t *cp)
346 {
347         struct page *page = cp->buffer;
348         return atomic_read((atomic_t *)&page->lru.next);
349 }
350
351 static inline void cas_buffer_inc(cas_page_t *cp)
352 {
353         struct page *page = cp->buffer;
354         atomic_inc((atomic_t *)&page->lru.next);
355 }
356
357 static inline void cas_buffer_dec(cas_page_t *cp)
358 {
359         struct page *page = cp->buffer;
360         atomic_dec((atomic_t *)&page->lru.next);
361 }
362
363 static void cas_enable_irq(struct cas *cp, const int ring)
364 {
365         if (ring == 0) { /* all but TX_DONE */
366                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
367                 return;
368         }
369
370         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
371                 switch (ring) {
372 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
373 #ifdef USE_PCI_INTB
374                 case 1:
375 #endif
376 #ifdef USE_PCI_INTC
377                 case 2:
378 #endif
379 #ifdef USE_PCI_INTD
380                 case 3:
381 #endif
382                         writel(INTRN_MASK_RX_EN, cp->regs +
383                                REG_PLUS_INTRN_MASK(ring));
384                         break;
385 #endif
386                 default:
387                         break;
388                 }
389         }
390 }
391
392 static inline void cas_unmask_intr(struct cas *cp)
393 {
394         int i;
395
396         for (i = 0; i < N_RX_COMP_RINGS; i++)
397                 cas_enable_irq(cp, i);
398 }
399
400 static inline void cas_entropy_gather(struct cas *cp)
401 {
402 #ifdef USE_ENTROPY_DEV
403         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
404                 return;
405
406         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
407                             readl(cp->regs + REG_ENTROPY_IV),
408                             sizeof(uint64_t)*8);
409 #endif
410 }
411
412 static inline void cas_entropy_reset(struct cas *cp)
413 {
414 #ifdef USE_ENTROPY_DEV
415         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
416                 return;
417
418         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
419                cp->regs + REG_BIM_LOCAL_DEV_EN);
420         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
421         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
422
423         /* if we read back 0x0, we don't have an entropy device */
424         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
425                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
426 #endif
427 }
428
429 /* access to the phy. the following assumes that we've initialized the MIF to
430  * be in frame rather than bit-bang mode
431  */
432 static u16 cas_phy_read(struct cas *cp, int reg)
433 {
434         u32 cmd;
435         int limit = STOP_TRIES_PHY;
436
437         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
438         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
439         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
440         cmd |= MIF_FRAME_TURN_AROUND_MSB;
441         writel(cmd, cp->regs + REG_MIF_FRAME);
442
443         /* poll for completion */
444         while (limit-- > 0) {
445                 udelay(10);
446                 cmd = readl(cp->regs + REG_MIF_FRAME);
447                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
448                         return (cmd & MIF_FRAME_DATA_MASK);
449         }
450         return 0xFFFF; /* -1 */
451 }
452
453 static int cas_phy_write(struct cas *cp, int reg, u16 val)
454 {
455         int limit = STOP_TRIES_PHY;
456         u32 cmd;
457
458         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
459         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
460         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
461         cmd |= MIF_FRAME_TURN_AROUND_MSB;
462         cmd |= val & MIF_FRAME_DATA_MASK;
463         writel(cmd, cp->regs + REG_MIF_FRAME);
464
465         /* poll for completion */
466         while (limit-- > 0) {
467                 udelay(10);
468                 cmd = readl(cp->regs + REG_MIF_FRAME);
469                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
470                         return 0;
471         }
472         return -1;
473 }
474
475 static void cas_phy_powerup(struct cas *cp)
476 {
477         u16 ctl = cas_phy_read(cp, MII_BMCR);
478
479         if ((ctl & BMCR_PDOWN) == 0)
480                 return;
481         ctl &= ~BMCR_PDOWN;
482         cas_phy_write(cp, MII_BMCR, ctl);
483 }
484
485 static void cas_phy_powerdown(struct cas *cp)
486 {
487         u16 ctl = cas_phy_read(cp, MII_BMCR);
488
489         if (ctl & BMCR_PDOWN)
490                 return;
491         ctl |= BMCR_PDOWN;
492         cas_phy_write(cp, MII_BMCR, ctl);
493 }
494
495 /* cp->lock held. note: the last put_page will free the buffer */
496 static int cas_page_free(struct cas *cp, cas_page_t *page)
497 {
498         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
499                        PCI_DMA_FROMDEVICE);
500         cas_buffer_dec(page);
501         __free_pages(page->buffer, cp->page_order);
502         kfree(page);
503         return 0;
504 }
505
506 #ifdef RX_COUNT_BUFFERS
507 #define RX_USED_ADD(x, y)       ((x)->used += (y))
508 #define RX_USED_SET(x, y)       ((x)->used  = (y))
509 #else
510 #define RX_USED_ADD(x, y)
511 #define RX_USED_SET(x, y)
512 #endif
513
514 /* local page allocation routines for the receive buffers. jumbo pages
515  * require at least 8K contiguous and 8K aligned buffers.
516  */
517 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
518 {
519         cas_page_t *page;
520
521         page = kmalloc(sizeof(cas_page_t), flags);
522         if (!page)
523                 return NULL;
524
525         INIT_LIST_HEAD(&page->list);
526         RX_USED_SET(page, 0);
527         page->buffer = alloc_pages(flags, cp->page_order);
528         if (!page->buffer)
529                 goto page_err;
530         cas_buffer_init(page);
531         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
532                                       cp->page_size, PCI_DMA_FROMDEVICE);
533         return page;
534
535 page_err:
536         kfree(page);
537         return NULL;
538 }
539
540 /* initialize spare pool of rx buffers, but allocate during the open */
541 static void cas_spare_init(struct cas *cp)
542 {
543         spin_lock(&cp->rx_inuse_lock);
544         INIT_LIST_HEAD(&cp->rx_inuse_list);
545         spin_unlock(&cp->rx_inuse_lock);
546
547         spin_lock(&cp->rx_spare_lock);
548         INIT_LIST_HEAD(&cp->rx_spare_list);
549         cp->rx_spares_needed = RX_SPARE_COUNT;
550         spin_unlock(&cp->rx_spare_lock);
551 }
552
553 /* used on close. free all the spare buffers. */
554 static void cas_spare_free(struct cas *cp)
555 {
556         struct list_head list, *elem, *tmp;
557
558         /* free spare buffers */
559         INIT_LIST_HEAD(&list);
560         spin_lock(&cp->rx_spare_lock);
561         list_splice(&cp->rx_spare_list, &list);
562         INIT_LIST_HEAD(&cp->rx_spare_list);
563         spin_unlock(&cp->rx_spare_lock);
564         list_for_each_safe(elem, tmp, &list) {
565                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
566         }
567
568         INIT_LIST_HEAD(&list);
569 #if 1
570         /*
571          * Looks like Adrian had protected this with a different
572          * lock than used everywhere else to manipulate this list.
573          */
574         spin_lock(&cp->rx_inuse_lock);
575         list_splice(&cp->rx_inuse_list, &list);
576         INIT_LIST_HEAD(&cp->rx_inuse_list);
577         spin_unlock(&cp->rx_inuse_lock);
578 #else
579         spin_lock(&cp->rx_spare_lock);
580         list_splice(&cp->rx_inuse_list, &list);
581         INIT_LIST_HEAD(&cp->rx_inuse_list);
582         spin_unlock(&cp->rx_spare_lock);
583 #endif
584         list_for_each_safe(elem, tmp, &list) {
585                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
586         }
587 }
588
589 /* replenish spares if needed */
590 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
591 {
592         struct list_head list, *elem, *tmp;
593         int needed, i;
594
595         /* check inuse list. if we don't need any more free buffers,
596          * just free it
597          */
598
599         /* make a local copy of the list */
600         INIT_LIST_HEAD(&list);
601         spin_lock(&cp->rx_inuse_lock);
602         list_splice(&cp->rx_inuse_list, &list);
603         INIT_LIST_HEAD(&cp->rx_inuse_list);
604         spin_unlock(&cp->rx_inuse_lock);
605
606         list_for_each_safe(elem, tmp, &list) {
607                 cas_page_t *page = list_entry(elem, cas_page_t, list);
608
609                 if (cas_buffer_count(page) > 1)
610                         continue;
611
612                 list_del(elem);
613                 spin_lock(&cp->rx_spare_lock);
614                 if (cp->rx_spares_needed > 0) {
615                         list_add(elem, &cp->rx_spare_list);
616                         cp->rx_spares_needed--;
617                         spin_unlock(&cp->rx_spare_lock);
618                 } else {
619                         spin_unlock(&cp->rx_spare_lock);
620                         cas_page_free(cp, page);
621                 }
622         }
623
624         /* put any inuse buffers back on the list */
625         if (!list_empty(&list)) {
626                 spin_lock(&cp->rx_inuse_lock);
627                 list_splice(&list, &cp->rx_inuse_list);
628                 spin_unlock(&cp->rx_inuse_lock);
629         }
630
631         spin_lock(&cp->rx_spare_lock);
632         needed = cp->rx_spares_needed;
633         spin_unlock(&cp->rx_spare_lock);
634         if (!needed)
635                 return;
636
637         /* we still need spares, so try to allocate some */
638         INIT_LIST_HEAD(&list);
639         i = 0;
640         while (i < needed) {
641                 cas_page_t *spare = cas_page_alloc(cp, flags);
642                 if (!spare)
643                         break;
644                 list_add(&spare->list, &list);
645                 i++;
646         }
647
648         spin_lock(&cp->rx_spare_lock);
649         list_splice(&list, &cp->rx_spare_list);
650         cp->rx_spares_needed -= i;
651         spin_unlock(&cp->rx_spare_lock);
652 }
653
654 /* pull a page from the list. */
655 static cas_page_t *cas_page_dequeue(struct cas *cp)
656 {
657         struct list_head *entry;
658         int recover;
659
660         spin_lock(&cp->rx_spare_lock);
661         if (list_empty(&cp->rx_spare_list)) {
662                 /* try to do a quick recovery */
663                 spin_unlock(&cp->rx_spare_lock);
664                 cas_spare_recover(cp, GFP_ATOMIC);
665                 spin_lock(&cp->rx_spare_lock);
666                 if (list_empty(&cp->rx_spare_list)) {
667                         if (netif_msg_rx_err(cp))
668                                 printk(KERN_ERR "%s: no spare buffers "
669                                        "available.\n", cp->dev->name);
670                         spin_unlock(&cp->rx_spare_lock);
671                         return NULL;
672                 }
673         }
674
675         entry = cp->rx_spare_list.next;
676         list_del(entry);
677         recover = ++cp->rx_spares_needed;
678         spin_unlock(&cp->rx_spare_lock);
679
680         /* trigger the timer to do the recovery */
681         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
682 #if 1
683                 atomic_inc(&cp->reset_task_pending);
684                 atomic_inc(&cp->reset_task_pending_spare);
685                 schedule_work(&cp->reset_task);
686 #else
687                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
688                 schedule_work(&cp->reset_task);
689 #endif
690         }
691         return list_entry(entry, cas_page_t, list);
692 }
693
694
695 static void cas_mif_poll(struct cas *cp, const int enable)
696 {
697         u32 cfg;
698
699         cfg  = readl(cp->regs + REG_MIF_CFG);
700         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
701
702         if (cp->phy_type & CAS_PHY_MII_MDIO1)
703                 cfg |= MIF_CFG_PHY_SELECT;
704
705         /* poll and interrupt on link status change. */
706         if (enable) {
707                 cfg |= MIF_CFG_POLL_EN;
708                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
709                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
710         }
711         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
712                cp->regs + REG_MIF_MASK);
713         writel(cfg, cp->regs + REG_MIF_CFG);
714 }
715
716 /* Must be invoked under cp->lock */
717 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
718 {
719         u16 ctl;
720 #if 1
721         int lcntl;
722         int changed = 0;
723         int oldstate = cp->lstate;
724         int link_was_not_down = !(oldstate == link_down);
725 #endif
726         /* Setup link parameters */
727         if (!ep)
728                 goto start_aneg;
729         lcntl = cp->link_cntl;
730         if (ep->autoneg == AUTONEG_ENABLE)
731                 cp->link_cntl = BMCR_ANENABLE;
732         else {
733                 cp->link_cntl = 0;
734                 if (ep->speed == SPEED_100)
735                         cp->link_cntl |= BMCR_SPEED100;
736                 else if (ep->speed == SPEED_1000)
737                         cp->link_cntl |= CAS_BMCR_SPEED1000;
738                 if (ep->duplex == DUPLEX_FULL)
739                         cp->link_cntl |= BMCR_FULLDPLX;
740         }
741 #if 1
742         changed = (lcntl != cp->link_cntl);
743 #endif
744 start_aneg:
745         if (cp->lstate == link_up) {
746                 printk(KERN_INFO "%s: PCS link down.\n",
747                        cp->dev->name);
748         } else {
749                 if (changed) {
750                         printk(KERN_INFO "%s: link configuration changed\n",
751                                cp->dev->name);
752                 }
753         }
754         cp->lstate = link_down;
755         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
756         if (!cp->hw_running)
757                 return;
758 #if 1
759         /*
760          * WTZ: If the old state was link_up, we turn off the carrier
761          * to replicate everything we do elsewhere on a link-down
762          * event when we were already in a link-up state..
763          */
764         if (oldstate == link_up)
765                 netif_carrier_off(cp->dev);
766         if (changed  && link_was_not_down) {
767                 /*
768                  * WTZ: This branch will simply schedule a full reset after
769                  * we explicitly changed link modes in an ioctl. See if this
770                  * fixes the link-problems we were having for forced mode.
771                  */
772                 atomic_inc(&cp->reset_task_pending);
773                 atomic_inc(&cp->reset_task_pending_all);
774                 schedule_work(&cp->reset_task);
775                 cp->timer_ticks = 0;
776                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
777                 return;
778         }
779 #endif
780         if (cp->phy_type & CAS_PHY_SERDES) {
781                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
782
783                 if (cp->link_cntl & BMCR_ANENABLE) {
784                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
785                         cp->lstate = link_aneg;
786                 } else {
787                         if (cp->link_cntl & BMCR_FULLDPLX)
788                                 val |= PCS_MII_CTRL_DUPLEX;
789                         val &= ~PCS_MII_AUTONEG_EN;
790                         cp->lstate = link_force_ok;
791                 }
792                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
793                 writel(val, cp->regs + REG_PCS_MII_CTRL);
794
795         } else {
796                 cas_mif_poll(cp, 0);
797                 ctl = cas_phy_read(cp, MII_BMCR);
798                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
799                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
800                 ctl |= cp->link_cntl;
801                 if (ctl & BMCR_ANENABLE) {
802                         ctl |= BMCR_ANRESTART;
803                         cp->lstate = link_aneg;
804                 } else {
805                         cp->lstate = link_force_ok;
806                 }
807                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
808                 cas_phy_write(cp, MII_BMCR, ctl);
809                 cas_mif_poll(cp, 1);
810         }
811
812         cp->timer_ticks = 0;
813         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
814 }
815
816 /* Must be invoked under cp->lock. */
817 static int cas_reset_mii_phy(struct cas *cp)
818 {
819         int limit = STOP_TRIES_PHY;
820         u16 val;
821
822         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
823         udelay(100);
824         while (limit--) {
825                 val = cas_phy_read(cp, MII_BMCR);
826                 if ((val & BMCR_RESET) == 0)
827                         break;
828                 udelay(10);
829         }
830         return (limit <= 0);
831 }
832
833 static void cas_saturn_firmware_load(struct cas *cp)
834 {
835         cas_saturn_patch_t *patch = cas_saturn_patch;
836
837         cas_phy_powerdown(cp);
838
839         /* expanded memory access mode */
840         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
841
842         /* pointer configuration for new firmware */
843         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
844         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
845         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
846         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
847         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
848         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
849         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
850         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
851
852         /* download new firmware */
853         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
854         cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
855         while (patch->addr) {
856                 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
857                 patch++;
858         }
859
860         /* enable firmware */
861         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
862         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
863 }
864
865
866 /* phy initialization */
867 static void cas_phy_init(struct cas *cp)
868 {
869         u16 val;
870
871         /* if we're in MII/GMII mode, set up phy */
872         if (CAS_PHY_MII(cp->phy_type)) {
873                 writel(PCS_DATAPATH_MODE_MII,
874                        cp->regs + REG_PCS_DATAPATH_MODE);
875
876                 cas_mif_poll(cp, 0);
877                 cas_reset_mii_phy(cp); /* take out of isolate mode */
878
879                 if (PHY_LUCENT_B0 == cp->phy_id) {
880                         /* workaround link up/down issue with lucent */
881                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
882                         cas_phy_write(cp, MII_BMCR, 0x00f1);
883                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
884
885                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
886                         /* workarounds for broadcom phy */
887                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
888                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
889                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
890                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
891                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
892                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
893                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
894                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
895                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
896                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
897                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
898
899                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
900                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
901                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
902                         if (val & 0x0080) {
903                                 /* link workaround */
904                                 cas_phy_write(cp, BROADCOM_MII_REG4,
905                                               val & ~0x0080);
906                         }
907
908                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
909                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
910                                SATURN_PCFG_FSI : 0x0,
911                                cp->regs + REG_SATURN_PCFG);
912
913                         /* load firmware to address 10Mbps auto-negotiation
914                          * issue. NOTE: this will need to be changed if the
915                          * default firmware gets fixed.
916                          */
917                         if (PHY_NS_DP83065 == cp->phy_id) {
918                                 cas_saturn_firmware_load(cp);
919                         }
920                         cas_phy_powerup(cp);
921                 }
922
923                 /* advertise capabilities */
924                 val = cas_phy_read(cp, MII_BMCR);
925                 val &= ~BMCR_ANENABLE;
926                 cas_phy_write(cp, MII_BMCR, val);
927                 udelay(10);
928
929                 cas_phy_write(cp, MII_ADVERTISE,
930                               cas_phy_read(cp, MII_ADVERTISE) |
931                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
932                                ADVERTISE_100HALF | ADVERTISE_100FULL |
933                                CAS_ADVERTISE_PAUSE |
934                                CAS_ADVERTISE_ASYM_PAUSE));
935
936                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
937                         /* make sure that we don't advertise half
938                          * duplex to avoid a chip issue
939                          */
940                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
941                         val &= ~CAS_ADVERTISE_1000HALF;
942                         val |= CAS_ADVERTISE_1000FULL;
943                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
944                 }
945
946         } else {
947                 /* reset pcs for serdes */
948                 u32 val;
949                 int limit;
950
951                 writel(PCS_DATAPATH_MODE_SERDES,
952                        cp->regs + REG_PCS_DATAPATH_MODE);
953
954                 /* enable serdes pins on saturn */
955                 if (cp->cas_flags & CAS_FLAG_SATURN)
956                         writel(0, cp->regs + REG_SATURN_PCFG);
957
958                 /* Reset PCS unit. */
959                 val = readl(cp->regs + REG_PCS_MII_CTRL);
960                 val |= PCS_MII_RESET;
961                 writel(val, cp->regs + REG_PCS_MII_CTRL);
962
963                 limit = STOP_TRIES;
964                 while (limit-- > 0) {
965                         udelay(10);
966                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
967                              PCS_MII_RESET) == 0)
968                                 break;
969                 }
970                 if (limit <= 0)
971                         printk(KERN_WARNING "%s: PCS reset bit would not "
972                                "clear [%08x].\n", cp->dev->name,
973                                readl(cp->regs + REG_PCS_STATE_MACHINE));
974
975                 /* Make sure PCS is disabled while changing advertisement
976                  * configuration.
977                  */
978                 writel(0x0, cp->regs + REG_PCS_CFG);
979
980                 /* Advertise all capabilities except half-duplex. */
981                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
982                 val &= ~PCS_MII_ADVERT_HD;
983                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
984                         PCS_MII_ADVERT_ASYM_PAUSE);
985                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
986
987                 /* enable PCS */
988                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
989
990                 /* pcs workaround: enable sync detect */
991                 writel(PCS_SERDES_CTRL_SYNCD_EN,
992                        cp->regs + REG_PCS_SERDES_CTRL);
993         }
994 }
995
996
997 static int cas_pcs_link_check(struct cas *cp)
998 {
999         u32 stat, state_machine;
1000         int retval = 0;
1001
1002         /* The link status bit latches on zero, so you must
1003          * read it twice in such a case to see a transition
1004          * to the link being up.
1005          */
1006         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1007         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1008                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1009
1010         /* The remote-fault indication is only valid
1011          * when autoneg has completed.
1012          */
1013         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1014                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1015             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
1016                 if (netif_msg_link(cp))
1017                         printk(KERN_INFO "%s: PCS RemoteFault\n",
1018                                cp->dev->name);
1019         }
1020
1021         /* work around link detection issue by querying the PCS state
1022          * machine directly.
1023          */
1024         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1025         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1026                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1027         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1028                 stat |= PCS_MII_STATUS_LINK_STATUS;
1029         }
1030
1031         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1032                 if (cp->lstate != link_up) {
1033                         if (cp->opened) {
1034                                 cp->lstate = link_up;
1035                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1036
1037                                 cas_set_link_modes(cp);
1038                                 netif_carrier_on(cp->dev);
1039                         }
1040                 }
1041         } else if (cp->lstate == link_up) {
1042                 cp->lstate = link_down;
1043                 if (link_transition_timeout != 0 &&
1044                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1045                     !cp->link_transition_jiffies_valid) {
1046                         /*
1047                          * force a reset, as a workaround for the
1048                          * link-failure problem. May want to move this to a
1049                          * point a bit earlier in the sequence. If we had
1050                          * generated a reset a short time ago, we'll wait for
1051                          * the link timer to check the status until a
1052                          * timer expires (link_transistion_jiffies_valid is
1053                          * true when the timer is running.)  Instead of using
1054                          * a system timer, we just do a check whenever the
1055                          * link timer is running - this clears the flag after
1056                          * a suitable delay.
1057                          */
1058                         retval = 1;
1059                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1060                         cp->link_transition_jiffies = jiffies;
1061                         cp->link_transition_jiffies_valid = 1;
1062                 } else {
1063                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1064                 }
1065                 netif_carrier_off(cp->dev);
1066                 if (cp->opened && netif_msg_link(cp)) {
1067                         printk(KERN_INFO "%s: PCS link down.\n",
1068                                cp->dev->name);
1069                 }
1070
1071                 /* Cassini only: if you force a mode, there can be
1072                  * sync problems on link down. to fix that, the following
1073                  * things need to be checked:
1074                  * 1) read serialink state register
1075                  * 2) read pcs status register to verify link down.
1076                  * 3) if link down and serial link == 0x03, then you need
1077                  *    to global reset the chip.
1078                  */
1079                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1080                         /* should check to see if we're in a forced mode */
1081                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1082                         if (stat == 0x03)
1083                                 return 1;
1084                 }
1085         } else if (cp->lstate == link_down) {
1086                 if (link_transition_timeout != 0 &&
1087                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1088                     !cp->link_transition_jiffies_valid) {
1089                         /* force a reset, as a workaround for the
1090                          * link-failure problem.  May want to move
1091                          * this to a point a bit earlier in the
1092                          * sequence.
1093                          */
1094                         retval = 1;
1095                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1096                         cp->link_transition_jiffies = jiffies;
1097                         cp->link_transition_jiffies_valid = 1;
1098                 } else {
1099                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1100                 }
1101         }
1102
1103         return retval;
1104 }
1105
1106 static int cas_pcs_interrupt(struct net_device *dev,
1107                              struct cas *cp, u32 status)
1108 {
1109         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1110
1111         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1112                 return 0;
1113         return cas_pcs_link_check(cp);
1114 }
1115
1116 static int cas_txmac_interrupt(struct net_device *dev,
1117                                struct cas *cp, u32 status)
1118 {
1119         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1120
1121         if (!txmac_stat)
1122                 return 0;
1123
1124         if (netif_msg_intr(cp))
1125                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1126                         cp->dev->name, txmac_stat);
1127
1128         /* Defer timer expiration is quite normal,
1129          * don't even log the event.
1130          */
1131         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1132             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1133                 return 0;
1134
1135         spin_lock(&cp->stat_lock[0]);
1136         if (txmac_stat & MAC_TX_UNDERRUN) {
1137                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1138                        dev->name);
1139                 cp->net_stats[0].tx_fifo_errors++;
1140         }
1141
1142         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1143                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1144                        dev->name);
1145                 cp->net_stats[0].tx_errors++;
1146         }
1147
1148         /* The rest are all cases of one of the 16-bit TX
1149          * counters expiring.
1150          */
1151         if (txmac_stat & MAC_TX_COLL_NORMAL)
1152                 cp->net_stats[0].collisions += 0x10000;
1153
1154         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1155                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1156                 cp->net_stats[0].collisions += 0x10000;
1157         }
1158
1159         if (txmac_stat & MAC_TX_COLL_LATE) {
1160                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1161                 cp->net_stats[0].collisions += 0x10000;
1162         }
1163         spin_unlock(&cp->stat_lock[0]);
1164
1165         /* We do not keep track of MAC_TX_COLL_FIRST and
1166          * MAC_TX_PEAK_ATTEMPTS events.
1167          */
1168         return 0;
1169 }
1170
1171 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1172 {
1173         cas_hp_inst_t *inst;
1174         u32 val;
1175         int i;
1176
1177         i = 0;
1178         while ((inst = firmware) && inst->note) {
1179                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1180
1181                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1182                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1183                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1184
1185                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1186                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1187                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1188                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1189                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1190                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1191                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1192                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1193
1194                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1195                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1196                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1197                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1198                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1199                 ++firmware;
1200                 ++i;
1201         }
1202 }
1203
1204 static void cas_init_rx_dma(struct cas *cp)
1205 {
1206         u64 desc_dma = cp->block_dvma;
1207         u32 val;
1208         int i, size;
1209
1210         /* rx free descriptors */
1211         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1212         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1213         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1214         if ((N_RX_DESC_RINGS > 1) &&
1215             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1216                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1217         writel(val, cp->regs + REG_RX_CFG);
1218
1219         val = (unsigned long) cp->init_rxds[0] -
1220                 (unsigned long) cp->init_block;
1221         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1222         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1223         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1224
1225         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1226                 /* rx desc 2 is for IPSEC packets. however,
1227                  * we don't it that for that purpose.
1228                  */
1229                 val = (unsigned long) cp->init_rxds[1] -
1230                         (unsigned long) cp->init_block;
1231                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1232                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1233                        REG_PLUS_RX_DB1_LOW);
1234                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1235                        REG_PLUS_RX_KICK1);
1236         }
1237
1238         /* rx completion registers */
1239         val = (unsigned long) cp->init_rxcs[0] -
1240                 (unsigned long) cp->init_block;
1241         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1242         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1243
1244         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1245                 /* rx comp 2-4 */
1246                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1247                         val = (unsigned long) cp->init_rxcs[i] -
1248                                 (unsigned long) cp->init_block;
1249                         writel((desc_dma + val) >> 32, cp->regs +
1250                                REG_PLUS_RX_CBN_HI(i));
1251                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1252                                REG_PLUS_RX_CBN_LOW(i));
1253                 }
1254         }
1255
1256         /* read selective clear regs to prevent spurious interrupts
1257          * on reset because complete == kick.
1258          * selective clear set up to prevent interrupts on resets
1259          */
1260         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1261         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1262         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1263                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1264                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1265
1266                 /* 2 is different from 3 and 4 */
1267                 if (N_RX_COMP_RINGS > 1)
1268                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1269                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1270
1271                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1272                         writel(INTR_RX_DONE_ALT,
1273                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1274         }
1275
1276         /* set up pause thresholds */
1277         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1278                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1279         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1280                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1281         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1282
1283         /* zero out dma reassembly buffers */
1284         for (i = 0; i < 64; i++) {
1285                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1286                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1287                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1288                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1289         }
1290
1291         /* make sure address register is 0 for normal operation */
1292         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1293         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1294
1295         /* interrupt mitigation */
1296 #ifdef USE_RX_BLANK
1297         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1298         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1299         writel(val, cp->regs + REG_RX_BLANK);
1300 #else
1301         writel(0x0, cp->regs + REG_RX_BLANK);
1302 #endif
1303
1304         /* interrupt generation as a function of low water marks for
1305          * free desc and completion entries. these are used to trigger
1306          * housekeeping for rx descs. we don't use the free interrupt
1307          * as it's not very useful
1308          */
1309         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1310         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1311         writel(val, cp->regs + REG_RX_AE_THRESH);
1312         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1313                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1314                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1315         }
1316
1317         /* Random early detect registers. useful for congestion avoidance.
1318          * this should be tunable.
1319          */
1320         writel(0x0, cp->regs + REG_RX_RED);
1321
1322         /* receive page sizes. default == 2K (0x800) */
1323         val = 0;
1324         if (cp->page_size == 0x1000)
1325                 val = 0x1;
1326         else if (cp->page_size == 0x2000)
1327                 val = 0x2;
1328         else if (cp->page_size == 0x4000)
1329                 val = 0x3;
1330
1331         /* round mtu + offset. constrain to page size. */
1332         size = cp->dev->mtu + 64;
1333         if (size > cp->page_size)
1334                 size = cp->page_size;
1335
1336         if (size <= 0x400)
1337                 i = 0x0;
1338         else if (size <= 0x800)
1339                 i = 0x1;
1340         else if (size <= 0x1000)
1341                 i = 0x2;
1342         else
1343                 i = 0x3;
1344
1345         cp->mtu_stride = 1 << (i + 10);
1346         val  = CAS_BASE(RX_PAGE_SIZE, val);
1347         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1348         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1349         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1350         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1351
1352         /* enable the header parser if desired */
1353         if (CAS_HP_FIRMWARE == cas_prog_null)
1354                 return;
1355
1356         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1357         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1358         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1359         writel(val, cp->regs + REG_HP_CFG);
1360 }
1361
1362 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1363 {
1364         memset(rxc, 0, sizeof(*rxc));
1365         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1366 }
1367
1368 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1369  * flipping is protected by the fact that the chip will not
1370  * hand back the same page index while it's being processed.
1371  */
1372 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1373 {
1374         cas_page_t *page = cp->rx_pages[1][index];
1375         cas_page_t *new;
1376
1377         if (cas_buffer_count(page) == 1)
1378                 return page;
1379
1380         new = cas_page_dequeue(cp);
1381         if (new) {
1382                 spin_lock(&cp->rx_inuse_lock);
1383                 list_add(&page->list, &cp->rx_inuse_list);
1384                 spin_unlock(&cp->rx_inuse_lock);
1385         }
1386         return new;
1387 }
1388
1389 /* this needs to be changed if we actually use the ENC RX DESC ring */
1390 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1391                                  const int index)
1392 {
1393         cas_page_t **page0 = cp->rx_pages[0];
1394         cas_page_t **page1 = cp->rx_pages[1];
1395
1396         /* swap if buffer is in use */
1397         if (cas_buffer_count(page0[index]) > 1) {
1398                 cas_page_t *new = cas_page_spare(cp, index);
1399                 if (new) {
1400                         page1[index] = page0[index];
1401                         page0[index] = new;
1402                 }
1403         }
1404         RX_USED_SET(page0[index], 0);
1405         return page0[index];
1406 }
1407
1408 static void cas_clean_rxds(struct cas *cp)
1409 {
1410         /* only clean ring 0 as ring 1 is used for spare buffers */
1411         struct cas_rx_desc *rxd = cp->init_rxds[0];
1412         int i, size;
1413
1414         /* release all rx flows */
1415         for (i = 0; i < N_RX_FLOWS; i++) {
1416                 struct sk_buff *skb;
1417                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1418                         cas_skb_release(skb);
1419                 }
1420         }
1421
1422         /* initialize descriptors */
1423         size = RX_DESC_RINGN_SIZE(0);
1424         for (i = 0; i < size; i++) {
1425                 cas_page_t *page = cas_page_swap(cp, 0, i);
1426                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1427                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1428                                             CAS_BASE(RX_INDEX_RING, 0));
1429         }
1430
1431         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1432         cp->rx_last[0] = 0;
1433         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1434 }
1435
1436 static void cas_clean_rxcs(struct cas *cp)
1437 {
1438         int i, j;
1439
1440         /* take ownership of rx comp descriptors */
1441         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1442         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1443         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1444                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1445                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1446                         cas_rxc_init(rxc + j);
1447                 }
1448         }
1449 }
1450
1451 #if 0
1452 /* When we get a RX fifo overflow, the RX unit is probably hung
1453  * so we do the following.
1454  *
1455  * If any part of the reset goes wrong, we return 1 and that causes the
1456  * whole chip to be reset.
1457  */
1458 static int cas_rxmac_reset(struct cas *cp)
1459 {
1460         struct net_device *dev = cp->dev;
1461         int limit;
1462         u32 val;
1463
1464         /* First, reset MAC RX. */
1465         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1466         for (limit = 0; limit < STOP_TRIES; limit++) {
1467                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1468                         break;
1469                 udelay(10);
1470         }
1471         if (limit == STOP_TRIES) {
1472                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1473                        "chip.\n", dev->name);
1474                 return 1;
1475         }
1476
1477         /* Second, disable RX DMA. */
1478         writel(0, cp->regs + REG_RX_CFG);
1479         for (limit = 0; limit < STOP_TRIES; limit++) {
1480                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1481                         break;
1482                 udelay(10);
1483         }
1484         if (limit == STOP_TRIES) {
1485                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1486                        "chip.\n", dev->name);
1487                 return 1;
1488         }
1489
1490         mdelay(5);
1491
1492         /* Execute RX reset command. */
1493         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1494         for (limit = 0; limit < STOP_TRIES; limit++) {
1495                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1496                         break;
1497                 udelay(10);
1498         }
1499         if (limit == STOP_TRIES) {
1500                 printk(KERN_ERR "%s: RX reset command will not execute, "
1501                        "resetting whole chip.\n", dev->name);
1502                 return 1;
1503         }
1504
1505         /* reset driver rx state */
1506         cas_clean_rxds(cp);
1507         cas_clean_rxcs(cp);
1508
1509         /* Now, reprogram the rest of RX unit. */
1510         cas_init_rx_dma(cp);
1511
1512         /* re-enable */
1513         val = readl(cp->regs + REG_RX_CFG);
1514         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1515         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1516         val = readl(cp->regs + REG_MAC_RX_CFG);
1517         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1518         return 0;
1519 }
1520 #endif
1521
1522 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1523                                u32 status)
1524 {
1525         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1526
1527         if (!stat)
1528                 return 0;
1529
1530         if (netif_msg_intr(cp))
1531                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1532                         cp->dev->name, stat);
1533
1534         /* these are all rollovers */
1535         spin_lock(&cp->stat_lock[0]);
1536         if (stat & MAC_RX_ALIGN_ERR)
1537                 cp->net_stats[0].rx_frame_errors += 0x10000;
1538
1539         if (stat & MAC_RX_CRC_ERR)
1540                 cp->net_stats[0].rx_crc_errors += 0x10000;
1541
1542         if (stat & MAC_RX_LEN_ERR)
1543                 cp->net_stats[0].rx_length_errors += 0x10000;
1544
1545         if (stat & MAC_RX_OVERFLOW) {
1546                 cp->net_stats[0].rx_over_errors++;
1547                 cp->net_stats[0].rx_fifo_errors++;
1548         }
1549
1550         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1551          * events.
1552          */
1553         spin_unlock(&cp->stat_lock[0]);
1554         return 0;
1555 }
1556
1557 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1558                              u32 status)
1559 {
1560         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1561
1562         if (!stat)
1563                 return 0;
1564
1565         if (netif_msg_intr(cp))
1566                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1567                         cp->dev->name, stat);
1568
1569         /* This interrupt is just for pause frame and pause
1570          * tracking.  It is useful for diagnostics and debug
1571          * but probably by default we will mask these events.
1572          */
1573         if (stat & MAC_CTRL_PAUSE_STATE)
1574                 cp->pause_entered++;
1575
1576         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1577                 cp->pause_last_time_recvd = (stat >> 16);
1578
1579         return 0;
1580 }
1581
1582
1583 /* Must be invoked under cp->lock. */
1584 static inline int cas_mdio_link_not_up(struct cas *cp)
1585 {
1586         u16 val;
1587
1588         switch (cp->lstate) {
1589         case link_force_ret:
1590                 if (netif_msg_link(cp))
1591                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1592                                 " forced mode\n", cp->dev->name);
1593                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1594                 cp->timer_ticks = 5;
1595                 cp->lstate = link_force_ok;
1596                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1597                 break;
1598
1599         case link_aneg:
1600                 val = cas_phy_read(cp, MII_BMCR);
1601
1602                 /* Try forced modes. we try things in the following order:
1603                  * 1000 full -> 100 full/half -> 10 half
1604                  */
1605                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1606                 val |= BMCR_FULLDPLX;
1607                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1608                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1609                 cas_phy_write(cp, MII_BMCR, val);
1610                 cp->timer_ticks = 5;
1611                 cp->lstate = link_force_try;
1612                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1613                 break;
1614
1615         case link_force_try:
1616                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1617                 val = cas_phy_read(cp, MII_BMCR);
1618                 cp->timer_ticks = 5;
1619                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1620                         val &= ~CAS_BMCR_SPEED1000;
1621                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1622                         cas_phy_write(cp, MII_BMCR, val);
1623                         break;
1624                 }
1625
1626                 if (val & BMCR_SPEED100) {
1627                         if (val & BMCR_FULLDPLX) /* fd failed */
1628                                 val &= ~BMCR_FULLDPLX;
1629                         else { /* 100Mbps failed */
1630                                 val &= ~BMCR_SPEED100;
1631                         }
1632                         cas_phy_write(cp, MII_BMCR, val);
1633                         break;
1634                 }
1635         default:
1636                 break;
1637         }
1638         return 0;
1639 }
1640
1641
1642 /* must be invoked with cp->lock held */
1643 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1644 {
1645         int restart;
1646
1647         if (bmsr & BMSR_LSTATUS) {
1648                 /* Ok, here we got a link. If we had it due to a forced
1649                  * fallback, and we were configured for autoneg, we
1650                  * retry a short autoneg pass. If you know your hub is
1651                  * broken, use ethtool ;)
1652                  */
1653                 if ((cp->lstate == link_force_try) &&
1654                     (cp->link_cntl & BMCR_ANENABLE)) {
1655                         cp->lstate = link_force_ret;
1656                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1657                         cas_mif_poll(cp, 0);
1658                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1659                         cp->timer_ticks = 5;
1660                         if (cp->opened && netif_msg_link(cp))
1661                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1662                                        " autoneg once...\n", cp->dev->name);
1663                         cas_phy_write(cp, MII_BMCR,
1664                                       cp->link_fcntl | BMCR_ANENABLE |
1665                                       BMCR_ANRESTART);
1666                         cas_mif_poll(cp, 1);
1667
1668                 } else if (cp->lstate != link_up) {
1669                         cp->lstate = link_up;
1670                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1671
1672                         if (cp->opened) {
1673                                 cas_set_link_modes(cp);
1674                                 netif_carrier_on(cp->dev);
1675                         }
1676                 }
1677                 return 0;
1678         }
1679
1680         /* link not up. if the link was previously up, we restart the
1681          * whole process
1682          */
1683         restart = 0;
1684         if (cp->lstate == link_up) {
1685                 cp->lstate = link_down;
1686                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1687
1688                 netif_carrier_off(cp->dev);
1689                 if (cp->opened && netif_msg_link(cp))
1690                         printk(KERN_INFO "%s: Link down\n",
1691                                cp->dev->name);
1692                 restart = 1;
1693
1694         } else if (++cp->timer_ticks > 10)
1695                 cas_mdio_link_not_up(cp);
1696
1697         return restart;
1698 }
1699
1700 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1701                              u32 status)
1702 {
1703         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1704         u16 bmsr;
1705
1706         /* check for a link change */
1707         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1708                 return 0;
1709
1710         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1711         return cas_mii_link_check(cp, bmsr);
1712 }
1713
1714 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1715                              u32 status)
1716 {
1717         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1718
1719         if (!stat)
1720                 return 0;
1721
1722         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1723                readl(cp->regs + REG_BIM_DIAG));
1724
1725         /* cassini+ has this reserved */
1726         if ((stat & PCI_ERR_BADACK) &&
1727             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1728                 printk("<No ACK64# during ABS64 cycle> ");
1729
1730         if (stat & PCI_ERR_DTRTO)
1731                 printk("<Delayed transaction timeout> ");
1732         if (stat & PCI_ERR_OTHER)
1733                 printk("<other> ");
1734         if (stat & PCI_ERR_BIM_DMA_WRITE)
1735                 printk("<BIM DMA 0 write req> ");
1736         if (stat & PCI_ERR_BIM_DMA_READ)
1737                 printk("<BIM DMA 0 read req> ");
1738         printk("\n");
1739
1740         if (stat & PCI_ERR_OTHER) {
1741                 u16 cfg;
1742
1743                 /* Interrogate PCI config space for the
1744                  * true cause.
1745                  */
1746                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1747                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1748                        dev->name, cfg);
1749                 if (cfg & PCI_STATUS_PARITY)
1750                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1751                                dev->name);
1752                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1753                         printk(KERN_ERR "%s: PCI target abort.\n",
1754                                dev->name);
1755                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1756                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1757                                dev->name);
1758                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1759                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1760                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1761                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1762                                dev->name);
1763                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1764                         printk(KERN_ERR "%s: PCI parity error.\n",
1765                                dev->name);
1766
1767                 /* Write the error bits back to clear them. */
1768                 cfg &= (PCI_STATUS_PARITY |
1769                         PCI_STATUS_SIG_TARGET_ABORT |
1770                         PCI_STATUS_REC_TARGET_ABORT |
1771                         PCI_STATUS_REC_MASTER_ABORT |
1772                         PCI_STATUS_SIG_SYSTEM_ERROR |
1773                         PCI_STATUS_DETECTED_PARITY);
1774                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1775         }
1776
1777         /* For all PCI errors, we should reset the chip. */
1778         return 1;
1779 }
1780
1781 /* All non-normal interrupt conditions get serviced here.
1782  * Returns non-zero if we should just exit the interrupt
1783  * handler right now (ie. if we reset the card which invalidates
1784  * all of the other original irq status bits).
1785  */
1786 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1787                             u32 status)
1788 {
1789         if (status & INTR_RX_TAG_ERROR) {
1790                 /* corrupt RX tag framing */
1791                 if (netif_msg_rx_err(cp))
1792                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1793                                 cp->dev->name);
1794                 spin_lock(&cp->stat_lock[0]);
1795                 cp->net_stats[0].rx_errors++;
1796                 spin_unlock(&cp->stat_lock[0]);
1797                 goto do_reset;
1798         }
1799
1800         if (status & INTR_RX_LEN_MISMATCH) {
1801                 /* length mismatch. */
1802                 if (netif_msg_rx_err(cp))
1803                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1804                                 cp->dev->name);
1805                 spin_lock(&cp->stat_lock[0]);
1806                 cp->net_stats[0].rx_errors++;
1807                 spin_unlock(&cp->stat_lock[0]);
1808                 goto do_reset;
1809         }
1810
1811         if (status & INTR_PCS_STATUS) {
1812                 if (cas_pcs_interrupt(dev, cp, status))
1813                         goto do_reset;
1814         }
1815
1816         if (status & INTR_TX_MAC_STATUS) {
1817                 if (cas_txmac_interrupt(dev, cp, status))
1818                         goto do_reset;
1819         }
1820
1821         if (status & INTR_RX_MAC_STATUS) {
1822                 if (cas_rxmac_interrupt(dev, cp, status))
1823                         goto do_reset;
1824         }
1825
1826         if (status & INTR_MAC_CTRL_STATUS) {
1827                 if (cas_mac_interrupt(dev, cp, status))
1828                         goto do_reset;
1829         }
1830
1831         if (status & INTR_MIF_STATUS) {
1832                 if (cas_mif_interrupt(dev, cp, status))
1833                         goto do_reset;
1834         }
1835
1836         if (status & INTR_PCI_ERROR_STATUS) {
1837                 if (cas_pci_interrupt(dev, cp, status))
1838                         goto do_reset;
1839         }
1840         return 0;
1841
1842 do_reset:
1843 #if 1
1844         atomic_inc(&cp->reset_task_pending);
1845         atomic_inc(&cp->reset_task_pending_all);
1846         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1847                dev->name, status);
1848         schedule_work(&cp->reset_task);
1849 #else
1850         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1851         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1852         schedule_work(&cp->reset_task);
1853 #endif
1854         return 1;
1855 }
1856
1857 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1858  *       determining whether to do a netif_stop/wakeup
1859  */
1860 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1861 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1862 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1863                                   const int len)
1864 {
1865         unsigned long off = addr + len;
1866
1867         if (CAS_TABORT(cp) == 1)
1868                 return 0;
1869         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1870                 return 0;
1871         return TX_TARGET_ABORT_LEN;
1872 }
1873
1874 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1875 {
1876         struct cas_tx_desc *txds;
1877         struct sk_buff **skbs;
1878         struct net_device *dev = cp->dev;
1879         int entry, count;
1880
1881         spin_lock(&cp->tx_lock[ring]);
1882         txds = cp->init_txds[ring];
1883         skbs = cp->tx_skbs[ring];
1884         entry = cp->tx_old[ring];
1885
1886         count = TX_BUFF_COUNT(ring, entry, limit);
1887         while (entry != limit) {
1888                 struct sk_buff *skb = skbs[entry];
1889                 dma_addr_t daddr;
1890                 u32 dlen;
1891                 int frag;
1892
1893                 if (!skb) {
1894                         /* this should never occur */
1895                         entry = TX_DESC_NEXT(ring, entry);
1896                         continue;
1897                 }
1898
1899                 /* however, we might get only a partial skb release. */
1900                 count -= skb_shinfo(skb)->nr_frags +
1901                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1902                 if (count < 0)
1903                         break;
1904
1905                 if (netif_msg_tx_done(cp))
1906                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1907                                cp->dev->name, ring, entry);
1908
1909                 skbs[entry] = NULL;
1910                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1911
1912                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1913                         struct cas_tx_desc *txd = txds + entry;
1914
1915                         daddr = le64_to_cpu(txd->buffer);
1916                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1917                                        le64_to_cpu(txd->control));
1918                         pci_unmap_page(cp->pdev, daddr, dlen,
1919                                        PCI_DMA_TODEVICE);
1920                         entry = TX_DESC_NEXT(ring, entry);
1921
1922                         /* tiny buffer may follow */
1923                         if (cp->tx_tiny_use[ring][entry].used) {
1924                                 cp->tx_tiny_use[ring][entry].used = 0;
1925                                 entry = TX_DESC_NEXT(ring, entry);
1926                         }
1927                 }
1928
1929                 spin_lock(&cp->stat_lock[ring]);
1930                 cp->net_stats[ring].tx_packets++;
1931                 cp->net_stats[ring].tx_bytes += skb->len;
1932                 spin_unlock(&cp->stat_lock[ring]);
1933                 dev_kfree_skb_irq(skb);
1934         }
1935         cp->tx_old[ring] = entry;
1936
1937         /* this is wrong for multiple tx rings. the net device needs
1938          * multiple queues for this to do the right thing.  we wait
1939          * for 2*packets to be available when using tiny buffers
1940          */
1941         if (netif_queue_stopped(dev) &&
1942             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1943                 netif_wake_queue(dev);
1944         spin_unlock(&cp->tx_lock[ring]);
1945 }
1946
1947 static void cas_tx(struct net_device *dev, struct cas *cp,
1948                    u32 status)
1949 {
1950         int limit, ring;
1951 #ifdef USE_TX_COMPWB
1952         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1953 #endif
1954         if (netif_msg_intr(cp))
1955                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1956                         cp->dev->name, status, (unsigned long long)compwb);
1957         /* process all the rings */
1958         for (ring = 0; ring < N_TX_RINGS; ring++) {
1959 #ifdef USE_TX_COMPWB
1960                 /* use the completion writeback registers */
1961                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1962                         CAS_VAL(TX_COMPWB_LSB, compwb);
1963                 compwb = TX_COMPWB_NEXT(compwb);
1964 #else
1965                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1966 #endif
1967                 if (cp->tx_old[ring] != limit)
1968                         cas_tx_ringN(cp, ring, limit);
1969         }
1970 }
1971
1972
1973 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1974                               int entry, const u64 *words,
1975                               struct sk_buff **skbref)
1976 {
1977         int dlen, hlen, len, i, alloclen;
1978         int off, swivel = RX_SWIVEL_OFF_VAL;
1979         struct cas_page *page;
1980         struct sk_buff *skb;
1981         void *addr, *crcaddr;
1982         char *p;
1983
1984         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1985         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1986         len  = hlen + dlen;
1987
1988         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1989                 alloclen = len;
1990         else
1991                 alloclen = max(hlen, RX_COPY_MIN);
1992
1993         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1994         if (skb == NULL)
1995                 return -1;
1996
1997         *skbref = skb;
1998         skb_reserve(skb, swivel);
1999
2000         p = skb->data;
2001         addr = crcaddr = NULL;
2002         if (hlen) { /* always copy header pages */
2003                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2004                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2005                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
2006                         swivel;
2007
2008                 i = hlen;
2009                 if (!dlen) /* attach FCS */
2010                         i += cp->crc_size;
2011                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2012                                     PCI_DMA_FROMDEVICE);
2013                 addr = cas_page_map(page->buffer);
2014                 memcpy(p, addr + off, i);
2015                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2016                                     PCI_DMA_FROMDEVICE);
2017                 cas_page_unmap(addr);
2018                 RX_USED_ADD(page, 0x100);
2019                 p += hlen;
2020                 swivel = 0;
2021         }
2022
2023
2024         if (alloclen < (hlen + dlen)) {
2025                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2026
2027                 /* normal or jumbo packets. we use frags */
2028                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2029                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2030                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2031
2032                 hlen = min(cp->page_size - off, dlen);
2033                 if (hlen < 0) {
2034                         if (netif_msg_rx_err(cp)) {
2035                                 printk(KERN_DEBUG "%s: rx page overflow: "
2036                                        "%d\n", cp->dev->name, hlen);
2037                         }
2038                         dev_kfree_skb_irq(skb);
2039                         return -1;
2040                 }
2041                 i = hlen;
2042                 if (i == dlen)  /* attach FCS */
2043                         i += cp->crc_size;
2044                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2045                                     PCI_DMA_FROMDEVICE);
2046
2047                 /* make sure we always copy a header */
2048                 swivel = 0;
2049                 if (p == (char *) skb->data) { /* not split */
2050                         addr = cas_page_map(page->buffer);
2051                         memcpy(p, addr + off, RX_COPY_MIN);
2052                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2053                                         PCI_DMA_FROMDEVICE);
2054                         cas_page_unmap(addr);
2055                         off += RX_COPY_MIN;
2056                         swivel = RX_COPY_MIN;
2057                         RX_USED_ADD(page, cp->mtu_stride);
2058                 } else {
2059                         RX_USED_ADD(page, hlen);
2060                 }
2061                 skb_put(skb, alloclen);
2062
2063                 skb_shinfo(skb)->nr_frags++;
2064                 skb->data_len += hlen - swivel;
2065                 skb->len      += hlen - swivel;
2066
2067                 get_page(page->buffer);
2068                 cas_buffer_inc(page);
2069                 frag->page = page->buffer;
2070                 frag->page_offset = off;
2071                 frag->size = hlen - swivel;
2072
2073                 /* any more data? */
2074                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2075                         hlen = dlen;
2076                         off = 0;
2077
2078                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2079                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2080                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2081                                             hlen + cp->crc_size,
2082                                             PCI_DMA_FROMDEVICE);
2083                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2084                                             hlen + cp->crc_size,
2085                                             PCI_DMA_FROMDEVICE);
2086
2087                         skb_shinfo(skb)->nr_frags++;
2088                         skb->data_len += hlen;
2089                         skb->len      += hlen;
2090                         frag++;
2091
2092                         get_page(page->buffer);
2093                         cas_buffer_inc(page);
2094                         frag->page = page->buffer;
2095                         frag->page_offset = 0;
2096                         frag->size = hlen;
2097                         RX_USED_ADD(page, hlen + cp->crc_size);
2098                 }
2099
2100                 if (cp->crc_size) {
2101                         addr = cas_page_map(page->buffer);
2102                         crcaddr  = addr + off + hlen;
2103                 }
2104
2105         } else {
2106                 /* copying packet */
2107                 if (!dlen)
2108                         goto end_copy_pkt;
2109
2110                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2111                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2112                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2113                 hlen = min(cp->page_size - off, dlen);
2114                 if (hlen < 0) {
2115                         if (netif_msg_rx_err(cp)) {
2116                                 printk(KERN_DEBUG "%s: rx page overflow: "
2117                                        "%d\n", cp->dev->name, hlen);
2118                         }
2119                         dev_kfree_skb_irq(skb);
2120                         return -1;
2121                 }
2122                 i = hlen;
2123                 if (i == dlen) /* attach FCS */
2124                         i += cp->crc_size;
2125                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2126                                     PCI_DMA_FROMDEVICE);
2127                 addr = cas_page_map(page->buffer);
2128                 memcpy(p, addr + off, i);
2129                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2130                                     PCI_DMA_FROMDEVICE);
2131                 cas_page_unmap(addr);
2132                 if (p == (char *) skb->data) /* not split */
2133                         RX_USED_ADD(page, cp->mtu_stride);
2134                 else
2135                         RX_USED_ADD(page, i);
2136
2137                 /* any more data? */
2138                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2139                         p += hlen;
2140                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2141                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2142                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2143                                             dlen + cp->crc_size,
2144                                             PCI_DMA_FROMDEVICE);
2145                         addr = cas_page_map(page->buffer);
2146                         memcpy(p, addr, dlen + cp->crc_size);
2147                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2148                                             dlen + cp->crc_size,
2149                                             PCI_DMA_FROMDEVICE);
2150                         cas_page_unmap(addr);
2151                         RX_USED_ADD(page, dlen + cp->crc_size);
2152                 }
2153 end_copy_pkt:
2154                 if (cp->crc_size) {
2155                         addr    = NULL;
2156                         crcaddr = skb->data + alloclen;
2157                 }
2158                 skb_put(skb, alloclen);
2159         }
2160
2161         i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2162         if (cp->crc_size) {
2163                 /* checksum includes FCS. strip it out. */
2164                 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2165                 if (addr)
2166                         cas_page_unmap(addr);
2167         }
2168         skb->csum = ntohs(i ^ 0xffff);
2169         skb->ip_summed = CHECKSUM_COMPLETE;
2170         skb->protocol = eth_type_trans(skb, cp->dev);
2171         return len;
2172 }
2173
2174
2175 /* we can handle up to 64 rx flows at a time. we do the same thing
2176  * as nonreassm except that we batch up the buffers.
2177  * NOTE: we currently just treat each flow as a bunch of packets that
2178  *       we pass up. a better way would be to coalesce the packets
2179  *       into a jumbo packet. to do that, we need to do the following:
2180  *       1) the first packet will have a clean split between header and
2181  *          data. save both.
2182  *       2) each time the next flow packet comes in, extend the
2183  *          data length and merge the checksums.
2184  *       3) on flow release, fix up the header.
2185  *       4) make sure the higher layer doesn't care.
2186  * because packets get coalesced, we shouldn't run into fragment count
2187  * issues.
2188  */
2189 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2190                                    struct sk_buff *skb)
2191 {
2192         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2193         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2194
2195         /* this is protected at a higher layer, so no need to
2196          * do any additional locking here. stick the buffer
2197          * at the end.
2198          */
2199         __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2200         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2201                 while ((skb = __skb_dequeue(flow))) {
2202                         cas_skb_release(skb);
2203                 }
2204         }
2205 }
2206
2207 /* put rx descriptor back on ring. if a buffer is in use by a higher
2208  * layer, this will need to put in a replacement.
2209  */
2210 static void cas_post_page(struct cas *cp, const int ring, const int index)
2211 {
2212         cas_page_t *new;
2213         int entry;
2214
2215         entry = cp->rx_old[ring];
2216
2217         new = cas_page_swap(cp, ring, index);
2218         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2219         cp->init_rxds[ring][entry].index  =
2220                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2221                             CAS_BASE(RX_INDEX_RING, ring));
2222
2223         entry = RX_DESC_ENTRY(ring, entry + 1);
2224         cp->rx_old[ring] = entry;
2225
2226         if (entry % 4)
2227                 return;
2228
2229         if (ring == 0)
2230                 writel(entry, cp->regs + REG_RX_KICK);
2231         else if ((N_RX_DESC_RINGS > 1) &&
2232                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2233                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2234 }
2235
2236
2237 /* only when things are bad */
2238 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2239 {
2240         unsigned int entry, last, count, released;
2241         int cluster;
2242         cas_page_t **page = cp->rx_pages[ring];
2243
2244         entry = cp->rx_old[ring];
2245
2246         if (netif_msg_intr(cp))
2247                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2248                        cp->dev->name, ring, entry);
2249
2250         cluster = -1;
2251         count = entry & 0x3;
2252         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2253         released = 0;
2254         while (entry != last) {
2255                 /* make a new buffer if it's still in use */
2256                 if (cas_buffer_count(page[entry]) > 1) {
2257                         cas_page_t *new = cas_page_dequeue(cp);
2258                         if (!new) {
2259                                 /* let the timer know that we need to
2260                                  * do this again
2261                                  */
2262                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2263                                 if (!timer_pending(&cp->link_timer))
2264                                         mod_timer(&cp->link_timer, jiffies +
2265                                                   CAS_LINK_FAST_TIMEOUT);
2266                                 cp->rx_old[ring]  = entry;
2267                                 cp->rx_last[ring] = num ? num - released : 0;
2268                                 return -ENOMEM;
2269                         }
2270                         spin_lock(&cp->rx_inuse_lock);
2271                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2272                         spin_unlock(&cp->rx_inuse_lock);
2273                         cp->init_rxds[ring][entry].buffer =
2274                                 cpu_to_le64(new->dma_addr);
2275                         page[entry] = new;
2276
2277                 }
2278
2279                 if (++count == 4) {
2280                         cluster = entry;
2281                         count = 0;
2282                 }
2283                 released++;
2284                 entry = RX_DESC_ENTRY(ring, entry + 1);
2285         }
2286         cp->rx_old[ring] = entry;
2287
2288         if (cluster < 0)
2289                 return 0;
2290
2291         if (ring == 0)
2292                 writel(cluster, cp->regs + REG_RX_KICK);
2293         else if ((N_RX_DESC_RINGS > 1) &&
2294                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2295                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2296         return 0;
2297 }
2298
2299
2300 /* process a completion ring. packets are set up in three basic ways:
2301  * small packets: should be copied header + data in single buffer.
2302  * large packets: header and data in a single buffer.
2303  * split packets: header in a separate buffer from data.
2304  *                data may be in multiple pages. data may be > 256
2305  *                bytes but in a single page.
2306  *
2307  * NOTE: RX page posting is done in this routine as well. while there's
2308  *       the capability of using multiple RX completion rings, it isn't
2309  *       really worthwhile due to the fact that the page posting will
2310  *       force serialization on the single descriptor ring.
2311  */
2312 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2313 {
2314         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2315         int entry, drops;
2316         int npackets = 0;
2317
2318         if (netif_msg_intr(cp))
2319                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2320                        cp->dev->name, ring,
2321                        readl(cp->regs + REG_RX_COMP_HEAD),
2322                        cp->rx_new[ring]);
2323
2324         entry = cp->rx_new[ring];
2325         drops = 0;
2326         while (1) {
2327                 struct cas_rx_comp *rxc = rxcs + entry;
2328                 struct sk_buff *skb;
2329                 int type, len;
2330                 u64 words[4];
2331                 int i, dring;
2332
2333                 words[0] = le64_to_cpu(rxc->word1);
2334                 words[1] = le64_to_cpu(rxc->word2);
2335                 words[2] = le64_to_cpu(rxc->word3);
2336                 words[3] = le64_to_cpu(rxc->word4);
2337
2338                 /* don't touch if still owned by hw */
2339                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2340                 if (type == 0)
2341                         break;
2342
2343                 /* hw hasn't cleared the zero bit yet */
2344                 if (words[3] & RX_COMP4_ZERO) {
2345                         break;
2346                 }
2347
2348                 /* get info on the packet */
2349                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2350                         spin_lock(&cp->stat_lock[ring]);
2351                         cp->net_stats[ring].rx_errors++;
2352                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2353                                 cp->net_stats[ring].rx_length_errors++;
2354                         if (words[3] & RX_COMP4_BAD)
2355                                 cp->net_stats[ring].rx_crc_errors++;
2356                         spin_unlock(&cp->stat_lock[ring]);
2357
2358                         /* We'll just return it to Cassini. */
2359                 drop_it:
2360                         spin_lock(&cp->stat_lock[ring]);
2361                         ++cp->net_stats[ring].rx_dropped;
2362                         spin_unlock(&cp->stat_lock[ring]);
2363                         goto next;
2364                 }
2365
2366                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2367                 if (len < 0) {
2368                         ++drops;
2369                         goto drop_it;
2370                 }
2371
2372                 /* see if it's a flow re-assembly or not. the driver
2373                  * itself handles release back up.
2374                  */
2375                 if (RX_DONT_BATCH || (type == 0x2)) {
2376                         /* non-reassm: these always get released */
2377                         cas_skb_release(skb);
2378                 } else {
2379                         cas_rx_flow_pkt(cp, words, skb);
2380                 }
2381
2382                 spin_lock(&cp->stat_lock[ring]);
2383                 cp->net_stats[ring].rx_packets++;
2384                 cp->net_stats[ring].rx_bytes += len;
2385                 spin_unlock(&cp->stat_lock[ring]);
2386                 cp->dev->last_rx = jiffies;
2387
2388         next:
2389                 npackets++;
2390
2391                 /* should it be released? */
2392                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2393                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2394                         dring = CAS_VAL(RX_INDEX_RING, i);
2395                         i = CAS_VAL(RX_INDEX_NUM, i);
2396                         cas_post_page(cp, dring, i);
2397                 }
2398
2399                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2400                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2401                         dring = CAS_VAL(RX_INDEX_RING, i);
2402                         i = CAS_VAL(RX_INDEX_NUM, i);
2403                         cas_post_page(cp, dring, i);
2404                 }
2405
2406                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2407                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2408                         dring = CAS_VAL(RX_INDEX_RING, i);
2409                         i = CAS_VAL(RX_INDEX_NUM, i);
2410                         cas_post_page(cp, dring, i);
2411                 }
2412
2413                 /* skip to the next entry */
2414                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2415                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2416 #ifdef USE_NAPI
2417                 if (budget && (npackets >= budget))
2418                         break;
2419 #endif
2420         }
2421         cp->rx_new[ring] = entry;
2422
2423         if (drops)
2424                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2425                        cp->dev->name);
2426         return npackets;
2427 }
2428
2429
2430 /* put completion entries back on the ring */
2431 static void cas_post_rxcs_ringN(struct net_device *dev,
2432                                 struct cas *cp, int ring)
2433 {
2434         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2435         int last, entry;
2436
2437         last = cp->rx_cur[ring];
2438         entry = cp->rx_new[ring];
2439         if (netif_msg_intr(cp))
2440                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2441                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2442                        entry);
2443
2444         /* zero and re-mark descriptors */
2445         while (last != entry) {
2446                 cas_rxc_init(rxc + last);
2447                 last = RX_COMP_ENTRY(ring, last + 1);
2448         }
2449         cp->rx_cur[ring] = last;
2450
2451         if (ring == 0)
2452                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2453         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2454                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2455 }
2456
2457
2458
2459 /* cassini can use all four PCI interrupts for the completion ring.
2460  * rings 3 and 4 are identical
2461  */
2462 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2463 static inline void cas_handle_irqN(struct net_device *dev,
2464                                    struct cas *cp, const u32 status,
2465                                    const int ring)
2466 {
2467         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2468                 cas_post_rxcs_ringN(dev, cp, ring);
2469 }
2470
2471 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2472 {
2473         struct net_device *dev = dev_id;
2474         struct cas *cp = netdev_priv(dev);
2475         unsigned long flags;
2476         int ring;
2477         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2478
2479         /* check for shared irq */
2480         if (status == 0)
2481                 return IRQ_NONE;
2482
2483         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2484         spin_lock_irqsave(&cp->lock, flags);
2485         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2486 #ifdef USE_NAPI
2487                 cas_mask_intr(cp);
2488                 netif_rx_schedule(dev, &cp->napi);
2489 #else
2490                 cas_rx_ringN(cp, ring, 0);
2491 #endif
2492                 status &= ~INTR_RX_DONE_ALT;
2493         }
2494
2495         if (status)
2496                 cas_handle_irqN(dev, cp, status, ring);
2497         spin_unlock_irqrestore(&cp->lock, flags);
2498         return IRQ_HANDLED;
2499 }
2500 #endif
2501
2502 #ifdef USE_PCI_INTB
2503 /* everything but rx packets */
2504 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2505 {
2506         if (status & INTR_RX_BUF_UNAVAIL_1) {
2507                 /* Frame arrived, no free RX buffers available.
2508                  * NOTE: we can get this on a link transition. */
2509                 cas_post_rxds_ringN(cp, 1, 0);
2510                 spin_lock(&cp->stat_lock[1]);
2511                 cp->net_stats[1].rx_dropped++;
2512                 spin_unlock(&cp->stat_lock[1]);
2513         }
2514
2515         if (status & INTR_RX_BUF_AE_1)
2516                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2517                                     RX_AE_FREEN_VAL(1));
2518
2519         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2520                 cas_post_rxcs_ringN(cp, 1);
2521 }
2522
2523 /* ring 2 handles a few more events than 3 and 4 */
2524 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2525 {
2526         struct net_device *dev = dev_id;
2527         struct cas *cp = netdev_priv(dev);
2528         unsigned long flags;
2529         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2530
2531         /* check for shared interrupt */
2532         if (status == 0)
2533                 return IRQ_NONE;
2534
2535         spin_lock_irqsave(&cp->lock, flags);
2536         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2537 #ifdef USE_NAPI
2538                 cas_mask_intr(cp);
2539                 netif_rx_schedule(dev, &cp->napi);
2540 #else
2541                 cas_rx_ringN(cp, 1, 0);
2542 #endif
2543                 status &= ~INTR_RX_DONE_ALT;
2544         }
2545         if (status)
2546                 cas_handle_irq1(cp, status);
2547         spin_unlock_irqrestore(&cp->lock, flags);
2548         return IRQ_HANDLED;
2549 }
2550 #endif
2551
2552 static inline void cas_handle_irq(struct net_device *dev,
2553                                   struct cas *cp, const u32 status)
2554 {
2555         /* housekeeping interrupts */
2556         if (status & INTR_ERROR_MASK)
2557                 cas_abnormal_irq(dev, cp, status);
2558
2559         if (status & INTR_RX_BUF_UNAVAIL) {
2560                 /* Frame arrived, no free RX buffers available.
2561                  * NOTE: we can get this on a link transition.
2562                  */
2563                 cas_post_rxds_ringN(cp, 0, 0);
2564                 spin_lock(&cp->stat_lock[0]);
2565                 cp->net_stats[0].rx_dropped++;
2566                 spin_unlock(&cp->stat_lock[0]);
2567         } else if (status & INTR_RX_BUF_AE) {
2568                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2569                                     RX_AE_FREEN_VAL(0));
2570         }
2571
2572         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2573                 cas_post_rxcs_ringN(dev, cp, 0);
2574 }
2575
2576 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2577 {
2578         struct net_device *dev = dev_id;
2579         struct cas *cp = netdev_priv(dev);
2580         unsigned long flags;
2581         u32 status = readl(cp->regs + REG_INTR_STATUS);
2582
2583         if (status == 0)
2584                 return IRQ_NONE;
2585
2586         spin_lock_irqsave(&cp->lock, flags);
2587         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2588                 cas_tx(dev, cp, status);
2589                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2590         }
2591
2592         if (status & INTR_RX_DONE) {
2593 #ifdef USE_NAPI
2594                 cas_mask_intr(cp);
2595                 netif_rx_schedule(dev, &cp->napi);
2596 #else
2597                 cas_rx_ringN(cp, 0, 0);
2598 #endif
2599                 status &= ~INTR_RX_DONE;
2600         }
2601
2602         if (status)
2603                 cas_handle_irq(dev, cp, status);
2604         spin_unlock_irqrestore(&cp->lock, flags);
2605         return IRQ_HANDLED;
2606 }
2607
2608
2609 #ifdef USE_NAPI
2610 static int cas_poll(struct napi_struct *napi, int budget)
2611 {
2612         struct cas *cp = container_of(napi, struct cas, napi);
2613         struct net_device *dev = cp->dev;
2614         int i, enable_intr, todo, credits;
2615         u32 status = readl(cp->regs + REG_INTR_STATUS);
2616         unsigned long flags;
2617
2618         spin_lock_irqsave(&cp->lock, flags);
2619         cas_tx(dev, cp, status);
2620         spin_unlock_irqrestore(&cp->lock, flags);
2621
2622         /* NAPI rx packets. we spread the credits across all of the
2623          * rxc rings
2624          *
2625          * to make sure we're fair with the work we loop through each
2626          * ring N_RX_COMP_RING times with a request of
2627          * budget / N_RX_COMP_RINGS
2628          */
2629         enable_intr = 1;
2630         credits = 0;
2631         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2632                 int j;
2633                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2634                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2635                         if (credits >= budget) {
2636                                 enable_intr = 0;
2637                                 goto rx_comp;
2638                         }
2639                 }
2640         }
2641
2642 rx_comp:
2643         /* final rx completion */
2644         spin_lock_irqsave(&cp->lock, flags);
2645         if (status)
2646                 cas_handle_irq(dev, cp, status);
2647
2648 #ifdef USE_PCI_INTB
2649         if (N_RX_COMP_RINGS > 1) {
2650                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2651                 if (status)
2652                         cas_handle_irq1(dev, cp, status);
2653         }
2654 #endif
2655
2656 #ifdef USE_PCI_INTC
2657         if (N_RX_COMP_RINGS > 2) {
2658                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2659                 if (status)
2660                         cas_handle_irqN(dev, cp, status, 2);
2661         }
2662 #endif
2663
2664 #ifdef USE_PCI_INTD
2665         if (N_RX_COMP_RINGS > 3) {
2666                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2667                 if (status)
2668                         cas_handle_irqN(dev, cp, status, 3);
2669         }
2670 #endif
2671         spin_unlock_irqrestore(&cp->lock, flags);
2672         if (enable_intr) {
2673                 netif_rx_complete(dev, napi);
2674                 cas_unmask_intr(cp);
2675         }
2676         return credits;
2677 }
2678 #endif
2679
2680 #ifdef CONFIG_NET_POLL_CONTROLLER
2681 static void cas_netpoll(struct net_device *dev)
2682 {
2683         struct cas *cp = netdev_priv(dev);
2684
2685         cas_disable_irq(cp, 0);
2686         cas_interrupt(cp->pdev->irq, dev);
2687         cas_enable_irq(cp, 0);
2688
2689 #ifdef USE_PCI_INTB
2690         if (N_RX_COMP_RINGS > 1) {
2691                 /* cas_interrupt1(); */
2692         }
2693 #endif
2694 #ifdef USE_PCI_INTC
2695         if (N_RX_COMP_RINGS > 2) {
2696                 /* cas_interruptN(); */
2697         }
2698 #endif
2699 #ifdef USE_PCI_INTD
2700         if (N_RX_COMP_RINGS > 3) {
2701                 /* cas_interruptN(); */
2702         }
2703 #endif
2704 }
2705 #endif
2706
2707 static void cas_tx_timeout(struct net_device *dev)
2708 {
2709         struct cas *cp = netdev_priv(dev);
2710
2711         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2712         if (!cp->hw_running) {
2713                 printk("%s: hrm.. hw not running!\n", dev->name);
2714                 return;
2715         }
2716
2717         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2718                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2719
2720         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2721                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2722
2723         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2724                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2725                dev->name,
2726                readl(cp->regs + REG_TX_CFG),
2727                readl(cp->regs + REG_MAC_TX_STATUS),
2728                readl(cp->regs + REG_MAC_TX_CFG),
2729                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2730                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2731                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2732                readl(cp->regs + REG_TX_SM_1),
2733                readl(cp->regs + REG_TX_SM_2));
2734
2735         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2736                dev->name,
2737                readl(cp->regs + REG_RX_CFG),
2738                readl(cp->regs + REG_MAC_RX_STATUS),
2739                readl(cp->regs + REG_MAC_RX_CFG));
2740
2741         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2742                dev->name,
2743                readl(cp->regs + REG_HP_STATE_MACHINE),
2744                readl(cp->regs + REG_HP_STATUS0),
2745                readl(cp->regs + REG_HP_STATUS1),
2746                readl(cp->regs + REG_HP_STATUS2));
2747
2748 #if 1
2749         atomic_inc(&cp->reset_task_pending);
2750         atomic_inc(&cp->reset_task_pending_all);
2751         schedule_work(&cp->reset_task);
2752 #else
2753         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2754         schedule_work(&cp->reset_task);
2755 #endif
2756 }
2757
2758 static inline int cas_intme(int ring, int entry)
2759 {
2760         /* Algorithm: IRQ every 1/2 of descriptors. */
2761         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2762                 return 1;
2763         return 0;
2764 }
2765
2766
2767 static void cas_write_txd(struct cas *cp, int ring, int entry,
2768                           dma_addr_t mapping, int len, u64 ctrl, int last)
2769 {
2770         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2771
2772         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2773         if (cas_intme(ring, entry))
2774                 ctrl |= TX_DESC_INTME;
2775         if (last)
2776                 ctrl |= TX_DESC_EOF;
2777         txd->control = cpu_to_le64(ctrl);
2778         txd->buffer = cpu_to_le64(mapping);
2779 }
2780
2781 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2782                                 const int entry)
2783 {
2784         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2785 }
2786
2787 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2788                                      const int entry, const int tentry)
2789 {
2790         cp->tx_tiny_use[ring][tentry].nbufs++;
2791         cp->tx_tiny_use[ring][entry].used = 1;
2792         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2793 }
2794
2795 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2796                                     struct sk_buff *skb)
2797 {
2798         struct net_device *dev = cp->dev;
2799         int entry, nr_frags, frag, tabort, tentry;
2800         dma_addr_t mapping;
2801         unsigned long flags;
2802         u64 ctrl;
2803         u32 len;
2804
2805         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2806
2807         /* This is a hard error, log it. */
2808         if (TX_BUFFS_AVAIL(cp, ring) <=
2809             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2810                 netif_stop_queue(dev);
2811                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2812                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2813                        "queue awake!\n", dev->name);
2814                 return 1;
2815         }
2816
2817         ctrl = 0;
2818         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2819                 const u64 csum_start_off = skb_transport_offset(skb);
2820                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2821
2822                 ctrl =  TX_DESC_CSUM_EN |
2823                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2824                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2825         }
2826
2827         entry = cp->tx_new[ring];
2828         cp->tx_skbs[ring][entry] = skb;
2829
2830         nr_frags = skb_shinfo(skb)->nr_frags;
2831         len = skb_headlen(skb);
2832         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2833                                offset_in_page(skb->data), len,
2834                                PCI_DMA_TODEVICE);
2835
2836         tentry = entry;
2837         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2838         if (unlikely(tabort)) {
2839                 /* NOTE: len is always >  tabort */
2840                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2841                               ctrl | TX_DESC_SOF, 0);
2842                 entry = TX_DESC_NEXT(ring, entry);
2843
2844                 skb_copy_from_linear_data_offset(skb, len - tabort,
2845                               tx_tiny_buf(cp, ring, entry), tabort);
2846                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2847                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2848                               (nr_frags == 0));
2849         } else {
2850                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2851                               TX_DESC_SOF, (nr_frags == 0));
2852         }
2853         entry = TX_DESC_NEXT(ring, entry);
2854
2855         for (frag = 0; frag < nr_frags; frag++) {
2856                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2857
2858                 len = fragp->size;
2859                 mapping = pci_map_page(cp->pdev, fragp->page,
2860                                        fragp->page_offset, len,
2861                                        PCI_DMA_TODEVICE);
2862
2863                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2864                 if (unlikely(tabort)) {
2865                         void *addr;
2866
2867                         /* NOTE: len is always > tabort */
2868                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2869                                       ctrl, 0);
2870                         entry = TX_DESC_NEXT(ring, entry);
2871
2872                         addr = cas_page_map(fragp->page);
2873                         memcpy(tx_tiny_buf(cp, ring, entry),
2874                                addr + fragp->page_offset + len - tabort,
2875                                tabort);
2876                         cas_page_unmap(addr);
2877                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2878                         len     = tabort;
2879                 }
2880
2881                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2882                               (frag + 1 == nr_frags));
2883                 entry = TX_DESC_NEXT(ring, entry);
2884         }
2885
2886         cp->tx_new[ring] = entry;
2887         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2888                 netif_stop_queue(dev);
2889
2890         if (netif_msg_tx_queued(cp))
2891                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2892                        "avail %d\n",
2893                        dev->name, ring, entry, skb->len,
2894                        TX_BUFFS_AVAIL(cp, ring));
2895         writel(entry, cp->regs + REG_TX_KICKN(ring));
2896         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2897         return 0;
2898 }
2899
2900 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2901 {
2902         struct cas *cp = netdev_priv(dev);
2903
2904         /* this is only used as a load-balancing hint, so it doesn't
2905          * need to be SMP safe
2906          */
2907         static int ring;
2908
2909         if (skb_padto(skb, cp->min_frame_size))
2910                 return 0;
2911
2912         /* XXX: we need some higher-level QoS hooks to steer packets to
2913          *      individual queues.
2914          */
2915         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2916                 return 1;
2917         dev->trans_start = jiffies;
2918         return 0;
2919 }
2920
2921 static void cas_init_tx_dma(struct cas *cp)
2922 {
2923         u64 desc_dma = cp->block_dvma;
2924         unsigned long off;
2925         u32 val;
2926         int i;
2927
2928         /* set up tx completion writeback registers. must be 8-byte aligned */
2929 #ifdef USE_TX_COMPWB
2930         off = offsetof(struct cas_init_block, tx_compwb);
2931         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2932         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2933 #endif
2934
2935         /* enable completion writebacks, enable paced mode,
2936          * disable read pipe, and disable pre-interrupt compwbs
2937          */
2938         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2939                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2940                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2941                 TX_CFG_INTR_COMPWB_DIS;
2942
2943         /* write out tx ring info and tx desc bases */
2944         for (i = 0; i < MAX_TX_RINGS; i++) {
2945                 off = (unsigned long) cp->init_txds[i] -
2946                         (unsigned long) cp->init_block;
2947
2948                 val |= CAS_TX_RINGN_BASE(i);
2949                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2950                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2951                        REG_TX_DBN_LOW(i));
2952                 /* don't zero out the kick register here as the system
2953                  * will wedge
2954                  */
2955         }
2956         writel(val, cp->regs + REG_TX_CFG);
2957
2958         /* program max burst sizes. these numbers should be different
2959          * if doing QoS.
2960          */
2961 #ifdef USE_QOS
2962         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2963         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2964         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2965         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2966 #else
2967         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2968         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2969         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2970         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2971 #endif
2972 }
2973
2974 /* Must be invoked under cp->lock. */
2975 static inline void cas_init_dma(struct cas *cp)
2976 {
2977         cas_init_tx_dma(cp);
2978         cas_init_rx_dma(cp);
2979 }
2980
2981 /* Must be invoked under cp->lock. */
2982 static u32 cas_setup_multicast(struct cas *cp)
2983 {
2984         u32 rxcfg = 0;
2985         int i;
2986
2987         if (cp->dev->flags & IFF_PROMISC) {
2988                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2989
2990         } else if (cp->dev->flags & IFF_ALLMULTI) {
2991                 for (i=0; i < 16; i++)
2992                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2993                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2994
2995         } else {
2996                 u16 hash_table[16];
2997                 u32 crc;
2998                 struct dev_mc_list *dmi = cp->dev->mc_list;
2999                 int i;
3000
3001                 /* use the alternate mac address registers for the
3002                  * first 15 multicast addresses
3003                  */
3004                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
3005                         if (!dmi) {
3006                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
3007                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
3008                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
3009                                 continue;
3010                         }
3011                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
3012                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
3013                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
3014                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
3015                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
3016                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
3017                         dmi = dmi->next;
3018                 }
3019
3020                 /* use hw hash table for the next series of
3021                  * multicast addresses
3022                  */
3023                 memset(hash_table, 0, sizeof(hash_table));
3024                 while (dmi) {
3025                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3026                         crc >>= 24;
3027                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3028                         dmi = dmi->next;
3029                 }
3030                 for (i=0; i < 16; i++)
3031                         writel(hash_table[i], cp->regs +
3032                                REG_MAC_HASH_TABLEN(i));
3033                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3034         }
3035
3036         return rxcfg;
3037 }
3038
3039 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3040 static void cas_clear_mac_err(struct cas *cp)
3041 {
3042         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3043         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3044         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3045         writel(0, cp->regs + REG_MAC_COLL_LATE);
3046         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3047         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3048         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3049         writel(0, cp->regs + REG_MAC_LEN_ERR);
3050         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3051         writel(0, cp->regs + REG_MAC_FCS_ERR);
3052         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3053 }
3054
3055
3056 static void cas_mac_reset(struct cas *cp)
3057 {
3058         int i;
3059
3060         /* do both TX and RX reset */
3061         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3062         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3063
3064         /* wait for TX */
3065         i = STOP_TRIES;
3066         while (i-- > 0) {
3067                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3068                         break;
3069                 udelay(10);
3070         }
3071
3072         /* wait for RX */
3073         i = STOP_TRIES;
3074         while (i-- > 0) {
3075                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3076                         break;
3077                 udelay(10);
3078         }
3079
3080         if (readl(cp->regs + REG_MAC_TX_RESET) |
3081             readl(cp->regs + REG_MAC_RX_RESET))
3082                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3083                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3084                        readl(cp->regs + REG_MAC_RX_RESET),
3085                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3086 }
3087
3088
3089 /* Must be invoked under cp->lock. */
3090 static void cas_init_mac(struct cas *cp)
3091 {
3092         unsigned char *e = &cp->dev->dev_addr[0];
3093         int i;
3094 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3095         u32 rxcfg;
3096 #endif
3097         cas_mac_reset(cp);
3098
3099         /* setup core arbitration weight register */
3100         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3101
3102         /* XXX Use pci_dma_burst_advice() */
3103 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3104         /* set the infinite burst register for chips that don't have
3105          * pci issues.
3106          */
3107         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3108                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3109 #endif
3110
3111         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3112
3113         writel(0x00, cp->regs + REG_MAC_IPG0);
3114         writel(0x08, cp->regs + REG_MAC_IPG1);
3115         writel(0x04, cp->regs + REG_MAC_IPG2);
3116
3117         /* change later for 802.3z */
3118         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3119
3120         /* min frame + FCS */
3121         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3122
3123         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3124          * specify the maximum frame size to prevent RX tag errors on
3125          * oversized frames.
3126          */
3127         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3128                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3129                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3130                cp->regs + REG_MAC_FRAMESIZE_MAX);
3131
3132         /* NOTE: crc_size is used as a surrogate for half-duplex.
3133          * workaround saturn half-duplex issue by increasing preamble
3134          * size to 65 bytes.
3135          */
3136         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3137                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3138         else
3139                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3140         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3141         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3142         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3143
3144         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3145
3146         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3147         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3148         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3149         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3150         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3151
3152         /* setup mac address in perfect filter array */
3153         for (i = 0; i < 45; i++)
3154                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3155
3156         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3157         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3158         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3159
3160         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3161         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3162         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3163
3164 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3165         cp->mac_rx_cfg = cas_setup_multicast(cp);
3166 #else
3167         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3168          * a writel does not seem to be necessary because Cassini
3169          * seems to preserve the configuration when we do the reset.
3170          * If the chip is in trouble, though, it is not clear if we
3171          * can really count on this behavior. cas_set_multicast uses
3172          * spin_lock_irqsave, but we are called only in cas_init_hw and
3173          * cas_init_hw is protected by cas_lock_all, which calls
3174          * spin_lock_irq (so it doesn't need to save the flags, and
3175          * we should be OK for the writel, as that is the only
3176          * difference).
3177          */
3178         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3179         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3180 #endif
3181         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3182         cas_clear_mac_err(cp);
3183         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3184
3185         /* Setup MAC interrupts.  We want to get all of the interesting
3186          * counter expiration events, but we do not want to hear about
3187          * normal rx/tx as the DMA engine tells us that.
3188          */
3189         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3190         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3191
3192         /* Don't enable even the PAUSE interrupts for now, we
3193          * make no use of those events other than to record them.
3194          */
3195         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3196 }
3197
3198 /* Must be invoked under cp->lock. */
3199 static void cas_init_pause_thresholds(struct cas *cp)
3200 {
3201         /* Calculate pause thresholds.  Setting the OFF threshold to the
3202          * full RX fifo size effectively disables PAUSE generation
3203          */
3204         if (cp->rx_fifo_size <= (2 * 1024)) {
3205                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3206         } else {
3207                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3208                 if (max_frame * 3 > cp->rx_fifo_size) {
3209                         cp->rx_pause_off = 7104;
3210                         cp->rx_pause_on  = 960;
3211                 } else {
3212                         int off = (cp->rx_fifo_size - (max_frame * 2));
3213                         int on = off - max_frame;
3214                         cp->rx_pause_off = off;
3215                         cp->rx_pause_on = on;
3216                 }
3217         }
3218 }
3219
3220 static int cas_vpd_match(const void __iomem *p, const char *str)
3221 {
3222         int len = strlen(str) + 1;
3223         int i;
3224
3225         for (i = 0; i < len; i++) {
3226                 if (readb(p + i) != str[i])
3227                         return 0;
3228         }
3229         return 1;
3230 }
3231
3232
3233 /* get the mac address by reading the vpd information in the rom.
3234  * also get the phy type and determine if there's an entropy generator.
3235  * NOTE: this is a bit convoluted for the following reasons:
3236  *  1) vpd info has order-dependent mac addresses for multinic cards
3237  *  2) the only way to determine the nic order is to use the slot
3238  *     number.
3239  *  3) fiber cards don't have bridges, so their slot numbers don't
3240  *     mean anything.
3241  *  4) we don't actually know we have a fiber card until after
3242  *     the mac addresses are parsed.
3243  */
3244 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3245                             const int offset)
3246 {
3247         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3248         void __iomem *base, *kstart;
3249         int i, len;
3250         int found = 0;
3251 #define VPD_FOUND_MAC        0x01
3252 #define VPD_FOUND_PHY        0x02
3253
3254         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3255         int mac_off  = 0;
3256
3257         /* give us access to the PROM */
3258         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3259                cp->regs + REG_BIM_LOCAL_DEV_EN);
3260
3261         /* check for an expansion rom */
3262         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3263                 goto use_random_mac_addr;
3264
3265         /* search for beginning of vpd */
3266         base = NULL;
3267         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3268                 /* check for PCIR */
3269                 if ((readb(p + i + 0) == 0x50) &&
3270                     (readb(p + i + 1) == 0x43) &&
3271                     (readb(p + i + 2) == 0x49) &&
3272                     (readb(p + i + 3) == 0x52)) {
3273                         base = p + (readb(p + i + 8) |
3274                                     (readb(p + i + 9) << 8));
3275                         break;
3276                 }
3277         }