[PATCH] netdrvr: Convert cassini to pci_iomap
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page. 
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering 
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.  
67  */
68
69 #include <linux/config.h>
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/ioport.h>
79 #include <linux/pci.h>
80 #include <linux/mm.h>
81 #include <linux/highmem.h>
82 #include <linux/list.h>
83 #include <linux/dma-mapping.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/crc32.h>
90 #include <linux/random.h>
91 #include <linux/mii.h>
92 #include <linux/ip.h>
93 #include <linux/tcp.h>
94 #include <linux/mutex.h>
95
96 #include <net/checksum.h>
97
98 #include <asm/atomic.h>
99 #include <asm/system.h>
100 #include <asm/io.h>
101 #include <asm/byteorder.h>
102 #include <asm/uaccess.h>
103
104 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
106 #define CAS_NCPUS            num_online_cpus()
107
108 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
109 #define USE_NAPI
110 #define cas_skb_release(x)  netif_receive_skb(x)
111 #else
112 #define cas_skb_release(x)  netif_rx(x)
113 #endif
114
115 /* select which firmware to use */
116 #define USE_HP_WORKAROUND     
117 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
118 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
119
120 #include "cassini.h"
121
122 #define USE_TX_COMPWB      /* use completion writeback registers */
123 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
124 #define USE_RX_BLANK       /* hw interrupt mitigation */
125 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
126
127 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
128  * also, we need to make cp->lock finer-grained.
129  */
130 #undef  USE_PCI_INTB
131 #undef  USE_PCI_INTC
132 #undef  USE_PCI_INTD
133 #undef  USE_QOS
134
135 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
136
137 /* rx processing options */
138 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
139 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
140 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
141 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
142 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
143
144 #define DRV_MODULE_NAME         "cassini"
145 #define PFX DRV_MODULE_NAME     ": "
146 #define DRV_MODULE_VERSION      "1.4"
147 #define DRV_MODULE_RELDATE      "1 July 2004"
148
149 #define CAS_DEF_MSG_ENABLE        \
150         (NETIF_MSG_DRV          | \
151          NETIF_MSG_PROBE        | \
152          NETIF_MSG_LINK         | \
153          NETIF_MSG_TIMER        | \
154          NETIF_MSG_IFDOWN       | \
155          NETIF_MSG_IFUP         | \
156          NETIF_MSG_RX_ERR       | \
157          NETIF_MSG_TX_ERR)
158
159 /* length of time before we decide the hardware is borked,
160  * and dev->tx_timeout() should be called to fix the problem
161  */
162 #define CAS_TX_TIMEOUT                  (HZ)
163 #define CAS_LINK_TIMEOUT                (22*HZ/10)
164 #define CAS_LINK_FAST_TIMEOUT           (1)
165
166 /* timeout values for state changing. these specify the number
167  * of 10us delays to be used before giving up.
168  */
169 #define STOP_TRIES_PHY 1000
170 #define STOP_TRIES     5000
171
172 /* specify a minimum frame size to deal with some fifo issues 
173  * max mtu == 2 * page size - ethernet header - 64 - swivel =
174  *            2 * page_size - 0x50
175  */
176 #define CAS_MIN_FRAME                   97
177 #define CAS_1000MB_MIN_FRAME            255
178 #define CAS_MIN_MTU                     60
179 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
180
181 #if 1
182 /*
183  * Eliminate these and use separate atomic counters for each, to
184  * avoid a race condition.
185  */
186 #else
187 #define CAS_RESET_MTU                   1
188 #define CAS_RESET_ALL                   2
189 #define CAS_RESET_SPARE                 3
190 #endif
191
192 static char version[] __devinitdata =
193         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
194
195 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
196 static int link_mode;
197
198 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
199 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
200 MODULE_LICENSE("GPL");
201 module_param(cassini_debug, int, 0);
202 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
203 module_param(link_mode, int, 0);
204 MODULE_PARM_DESC(link_mode, "default link mode");
205
206 /*
207  * Work around for a PCS bug in which the link goes down due to the chip
208  * being confused and never showing a link status of "up."
209  */
210 #define DEFAULT_LINKDOWN_TIMEOUT 5
211 /* 
212  * Value in seconds, for user input.
213  */
214 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
215 module_param(linkdown_timeout, int, 0);
216 MODULE_PARM_DESC(linkdown_timeout,
217 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
218
219 /*
220  * value in 'ticks' (units used by jiffies). Set when we init the
221  * module because 'HZ' in actually a function call on some flavors of
222  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
223  */
224 static int link_transition_timeout;
225
226
227
228 static u16 link_modes[] __devinitdata = {
229         BMCR_ANENABLE,                   /* 0 : autoneg */
230         0,                               /* 1 : 10bt half duplex */
231         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
232         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
233         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
234         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
235 };
236
237 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
238         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242         { 0, }
243 };
244
245 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
246
247 static void cas_set_link_modes(struct cas *cp);
248
249 static inline void cas_lock_tx(struct cas *cp)
250 {
251         int i;
252
253         for (i = 0; i < N_TX_RINGS; i++)  
254                 spin_lock(&cp->tx_lock[i]);
255 }
256
257 static inline void cas_lock_all(struct cas *cp)
258 {
259         spin_lock_irq(&cp->lock);
260         cas_lock_tx(cp);
261 }
262
263 /* WTZ: QA was finding deadlock problems with the previous
264  * versions after long test runs with multiple cards per machine.
265  * See if replacing cas_lock_all with safer versions helps. The
266  * symptoms QA is reporting match those we'd expect if interrupts
267  * aren't being properly restored, and we fixed a previous deadlock
268  * with similar symptoms by using save/restore versions in other
269  * places.
270  */
271 #define cas_lock_all_save(cp, flags) \
272 do { \
273         struct cas *xxxcp = (cp); \
274         spin_lock_irqsave(&xxxcp->lock, flags); \
275         cas_lock_tx(xxxcp); \
276 } while (0)
277
278 static inline void cas_unlock_tx(struct cas *cp)
279 {
280         int i;
281
282         for (i = N_TX_RINGS; i > 0; i--)  
283                 spin_unlock(&cp->tx_lock[i - 1]);  
284 }
285
286 static inline void cas_unlock_all(struct cas *cp)
287 {
288         cas_unlock_tx(cp);
289         spin_unlock_irq(&cp->lock);
290 }
291
292 #define cas_unlock_all_restore(cp, flags) \
293 do { \
294         struct cas *xxxcp = (cp); \
295         cas_unlock_tx(xxxcp); \
296         spin_unlock_irqrestore(&xxxcp->lock, flags); \
297 } while (0)
298
299 static void cas_disable_irq(struct cas *cp, const int ring)
300 {
301         /* Make sure we won't get any more interrupts */
302         if (ring == 0) {
303                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
304                 return;
305         }
306
307         /* disable completion interrupts and selectively mask */
308         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
309                 switch (ring) {
310 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
311 #ifdef USE_PCI_INTB
312                 case 1:
313 #endif
314 #ifdef USE_PCI_INTC
315                 case 2:
316 #endif
317 #ifdef USE_PCI_INTD
318                 case 3:
319 #endif
320                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, 
321                                cp->regs + REG_PLUS_INTRN_MASK(ring));
322                         break;
323 #endif
324                 default:
325                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
326                                REG_PLUS_INTRN_MASK(ring));
327                         break;
328                 }
329         }
330 }
331
332 static inline void cas_mask_intr(struct cas *cp)
333 {
334         int i;
335
336         for (i = 0; i < N_RX_COMP_RINGS; i++)
337                 cas_disable_irq(cp, i);
338 }
339
340 static inline void cas_buffer_init(cas_page_t *cp)
341 {
342         struct page *page = cp->buffer;
343         atomic_set((atomic_t *)&page->lru.next, 1);
344 }
345
346 static inline int cas_buffer_count(cas_page_t *cp)
347 {
348         struct page *page = cp->buffer;
349         return atomic_read((atomic_t *)&page->lru.next);
350 }
351
352 static inline void cas_buffer_inc(cas_page_t *cp)
353 {
354         struct page *page = cp->buffer;
355         atomic_inc((atomic_t *)&page->lru.next);
356 }
357
358 static inline void cas_buffer_dec(cas_page_t *cp)
359 {
360         struct page *page = cp->buffer;
361         atomic_dec((atomic_t *)&page->lru.next);
362 }
363
364 static void cas_enable_irq(struct cas *cp, const int ring)
365 {
366         if (ring == 0) { /* all but TX_DONE */
367                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
368                 return;
369         }
370
371         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
372                 switch (ring) {
373 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
374 #ifdef USE_PCI_INTB
375                 case 1:
376 #endif
377 #ifdef USE_PCI_INTC
378                 case 2:
379 #endif
380 #ifdef USE_PCI_INTD
381                 case 3:
382 #endif
383                         writel(INTRN_MASK_RX_EN, cp->regs +
384                                REG_PLUS_INTRN_MASK(ring));
385                         break;
386 #endif
387                 default:
388                         break;
389                 }
390         }
391 }
392
393 static inline void cas_unmask_intr(struct cas *cp)
394 {
395         int i;
396
397         for (i = 0; i < N_RX_COMP_RINGS; i++)
398                 cas_enable_irq(cp, i);
399 }
400
401 static inline void cas_entropy_gather(struct cas *cp)
402 {
403 #ifdef USE_ENTROPY_DEV
404         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
405                 return;
406
407         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
408                             readl(cp->regs + REG_ENTROPY_IV),
409                             sizeof(uint64_t)*8);
410 #endif
411 }
412
413 static inline void cas_entropy_reset(struct cas *cp)
414 {
415 #ifdef USE_ENTROPY_DEV
416         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
417                 return;
418
419         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, 
420                cp->regs + REG_BIM_LOCAL_DEV_EN);
421         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
422         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
423
424         /* if we read back 0x0, we don't have an entropy device */
425         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
426                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
427 #endif
428 }
429
430 /* access to the phy. the following assumes that we've initialized the MIF to 
431  * be in frame rather than bit-bang mode
432  */
433 static u16 cas_phy_read(struct cas *cp, int reg)
434 {
435         u32 cmd;
436         int limit = STOP_TRIES_PHY;
437
438         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
439         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
440         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
441         cmd |= MIF_FRAME_TURN_AROUND_MSB;
442         writel(cmd, cp->regs + REG_MIF_FRAME);
443         
444         /* poll for completion */
445         while (limit-- > 0) {
446                 udelay(10);
447                 cmd = readl(cp->regs + REG_MIF_FRAME);
448                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
449                         return (cmd & MIF_FRAME_DATA_MASK);
450         }
451         return 0xFFFF; /* -1 */
452 }
453
454 static int cas_phy_write(struct cas *cp, int reg, u16 val)
455 {
456         int limit = STOP_TRIES_PHY;
457         u32 cmd;
458
459         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
460         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
461         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
462         cmd |= MIF_FRAME_TURN_AROUND_MSB;
463         cmd |= val & MIF_FRAME_DATA_MASK;
464         writel(cmd, cp->regs + REG_MIF_FRAME);
465         
466         /* poll for completion */
467         while (limit-- > 0) {
468                 udelay(10);
469                 cmd = readl(cp->regs + REG_MIF_FRAME);
470                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
471                         return 0;
472         }
473         return -1;
474 }
475
476 static void cas_phy_powerup(struct cas *cp)
477 {
478         u16 ctl = cas_phy_read(cp, MII_BMCR);   
479
480         if ((ctl & BMCR_PDOWN) == 0)
481                 return;
482         ctl &= ~BMCR_PDOWN;
483         cas_phy_write(cp, MII_BMCR, ctl);
484 }
485
486 static void cas_phy_powerdown(struct cas *cp)
487 {
488         u16 ctl = cas_phy_read(cp, MII_BMCR);   
489
490         if (ctl & BMCR_PDOWN)
491                 return;
492         ctl |= BMCR_PDOWN;
493         cas_phy_write(cp, MII_BMCR, ctl);
494 }
495
496 /* cp->lock held. note: the last put_page will free the buffer */
497 static int cas_page_free(struct cas *cp, cas_page_t *page)
498 {
499         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size, 
500                        PCI_DMA_FROMDEVICE);
501         cas_buffer_dec(page);
502         __free_pages(page->buffer, cp->page_order);
503         kfree(page);
504         return 0;
505 }
506
507 #ifdef RX_COUNT_BUFFERS
508 #define RX_USED_ADD(x, y)       ((x)->used += (y))
509 #define RX_USED_SET(x, y)       ((x)->used  = (y))
510 #else
511 #define RX_USED_ADD(x, y) 
512 #define RX_USED_SET(x, y)
513 #endif
514
515 /* local page allocation routines for the receive buffers. jumbo pages
516  * require at least 8K contiguous and 8K aligned buffers.
517  */
518 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
519 {
520         cas_page_t *page;
521
522         page = kmalloc(sizeof(cas_page_t), flags);
523         if (!page)
524                 return NULL;
525
526         INIT_LIST_HEAD(&page->list);
527         RX_USED_SET(page, 0);
528         page->buffer = alloc_pages(flags, cp->page_order);
529         if (!page->buffer)
530                 goto page_err;
531         cas_buffer_init(page);
532         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
533                                       cp->page_size, PCI_DMA_FROMDEVICE);
534         return page;
535
536 page_err:
537         kfree(page);
538         return NULL;
539 }
540
541 /* initialize spare pool of rx buffers, but allocate during the open */
542 static void cas_spare_init(struct cas *cp)
543 {
544         spin_lock(&cp->rx_inuse_lock);
545         INIT_LIST_HEAD(&cp->rx_inuse_list);
546         spin_unlock(&cp->rx_inuse_lock);
547
548         spin_lock(&cp->rx_spare_lock);
549         INIT_LIST_HEAD(&cp->rx_spare_list);
550         cp->rx_spares_needed = RX_SPARE_COUNT;
551         spin_unlock(&cp->rx_spare_lock);
552 }
553
554 /* used on close. free all the spare buffers. */
555 static void cas_spare_free(struct cas *cp)
556 {
557         struct list_head list, *elem, *tmp;
558
559         /* free spare buffers */
560         INIT_LIST_HEAD(&list);
561         spin_lock(&cp->rx_spare_lock);
562         list_splice(&cp->rx_spare_list, &list);
563         INIT_LIST_HEAD(&cp->rx_spare_list);
564         spin_unlock(&cp->rx_spare_lock);
565         list_for_each_safe(elem, tmp, &list) {
566                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
567         }
568
569         INIT_LIST_HEAD(&list);
570 #if 1
571         /*
572          * Looks like Adrian had protected this with a different
573          * lock than used everywhere else to manipulate this list.
574          */
575         spin_lock(&cp->rx_inuse_lock);
576         list_splice(&cp->rx_inuse_list, &list);
577         INIT_LIST_HEAD(&cp->rx_inuse_list);
578         spin_unlock(&cp->rx_inuse_lock);
579 #else
580         spin_lock(&cp->rx_spare_lock);
581         list_splice(&cp->rx_inuse_list, &list);
582         INIT_LIST_HEAD(&cp->rx_inuse_list);
583         spin_unlock(&cp->rx_spare_lock);
584 #endif
585         list_for_each_safe(elem, tmp, &list) {
586                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
587         }
588 }
589
590 /* replenish spares if needed */
591 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
592 {
593         struct list_head list, *elem, *tmp;
594         int needed, i;
595
596         /* check inuse list. if we don't need any more free buffers,
597          * just free it
598          */
599
600         /* make a local copy of the list */
601         INIT_LIST_HEAD(&list);
602         spin_lock(&cp->rx_inuse_lock);
603         list_splice(&cp->rx_inuse_list, &list);
604         INIT_LIST_HEAD(&cp->rx_inuse_list);
605         spin_unlock(&cp->rx_inuse_lock);
606         
607         list_for_each_safe(elem, tmp, &list) {
608                 cas_page_t *page = list_entry(elem, cas_page_t, list);
609
610                 if (cas_buffer_count(page) > 1)
611                         continue;
612
613                 list_del(elem);
614                 spin_lock(&cp->rx_spare_lock);
615                 if (cp->rx_spares_needed > 0) {
616                         list_add(elem, &cp->rx_spare_list);
617                         cp->rx_spares_needed--;
618                         spin_unlock(&cp->rx_spare_lock);
619                 } else {
620                         spin_unlock(&cp->rx_spare_lock);
621                         cas_page_free(cp, page);
622                 }
623         }
624
625         /* put any inuse buffers back on the list */
626         if (!list_empty(&list)) {
627                 spin_lock(&cp->rx_inuse_lock);
628                 list_splice(&list, &cp->rx_inuse_list);
629                 spin_unlock(&cp->rx_inuse_lock);
630         }
631         
632         spin_lock(&cp->rx_spare_lock);
633         needed = cp->rx_spares_needed;
634         spin_unlock(&cp->rx_spare_lock);
635         if (!needed)
636                 return;
637
638         /* we still need spares, so try to allocate some */
639         INIT_LIST_HEAD(&list);
640         i = 0;
641         while (i < needed) {
642                 cas_page_t *spare = cas_page_alloc(cp, flags);
643                 if (!spare) 
644                         break;
645                 list_add(&spare->list, &list);
646                 i++;
647         }
648
649         spin_lock(&cp->rx_spare_lock);
650         list_splice(&list, &cp->rx_spare_list);
651         cp->rx_spares_needed -= i;
652         spin_unlock(&cp->rx_spare_lock);
653 }
654
655 /* pull a page from the list. */
656 static cas_page_t *cas_page_dequeue(struct cas *cp)
657 {
658         struct list_head *entry;
659         int recover;
660
661         spin_lock(&cp->rx_spare_lock);
662         if (list_empty(&cp->rx_spare_list)) {
663                 /* try to do a quick recovery */
664                 spin_unlock(&cp->rx_spare_lock);
665                 cas_spare_recover(cp, GFP_ATOMIC);
666                 spin_lock(&cp->rx_spare_lock);
667                 if (list_empty(&cp->rx_spare_list)) {
668                         if (netif_msg_rx_err(cp))
669                                 printk(KERN_ERR "%s: no spare buffers "
670                                        "available.\n", cp->dev->name);
671                         spin_unlock(&cp->rx_spare_lock);
672                         return NULL;
673                 }
674         }
675
676         entry = cp->rx_spare_list.next;
677         list_del(entry);
678         recover = ++cp->rx_spares_needed;
679         spin_unlock(&cp->rx_spare_lock);
680
681         /* trigger the timer to do the recovery */
682         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
683 #if 1
684                 atomic_inc(&cp->reset_task_pending);
685                 atomic_inc(&cp->reset_task_pending_spare);
686                 schedule_work(&cp->reset_task);
687 #else
688                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
689                 schedule_work(&cp->reset_task);
690 #endif
691         }
692         return list_entry(entry, cas_page_t, list);
693 }
694
695
696 static void cas_mif_poll(struct cas *cp, const int enable)
697 {
698         u32 cfg;
699         
700         cfg  = readl(cp->regs + REG_MIF_CFG); 
701         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
702
703         if (cp->phy_type & CAS_PHY_MII_MDIO1)
704                 cfg |= MIF_CFG_PHY_SELECT; 
705
706         /* poll and interrupt on link status change. */
707         if (enable) {
708                 cfg |= MIF_CFG_POLL_EN;
709                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
710                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
711         }
712         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, 
713                cp->regs + REG_MIF_MASK); 
714         writel(cfg, cp->regs + REG_MIF_CFG);
715 }
716
717 /* Must be invoked under cp->lock */
718 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
719 {
720         u16 ctl;
721 #if 1
722         int lcntl;
723         int changed = 0;
724         int oldstate = cp->lstate;
725         int link_was_not_down = !(oldstate == link_down);
726 #endif
727         /* Setup link parameters */
728         if (!ep)
729                 goto start_aneg;
730         lcntl = cp->link_cntl;
731         if (ep->autoneg == AUTONEG_ENABLE)
732                 cp->link_cntl = BMCR_ANENABLE;
733         else {
734                 cp->link_cntl = 0;
735                 if (ep->speed == SPEED_100)
736                         cp->link_cntl |= BMCR_SPEED100;
737                 else if (ep->speed == SPEED_1000)
738                         cp->link_cntl |= CAS_BMCR_SPEED1000;
739                 if (ep->duplex == DUPLEX_FULL)
740                         cp->link_cntl |= BMCR_FULLDPLX;
741         }
742 #if 1
743         changed = (lcntl != cp->link_cntl);
744 #endif
745 start_aneg:
746         if (cp->lstate == link_up) {
747                 printk(KERN_INFO "%s: PCS link down.\n",
748                        cp->dev->name);
749         } else {
750                 if (changed) {
751                         printk(KERN_INFO "%s: link configuration changed\n",
752                                cp->dev->name);
753                 }
754         }
755         cp->lstate = link_down;
756         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
757         if (!cp->hw_running)
758                 return;
759 #if 1
760         /*
761          * WTZ: If the old state was link_up, we turn off the carrier
762          * to replicate everything we do elsewhere on a link-down
763          * event when we were already in a link-up state..  
764          */
765         if (oldstate == link_up)
766                 netif_carrier_off(cp->dev);
767         if (changed  && link_was_not_down) {
768                 /*
769                  * WTZ: This branch will simply schedule a full reset after
770                  * we explicitly changed link modes in an ioctl. See if this
771                  * fixes the link-problems we were having for forced mode. 
772                  */
773                 atomic_inc(&cp->reset_task_pending);
774                 atomic_inc(&cp->reset_task_pending_all);
775                 schedule_work(&cp->reset_task);
776                 cp->timer_ticks = 0;
777                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
778                 return;
779         }
780 #endif
781         if (cp->phy_type & CAS_PHY_SERDES) {
782                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
783
784                 if (cp->link_cntl & BMCR_ANENABLE) {
785                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
786                         cp->lstate = link_aneg;
787                 } else {
788                         if (cp->link_cntl & BMCR_FULLDPLX)
789                                 val |= PCS_MII_CTRL_DUPLEX;
790                         val &= ~PCS_MII_AUTONEG_EN;
791                         cp->lstate = link_force_ok;
792                 }
793                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
794                 writel(val, cp->regs + REG_PCS_MII_CTRL);
795
796         } else {
797                 cas_mif_poll(cp, 0);
798                 ctl = cas_phy_read(cp, MII_BMCR);
799                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | 
800                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
801                 ctl |= cp->link_cntl;
802                 if (ctl & BMCR_ANENABLE) {
803                         ctl |= BMCR_ANRESTART;
804                         cp->lstate = link_aneg;
805                 } else {
806                         cp->lstate = link_force_ok;
807                 }
808                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
809                 cas_phy_write(cp, MII_BMCR, ctl);
810                 cas_mif_poll(cp, 1);
811         }
812
813         cp->timer_ticks = 0;
814         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
815 }
816
817 /* Must be invoked under cp->lock. */
818 static int cas_reset_mii_phy(struct cas *cp)
819 {
820         int limit = STOP_TRIES_PHY;
821         u16 val;
822         
823         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
824         udelay(100);
825         while (limit--) {
826                 val = cas_phy_read(cp, MII_BMCR);
827                 if ((val & BMCR_RESET) == 0)
828                         break;
829                 udelay(10);
830         }
831         return (limit <= 0);
832 }
833
834 static void cas_saturn_firmware_load(struct cas *cp)
835 {
836         cas_saturn_patch_t *patch = cas_saturn_patch;
837
838         cas_phy_powerdown(cp);
839
840         /* expanded memory access mode */
841         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
842
843         /* pointer configuration for new firmware */
844         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
845         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
846         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
847         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
848         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
849         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
850         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
851         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
852
853         /* download new firmware */
854         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
855         cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
856         while (patch->addr) {
857                 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
858                 patch++;
859         }
860
861         /* enable firmware */
862         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
863         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
864 }
865
866
867 /* phy initialization */
868 static void cas_phy_init(struct cas *cp)
869 {
870         u16 val;
871
872         /* if we're in MII/GMII mode, set up phy */
873         if (CAS_PHY_MII(cp->phy_type)) {
874                 writel(PCS_DATAPATH_MODE_MII,
875                        cp->regs + REG_PCS_DATAPATH_MODE);
876
877                 cas_mif_poll(cp, 0);
878                 cas_reset_mii_phy(cp); /* take out of isolate mode */
879
880                 if (PHY_LUCENT_B0 == cp->phy_id) {
881                         /* workaround link up/down issue with lucent */
882                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
883                         cas_phy_write(cp, MII_BMCR, 0x00f1);
884                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
885
886                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
887                         /* workarounds for broadcom phy */
888                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
889                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
890                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
891                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
892                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
893                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
894                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
895                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
896                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
897                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
898                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
899
900                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
901                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
902                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
903                         if (val & 0x0080) {
904                                 /* link workaround */
905                                 cas_phy_write(cp, BROADCOM_MII_REG4, 
906                                               val & ~0x0080);
907                         }
908                         
909                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
910                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? 
911                                SATURN_PCFG_FSI : 0x0, 
912                                cp->regs + REG_SATURN_PCFG);
913
914                         /* load firmware to address 10Mbps auto-negotiation
915                          * issue. NOTE: this will need to be changed if the 
916                          * default firmware gets fixed.
917                          */
918                         if (PHY_NS_DP83065 == cp->phy_id) {
919                                 cas_saturn_firmware_load(cp);
920                         }
921                         cas_phy_powerup(cp);
922                 }
923
924                 /* advertise capabilities */
925                 val = cas_phy_read(cp, MII_BMCR);
926                 val &= ~BMCR_ANENABLE;
927                 cas_phy_write(cp, MII_BMCR, val);
928                 udelay(10);
929
930                 cas_phy_write(cp, MII_ADVERTISE,
931                               cas_phy_read(cp, MII_ADVERTISE) |
932                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
933                                ADVERTISE_100HALF | ADVERTISE_100FULL |
934                                CAS_ADVERTISE_PAUSE | 
935                                CAS_ADVERTISE_ASYM_PAUSE));
936                 
937                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
938                         /* make sure that we don't advertise half
939                          * duplex to avoid a chip issue
940                          */
941                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
942                         val &= ~CAS_ADVERTISE_1000HALF;
943                         val |= CAS_ADVERTISE_1000FULL;
944                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
945                 }
946
947         } else {
948                 /* reset pcs for serdes */
949                 u32 val;
950                 int limit;
951
952                 writel(PCS_DATAPATH_MODE_SERDES,
953                        cp->regs + REG_PCS_DATAPATH_MODE);
954
955                 /* enable serdes pins on saturn */
956                 if (cp->cas_flags & CAS_FLAG_SATURN)
957                         writel(0, cp->regs + REG_SATURN_PCFG);
958
959                 /* Reset PCS unit. */
960                 val = readl(cp->regs + REG_PCS_MII_CTRL);
961                 val |= PCS_MII_RESET;
962                 writel(val, cp->regs + REG_PCS_MII_CTRL);
963
964                 limit = STOP_TRIES;
965                 while (limit-- > 0) {
966                         udelay(10);
967                         if ((readl(cp->regs + REG_PCS_MII_CTRL) & 
968                              PCS_MII_RESET) == 0)
969                                 break;
970                 }
971                 if (limit <= 0)
972                         printk(KERN_WARNING "%s: PCS reset bit would not "
973                                "clear [%08x].\n", cp->dev->name,
974                                readl(cp->regs + REG_PCS_STATE_MACHINE));
975
976                 /* Make sure PCS is disabled while changing advertisement
977                  * configuration.
978                  */
979                 writel(0x0, cp->regs + REG_PCS_CFG);
980
981                 /* Advertise all capabilities except half-duplex. */
982                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
983                 val &= ~PCS_MII_ADVERT_HD;
984                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | 
985                         PCS_MII_ADVERT_ASYM_PAUSE);
986                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
987
988                 /* enable PCS */
989                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
990
991                 /* pcs workaround: enable sync detect */
992                 writel(PCS_SERDES_CTRL_SYNCD_EN,
993                        cp->regs + REG_PCS_SERDES_CTRL);
994         }
995 }
996
997
998 static int cas_pcs_link_check(struct cas *cp)
999 {
1000         u32 stat, state_machine;
1001         int retval = 0;
1002
1003         /* The link status bit latches on zero, so you must
1004          * read it twice in such a case to see a transition
1005          * to the link being up.
1006          */
1007         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1008         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1009                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1010
1011         /* The remote-fault indication is only valid
1012          * when autoneg has completed.
1013          */
1014         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1015                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1016             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
1017                 if (netif_msg_link(cp))
1018                         printk(KERN_INFO "%s: PCS RemoteFault\n", 
1019                                cp->dev->name);
1020         }
1021
1022         /* work around link detection issue by querying the PCS state
1023          * machine directly.
1024          */
1025         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1026         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1027                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1028         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1029                 stat |= PCS_MII_STATUS_LINK_STATUS;
1030         }
1031
1032         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1033                 if (cp->lstate != link_up) {
1034                         if (cp->opened) {
1035                                 cp->lstate = link_up;
1036                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1037                                 
1038                                 cas_set_link_modes(cp);
1039                                 netif_carrier_on(cp->dev);
1040                         }
1041                 }
1042         } else if (cp->lstate == link_up) {
1043                 cp->lstate = link_down;
1044                 if (link_transition_timeout != 0 &&
1045                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1046                     !cp->link_transition_jiffies_valid) {
1047                         /*
1048                          * force a reset, as a workaround for the 
1049                          * link-failure problem. May want to move this to a 
1050                          * point a bit earlier in the sequence. If we had
1051                          * generated a reset a short time ago, we'll wait for
1052                          * the link timer to check the status until a
1053                          * timer expires (link_transistion_jiffies_valid is
1054                          * true when the timer is running.)  Instead of using
1055                          * a system timer, we just do a check whenever the
1056                          * link timer is running - this clears the flag after
1057                          * a suitable delay.
1058                          */
1059                         retval = 1;
1060                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1061                         cp->link_transition_jiffies = jiffies;
1062                         cp->link_transition_jiffies_valid = 1;
1063                 } else {
1064                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1065                 }
1066                 netif_carrier_off(cp->dev);
1067                 if (cp->opened && netif_msg_link(cp)) {
1068                         printk(KERN_INFO "%s: PCS link down.\n",
1069                                cp->dev->name);
1070                 }
1071
1072                 /* Cassini only: if you force a mode, there can be
1073                  * sync problems on link down. to fix that, the following
1074                  * things need to be checked:
1075                  * 1) read serialink state register
1076                  * 2) read pcs status register to verify link down.
1077                  * 3) if link down and serial link == 0x03, then you need
1078                  *    to global reset the chip.
1079                  */
1080                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1081                         /* should check to see if we're in a forced mode */
1082                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1083                         if (stat == 0x03)
1084                                 return 1;
1085                 }
1086         } else if (cp->lstate == link_down) {
1087                 if (link_transition_timeout != 0 &&
1088                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1089                     !cp->link_transition_jiffies_valid) {
1090                         /* force a reset, as a workaround for the
1091                          * link-failure problem.  May want to move
1092                          * this to a point a bit earlier in the
1093                          * sequence.
1094                          */
1095                         retval = 1;
1096                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1097                         cp->link_transition_jiffies = jiffies;
1098                         cp->link_transition_jiffies_valid = 1;
1099                 } else {
1100                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1101                 }
1102         }
1103
1104         return retval;
1105 }
1106
1107 static int cas_pcs_interrupt(struct net_device *dev, 
1108                              struct cas *cp, u32 status)
1109 {
1110         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1111
1112         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) 
1113                 return 0;
1114         return cas_pcs_link_check(cp);
1115 }
1116
1117 static int cas_txmac_interrupt(struct net_device *dev, 
1118                                struct cas *cp, u32 status)
1119 {
1120         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1121
1122         if (!txmac_stat)
1123                 return 0;
1124
1125         if (netif_msg_intr(cp))
1126                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1127                         cp->dev->name, txmac_stat);
1128
1129         /* Defer timer expiration is quite normal,
1130          * don't even log the event.
1131          */
1132         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1133             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1134                 return 0;
1135
1136         spin_lock(&cp->stat_lock[0]);
1137         if (txmac_stat & MAC_TX_UNDERRUN) {
1138                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1139                        dev->name);
1140                 cp->net_stats[0].tx_fifo_errors++;
1141         }
1142
1143         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1144                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1145                        dev->name);
1146                 cp->net_stats[0].tx_errors++;
1147         }
1148
1149         /* The rest are all cases of one of the 16-bit TX
1150          * counters expiring.
1151          */
1152         if (txmac_stat & MAC_TX_COLL_NORMAL)
1153                 cp->net_stats[0].collisions += 0x10000;
1154
1155         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1156                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1157                 cp->net_stats[0].collisions += 0x10000;
1158         }
1159
1160         if (txmac_stat & MAC_TX_COLL_LATE) {
1161                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1162                 cp->net_stats[0].collisions += 0x10000;
1163         }
1164         spin_unlock(&cp->stat_lock[0]);
1165
1166         /* We do not keep track of MAC_TX_COLL_FIRST and
1167          * MAC_TX_PEAK_ATTEMPTS events.
1168          */
1169         return 0;
1170 }
1171
1172 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) 
1173 {
1174         cas_hp_inst_t *inst;
1175         u32 val;
1176         int i;
1177
1178         i = 0;
1179         while ((inst = firmware) && inst->note) {
1180                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1181
1182                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1183                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1184                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1185
1186                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1187                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1188                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1189                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1190                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1191                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1192                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1193                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1194
1195                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1196                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1197                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1198                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1199                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1200                 ++firmware;
1201                 ++i;
1202         }
1203 }
1204
1205 static void cas_init_rx_dma(struct cas *cp)
1206 {
1207         u64 desc_dma = cp->block_dvma; 
1208         u32 val;
1209         int i, size;
1210
1211         /* rx free descriptors */
1212         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); 
1213         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1214         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1215         if ((N_RX_DESC_RINGS > 1) &&
1216             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1217                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1218         writel(val, cp->regs + REG_RX_CFG);
1219
1220         val = (unsigned long) cp->init_rxds[0] - 
1221                 (unsigned long) cp->init_block;
1222         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1223         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1224         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1225
1226         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1227                 /* rx desc 2 is for IPSEC packets. however, 
1228                  * we don't it that for that purpose.
1229                  */
1230                 val = (unsigned long) cp->init_rxds[1] - 
1231                         (unsigned long) cp->init_block;
1232                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1233                 writel((desc_dma + val) & 0xffffffff, cp->regs + 
1234                        REG_PLUS_RX_DB1_LOW);
1235                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + 
1236                        REG_PLUS_RX_KICK1);
1237         }
1238         
1239         /* rx completion registers */
1240         val = (unsigned long) cp->init_rxcs[0] - 
1241                 (unsigned long) cp->init_block;
1242         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1243         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1244
1245         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1246                 /* rx comp 2-4 */
1247                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1248                         val = (unsigned long) cp->init_rxcs[i] - 
1249                                 (unsigned long) cp->init_block;
1250                         writel((desc_dma + val) >> 32, cp->regs + 
1251                                REG_PLUS_RX_CBN_HI(i));
1252                         writel((desc_dma + val) & 0xffffffff, cp->regs + 
1253                                REG_PLUS_RX_CBN_LOW(i));
1254                 }
1255         }
1256
1257         /* read selective clear regs to prevent spurious interrupts
1258          * on reset because complete == kick.
1259          * selective clear set up to prevent interrupts on resets
1260          */
1261         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1262         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1263         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1264                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1265                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1266
1267                 /* 2 is different from 3 and 4 */
1268                 if (N_RX_COMP_RINGS > 1)
1269                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, 
1270                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1271
1272                 for (i = 2; i < N_RX_COMP_RINGS; i++) 
1273                         writel(INTR_RX_DONE_ALT, 
1274                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1275         }
1276
1277         /* set up pause thresholds */
1278         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1279                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1280         val |= CAS_BASE(RX_PAUSE_THRESH_ON, 
1281                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1282         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1283         
1284         /* zero out dma reassembly buffers */
1285         for (i = 0; i < 64; i++) {
1286                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1287                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1288                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1289                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1290         }
1291
1292         /* make sure address register is 0 for normal operation */
1293         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1294         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1295
1296         /* interrupt mitigation */
1297 #ifdef USE_RX_BLANK
1298         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1299         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1300         writel(val, cp->regs + REG_RX_BLANK);
1301 #else
1302         writel(0x0, cp->regs + REG_RX_BLANK);
1303 #endif
1304
1305         /* interrupt generation as a function of low water marks for
1306          * free desc and completion entries. these are used to trigger
1307          * housekeeping for rx descs. we don't use the free interrupt
1308          * as it's not very useful
1309          */
1310         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1311         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1312         writel(val, cp->regs + REG_RX_AE_THRESH);
1313         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1314                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1315                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1316         }
1317
1318         /* Random early detect registers. useful for congestion avoidance.
1319          * this should be tunable.
1320          */
1321         writel(0x0, cp->regs + REG_RX_RED);
1322         
1323         /* receive page sizes. default == 2K (0x800) */
1324         val = 0;
1325         if (cp->page_size == 0x1000)
1326                 val = 0x1;
1327         else if (cp->page_size == 0x2000)
1328                 val = 0x2;
1329         else if (cp->page_size == 0x4000)
1330                 val = 0x3;
1331         
1332         /* round mtu + offset. constrain to page size. */
1333         size = cp->dev->mtu + 64;
1334         if (size > cp->page_size)
1335                 size = cp->page_size;
1336
1337         if (size <= 0x400)
1338                 i = 0x0;
1339         else if (size <= 0x800)
1340                 i = 0x1;
1341         else if (size <= 0x1000)
1342                 i = 0x2;
1343         else
1344                 i = 0x3;
1345
1346         cp->mtu_stride = 1 << (i + 10);
1347         val  = CAS_BASE(RX_PAGE_SIZE, val);
1348         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); 
1349         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1350         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1351         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1352         
1353         /* enable the header parser if desired */
1354         if (CAS_HP_FIRMWARE == cas_prog_null)
1355                 return;
1356
1357         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1358         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1359         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1360         writel(val, cp->regs + REG_HP_CFG);
1361 }
1362
1363 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1364 {
1365         memset(rxc, 0, sizeof(*rxc));
1366         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); 
1367 }
1368
1369 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1370  * flipping is protected by the fact that the chip will not
1371  * hand back the same page index while it's being processed.
1372  */
1373 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1374 {
1375         cas_page_t *page = cp->rx_pages[1][index];
1376         cas_page_t *new;
1377
1378         if (cas_buffer_count(page) == 1)
1379                 return page;
1380
1381         new = cas_page_dequeue(cp);
1382         if (new) {
1383                 spin_lock(&cp->rx_inuse_lock);
1384                 list_add(&page->list, &cp->rx_inuse_list);
1385                 spin_unlock(&cp->rx_inuse_lock);
1386         }
1387         return new;
1388 }
1389                                    
1390 /* this needs to be changed if we actually use the ENC RX DESC ring */
1391 static cas_page_t *cas_page_swap(struct cas *cp, const int ring, 
1392                                  const int index)
1393 {
1394         cas_page_t **page0 = cp->rx_pages[0];
1395         cas_page_t **page1 = cp->rx_pages[1];
1396
1397         /* swap if buffer is in use */
1398         if (cas_buffer_count(page0[index]) > 1) {
1399                 cas_page_t *new = cas_page_spare(cp, index);
1400                 if (new) {
1401                         page1[index] = page0[index];
1402                         page0[index] = new;
1403                 }
1404         } 
1405         RX_USED_SET(page0[index], 0);
1406         return page0[index];
1407 }
1408
1409 static void cas_clean_rxds(struct cas *cp)
1410 {
1411         /* only clean ring 0 as ring 1 is used for spare buffers */
1412         struct cas_rx_desc *rxd = cp->init_rxds[0];
1413         int i, size;
1414
1415         /* release all rx flows */
1416         for (i = 0; i < N_RX_FLOWS; i++) {
1417                 struct sk_buff *skb;
1418                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1419                         cas_skb_release(skb);
1420                 }
1421         }
1422
1423         /* initialize descriptors */
1424         size = RX_DESC_RINGN_SIZE(0);
1425         for (i = 0; i < size; i++) {
1426                 cas_page_t *page = cas_page_swap(cp, 0, i);
1427                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1428                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | 
1429                                             CAS_BASE(RX_INDEX_RING, 0));
1430         }
1431
1432         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4; 
1433         cp->rx_last[0] = 0;
1434         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1435 }
1436
1437 static void cas_clean_rxcs(struct cas *cp)
1438 {
1439         int i, j;
1440
1441         /* take ownership of rx comp descriptors */
1442         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1443         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1444         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1445                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1446                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1447                         cas_rxc_init(rxc + j);
1448                 }
1449         }
1450 }
1451
1452 #if 0
1453 /* When we get a RX fifo overflow, the RX unit is probably hung
1454  * so we do the following.
1455  *
1456  * If any part of the reset goes wrong, we return 1 and that causes the
1457  * whole chip to be reset.
1458  */
1459 static int cas_rxmac_reset(struct cas *cp)
1460 {
1461         struct net_device *dev = cp->dev;
1462         int limit;
1463         u32 val;
1464
1465         /* First, reset MAC RX. */
1466         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1467         for (limit = 0; limit < STOP_TRIES; limit++) {
1468                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1469                         break;
1470                 udelay(10);
1471         }
1472         if (limit == STOP_TRIES) {
1473                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1474                        "chip.\n", dev->name);
1475                 return 1;
1476         }
1477
1478         /* Second, disable RX DMA. */
1479         writel(0, cp->regs + REG_RX_CFG);
1480         for (limit = 0; limit < STOP_TRIES; limit++) {
1481                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1482                         break;
1483                 udelay(10);
1484         }
1485         if (limit == STOP_TRIES) {
1486                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1487                        "chip.\n", dev->name);
1488                 return 1;
1489         }
1490
1491         mdelay(5);
1492
1493         /* Execute RX reset command. */
1494         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1495         for (limit = 0; limit < STOP_TRIES; limit++) {
1496                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1497                         break;
1498                 udelay(10);
1499         }
1500         if (limit == STOP_TRIES) {
1501                 printk(KERN_ERR "%s: RX reset command will not execute, "
1502                        "resetting whole chip.\n", dev->name);
1503                 return 1;
1504         }
1505
1506         /* reset driver rx state */
1507         cas_clean_rxds(cp);
1508         cas_clean_rxcs(cp);
1509
1510         /* Now, reprogram the rest of RX unit. */
1511         cas_init_rx_dma(cp);
1512
1513         /* re-enable */
1514         val = readl(cp->regs + REG_RX_CFG);
1515         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1516         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1517         val = readl(cp->regs + REG_MAC_RX_CFG);
1518         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1519         return 0;
1520 }
1521 #endif
1522
1523 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1524                                u32 status)
1525 {
1526         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1527
1528         if (!stat)
1529                 return 0;
1530
1531         if (netif_msg_intr(cp))
1532                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1533                         cp->dev->name, stat);
1534
1535         /* these are all rollovers */
1536         spin_lock(&cp->stat_lock[0]);
1537         if (stat & MAC_RX_ALIGN_ERR) 
1538                 cp->net_stats[0].rx_frame_errors += 0x10000;
1539
1540         if (stat & MAC_RX_CRC_ERR)
1541                 cp->net_stats[0].rx_crc_errors += 0x10000;
1542
1543         if (stat & MAC_RX_LEN_ERR)
1544                 cp->net_stats[0].rx_length_errors += 0x10000;
1545
1546         if (stat & MAC_RX_OVERFLOW) {
1547                 cp->net_stats[0].rx_over_errors++;
1548                 cp->net_stats[0].rx_fifo_errors++;
1549         }
1550
1551         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1552          * events.
1553          */
1554         spin_unlock(&cp->stat_lock[0]);
1555         return 0;
1556 }
1557
1558 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1559                              u32 status)
1560 {
1561         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1562
1563         if (!stat)
1564                 return 0;
1565
1566         if (netif_msg_intr(cp))
1567                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1568                         cp->dev->name, stat);
1569
1570         /* This interrupt is just for pause frame and pause
1571          * tracking.  It is useful for diagnostics and debug
1572          * but probably by default we will mask these events.
1573          */
1574         if (stat & MAC_CTRL_PAUSE_STATE)
1575                 cp->pause_entered++;
1576
1577         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1578                 cp->pause_last_time_recvd = (stat >> 16);
1579
1580         return 0;
1581 }
1582
1583         
1584 /* Must be invoked under cp->lock. */
1585 static inline int cas_mdio_link_not_up(struct cas *cp)
1586 {
1587         u16 val;
1588         
1589         switch (cp->lstate) {
1590         case link_force_ret:
1591                 if (netif_msg_link(cp))
1592                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1593                                 " forced mode\n", cp->dev->name);
1594                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1595                 cp->timer_ticks = 5;
1596                 cp->lstate = link_force_ok;
1597                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1598                 break;
1599                 
1600         case link_aneg:
1601                 val = cas_phy_read(cp, MII_BMCR);
1602
1603                 /* Try forced modes. we try things in the following order:
1604                  * 1000 full -> 100 full/half -> 10 half
1605                  */
1606                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1607                 val |= BMCR_FULLDPLX;
1608                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 
1609                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1610                 cas_phy_write(cp, MII_BMCR, val);
1611                 cp->timer_ticks = 5;
1612                 cp->lstate = link_force_try;
1613                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1614                 break;
1615
1616         case link_force_try:
1617                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1618                 val = cas_phy_read(cp, MII_BMCR);
1619                 cp->timer_ticks = 5;
1620                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1621                         val &= ~CAS_BMCR_SPEED1000;
1622                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1623                         cas_phy_write(cp, MII_BMCR, val);
1624                         break;
1625                 }
1626
1627                 if (val & BMCR_SPEED100) {
1628                         if (val & BMCR_FULLDPLX) /* fd failed */
1629                                 val &= ~BMCR_FULLDPLX;
1630                         else { /* 100Mbps failed */
1631                                 val &= ~BMCR_SPEED100;
1632                         }
1633                         cas_phy_write(cp, MII_BMCR, val);
1634                         break;
1635                 }
1636         default:
1637                 break;
1638         }
1639         return 0;
1640 }
1641
1642
1643 /* must be invoked with cp->lock held */
1644 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1645 {
1646         int restart;
1647
1648         if (bmsr & BMSR_LSTATUS) {
1649                 /* Ok, here we got a link. If we had it due to a forced
1650                  * fallback, and we were configured for autoneg, we 
1651                  * retry a short autoneg pass. If you know your hub is
1652                  * broken, use ethtool ;)
1653                  */
1654                 if ((cp->lstate == link_force_try) && 
1655                     (cp->link_cntl & BMCR_ANENABLE)) {
1656                         cp->lstate = link_force_ret;
1657                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1658                         cas_mif_poll(cp, 0);
1659                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1660                         cp->timer_ticks = 5;
1661                         if (cp->opened && netif_msg_link(cp))
1662                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1663                                        " autoneg once...\n", cp->dev->name);
1664                         cas_phy_write(cp, MII_BMCR,
1665                                       cp->link_fcntl | BMCR_ANENABLE |
1666                                       BMCR_ANRESTART);
1667                         cas_mif_poll(cp, 1);
1668
1669                 } else if (cp->lstate != link_up) {
1670                         cp->lstate = link_up;
1671                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1672
1673                         if (cp->opened) {
1674                                 cas_set_link_modes(cp);
1675                                 netif_carrier_on(cp->dev);
1676                         }
1677                 }
1678                 return 0;
1679         }
1680
1681         /* link not up. if the link was previously up, we restart the
1682          * whole process
1683          */
1684         restart = 0;
1685         if (cp->lstate == link_up) {
1686                 cp->lstate = link_down;
1687                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1688
1689                 netif_carrier_off(cp->dev);
1690                 if (cp->opened && netif_msg_link(cp))
1691                         printk(KERN_INFO "%s: Link down\n",
1692                                cp->dev->name);
1693                 restart = 1;
1694                 
1695         } else if (++cp->timer_ticks > 10)
1696                 cas_mdio_link_not_up(cp);
1697                 
1698         return restart;
1699 }
1700
1701 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1702                              u32 status)
1703 {
1704         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1705         u16 bmsr;
1706
1707         /* check for a link change */
1708         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1709                 return 0;
1710
1711         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1712         return cas_mii_link_check(cp, bmsr);
1713 }
1714
1715 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1716                              u32 status)
1717 {
1718         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1719
1720         if (!stat)
1721                 return 0;
1722
1723         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1724                readl(cp->regs + REG_BIM_DIAG));
1725
1726         /* cassini+ has this reserved */
1727         if ((stat & PCI_ERR_BADACK) &&
1728             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1729                 printk("<No ACK64# during ABS64 cycle> ");
1730
1731         if (stat & PCI_ERR_DTRTO)
1732                 printk("<Delayed transaction timeout> ");
1733         if (stat & PCI_ERR_OTHER)
1734                 printk("<other> ");
1735         if (stat & PCI_ERR_BIM_DMA_WRITE)
1736                 printk("<BIM DMA 0 write req> ");
1737         if (stat & PCI_ERR_BIM_DMA_READ)
1738                 printk("<BIM DMA 0 read req> ");
1739         printk("\n");
1740
1741         if (stat & PCI_ERR_OTHER) {
1742                 u16 cfg;
1743
1744                 /* Interrogate PCI config space for the
1745                  * true cause.
1746                  */
1747                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1748                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1749                        dev->name, cfg);
1750                 if (cfg & PCI_STATUS_PARITY)
1751                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1752                                dev->name);
1753                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1754                         printk(KERN_ERR "%s: PCI target abort.\n",
1755                                dev->name);
1756                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1757                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1758                                dev->name);
1759                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1760                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1761                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1762                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1763                                dev->name);
1764                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1765                         printk(KERN_ERR "%s: PCI parity error.\n",
1766                                dev->name);
1767
1768                 /* Write the error bits back to clear them. */
1769                 cfg &= (PCI_STATUS_PARITY |
1770                         PCI_STATUS_SIG_TARGET_ABORT |
1771                         PCI_STATUS_REC_TARGET_ABORT |
1772                         PCI_STATUS_REC_MASTER_ABORT |
1773                         PCI_STATUS_SIG_SYSTEM_ERROR |
1774                         PCI_STATUS_DETECTED_PARITY);
1775                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1776         }
1777
1778         /* For all PCI errors, we should reset the chip. */
1779         return 1;
1780 }
1781
1782 /* All non-normal interrupt conditions get serviced here.
1783  * Returns non-zero if we should just exit the interrupt
1784  * handler right now (ie. if we reset the card which invalidates
1785  * all of the other original irq status bits).
1786  */
1787 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1788                             u32 status)
1789 {
1790         if (status & INTR_RX_TAG_ERROR) {
1791                 /* corrupt RX tag framing */
1792                 if (netif_msg_rx_err(cp))
1793                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1794                                 cp->dev->name);
1795                 spin_lock(&cp->stat_lock[0]);
1796                 cp->net_stats[0].rx_errors++;
1797                 spin_unlock(&cp->stat_lock[0]);
1798                 goto do_reset;
1799         }
1800
1801         if (status & INTR_RX_LEN_MISMATCH) {
1802                 /* length mismatch. */
1803                 if (netif_msg_rx_err(cp))
1804                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1805                                 cp->dev->name);
1806                 spin_lock(&cp->stat_lock[0]);
1807                 cp->net_stats[0].rx_errors++;
1808                 spin_unlock(&cp->stat_lock[0]);
1809                 goto do_reset;
1810         }
1811
1812         if (status & INTR_PCS_STATUS) {
1813                 if (cas_pcs_interrupt(dev, cp, status))
1814                         goto do_reset;
1815         }
1816
1817         if (status & INTR_TX_MAC_STATUS) {
1818                 if (cas_txmac_interrupt(dev, cp, status))
1819                         goto do_reset;
1820         }
1821
1822         if (status & INTR_RX_MAC_STATUS) {
1823                 if (cas_rxmac_interrupt(dev, cp, status))
1824                         goto do_reset;
1825         }
1826
1827         if (status & INTR_MAC_CTRL_STATUS) {
1828                 if (cas_mac_interrupt(dev, cp, status))
1829                         goto do_reset;
1830         }
1831
1832         if (status & INTR_MIF_STATUS) {
1833                 if (cas_mif_interrupt(dev, cp, status))
1834                         goto do_reset;
1835         }
1836
1837         if (status & INTR_PCI_ERROR_STATUS) {
1838                 if (cas_pci_interrupt(dev, cp, status))
1839                         goto do_reset;
1840         }
1841         return 0;
1842
1843 do_reset:
1844 #if 1
1845         atomic_inc(&cp->reset_task_pending);
1846         atomic_inc(&cp->reset_task_pending_all);
1847         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1848                dev->name, status);
1849         schedule_work(&cp->reset_task);
1850 #else
1851         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1852         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1853         schedule_work(&cp->reset_task);
1854 #endif
1855         return 1;
1856 }
1857
1858 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1859  *       determining whether to do a netif_stop/wakeup
1860  */
1861 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1862 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1863 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1864                                   const int len)
1865 {
1866         unsigned long off = addr + len;
1867
1868         if (CAS_TABORT(cp) == 1)
1869                 return 0;
1870         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1871                 return 0;
1872         return TX_TARGET_ABORT_LEN;
1873 }
1874
1875 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1876 {
1877         struct cas_tx_desc *txds;
1878         struct sk_buff **skbs;
1879         struct net_device *dev = cp->dev;
1880         int entry, count;
1881
1882         spin_lock(&cp->tx_lock[ring]);
1883         txds = cp->init_txds[ring];
1884         skbs = cp->tx_skbs[ring];
1885         entry = cp->tx_old[ring];
1886
1887         count = TX_BUFF_COUNT(ring, entry, limit);
1888         while (entry != limit) {
1889                 struct sk_buff *skb = skbs[entry];
1890                 dma_addr_t daddr;
1891                 u32 dlen;
1892                 int frag;
1893
1894                 if (!skb) {
1895                         /* this should never occur */
1896                         entry = TX_DESC_NEXT(ring, entry);
1897                         continue;
1898                 }
1899
1900                 /* however, we might get only a partial skb release. */
1901                 count -= skb_shinfo(skb)->nr_frags +
1902                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1903                 if (count < 0)
1904                         break;
1905
1906                 if (netif_msg_tx_done(cp))
1907                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1908                                cp->dev->name, ring, entry);
1909
1910                 skbs[entry] = NULL;
1911                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1912                 
1913                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1914                         struct cas_tx_desc *txd = txds + entry;
1915
1916                         daddr = le64_to_cpu(txd->buffer);
1917                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1918                                        le64_to_cpu(txd->control));
1919                         pci_unmap_page(cp->pdev, daddr, dlen,
1920                                        PCI_DMA_TODEVICE);
1921                         entry = TX_DESC_NEXT(ring, entry);
1922
1923                         /* tiny buffer may follow */
1924                         if (cp->tx_tiny_use[ring][entry].used) {
1925                                 cp->tx_tiny_use[ring][entry].used = 0;
1926                                 entry = TX_DESC_NEXT(ring, entry);
1927                         } 
1928                 }
1929
1930                 spin_lock(&cp->stat_lock[ring]);
1931                 cp->net_stats[ring].tx_packets++;
1932                 cp->net_stats[ring].tx_bytes += skb->len;
1933                 spin_unlock(&cp->stat_lock[ring]);
1934                 dev_kfree_skb_irq(skb);
1935         }
1936         cp->tx_old[ring] = entry;
1937
1938         /* this is wrong for multiple tx rings. the net device needs
1939          * multiple queues for this to do the right thing.  we wait
1940          * for 2*packets to be available when using tiny buffers
1941          */
1942         if (netif_queue_stopped(dev) &&
1943             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1944                 netif_wake_queue(dev);
1945         spin_unlock(&cp->tx_lock[ring]);
1946 }
1947
1948 static void cas_tx(struct net_device *dev, struct cas *cp,
1949                    u32 status)
1950 {
1951         int limit, ring;
1952 #ifdef USE_TX_COMPWB
1953         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1954 #endif
1955         if (netif_msg_intr(cp))
1956                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1957                         cp->dev->name, status, (unsigned long long)compwb);
1958         /* process all the rings */
1959         for (ring = 0; ring < N_TX_RINGS; ring++) {
1960 #ifdef USE_TX_COMPWB
1961                 /* use the completion writeback registers */
1962                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1963                         CAS_VAL(TX_COMPWB_LSB, compwb);
1964                 compwb = TX_COMPWB_NEXT(compwb);
1965 #else
1966                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1967 #endif
1968                 if (cp->tx_old[ring] != limit) 
1969                         cas_tx_ringN(cp, ring, limit);
1970         }
1971 }
1972
1973
1974 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, 
1975                               int entry, const u64 *words, 
1976                               struct sk_buff **skbref)
1977 {
1978         int dlen, hlen, len, i, alloclen;
1979         int off, swivel = RX_SWIVEL_OFF_VAL;
1980         struct cas_page *page;
1981         struct sk_buff *skb;
1982         void *addr, *crcaddr;
1983         char *p; 
1984
1985         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1986         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1987         len  = hlen + dlen;
1988
1989         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) 
1990                 alloclen = len;
1991         else 
1992                 alloclen = max(hlen, RX_COPY_MIN);
1993
1994         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1995         if (skb == NULL) 
1996                 return -1;
1997
1998         *skbref = skb;
1999         skb->dev = cp->dev;
2000         skb_reserve(skb, swivel);
2001
2002         p = skb->data;
2003         addr = crcaddr = NULL;
2004         if (hlen) { /* always copy header pages */
2005                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2006                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2007                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + 
2008                         swivel;
2009
2010                 i = hlen;
2011                 if (!dlen) /* attach FCS */
2012                         i += cp->crc_size;
2013                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2014                                     PCI_DMA_FROMDEVICE);
2015                 addr = cas_page_map(page->buffer);
2016                 memcpy(p, addr + off, i);
2017                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2018                                     PCI_DMA_FROMDEVICE);
2019                 cas_page_unmap(addr);
2020                 RX_USED_ADD(page, 0x100);
2021                 p += hlen;
2022                 swivel = 0;
2023         } 
2024
2025
2026         if (alloclen < (hlen + dlen)) {
2027                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2028
2029                 /* normal or jumbo packets. we use frags */
2030                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2031                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2032                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2033
2034                 hlen = min(cp->page_size - off, dlen);
2035                 if (hlen < 0) {
2036                         if (netif_msg_rx_err(cp)) {
2037                                 printk(KERN_DEBUG "%s: rx page overflow: "
2038                                        "%d\n", cp->dev->name, hlen);
2039                         }
2040                         dev_kfree_skb_irq(skb);
2041                         return -1;
2042                 }
2043                 i = hlen;
2044                 if (i == dlen)  /* attach FCS */
2045                         i += cp->crc_size;
2046                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2047                                     PCI_DMA_FROMDEVICE);
2048
2049                 /* make sure we always copy a header */
2050                 swivel = 0;
2051                 if (p == (char *) skb->data) { /* not split */
2052                         addr = cas_page_map(page->buffer);
2053                         memcpy(p, addr + off, RX_COPY_MIN);
2054                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2055                                         PCI_DMA_FROMDEVICE);
2056                         cas_page_unmap(addr);
2057                         off += RX_COPY_MIN;
2058                         swivel = RX_COPY_MIN;
2059                         RX_USED_ADD(page, cp->mtu_stride);
2060                 } else {
2061                         RX_USED_ADD(page, hlen);
2062                 }
2063                 skb_put(skb, alloclen);
2064
2065                 skb_shinfo(skb)->nr_frags++;
2066                 skb->data_len += hlen - swivel;
2067                 skb->len      += hlen - swivel;
2068
2069                 get_page(page->buffer);
2070                 cas_buffer_inc(page);
2071                 frag->page = page->buffer;
2072                 frag->page_offset = off;
2073                 frag->size = hlen - swivel;
2074                 
2075                 /* any more data? */
2076                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2077                         hlen = dlen;
2078                         off = 0;
2079
2080                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2081                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2082                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 
2083                                             hlen + cp->crc_size, 
2084                                             PCI_DMA_FROMDEVICE);
2085                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2086                                             hlen + cp->crc_size,
2087                                             PCI_DMA_FROMDEVICE);
2088
2089                         skb_shinfo(skb)->nr_frags++;
2090                         skb->data_len += hlen;
2091                         skb->len      += hlen; 
2092                         frag++;
2093
2094                         get_page(page->buffer);
2095                         cas_buffer_inc(page);
2096                         frag->page = page->buffer;
2097                         frag->page_offset = 0;
2098                         frag->size = hlen;
2099                         RX_USED_ADD(page, hlen + cp->crc_size);
2100                 }
2101
2102                 if (cp->crc_size) {
2103                         addr = cas_page_map(page->buffer);
2104                         crcaddr  = addr + off + hlen;
2105                 }
2106
2107         } else {
2108                 /* copying packet */
2109                 if (!dlen)
2110                         goto end_copy_pkt;
2111
2112                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2113                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2114                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2115                 hlen = min(cp->page_size - off, dlen);
2116                 if (hlen < 0) {
2117                         if (netif_msg_rx_err(cp)) {
2118                                 printk(KERN_DEBUG "%s: rx page overflow: "
2119                                        "%d\n", cp->dev->name, hlen);
2120                         }
2121                         dev_kfree_skb_irq(skb);
2122                         return -1;
2123                 }
2124                 i = hlen;
2125                 if (i == dlen) /* attach FCS */
2126                         i += cp->crc_size;
2127                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2128                                     PCI_DMA_FROMDEVICE);
2129                 addr = cas_page_map(page->buffer);
2130                 memcpy(p, addr + off, i);
2131                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2132                                     PCI_DMA_FROMDEVICE);
2133                 cas_page_unmap(addr);
2134                 if (p == (char *) skb->data) /* not split */
2135                         RX_USED_ADD(page, cp->mtu_stride);
2136                 else
2137                         RX_USED_ADD(page, i);
2138         
2139                 /* any more data? */
2140                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2141                         p += hlen;
2142                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2143                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2144                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 
2145                                             dlen + cp->crc_size, 
2146                                             PCI_DMA_FROMDEVICE);
2147                         addr = cas_page_map(page->buffer);
2148                         memcpy(p, addr, dlen + cp->crc_size);
2149                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2150                                             dlen + cp->crc_size,
2151                                             PCI_DMA_FROMDEVICE);
2152                         cas_page_unmap(addr);
2153                         RX_USED_ADD(page, dlen + cp->crc_size); 
2154                 }
2155 end_copy_pkt:
2156                 if (cp->crc_size) {
2157                         addr    = NULL;
2158                         crcaddr = skb->data + alloclen;
2159                 }
2160                 skb_put(skb, alloclen);
2161         }
2162
2163         i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2164         if (cp->crc_size) {
2165                 /* checksum includes FCS. strip it out. */
2166                 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2167                 if (addr)
2168                         cas_page_unmap(addr);
2169         }
2170         skb->csum = ntohs(i ^ 0xffff);
2171         skb->ip_summed = CHECKSUM_HW;
2172         skb->protocol = eth_type_trans(skb, cp->dev);
2173         return len;
2174 }
2175
2176
2177 /* we can handle up to 64 rx flows at a time. we do the same thing
2178  * as nonreassm except that we batch up the buffers. 
2179  * NOTE: we currently just treat each flow as a bunch of packets that
2180  *       we pass up. a better way would be to coalesce the packets
2181  *       into a jumbo packet. to do that, we need to do the following:
2182  *       1) the first packet will have a clean split between header and
2183  *          data. save both.
2184  *       2) each time the next flow packet comes in, extend the
2185  *          data length and merge the checksums.
2186  *       3) on flow release, fix up the header.
2187  *       4) make sure the higher layer doesn't care.
2188  * because packets get coalesced, we shouldn't run into fragment count 
2189  * issues.
2190  */
2191 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2192                                    struct sk_buff *skb)
2193 {
2194         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2195         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2196         
2197         /* this is protected at a higher layer, so no need to 
2198          * do any additional locking here. stick the buffer
2199          * at the end.
2200          */
2201         __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2202         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2203                 while ((skb = __skb_dequeue(flow))) {
2204                         cas_skb_release(skb);
2205                 }
2206         }
2207 }
2208
2209 /* put rx descriptor back on ring. if a buffer is in use by a higher
2210  * layer, this will need to put in a replacement.
2211  */
2212 static void cas_post_page(struct cas *cp, const int ring, const int index)
2213 {
2214         cas_page_t *new;
2215         int entry;
2216
2217         entry = cp->rx_old[ring];
2218
2219         new = cas_page_swap(cp, ring, index);
2220         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2221         cp->init_rxds[ring][entry].index  =
2222                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | 
2223                             CAS_BASE(RX_INDEX_RING, ring));
2224
2225         entry = RX_DESC_ENTRY(ring, entry + 1);
2226         cp->rx_old[ring] = entry;
2227         
2228         if (entry % 4)
2229                 return;
2230
2231         if (ring == 0)
2232                 writel(entry, cp->regs + REG_RX_KICK);
2233         else if ((N_RX_DESC_RINGS > 1) &&
2234                  (cp->cas_flags & CAS_FLAG_REG_PLUS)) 
2235                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2236 }
2237
2238
2239 /* only when things are bad */
2240 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2241 {
2242         unsigned int entry, last, count, released;
2243         int cluster;
2244         cas_page_t **page = cp->rx_pages[ring];
2245
2246         entry = cp->rx_old[ring];
2247
2248         if (netif_msg_intr(cp))
2249                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2250                        cp->dev->name, ring, entry);
2251
2252         cluster = -1;
2253         count = entry & 0x3; 
2254         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2255         released = 0;
2256         while (entry != last) {
2257                 /* make a new buffer if it's still in use */
2258                 if (cas_buffer_count(page[entry]) > 1) {
2259                         cas_page_t *new = cas_page_dequeue(cp);
2260                         if (!new) {
2261                                 /* let the timer know that we need to 
2262                                  * do this again
2263                                  */
2264                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2265                                 if (!timer_pending(&cp->link_timer))
2266                                         mod_timer(&cp->link_timer, jiffies + 
2267                                                   CAS_LINK_FAST_TIMEOUT);
2268                                 cp->rx_old[ring]  = entry;
2269                                 cp->rx_last[ring] = num ? num - released : 0;
2270                                 return -ENOMEM;
2271                         }
2272                         spin_lock(&cp->rx_inuse_lock);
2273                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2274                         spin_unlock(&cp->rx_inuse_lock);
2275                         cp->init_rxds[ring][entry].buffer = 
2276                                 cpu_to_le64(new->dma_addr);
2277                         page[entry] = new;
2278                         
2279                 }
2280
2281                 if (++count == 4) {
2282                         cluster = entry;
2283                         count = 0;
2284                 }
2285                 released++;
2286                 entry = RX_DESC_ENTRY(ring, entry + 1);
2287         }
2288         cp->rx_old[ring] = entry;
2289
2290         if (cluster < 0) 
2291                 return 0;
2292
2293         if (ring == 0)
2294                 writel(cluster, cp->regs + REG_RX_KICK);
2295         else if ((N_RX_DESC_RINGS > 1) &&
2296                  (cp->cas_flags & CAS_FLAG_REG_PLUS)) 
2297                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2298         return 0;
2299 }
2300
2301
2302 /* process a completion ring. packets are set up in three basic ways:
2303  * small packets: should be copied header + data in single buffer.
2304  * large packets: header and data in a single buffer.
2305  * split packets: header in a separate buffer from data. 
2306  *                data may be in multiple pages. data may be > 256
2307  *                bytes but in a single page. 
2308  *
2309  * NOTE: RX page posting is done in this routine as well. while there's
2310  *       the capability of using multiple RX completion rings, it isn't
2311  *       really worthwhile due to the fact that the page posting will
2312  *       force serialization on the single descriptor ring. 
2313  */
2314 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2315 {
2316         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2317         int entry, drops;
2318         int npackets = 0;
2319
2320         if (netif_msg_intr(cp))
2321                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2322                        cp->dev->name, ring,
2323                        readl(cp->regs + REG_RX_COMP_HEAD), 
2324                        cp->rx_new[ring]);
2325
2326         entry = cp->rx_new[ring];
2327         drops = 0;
2328         while (1) {
2329                 struct cas_rx_comp *rxc = rxcs + entry;
2330                 struct sk_buff *skb;
2331                 int type, len;
2332                 u64 words[4];
2333                 int i, dring;
2334
2335                 words[0] = le64_to_cpu(rxc->word1);
2336                 words[1] = le64_to_cpu(rxc->word2);
2337                 words[2] = le64_to_cpu(rxc->word3);
2338                 words[3] = le64_to_cpu(rxc->word4);
2339
2340                 /* don't touch if still owned by hw */
2341                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2342                 if (type == 0)
2343                         break;
2344
2345                 /* hw hasn't cleared the zero bit yet */
2346                 if (words[3] & RX_COMP4_ZERO) {
2347                         break;
2348                 }
2349
2350                 /* get info on the packet */
2351                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2352                         spin_lock(&cp->stat_lock[ring]);
2353                         cp->net_stats[ring].rx_errors++;
2354                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2355                                 cp->net_stats[ring].rx_length_errors++;
2356                         if (words[3] & RX_COMP4_BAD)
2357                                 cp->net_stats[ring].rx_crc_errors++;
2358                         spin_unlock(&cp->stat_lock[ring]);
2359
2360                         /* We'll just return it to Cassini. */
2361                 drop_it:
2362                         spin_lock(&cp->stat_lock[ring]);
2363                         ++cp->net_stats[ring].rx_dropped;
2364                         spin_unlock(&cp->stat_lock[ring]);
2365                         goto next;
2366                 }
2367
2368                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2369                 if (len < 0) {
2370                         ++drops;
2371                         goto drop_it;
2372                 }
2373
2374                 /* see if it's a flow re-assembly or not. the driver
2375                  * itself handles release back up.
2376                  */
2377                 if (RX_DONT_BATCH || (type == 0x2)) {
2378                         /* non-reassm: these always get released */
2379                         cas_skb_release(skb); 
2380                 } else {
2381                         cas_rx_flow_pkt(cp, words, skb);
2382                 }
2383
2384                 spin_lock(&cp->stat_lock[ring]);
2385                 cp->net_stats[ring].rx_packets++;
2386                 cp->net_stats[ring].rx_bytes += len;
2387                 spin_unlock(&cp->stat_lock[ring]);
2388                 cp->dev->last_rx = jiffies;
2389
2390         next:
2391                 npackets++;
2392
2393                 /* should it be released? */
2394                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2395                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2396                         dring = CAS_VAL(RX_INDEX_RING, i);
2397                         i = CAS_VAL(RX_INDEX_NUM, i);
2398                         cas_post_page(cp, dring, i);
2399                 }
2400                 
2401                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2402                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2403                         dring = CAS_VAL(RX_INDEX_RING, i);
2404                         i = CAS_VAL(RX_INDEX_NUM, i);
2405                         cas_post_page(cp, dring, i);
2406                 }
2407
2408                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2409                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2410                         dring = CAS_VAL(RX_INDEX_RING, i);
2411                         i = CAS_VAL(RX_INDEX_NUM, i);
2412                         cas_post_page(cp, dring, i);
2413                 }
2414
2415                 /* skip to the next entry */
2416                 entry = RX_COMP_ENTRY(ring, entry + 1 + 
2417                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2418 #ifdef USE_NAPI
2419                 if (budget && (npackets >= budget))
2420                         break;
2421 #endif
2422         }
2423         cp->rx_new[ring] = entry;
2424
2425         if (drops)
2426                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2427                        cp->dev->name);
2428         return npackets;
2429 }
2430
2431
2432 /* put completion entries back on the ring */
2433 static void cas_post_rxcs_ringN(struct net_device *dev,
2434                                 struct cas *cp, int ring)
2435 {
2436         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2437         int last, entry;
2438
2439         last = cp->rx_cur[ring];
2440         entry = cp->rx_new[ring]; 
2441         if (netif_msg_intr(cp))
2442                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2443                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2444                        entry);
2445         
2446         /* zero and re-mark descriptors */
2447         while (last != entry) {
2448                 cas_rxc_init(rxc + last);
2449                 last = RX_COMP_ENTRY(ring, last + 1);
2450         }
2451         cp->rx_cur[ring] = last;
2452
2453         if (ring == 0)
2454                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2455         else if (cp->cas_flags & CAS_FLAG_REG_PLUS) 
2456                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2457 }
2458
2459
2460
2461 /* cassini can use all four PCI interrupts for the completion ring. 
2462  * rings 3 and 4 are identical
2463  */
2464 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2465 static inline void cas_handle_irqN(struct net_device *dev, 
2466                                    struct cas *cp, const u32 status,
2467                                    const int ring)
2468 {
2469         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) 
2470                 cas_post_rxcs_ringN(dev, cp, ring);
2471 }
2472
2473 static irqreturn_t cas_interruptN(int irq, void *dev_id, struct pt_regs *regs)
2474 {
2475         struct net_device *dev = dev_id;
2476         struct cas *cp = netdev_priv(dev);
2477         unsigned long flags;
2478         int ring;
2479         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2480
2481         /* check for shared irq */
2482         if (status == 0)
2483                 return IRQ_NONE;
2484
2485         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2486         spin_lock_irqsave(&cp->lock, flags);
2487         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2488 #ifdef USE_NAPI
2489                 cas_mask_intr(cp);
2490                 netif_rx_schedule(dev);
2491 #else
2492                 cas_rx_ringN(cp, ring, 0);
2493 #endif
2494                 status &= ~INTR_RX_DONE_ALT;
2495         }
2496
2497         if (status)
2498                 cas_handle_irqN(dev, cp, status, ring);
2499         spin_unlock_irqrestore(&cp->lock, flags);
2500         return IRQ_HANDLED;
2501 }
2502 #endif
2503
2504 #ifdef USE_PCI_INTB
2505 /* everything but rx packets */
2506 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2507 {
2508         if (status & INTR_RX_BUF_UNAVAIL_1) {
2509                 /* Frame arrived, no free RX buffers available. 
2510                  * NOTE: we can get this on a link transition. */
2511                 cas_post_rxds_ringN(cp, 1, 0);
2512                 spin_lock(&cp->stat_lock[1]);
2513                 cp->net_stats[1].rx_dropped++;
2514                 spin_unlock(&cp->stat_lock[1]);
2515         }
2516
2517         if (status & INTR_RX_BUF_AE_1) 
2518                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - 
2519                                     RX_AE_FREEN_VAL(1));
2520
2521         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2522                 cas_post_rxcs_ringN(cp, 1);
2523 }
2524
2525 /* ring 2 handles a few more events than 3 and 4 */
2526 static irqreturn_t cas_interrupt1(int irq, void *dev_id, struct pt_regs *regs)
2527 {
2528         struct net_device *dev = dev_id;
2529         struct cas *cp = netdev_priv(dev);
2530         unsigned long flags;
2531         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2532
2533         /* check for shared interrupt */
2534         if (status == 0)
2535                 return IRQ_NONE;
2536
2537         spin_lock_irqsave(&cp->lock, flags);
2538         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2539 #ifdef USE_NAPI
2540                 cas_mask_intr(cp);
2541                 netif_rx_schedule(dev);
2542 #else
2543                 cas_rx_ringN(cp, 1, 0);
2544 #endif
2545                 status &= ~INTR_RX_DONE_ALT;
2546         }
2547         if (status)
2548                 cas_handle_irq1(cp, status);
2549         spin_unlock_irqrestore(&cp->lock, flags);
2550         return IRQ_HANDLED;
2551 }
2552 #endif
2553
2554 static inline void cas_handle_irq(struct net_device *dev,
2555                                   struct cas *cp, const u32 status)
2556 {
2557         /* housekeeping interrupts */
2558         if (status & INTR_ERROR_MASK)
2559                 cas_abnormal_irq(dev, cp, status);
2560
2561         if (status & INTR_RX_BUF_UNAVAIL) {
2562                 /* Frame arrived, no free RX buffers available. 
2563                  * NOTE: we can get this on a link transition.
2564                  */
2565                 cas_post_rxds_ringN(cp, 0, 0);
2566                 spin_lock(&cp->stat_lock[0]);
2567                 cp->net_stats[0].rx_dropped++;
2568                 spin_unlock(&cp->stat_lock[0]);
2569         } else if (status & INTR_RX_BUF_AE) {
2570                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2571                                     RX_AE_FREEN_VAL(0));
2572         }
2573
2574         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2575                 cas_post_rxcs_ringN(dev, cp, 0);
2576 }
2577
2578 static irqreturn_t cas_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2579 {
2580         struct net_device *dev = dev_id;
2581         struct cas *cp = netdev_priv(dev);
2582         unsigned long flags;
2583         u32 status = readl(cp->regs + REG_INTR_STATUS);
2584
2585         if (status == 0)
2586                 return IRQ_NONE;
2587
2588         spin_lock_irqsave(&cp->lock, flags);
2589         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2590                 cas_tx(dev, cp, status);
2591                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2592         }
2593
2594         if (status & INTR_RX_DONE) {
2595 #ifdef USE_NAPI
2596                 cas_mask_intr(cp);
2597                 netif_rx_schedule(dev);
2598 #else
2599                 cas_rx_ringN(cp, 0, 0);
2600 #endif
2601                 status &= ~INTR_RX_DONE;
2602         }
2603
2604         if (status)
2605                 cas_handle_irq(dev, cp, status);
2606         spin_unlock_irqrestore(&cp->lock, flags);
2607         return IRQ_HANDLED;
2608 }
2609
2610
2611 #ifdef USE_NAPI
2612 static int cas_poll(struct net_device *dev, int *budget)
2613 {
2614         struct cas *cp = netdev_priv(dev);
2615         int i, enable_intr, todo, credits;
2616         u32 status = readl(cp->regs + REG_INTR_STATUS);
2617         unsigned long flags;
2618
2619         spin_lock_irqsave(&cp->lock, flags);
2620         cas_tx(dev, cp, status);
2621         spin_unlock_irqrestore(&cp->lock, flags);
2622
2623         /* NAPI rx packets. we spread the credits across all of the
2624          * rxc rings
2625          */
2626         todo = min(*budget, dev->quota);
2627
2628         /* to make sure we're fair with the work we loop through each
2629          * ring N_RX_COMP_RING times with a request of 
2630          * todo / N_RX_COMP_RINGS
2631          */
2632         enable_intr = 1;
2633         credits = 0;
2634         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2635                 int j;
2636                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2637                         credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
2638                         if (credits >= todo) {
2639                                 enable_intr = 0;
2640                                 goto rx_comp;
2641                         }
2642                 }
2643         }
2644
2645 rx_comp:
2646         *budget    -= credits;
2647         dev->quota -= credits;
2648
2649         /* final rx completion */
2650         spin_lock_irqsave(&cp->lock, flags);
2651         if (status)
2652                 cas_handle_irq(dev, cp, status);
2653
2654 #ifdef USE_PCI_INTB
2655         if (N_RX_COMP_RINGS > 1) {
2656                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2657                 if (status)
2658                         cas_handle_irq1(dev, cp, status);
2659         }
2660 #endif
2661
2662 #ifdef USE_PCI_INTC
2663         if (N_RX_COMP_RINGS > 2) {
2664                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2665                 if (status)
2666                         cas_handle_irqN(dev, cp, status, 2);
2667         }
2668 #endif
2669
2670 #ifdef USE_PCI_INTD
2671         if (N_RX_COMP_RINGS > 3) {
2672                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2673                 if (status)
2674                         cas_handle_irqN(dev, cp, status, 3);
2675         }
2676 #endif
2677         spin_unlock_irqrestore(&cp->lock, flags);
2678         if (enable_intr) {
2679                 netif_rx_complete(dev);
2680                 cas_unmask_intr(cp);
2681                 return 0;
2682         }
2683         return 1;
2684 }
2685 #endif
2686
2687 #ifdef CONFIG_NET_POLL_CONTROLLER
2688 static void cas_netpoll(struct net_device *dev)
2689 {
2690         struct cas *cp = netdev_priv(dev);
2691
2692         cas_disable_irq(cp, 0);
2693         cas_interrupt(cp->pdev->irq, dev, NULL);
2694         cas_enable_irq(cp, 0);
2695
2696 #ifdef USE_PCI_INTB
2697         if (N_RX_COMP_RINGS > 1) {
2698                 /* cas_interrupt1(); */
2699         }
2700 #endif
2701 #ifdef USE_PCI_INTC
2702         if (N_RX_COMP_RINGS > 2) {
2703                 /* cas_interruptN(); */
2704         }
2705 #endif
2706 #ifdef USE_PCI_INTD
2707         if (N_RX_COMP_RINGS > 3) {
2708                 /* cas_interruptN(); */
2709         }
2710 #endif
2711 }
2712 #endif
2713
2714 static void cas_tx_timeout(struct net_device *dev)
2715 {
2716         struct cas *cp = netdev_priv(dev);
2717
2718         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2719         if (!cp->hw_running) {
2720                 printk("%s: hrm.. hw not running!\n", dev->name);
2721                 return;
2722         }
2723
2724         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2725                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2726
2727         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2728                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2729
2730         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2731                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2732                dev->name,
2733                readl(cp->regs + REG_TX_CFG),
2734                readl(cp->regs + REG_MAC_TX_STATUS),
2735                readl(cp->regs + REG_MAC_TX_CFG),
2736                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2737                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2738                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2739                readl(cp->regs + REG_TX_SM_1),
2740                readl(cp->regs + REG_TX_SM_2));
2741
2742         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2743                dev->name,
2744                readl(cp->regs + REG_RX_CFG),
2745                readl(cp->regs + REG_MAC_RX_STATUS),
2746                readl(cp->regs + REG_MAC_RX_CFG));
2747
2748         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2749                dev->name,
2750                readl(cp->regs + REG_HP_STATE_MACHINE),
2751                readl(cp->regs + REG_HP_STATUS0),
2752                readl(cp->regs + REG_HP_STATUS1),
2753                readl(cp->regs + REG_HP_STATUS2));
2754
2755 #if 1
2756         atomic_inc(&cp->reset_task_pending);
2757         atomic_inc(&cp->reset_task_pending_all);
2758         schedule_work(&cp->reset_task);
2759 #else
2760         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2761         schedule_work(&cp->reset_task);
2762 #endif
2763 }
2764
2765 static inline int cas_intme(int ring, int entry)
2766 {
2767         /* Algorithm: IRQ every 1/2 of descriptors. */
2768         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2769                 return 1;
2770         return 0;
2771 }
2772
2773
2774 static void cas_write_txd(struct cas *cp, int ring, int entry,
2775                           dma_addr_t mapping, int len, u64 ctrl, int last)
2776 {
2777         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2778
2779         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2780         if (cas_intme(ring, entry))
2781                 ctrl |= TX_DESC_INTME;
2782         if (last)
2783                 ctrl |= TX_DESC_EOF;
2784         txd->control = cpu_to_le64(ctrl);
2785         txd->buffer = cpu_to_le64(mapping);
2786 }
2787
2788 static inline void *tx_tiny_buf(struct cas *cp, const int ring, 
2789                                 const int entry)
2790 {
2791         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2792 }
2793
2794 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, 
2795                                      const int entry, const int tentry)
2796 {
2797         cp->tx_tiny_use[ring][tentry].nbufs++;
2798         cp->tx_tiny_use[ring][entry].used = 1;
2799         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2800 }
2801
2802 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, 
2803                                     struct sk_buff *skb)
2804 {
2805         struct net_device *dev = cp->dev;
2806         int entry, nr_frags, frag, tabort, tentry;
2807         dma_addr_t mapping;
2808         unsigned long flags;
2809         u64 ctrl;
2810         u32 len;
2811
2812         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2813
2814         /* This is a hard error, log it. */
2815         if (TX_BUFFS_AVAIL(cp, ring) <= 
2816             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2817                 netif_stop_queue(dev);
2818                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2819                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2820                        "queue awake!\n", dev->name);
2821                 return 1;
2822         }
2823
2824         ctrl = 0;
2825         if (skb->ip_summed == CHECKSUM_HW) {
2826                 u64 csum_start_off, csum_stuff_off;
2827
2828                 csum_start_off = (u64) (skb->h.raw - skb->data);
2829                 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
2830
2831                 ctrl =  TX_DESC_CSUM_EN | 
2832                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2833                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2834         }
2835
2836         entry = cp->tx_new[ring];
2837         cp->tx_skbs[ring][entry] = skb;
2838
2839         nr_frags = skb_shinfo(skb)->nr_frags;
2840         len = skb_headlen(skb);
2841         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2842                                offset_in_page(skb->data), len,
2843                                PCI_DMA_TODEVICE);
2844
2845         tentry = entry;
2846         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2847         if (unlikely(tabort)) {
2848                 /* NOTE: len is always >  tabort */
2849                 cas_write_txd(cp, ring, entry, mapping, len - tabort, 
2850                               ctrl | TX_DESC_SOF, 0);
2851                 entry = TX_DESC_NEXT(ring, entry);
2852
2853                 memcpy(tx_tiny_buf(cp, ring, entry), skb->data + 
2854                        len - tabort, tabort);
2855                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2856                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2857                               (nr_frags == 0));
2858         } else {
2859                 cas_write_txd(cp, ring, entry, mapping, len, ctrl | 
2860                               TX_DESC_SOF, (nr_frags == 0));
2861         }
2862         entry = TX_DESC_NEXT(ring, entry);
2863
2864         for (frag = 0; frag < nr_frags; frag++) {
2865                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2866
2867                 len = fragp->size;
2868                 mapping = pci_map_page(cp->pdev, fragp->page,
2869                                        fragp->page_offset, len,
2870                                        PCI_DMA_TODEVICE);
2871
2872                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2873                 if (unlikely(tabort)) {
2874                         void *addr;
2875
2876                         /* NOTE: len is always > tabort */
2877                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2878                                       ctrl, 0);
2879                         entry = TX_DESC_NEXT(ring, entry);
2880                         
2881                         addr = cas_page_map(fragp->page);
2882                         memcpy(tx_tiny_buf(cp, ring, entry),
2883                                addr + fragp->page_offset + len - tabort, 
2884                                tabort);
2885                         cas_page_unmap(addr);
2886                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2887                         len     = tabort;
2888                 }
2889
2890                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2891                               (frag + 1 == nr_frags));
2892                 entry = TX_DESC_NEXT(ring, entry);
2893         }
2894
2895         cp->tx_new[ring] = entry;
2896         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2897                 netif_stop_queue(dev);
2898
2899         if (netif_msg_tx_queued(cp))
2900                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2901                        "avail %d\n",
2902                        dev->name, ring, entry, skb->len, 
2903                        TX_BUFFS_AVAIL(cp, ring));
2904         writel(entry, cp->regs + REG_TX_KICKN(ring));
2905         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2906         return 0;
2907
2908
2909 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2910 {
2911         struct cas *cp = netdev_priv(dev);
2912
2913         /* this is only used as a load-balancing hint, so it doesn't
2914          * need to be SMP safe
2915          */
2916         static int ring; 
2917
2918         skb = skb_padto(skb, cp->min_frame_size);
2919         if (!skb)
2920                 return 0;
2921
2922         /* XXX: we need some higher-level QoS hooks to steer packets to
2923          *      individual queues.
2924          */
2925         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2926                 return 1;
2927         dev->trans_start = jiffies;
2928         return 0;
2929 }
2930
2931 static void cas_init_tx_dma(struct cas *cp)
2932 {
2933         u64 desc_dma = cp->block_dvma;
2934         unsigned long off;
2935         u32 val;
2936         int i;
2937
2938         /* set up tx completion writeback registers. must be 8-byte aligned */
2939 #ifdef USE_TX_COMPWB
2940         off = offsetof(struct cas_init_block, tx_compwb);
2941         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2942         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2943 #endif
2944
2945         /* enable completion writebacks, enable paced mode,
2946          * disable read pipe, and disable pre-interrupt compwbs
2947          */
2948         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | 
2949                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2950                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | 
2951                 TX_CFG_INTR_COMPWB_DIS;
2952
2953         /* write out tx ring info and tx desc bases */
2954         for (i = 0; i < MAX_TX_RINGS; i++) {
2955                 off = (unsigned long) cp->init_txds[i] - 
2956                         (unsigned long) cp->init_block;
2957
2958                 val |= CAS_TX_RINGN_BASE(i);
2959                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2960                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2961                        REG_TX_DBN_LOW(i));
2962                 /* don't zero out the kick register here as the system
2963                  * will wedge
2964                  */
2965         }
2966         writel(val, cp->regs + REG_TX_CFG);
2967
2968         /* program max burst sizes. these numbers should be different
2969          * if doing QoS.
2970          */
2971 #ifdef USE_QOS
2972         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2973         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2974         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2975         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2976 #else
2977         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2978         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2979         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2980         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2981 #endif
2982 }
2983
2984 /* Must be invoked under cp->lock. */
2985 static inline void cas_init_dma(struct cas *cp)
2986 {
2987         cas_init_tx_dma(cp);
2988         cas_init_rx_dma(cp);
2989 }
2990
2991 /* Must be invoked under cp->lock. */
2992 static u32 cas_setup_multicast(struct cas *cp)
2993 {
2994         u32 rxcfg = 0;
2995         int i;
2996         
2997         if (cp->dev->flags & IFF_PROMISC) {
2998                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2999
3000         } else if (cp->dev->flags & IFF_ALLMULTI) {
3001                 for (i=0; i < 16; i++)
3002                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
3003                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3004
3005         } else {
3006                 u16 hash_table[16];
3007                 u32 crc;
3008                 struct dev_mc_list *dmi = cp->dev->mc_list;
3009                 int i;
3010
3011                 /* use the alternate mac address registers for the
3012                  * first 15 multicast addresses
3013                  */
3014                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
3015                         if (!dmi) {
3016                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
3017                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
3018                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
3019                                 continue;
3020                         }
3021                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5], 
3022                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
3023                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3], 
3024                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
3025                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1], 
3026                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
3027                         dmi = dmi->next;
3028                 }
3029
3030                 /* use hw hash table for the next series of 
3031                  * multicast addresses
3032                  */
3033                 memset(hash_table, 0, sizeof(hash_table));
3034                 while (dmi) {
3035                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3036                         crc >>= 24;
3037                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3038                         dmi = dmi->next;
3039                 }
3040                 for (i=0; i < 16; i++)
3041                         writel(hash_table[i], cp->regs + 
3042                                REG_MAC_HASH_TABLEN(i));
3043                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3044         }
3045
3046         return rxcfg;
3047 }
3048
3049 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3050 static void cas_clear_mac_err(struct cas *cp)
3051 {
3052         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3053         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3054         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3055         writel(0, cp->regs + REG_MAC_COLL_LATE);
3056         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3057         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3058         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3059         writel(0, cp->regs + REG_MAC_LEN_ERR);
3060         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3061         writel(0, cp->regs + REG_MAC_FCS_ERR);
3062         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3063 }
3064
3065
3066 static void cas_mac_reset(struct cas *cp)
3067 {
3068         int i;
3069
3070         /* do both TX and RX reset */
3071         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3072         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3073
3074         /* wait for TX */
3075         i = STOP_TRIES;
3076         while (i-- > 0) {
3077                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3078                         break;
3079                 udelay(10);
3080         }
3081
3082         /* wait for RX */
3083         i = STOP_TRIES;
3084         while (i-- > 0) {
3085                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3086                         break;
3087                 udelay(10);
3088         }
3089
3090         if (readl(cp->regs + REG_MAC_TX_RESET) |
3091             readl(cp->regs + REG_MAC_RX_RESET))
3092                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3093                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3094                        readl(cp->regs + REG_MAC_RX_RESET),
3095                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3096 }
3097
3098
3099 /* Must be invoked under cp->lock. */
3100 static void cas_init_mac(struct cas *cp)
3101 {
3102         unsigned char *e = &cp->dev->dev_addr[0];
3103         int i;
3104 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3105         u32 rxcfg;
3106 #endif
3107         cas_mac_reset(cp);
3108
3109         /* setup core arbitration weight register */
3110         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3111
3112         /* XXX Use pci_dma_burst_advice() */
3113 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3114         /* set the infinite burst register for chips that don't have
3115          * pci issues.
3116          */
3117         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3118                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3119 #endif
3120
3121         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3122
3123         writel(0x00, cp->regs + REG_MAC_IPG0);
3124         writel(0x08, cp->regs + REG_MAC_IPG1);
3125         writel(0x04, cp->regs + REG_MAC_IPG2);
3126         
3127         /* change later for 802.3z */
3128         writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 
3129
3130         /* min frame + FCS */
3131         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3132
3133         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3134          * specify the maximum frame size to prevent RX tag errors on 
3135          * oversized frames.
3136          */
3137         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3138                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, 
3139                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), 
3140                cp->regs + REG_MAC_FRAMESIZE_MAX);
3141
3142         /* NOTE: crc_size is used as a surrogate for half-duplex. 
3143          * workaround saturn half-duplex issue by increasing preamble
3144          * size to 65 bytes.
3145          */
3146         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3147                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3148         else
3149                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3150         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3151         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3152         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3153
3154         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3155
3156         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3157         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3158         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3159         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3160         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3161
3162         /* setup mac address in perfect filter array */
3163         for (i = 0; i < 45; i++)
3164                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3165
3166         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3167         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3168         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3169
3170         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3171         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3172         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3173
3174 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3175         cp->mac_rx_cfg = cas_setup_multicast(cp);
3176 #else
3177         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3178          * a writel does not seem to be necessary because Cassini
3179          * seems to preserve the configuration when we do the reset.
3180          * If the chip is in trouble, though, it is not clear if we
3181          * can really count on this behavior. cas_set_multicast uses
3182          * spin_lock_irqsave, but we are called only in cas_init_hw and
3183          * cas_init_hw is protected by cas_lock_all, which calls
3184          * spin_lock_irq (so it doesn't need to save the flags, and
3185          * we should be OK for the writel, as that is the only 
3186          * difference).
3187          */
3188         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3189         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3190 #endif
3191         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3192         cas_clear_mac_err(cp);
3193         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3194
3195         /* Setup MAC interrupts.  We want to get all of the interesting
3196          * counter expiration events, but we do not want to hear about
3197          * normal rx/tx as the DMA engine tells us that.
3198          */
3199         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3200         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3201
3202         /* Don't enable even the PAUSE interrupts for now, we
3203          * make no use of those events other than to record them.
3204          */
3205         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3206 }
3207
3208 /* Must be invoked under cp->lock. */
3209 static void cas_init_pause_thresholds(struct cas *cp)
3210 {
3211         /* Calculate pause thresholds.  Setting the OFF threshold to the
3212          * full RX fifo size effectively disables PAUSE generation
3213          */
3214         if (cp->rx_fifo_size <= (2 * 1024)) {
3215                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3216         } else {
3217                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3218                 if (max_frame * 3 > cp->rx_fifo_size) {
3219                         cp->rx_pause_off = 7104;
3220                         cp->rx_pause_on  = 960;
3221                 } else {
3222                         int off = (cp->rx_fifo_size - (max_frame * 2));
3223                         int on = off - max_frame;
3224                         cp->rx_pause_off = off;
3225                         cp->rx_pause_on = on;
3226                 }
3227         }
3228 }
3229
3230 static int cas_vpd_match(const void __iomem *p, const char *str)
3231 {
3232         int len = strlen(str) + 1;
3233         int i;
3234         
3235         for (i = 0; i < len; i++) {
3236                 if (readb(p + i) != str[i])
3237                         return 0;
3238         }
3239         return 1;
3240 }
3241
3242
3243 /* get the mac address by reading the vpd information in the rom.
3244  * also get the phy type and determine if there's an entropy generator.
3245  * NOTE: this is a bit convoluted for the following reasons:
3246  *  1) vpd info has order-dependent mac addresses for multinic cards
3247  *  2) the only way to determine the nic order is to use the slot
3248  *     number.
3249  *  3) fiber cards don't have bridges, so their slot numbers don't
3250  *     mean anything.
3251  *  4) we don't actually know we have a fiber card until after 
3252  *     the mac addresses are parsed.
3253  */
3254 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3255                             const int offset)
3256 {
3257         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3258         void __iomem *base, *kstart;
3259         int i, len;
3260         int found = 0;
3261 #define VPD_FOUND_MAC        0x01
3262 #define VPD_FOUND_PHY        0x02
3263
3264         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3265         int mac_off  = 0;
3266
3267         /* give us access to the PROM */
3268         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3269                cp->regs + REG_BIM_LOCAL_DEV_EN);
3270