ae17b63b98b4f571dbee210f96e50496b2f4f08a
[linux-2.6.git] / drivers / net / bnx2.h
1 /* bnx2.h: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #ifndef BNX2_H
14 #define BNX2_H
15
16 #include <linux/config.h>
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20
21 #include <linux/kernel.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <asm/bitops.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #ifdef NETIF_F_HW_VLAN_TX
42 #include <linux/if_vlan.h>
43 #define BCM_VLAN 1
44 #endif
45 #ifdef NETIF_F_TSO
46 #include <net/ip.h>
47 #include <net/tcp.h>
48 #include <net/checksum.h>
49 #define BCM_TSO 1
50 #endif
51 #include <linux/workqueue.h>
52 #include <linux/crc32.h>
53 #include <linux/prefetch.h>
54
55 /* Hardware data structures and register definitions automatically
56  * generated from RTL code. Do not modify.
57  */
58
59 /*
60  *  tx_bd definition
61  */
62 struct tx_bd {
63         u32 tx_bd_haddr_hi;
64         u32 tx_bd_haddr_lo;                                   
65         u32 tx_bd_mss_nbytes;                                     
66         u32 tx_bd_vlan_tag_flags;                                      
67                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
68                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
69                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
70                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
71                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
72                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
73                 #define TX_BD_FLAGS_END                 (1<<6)
74                 #define TX_BD_FLAGS_START               (1<<7)
75                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
76                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
77                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
78                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
79
80 };
81
82
83 /*
84  *  rx_bd definition
85  */
86 struct rx_bd {
87         u32 rx_bd_haddr_hi;
88         u32 rx_bd_haddr_lo;
89         u32 rx_bd_len;
90         u32 rx_bd_flags;
91                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
92                 #define RX_BD_FLAGS_DUMMY               (1<<1)
93                 #define RX_BD_FLAGS_END                 (1<<2)
94                 #define RX_BD_FLAGS_START               (1<<3)
95
96 };
97
98
99 /*
100  *  status_block definition
101  */
102 struct status_block {
103         u32 status_attn_bits;
104                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
105                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
106                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
107                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
108                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
109                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
110                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
111                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
112                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
113                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
114                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
115                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
116                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
117                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
118                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
119                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
120                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
121                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
122                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
123                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
124                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
125                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
126                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
127                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
128                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
129                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
130                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
131                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
132                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
133
134         u32 status_attn_bits_ack;
135 #if defined(__BIG_ENDIAN)
136         u16 status_tx_quick_consumer_index0;
137         u16 status_tx_quick_consumer_index1;
138         u16 status_tx_quick_consumer_index2;
139         u16 status_tx_quick_consumer_index3;
140         u16 status_rx_quick_consumer_index0;
141         u16 status_rx_quick_consumer_index1;
142         u16 status_rx_quick_consumer_index2;
143         u16 status_rx_quick_consumer_index3;
144         u16 status_rx_quick_consumer_index4;
145         u16 status_rx_quick_consumer_index5;
146         u16 status_rx_quick_consumer_index6;
147         u16 status_rx_quick_consumer_index7;
148         u16 status_rx_quick_consumer_index8;
149         u16 status_rx_quick_consumer_index9;
150         u16 status_rx_quick_consumer_index10;
151         u16 status_rx_quick_consumer_index11;
152         u16 status_rx_quick_consumer_index12;
153         u16 status_rx_quick_consumer_index13;
154         u16 status_rx_quick_consumer_index14;
155         u16 status_rx_quick_consumer_index15;
156         u16 status_completion_producer_index;
157         u16 status_cmd_consumer_index;
158         u16 status_idx;
159         u16 status_unused;
160 #elif defined(__LITTLE_ENDIAN)
161         u16 status_tx_quick_consumer_index1;
162         u16 status_tx_quick_consumer_index0;
163         u16 status_tx_quick_consumer_index3;
164         u16 status_tx_quick_consumer_index2;
165         u16 status_rx_quick_consumer_index1;
166         u16 status_rx_quick_consumer_index0;
167         u16 status_rx_quick_consumer_index3;
168         u16 status_rx_quick_consumer_index2;
169         u16 status_rx_quick_consumer_index5;
170         u16 status_rx_quick_consumer_index4;
171         u16 status_rx_quick_consumer_index7;
172         u16 status_rx_quick_consumer_index6;
173         u16 status_rx_quick_consumer_index9;
174         u16 status_rx_quick_consumer_index8;
175         u16 status_rx_quick_consumer_index11;
176         u16 status_rx_quick_consumer_index10;
177         u16 status_rx_quick_consumer_index13;
178         u16 status_rx_quick_consumer_index12;
179         u16 status_rx_quick_consumer_index15;
180         u16 status_rx_quick_consumer_index14;
181         u16 status_cmd_consumer_index;
182         u16 status_completion_producer_index;
183         u16 status_unused;
184         u16 status_idx;
185 #endif
186 };
187
188
189 /*
190  *  statistics_block definition
191  */
192 struct statistics_block {
193         u32 stat_IfHCInOctets_hi;
194         u32 stat_IfHCInOctets_lo;
195         u32 stat_IfHCInBadOctets_hi;
196         u32 stat_IfHCInBadOctets_lo;
197         u32 stat_IfHCOutOctets_hi;
198         u32 stat_IfHCOutOctets_lo;
199         u32 stat_IfHCOutBadOctets_hi;
200         u32 stat_IfHCOutBadOctets_lo;
201         u32 stat_IfHCInUcastPkts_hi;
202         u32 stat_IfHCInUcastPkts_lo;
203         u32 stat_IfHCInMulticastPkts_hi;
204         u32 stat_IfHCInMulticastPkts_lo;
205         u32 stat_IfHCInBroadcastPkts_hi;
206         u32 stat_IfHCInBroadcastPkts_lo;
207         u32 stat_IfHCOutUcastPkts_hi;
208         u32 stat_IfHCOutUcastPkts_lo;
209         u32 stat_IfHCOutMulticastPkts_hi;
210         u32 stat_IfHCOutMulticastPkts_lo;
211         u32 stat_IfHCOutBroadcastPkts_hi;
212         u32 stat_IfHCOutBroadcastPkts_lo;
213         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
214         u32 stat_Dot3StatsCarrierSenseErrors;
215         u32 stat_Dot3StatsFCSErrors;
216         u32 stat_Dot3StatsAlignmentErrors;
217         u32 stat_Dot3StatsSingleCollisionFrames;
218         u32 stat_Dot3StatsMultipleCollisionFrames;
219         u32 stat_Dot3StatsDeferredTransmissions;
220         u32 stat_Dot3StatsExcessiveCollisions;
221         u32 stat_Dot3StatsLateCollisions;
222         u32 stat_EtherStatsCollisions;
223         u32 stat_EtherStatsFragments;
224         u32 stat_EtherStatsJabbers;
225         u32 stat_EtherStatsUndersizePkts;
226         u32 stat_EtherStatsOverrsizePkts;
227         u32 stat_EtherStatsPktsRx64Octets;
228         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
229         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
230         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
231         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
232         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
233         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
234         u32 stat_EtherStatsPktsTx64Octets;
235         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
236         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
237         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
238         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
239         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
240         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
241         u32 stat_XonPauseFramesReceived;
242         u32 stat_XoffPauseFramesReceived;
243         u32 stat_OutXonSent;
244         u32 stat_OutXoffSent;
245         u32 stat_FlowControlDone;
246         u32 stat_MacControlFramesReceived;
247         u32 stat_XoffStateEntered;
248         u32 stat_IfInFramesL2FilterDiscards;
249         u32 stat_IfInRuleCheckerDiscards;
250         u32 stat_IfInFTQDiscards;
251         u32 stat_IfInMBUFDiscards;
252         u32 stat_IfInRuleCheckerP4Hit;
253         u32 stat_CatchupInRuleCheckerDiscards;
254         u32 stat_CatchupInFTQDiscards;
255         u32 stat_CatchupInMBUFDiscards;
256         u32 stat_CatchupInRuleCheckerP4Hit;
257         u32 stat_GenStat00;
258         u32 stat_GenStat01;
259         u32 stat_GenStat02;
260         u32 stat_GenStat03;
261         u32 stat_GenStat04;
262         u32 stat_GenStat05;
263         u32 stat_GenStat06;
264         u32 stat_GenStat07;
265         u32 stat_GenStat08;
266         u32 stat_GenStat09;
267         u32 stat_GenStat10;
268         u32 stat_GenStat11;
269         u32 stat_GenStat12;
270         u32 stat_GenStat13;
271         u32 stat_GenStat14;
272         u32 stat_GenStat15;
273 };
274
275
276 /*
277  *  l2_fhdr definition
278  */
279 struct l2_fhdr {
280         u32 l2_fhdr_status;
281                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
282                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
283                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
284                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
285                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
286                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
287                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
288                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
289                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
290                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
291
292                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
293                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
294                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
295                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
296                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
297                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
298                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
299
300         u32 l2_fhdr_hash;
301 #if defined(__BIG_ENDIAN)
302         u16 l2_fhdr_pkt_len;
303         u16 l2_fhdr_vlan_tag;
304         u16 l2_fhdr_ip_xsum;
305         u16 l2_fhdr_tcp_udp_xsum;
306 #elif defined(__LITTLE_ENDIAN)
307         u16 l2_fhdr_vlan_tag;
308         u16 l2_fhdr_pkt_len;
309         u16 l2_fhdr_tcp_udp_xsum;
310         u16 l2_fhdr_ip_xsum;
311 #endif
312 };
313
314
315 /*
316  *  l2_context definition
317  */
318 #define BNX2_L2CTX_TYPE                                 0x00000000
319 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
320 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
321 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
322 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
323
324 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
325 #define BNX2_L2CTX_EST_NBD                              0x00000088
326 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
327 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
328 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
329 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
330
331 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
332 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
333 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
334 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
335 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
336 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
337 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
338 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
339 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
340 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
341
342
343 /*
344  *  l2_bd_chain_context definition
345  */
346 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
347 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
348 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
349 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
350 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
351 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
352 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
353
354 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
355 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
356 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
357 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
358 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
359 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
360
361
362 /*
363  *  pci_config_l definition
364  *  offset: 0000
365  */
366 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
367 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
368 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
369 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
370 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
371 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
372 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
373 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
374 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
375 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
376 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
377
378 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
379 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
380 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
381 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
382 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
383 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
384 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
385 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
386 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
387 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
388
389 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
390 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
391 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
392 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
393 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
394 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
395 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
396 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
397 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
398 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
399 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
400 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
401 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
402 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
403 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
404 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
405 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
406 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
407 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
408 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
409 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
410 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
411 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
412 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
413 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
414 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
415 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
416 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
417 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
418 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
419
420 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
421 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
422 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
423 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
424 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
425 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
426 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
427
428 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
429 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
430 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
431 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
432
433
434 /*
435  *  pci_reg definition
436  *  offset: 0x400
437  */
438 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
439 #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
440
441 #define BNX2_PCI_CONFIG_1                               0x00000404
442 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
443 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
444 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
445 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
446 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
447 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
448 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
449 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
450 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
451 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
452 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
453 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
454 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
455 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
456 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
457 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
458 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
459 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
460
461 #define BNX2_PCI_CONFIG_2                               0x00000408
462 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
463 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
464 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
465 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
466 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
467 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
468 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
469 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
470 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
471 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
472 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
473 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
474 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
475 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
476 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
477 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
478 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
479 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
480 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
481 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
482 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
483 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
484 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
485 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
486 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
487 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
488 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
489 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
490 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
491 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
492 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
493 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
494 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
495 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
496 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
497 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
498 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
499 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
500 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
501 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
502 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
503 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
504 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
505 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
506 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
507 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
508 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
509
510 #define BNX2_PCI_CONFIG_3                               0x0000040c
511 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
512 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
513 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
514 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
515 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
516 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
517 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
518
519 #define BNX2_PCI_PM_DATA_A                              0x00000410
520 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
521 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
522 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
523 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
524
525 #define BNX2_PCI_PM_DATA_B                              0x00000414
526 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
527 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
528 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
529 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
530
531 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
532 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
533 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
534 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
535 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
536
537 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
538 #define BNX2_PCI_VPD_INTF                               0x00000428
539 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
540
541 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
542 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
543 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
544
545 #define BNX2_PCI_VPD_DATA                               0x00000430
546 #define BNX2_PCI_ID_VAL1                                0x00000434
547 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
548 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
549
550 #define BNX2_PCI_ID_VAL2                                0x00000438
551 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
552 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
553
554 #define BNX2_PCI_ID_VAL3                                0x0000043c
555 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
556 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
557
558 #define BNX2_PCI_ID_VAL4                                0x00000440
559 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
560 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
561 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
562 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
563 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
564 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
565 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
566 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
567 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
568 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
569 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
570 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
571 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
572 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
573 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
574 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
575 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
576 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
577 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
578 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
579 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
580 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
581 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
582 #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
583 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
584 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
585 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
586 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
587 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
588 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
589
590 #define BNX2_PCI_ID_VAL5                                0x00000444
591 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
592 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
593 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
594 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
595 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
596 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
597
598 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
599 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
600 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
601 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
602 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
603
604 #define BNX2_PCI_ID_VAL6                                0x0000044c
605 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
606 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
607 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
608
609 #define BNX2_PCI_MSI_DATA                               0x00000450
610 #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
611
612 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
613 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
614
615
616 /*
617  *  misc_reg definition
618  *  offset: 0x800
619  */
620 #define BNX2_MISC_COMMAND                               0x00000800
621 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
622 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
623 #define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
624 #define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
625 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
626 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
627
628 #define BNX2_MISC_CFG                                   0x00000804
629 #define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
630 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
631 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
632 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
633 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
634 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
635 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
636 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
637 #define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
638 #define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
639 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
640 #define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
641 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
642 #define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
643 #define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
644
645 #define BNX2_MISC_ID                                    0x00000808
646 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
647 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
648 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
649 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
650
651 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
652 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
653 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
654 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
655 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
656 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
657 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
658 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
659 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
660 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
661 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
662 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
663 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
664 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
665 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
666 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
667 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
668 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
669 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
670 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
671 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
672 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
673 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
674 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
675 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
676 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
677 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
678 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
679 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
680
681 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
682 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
683 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
684 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
685 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
686 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
687 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
688 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
689 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
690 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
691 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
692 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
693 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
694 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
695 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
696 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
697 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
698 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
699 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
700 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
701 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
702 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
703 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
704 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
705 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
706 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
707 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
708 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
709 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
710
711 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
712 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
713 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
714 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
715 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
716 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
717 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
718 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
719 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
720 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
721 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
722 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
723 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
724 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
725 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
726 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
727 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
728 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
729 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
730 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
731 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
732 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
733 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
734 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
735 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
736 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
737 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
738 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
739 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
740
741 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
742 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
743 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
744 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
745 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
746 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
747 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
748 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
749 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
750 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
751 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
752 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
753 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
754 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
755 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
756 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
757 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
758 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
759 #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
760 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
761 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
762 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
763 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
764 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
765 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
766 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
767 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
768 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
769 #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
770 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
771
772 #define BNX2_MISC_GPIO                                  0x0000081c
773 #define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
774 #define BNX2_MISC_GPIO_SET                               (0xffL<<8)
775 #define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
776 #define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
777
778 #define BNX2_MISC_GPIO_INT                              0x00000820
779 #define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
780 #define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
781 #define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
782 #define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
783
784 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
785 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
786
787 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
788 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
789 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
790 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
791 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
792 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
793 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
794 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
795 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
796 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
797 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
798 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
799 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
800 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
801 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
802 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
803 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
804 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
805 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
806 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
807 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
808 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
809 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
810 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
811 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
812 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
813 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
814 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
815 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
816
817 #define BNX2_MISC_ARB_REQ0                              0x0000082c
818 #define BNX2_MISC_ARB_REQ1                              0x00000830
819 #define BNX2_MISC_ARB_REQ2                              0x00000834
820 #define BNX2_MISC_ARB_REQ3                              0x00000838
821 #define BNX2_MISC_ARB_REQ4                              0x0000083c
822 #define BNX2_MISC_ARB_FREE0                             0x00000840
823 #define BNX2_MISC_ARB_FREE1                             0x00000844
824 #define BNX2_MISC_ARB_FREE2                             0x00000848
825 #define BNX2_MISC_ARB_FREE3                             0x0000084c
826 #define BNX2_MISC_ARB_FREE4                             0x00000850
827 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
828 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
829 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
830 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
831 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
832 #define BNX2_MISC_ARB_GNT0                              0x00000868
833 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
834 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
835 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
836 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
837 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
838 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
839 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
840 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
841
842 #define BNX2_MISC_ARB_GNT1                              0x0000086c
843 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
844 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
845 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
846 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
847 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
848 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
849 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
850 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
851
852 #define BNX2_MISC_ARB_GNT2                              0x00000870
853 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
854 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
855 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
856 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
857 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
858 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
859 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
860 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
861
862 #define BNX2_MISC_ARB_GNT3                              0x00000874
863 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
864 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
865 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
866 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
867 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
868 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
869 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
870 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
871
872 #define BNX2_MISC_PRBS_CONTROL                          0x00000878
873 #define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
874 #define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
875 #define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
876 #define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
877 #define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
878 #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
879 #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
880 #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
881 #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
882
883 #define BNX2_MISC_PRBS_STATUS                           0x0000087c
884 #define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
885 #define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
886 #define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
887 #define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
888
889 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
890 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
891 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
892 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
893 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
894 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
895 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
896 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
897 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
898 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
899 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
900 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
901 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
902 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
903 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
904 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
905 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
906 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
907
908 #define BNX2_MISC_SMB_IN                                0x00000884
909 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
910 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
911 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
912 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
913 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
914 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
915 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
916 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
917 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
918 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
919
920 #define BNX2_MISC_SMB_OUT                               0x00000888
921 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
922 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
923 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
924 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
925 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
926 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
927 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
928 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
929 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
930 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
931 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
932 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
933 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
934 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
935 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
936 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
937 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
938 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
939 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
940 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
941 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
942 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
943 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
944
945 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
946 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
947
948 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
949 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
950
951 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
952 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
953
954 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
955 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
956
957 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
958 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
959
960 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
961 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
962
963 #define BNX2_MISC_PERR_ENA0                             0x000008a4
964 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
965 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
966 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
967 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
968 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
969 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
970 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
971 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
972 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
973 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
974 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
975 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
976 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
977 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
978 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
979 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
980 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
981 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
982 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
983 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
984 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
985 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
986 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
987 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
988 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
989 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
990 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
991 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
992 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
993 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
994 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
995 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
996
997 #define BNX2_MISC_PERR_ENA1                             0x000008a8
998 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
999 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1000 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1001 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1002 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1003 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1004 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1005 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1006 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1007 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1008 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1009 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1010 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1011 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1012 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1013 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1014 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1015 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1016 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1017 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1018 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1019 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1020 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1021 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1022 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1023 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1024 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1025 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1026 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1027 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1028 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1029 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1030
1031 #define BNX2_MISC_PERR_ENA2                             0x000008ac
1032 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1033 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1034 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1035 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1036 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1037 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1038 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1039 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1040 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1041
1042 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
1043 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1044 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1045
1046 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
1047 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1048 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1049
1050 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
1051 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1052
1053 #define BNX2_MISC_UNUSED0                               0x000008bc
1054
1055
1056 /*
1057  *  nvm_reg definition
1058  *  offset: 0x6400
1059  */
1060 #define BNX2_NVM_COMMAND                                0x00006400
1061 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1062 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1063 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1064 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1065 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1066 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1067 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1068 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1069 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1070 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1071 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1072
1073 #define BNX2_NVM_STATUS                                 0x00006404
1074 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1075 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1076 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1077
1078 #define BNX2_NVM_WRITE                                  0x00006408
1079 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1080 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1081 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1082 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1083 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1084 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1085 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1086 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1087
1088 #define BNX2_NVM_ADDR                                   0x0000640c
1089 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1090 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1091 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1092 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1093 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1094 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1095 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1096 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1097
1098 #define BNX2_NVM_READ                                   0x00006410
1099 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1100 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1101 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1102 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1103 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1104 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1105 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1106 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1107
1108 #define BNX2_NVM_CFG1                                   0x00006414
1109 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1110 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1111 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1112 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1113 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1114 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1115 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1116 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1117 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1118 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1119 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1120 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1121
1122 #define BNX2_NVM_CFG2                                   0x00006418
1123 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1124 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1125 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1126
1127 #define BNX2_NVM_CFG3                                   0x0000641c
1128 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1129 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1130 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1131 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1132
1133 #define BNX2_NVM_SW_ARB                                 0x00006420
1134 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1135 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
1136 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
1137 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
1138 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
1139 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
1140 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
1141 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
1142 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
1143 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
1144 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
1145 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
1146 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
1147 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
1148 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
1149 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
1150
1151 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
1152 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
1153 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
1154
1155 #define BNX2_NVM_WRITE1                                 0x00006428
1156 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
1157 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
1158 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
1159
1160
1161
1162 /*
1163  *  dma_reg definition
1164  *  offset: 0xc00
1165  */
1166 #define BNX2_DMA_COMMAND                                0x00000c00
1167 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
1168
1169 #define BNX2_DMA_STATUS                                 0x00000c04
1170 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
1171 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
1172 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
1173 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
1174 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
1175 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
1176 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
1177 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
1178 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
1179 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
1180 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
1181
1182 #define BNX2_DMA_CONFIG                                 0x00000c08
1183 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
1184 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
1185 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
1186 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
1187 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
1188 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
1189 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
1190 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
1191 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
1192 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
1193 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
1194 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
1195 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
1196 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
1197 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
1198 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
1199 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
1200 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
1201 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
1202
1203 #define BNX2_DMA_BLACKOUT                               0x00000c0c
1204 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
1205 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
1206 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
1207
1208 #define BNX2_DMA_RCHAN_STAT                             0x00000c30
1209 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
1210 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
1211 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
1212 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
1213 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
1214 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
1215 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
1216 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
1217 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
1218 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
1219 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
1220 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
1221 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
1222 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
1223 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
1224 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
1225
1226 #define BNX2_DMA_WCHAN_STAT                             0x00000c34
1227 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
1228 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
1229 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
1230 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
1231 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
1232 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
1233 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
1234 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
1235 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
1236 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
1237 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
1238 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
1239 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
1240 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
1241 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
1242 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
1243
1244 #define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
1245 #define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
1246 #define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
1247 #define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
1248 #define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
1249 #define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
1250 #define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
1251 #define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
1252 #define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
1253
1254 #define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
1255 #define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
1256 #define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
1257 #define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
1258 #define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
1259 #define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
1260 #define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
1261 #define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
1262 #define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
1263
1264 #define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
1265 #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
1266
1267 #define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
1268 #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
1269
1270 #define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
1271 #define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
1272 #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
1273 #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
1274 #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
1275
1276 #define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
1277 #define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
1278 #define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
1279 #define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
1280 #define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
1281 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
1282 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
1283 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
1284 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
1285 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
1286 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
1287 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
1288 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
1289 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
1290 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
1291 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
1292 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
1293 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
1294 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
1295 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
1296 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
1297 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
1298 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
1299
1300 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
1301 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
1302
1303 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
1304 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
1305 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
1306 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
1307 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
1308
1309 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
1310 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
1311 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
1312 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
1313 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
1314 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
1315 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
1316 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
1317 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
1318 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
1319 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
1320 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
1321 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
1322 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
1323 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
1324 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
1325 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
1326 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
1327 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
1328 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
1329 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
1330 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
1331 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
1332 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
1333 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
1334
1335 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
1336 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
1337 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
1338 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
1339 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
1340 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
1341 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
1342 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
1343 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
1344
1345 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
1346 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
1347 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
1348 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
1349 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
1350 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
1351
1352 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
1353 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
1354 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
1355 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
1356 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
1357 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
1358 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
1359
1360 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
1361 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
1362 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
1363 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
1364 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
1365 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
1366 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
1367
1368 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
1369
1370
1371 /*
1372  *  context_reg definition
1373  *  offset: 0x1000
1374  */
1375 #define BNX2_CTX_COMMAND                                0x00001000
1376 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
1377
1378 #define BNX2_CTX_STATUS                                 0x00001004
1379 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
1380 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
1381 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
1382 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
1383 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
1384
1385 #define BNX2_CTX_VIRT_ADDR                              0x00001008
1386 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
1387
1388 #define BNX2_CTX_PAGE_TBL                               0x0000100c
1389 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
1390
1391 #define BNX2_CTX_DATA_ADR                               0x00001010
1392 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
1393
1394 #define BNX2_CTX_DATA                                   0x00001014
1395 #define BNX2_CTX_LOCK                                   0x00001018
1396 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
1397 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
1398 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
1399 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
1400 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
1401 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
1402 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
1403 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
1404 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
1405 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
1406 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
1407 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
1408 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
1409 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
1410
1411 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
1412 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
1413 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
1414 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
1415 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
1416 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
1417
1418 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
1419 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
1420 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
1421
1422 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
1423 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
1424 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
1425 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
1426
1427 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
1428 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
1429 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
1430 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
1431 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
1432 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
1433 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
1434 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
1435
1436
1437 /*
1438  *  emac_reg definition
1439  *  offset: 0x1400
1440  */
1441 #define BNX2_EMAC_MODE                                  0x00001400
1442 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
1443 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
1444 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
1445 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
1446 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
1447 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
1448 #define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
1449 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
1450 #define BNX2_EMAC_MODE_25G                               (1L<<5)
1451 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
1452 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
1453 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
1454 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
1455 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
1456 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
1457 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
1458 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
1459
1460 #define BNX2_EMAC_STATUS                                0x00001404
1461 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
1462 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
1463 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
1464 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
1465 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
1466 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
1467
1468 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
1469 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
1470 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
1471 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
1472 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
1473
1474 #define BNX2_EMAC_LED                                   0x0000140c
1475 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
1476 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
1477 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
1478 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
1479 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
1480 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
1481 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
1482 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
1483 #define BNX2_EMAC_LED_100MB                              (1L<<8)
1484 #define BNX2_EMAC_LED_10MB                               (1L<<9)
1485 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
1486 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
1487 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
1488
1489 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
1490 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
1491 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
1492 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
1493 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
1494 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
1495 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
1496 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
1497 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
1498 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
1499 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
1500 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
1501 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
1502 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
1503 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
1504 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
1505 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
1506 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
1507 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
1508 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
1509 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
1510 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
1511 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
1512 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
1513 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
1514 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
1515 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
1516 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
1517 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
1518 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
1519 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
1520 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
1521 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
1522 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
1523
1524 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
1525 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
1526 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
1527
1528 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
1529 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
1530 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
1531 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
1532 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
1533 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
1534 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
1535 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
1536 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
1537 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
1538 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
1539 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
1540 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
1541 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
1542 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
1543 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
1544 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
1545
1546 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
1547 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
1548 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
1549
1550 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
1551 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
1552 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
1553 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
1554 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
1555 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
1556 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
1557 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
1558 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
1559 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
1560 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
1561 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
1562
1563 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
1564 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
1565 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
1566
1567 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
1568 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
1569 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
1570 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
1571 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
1572 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
1573 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
1574 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
1575 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
1576
1577 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
1578 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
1579
1580 #define BNX2_EMAC_TX_MODE                               0x000014bc
1581 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
1582 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
1583 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
1584 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
1585 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
1586 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
1587
1588 #define BNX2_EMAC_TX_STATUS                             0x000014c0
1589 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
1590 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
1591 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
1592 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
1593 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
1594
1595 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
1596 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
1597 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
1598 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
1599
1600 #define BNX2_EMAC_RX_MODE                               0x000014c8
1601 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
1602 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
1603 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
1604 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
1605 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
1606 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
1607 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
1608 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
1609 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
1610 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
1611 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
1612 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
1613
1614 #define BNX2_EMAC_RX_STATUS                             0x000014cc
1615 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
1616 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
1617 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
1618
1619 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
1620 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
1621 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
1622 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
1623 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
1624 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
1625 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
1626 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
1627 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
1628 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
1629 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
1630 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
1631 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
1632 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
1633 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
1634 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
1635 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
1636 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
1637 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
1638 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
1639 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
1640 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
1641 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
1642 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
1643 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
1644 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
1645 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
1646 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
1647 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
1648 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
1649 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
1650 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
1651 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
1652 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
1653 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
1654 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
1655 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
1656 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
1657 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
1658 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
1659 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
1660 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
1661
1662 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
1663 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
1664 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
1665 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
1666 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
1667 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
1668 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
1669 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
1670 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
1671 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
1672 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
1673 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
1674 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
1675 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
1676 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
1677 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
1678 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
1679 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
1680 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
1681 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
1682 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
1683 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
1684 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
1685 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
1686 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
1687 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
1688 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
1689 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
1690
1691 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
1692 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
1693 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
1694
1695 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
1696 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
1697 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
1698 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
1699 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
1700 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
1701 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
1702 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
1703 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
1704 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
1705 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
1706 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
1707 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
1708 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
1709 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
1710 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
1711 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
1712 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
1713 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
1714 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
1715 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
1716 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
1717 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
1718 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
1719 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
1720 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
1721 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
1722 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
1723 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
1724 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
1725 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
1726 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
1727 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
1728 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
1729 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
1730 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
1731 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
1732 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
1733 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
1734 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
1735 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
1736 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
1737 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
1738 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
1739 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
1740 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
1741 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
1742 #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
1743 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
1744 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
1745
1746 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
1747 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
1748 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
1749 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
1750 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
1751 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
1752 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
1753 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
1754 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
1755 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
1756 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
1757 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
1758 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
1759 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
1760 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
1761 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
1762 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
1763 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
1764 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
1765 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
1766 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
1767 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
1768 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
1769 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
1770 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
1771 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
1772 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
1773
1774 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
1775 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
1776 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
1777 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
1778 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
1779 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
1780 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
1781 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
1782 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
1783 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
1784 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
1785 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
1786 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
1787 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
1788 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
1789 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
1790 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
1791 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
1792 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
1793 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
1794 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
1795 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
1796 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
1797 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
1798 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
1799 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
1800 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
1801 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
1802 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
1803 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
1804 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
1805 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
1806 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
1807 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
1808 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
1809 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
1810 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
1811 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
1812 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
1813 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
1814 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
1815 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
1816 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
1817 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
1818 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
1819 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
1820 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
1821 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
1822 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
1823 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
1824 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
1825 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
1826 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
1827 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
1828 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
1829 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
1830 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
1831 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
1832 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
1833 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
1834 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
1835 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
1836 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
1837 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
1838 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
1839 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
1840 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
1841
1842 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
1843 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
1844 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
1845 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
1846 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
1847
1848 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
1849 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
1850 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
1851 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
1852 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
1853 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
1854 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
1855 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
1856 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
1857 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
1858 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
1859 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
1860 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
1861 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
1862 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
1863 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
1864 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
1865 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
1866 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
1867 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
1868 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
1869 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
1870 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
1871 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
1872 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
1873 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
1874 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
1875 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
1876 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
1877
1878 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
1879 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
1880 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
1881 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
1882 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
1883 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
1884 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
1885 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
1886 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
1887 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
1888 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
1889 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
1890 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
1891 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
1892 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
1893 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
1894 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
1895 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
1896 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
1897 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
1898 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
1899 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
1900 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
1901 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
1902 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
1903 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
1904 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
1905 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
1906
1907 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
1908 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
1909 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
1910 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
1911 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
1912 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
1913 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
1914 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
1915 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
1916 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
1917 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
1918 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
1919 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
1920 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
1921 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
1922 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
1923 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
1924 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
1925 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
1926 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
1927 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
1928 #define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
1929 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
1930
1931
1932 /*
1933  *  rpm_reg definition
1934  *  offset: 0x1800
1935  */
1936 #define BNX2_RPM_COMMAND                                0x00001800
1937 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
1938 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
1939
1940 #define BNX2_RPM_STATUS                                 0x00001804
1941 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
1942 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
1943
1944 #define BNX2_RPM_CONFIG                                 0x00001808
1945 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
1946 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
1947 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
1948 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
1949 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
1950 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
1951
1952 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
1953 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
1954
1955 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
1956 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
1957
1958 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
1959 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
1960
1961 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
1962 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
1963
1964 #define BNX2_RPM_SORT_USER0                             0x00001820
1965 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
1966 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
1967 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
1968 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
1969 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
1970 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
1971 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
1972 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
1973
1974 #define BNX2_RPM_SORT_USER1                             0x00001824
1975 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
1976 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
1977 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
1978 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
1979 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
1980 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
1981 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
1982 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
1983
1984 #define BNX2_RPM_SORT_USER2                             0x00001828
1985 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
1986 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
1987 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
1988 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
1989 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
1990 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
1991 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
1992 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
1993
1994 #define BNX2_RPM_SORT_USER3                             0x0000182c
1995 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
1996 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
1997 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
1998 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
1999 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
2000 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
2001 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
2002 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
2003
2004 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
2005 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
2006 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
2007 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
2008 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
2009 #define BNX2_RPM_STAT_AC0                               0x00001880
2010 #define BNX2_RPM_STAT_AC1                               0x00001884
2011 #define BNX2_RPM_STAT_AC2                               0x00001888
2012 #define BNX2_RPM_STAT_AC3                               0x0000188c
2013 #define BNX2_RPM_STAT_AC4                               0x00001890
2014 #define BNX2_RPM_RC_CNTL_0                              0x00001900
2015 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
2016 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
2017 #define BNX2_RPM_RC_CNTL_0_PRIORITY                      (1L<<11)
2018 #define BNX2_RPM_RC_CNTL_0_P4                            (1L<<12)
2019 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE                      (0x7L<<13)
2020 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START                (0L<<13)
2021 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                   (1L<<13)
2022 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
2023 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
2024 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
2025 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
2026 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
2027 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
2028 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
2029 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
2030 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
2031 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
2032 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
2033 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
2034 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
2035 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
2036 #define BNX2_RPM_RC_CNTL_0_P2                            (1L<<28)
2037 #define BNX2_RPM_RC_CNTL_0_P3                            (1L<<29)
2038 #define BNX2_RPM_RC_CNTL_0_NBIT                          (1L<<30)
2039
2040 #define BNX2_RPM_RC_VALUE_MASK_0                        0x00001904
2041 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE                   (0xffffL<<0)
2042 #define BNX2_RPM_RC_VALUE_MASK_0_MASK                    (0xffffL<<16)
2043
2044 #define BNX2_RPM_RC_CNTL_1                              0x00001908
2045 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
2046 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
2047
2048 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
2049 #define BNX2_RPM_RC_CNTL_2                              0x00001910
2050 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
2051 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
2052
2053 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
2054 #define BNX2_RPM_RC_CNTL_3                              0x00001918
2055 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
2056 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
2057
2058 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
2059 #define BNX2_RPM_RC_CNTL_4                              0x00001920
2060 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
2061 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
2062
2063 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
2064 #define BNX2_RPM_RC_CNTL_5                              0x00001928
2065 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
2066 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
2067
2068 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
2069 #define BNX2_RPM_RC_CNTL_6                              0x00001930
2070 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
2071 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
2072
2073 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
2074 #define BNX2_RPM_RC_CNTL_7                              0x00001938
2075 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
2076 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
2077
2078 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
2079 #define BNX2_RPM_RC_CNTL_8                              0x00001940
2080 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
2081 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
2082
2083 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
2084 #define BNX2_RPM_RC_CNTL_9                              0x00001948
2085 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
2086 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
2087
2088 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
2089 #define BNX2_RPM_RC_CNTL_10                             0x00001950
2090 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
2091 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
2092
2093 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
2094 #define BNX2_RPM_RC_CNTL_11                             0x00001958
2095 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
2096 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
2097
2098 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
2099 #define BNX2_RPM_RC_CNTL_12                             0x00001960
2100 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
2101 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
2102
2103 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
2104 #define BNX2_RPM_RC_CNTL_13                             0x00001968
2105 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
2106 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
2107
2108 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
2109 #define BNX2_RPM_RC_CNTL_14                             0x00001970
2110 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
2111 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
2112
2113 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
2114 #define BNX2_RPM_RC_CNTL_15                             0x00001978
2115 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
2116 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
2117
2118 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
2119 #define BNX2_RPM_RC_CONFIG                              0x00001980
2120 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
2121 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
2122
2123 #define BNX2_RPM_DEBUG0                                 0x00001984
2124 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
2125 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                  (1L<<16)
2126 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                   (1L<<17)
2127 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                   (1L<<18)
2128 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                    (1L<<19)
2129 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                    (1L<<20)
2130 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR              (1L<<21)
2131 #define BNX2_RPM_DEBUG0_LLC_SNAP                         (1L<<22)
2132 #define BNX2_RPM_DEBUG0_FM_STARTED                       (1L<<23)
2133 #define BNX2_RPM_DEBUG0_DONE                             (1L<<24)
2134 #define BNX2_RPM_DEBUG0_WAIT_4_DONE                      (1L<<25)
2135 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                  (1L<<26)
2136 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM              (1L<<27)
2137 #define BNX2_RPM_DEBUG0_IGNORE_VLAN                      (1L<<28)
2138 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                    (1L<<31)
2139
2140 #define BNX2_RPM_DEBUG1                                 0x00001988
2141 #define BNX2_RPM_DEBUG1_FSM_CUR_ST                       (0xffffL<<0)
2142 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                  (0L<<0)
2143 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL          (1L<<0)
2144 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC        (2L<<0)
2145 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP           (4L<<0)
2146 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP           (8L<<0)
2147 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START              (16L<<0)
2148 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                    (32L<<0)
2149 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                   (64L<<0)
2150 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                   (128L<<0)
2151 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                    (256L<<0)
2152 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                   (512L<<0)
2153 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD           (1024L<<0)
2154 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                  (2048L<<0)
2155 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY             (0x2000L<<0)
2156 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT          (0x4000L<<0)
2157 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT          (0x8000L<<0)
2158 #define BNX2_RPM_DEBUG1_HDR_BCNT                         (0x7ffL<<16)
2159 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                  (1L<<28)
2160 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                  (1L<<29)
2161 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                  (1L<<30)
2162 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                     (1L<<31)
2163
2164 #define BNX2_RPM_DEBUG2                                 0x0000198c
2165 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC                      (0xffffL<<0)
2166 #define BNX2_RPM_DEBUG2_IP_BCNT                          (0xffL<<16)
2167 #define BNX2_RPM_DEBUG2_THIS_CMD_M4                      (1L<<24)
2168 #define BNX2_RPM_DEBUG2_THIS_CMD_M3                      (1L<<25)
2169 #define BNX2_RPM_DEBUG2_THIS_CMD_M2                      (1L<<26)
2170 #define BNX2_RPM_DEBUG2_THIS_CMD_M1                      (1L<<27)
2171 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY                      (1L<<28)
2172 #define BNX2_RPM_DEBUG2_FM_DISCARD                       (1L<<29)
2173 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2               (1L<<30)
2174 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1               (1L<<31)
2175
2176 #define BNX2_RPM_DEBUG3                                 0x00001990
2177 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                   (0x1ffL<<0)
2178 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT             (1L<<9)
2179 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT             (1L<<10)
2180 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT              (1L<<11)
2181 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ                (1L<<12)
2182 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ               (1L<<13)
2183 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL               (1L<<14)
2184 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP                (1L<<15)
2185 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT               (0xfL<<16)
2186 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL             (1L<<21)
2187 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD                     (1L<<22)
2188 #define BNX2_RPM_DEBUG3_DROP_NXT                         (1L<<23)
2189 #define BNX2_RPM_DEBUG3_FTQ_FSM                          (0x3L<<24)
2190 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                     (0x0L<<24)
2191 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                 (0x1L<<24)
2192 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                (0x2L<<24)
2193 #define BNX2_RPM_DEBUG3_MBWRITE_FSM                      (0x3L<<26)
2194 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF             (0x0L<<26)
2195 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF             (0x1L<<26)
2196 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA             (0x2L<<26)
2197 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA            (0x3L<<26)
2198 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF             (0x4L<<26)
2199 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK          (0x5L<<26)
2200 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
2201 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                 (0x7L<<26)
2202 #define BNX2_RPM_DEBUG3_MBFREE_FSM                       (1L<<29)
2203 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                  (0L<<29)
2204 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK              (1L<<29)
2205 #define BNX2_RPM_DEBUG3_MBALLOC_FSM                      (1L<<30)
2206 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF              (0x0L<<30)
2207 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF             (0x1L<<30)
2208 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                  (1L<<31)
2209
2210 #define BNX2_RPM_DEBUG4                                 0x00001994
2211 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER                (0x1ffffffL<<0)
2212 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                  (0x7L<<25)
2213 #define BNX2_RPM_DEBUG4_MBWRITE_FSM                      (0x7L<<28)
2214 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY                      (1L<<31)
2215
2216 #define BNX2_RPM_DEBUG5                                 0x00001998
2217 #define BNX2_RPM_DEBUG5_RDROP_WPTR                       (0x1fL<<0)
2218 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                  (0x1fL<<5)
2219 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                    (0x1fL<<10)
2220 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                    (0x1fL<<15)
2221 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                 (1L<<20)
2222 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                   (1L<<21)
2223 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
2224 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT             (1L<<23)
2225 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                  (1L<<24)
2226 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL            (1L<<25)
2227 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                 (1L<<26)
2228 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                 (1L<<27)
2229 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                 (1L<<28)
2230 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY               (1L<<29)
2231 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                   (1L<<30)
2232 #define BNX2_RPM_DEBUG5_HOLDREG_RD                       (1L<<31)
2233
2234 #define BNX2_RPM_DEBUG6                                 0x0000199c
2235 #define BNX2_RPM_DEBUG6_ACPI_VEC                         (0xffffL<<0)
2236 #define BNX2_RPM_DEBUG6_VEC                              (0xffffL<<16)
2237
2238 #define BNX2_RPM_DEBUG7                                 0x000019a0
2239 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC                (0xffffffffL<<0)
2240
2241 #define BNX2_RPM_DEBUG8                                 0x000019a4
2242 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM                      (0xfL<<0)
2243 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                 (0L<<0)
2244 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR          (1L<<0)
2245 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR          (2L<<0)
2246 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR          (3L<<0)
2247 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF       (4L<<0)
2248 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA              (5L<<0)
2249 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR              (6L<<0)
2250 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR              (7L<<0)
2251 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR              (8L<<0)
2252 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR              (9L<<0)
2253 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF           (10L<<0)
2254 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0                    (1L<<4)
2255 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA               (1L<<5)
2256 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT              (1L<<6)
2257 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3                (1L<<7)
2258 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2                (1L<<8)
2259 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES             (1L<<9)
2260 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES             (1L<<10)
2261 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES            (1L<<11)
2262 #define BNX2_RPM_DEBUG8_EOF_DET                          (1L<<12)
2263 #define BNX2_RPM_DEBUG8_SOF_DET                          (1L<<13)
2264 #define BNX2_RPM_DEBUG8_WAIT_4_SOF                       (1L<<14)
2265 #define BNX2_RPM_DEBUG8_ALL_DONE                         (1L<<15)
2266 #define BNX2_RPM_DEBUG8_THBUF_ADDR                       (0x7fL<<16)
2267 #define BNX2_RPM_DEBUG8_BYTE_CTR                         (0xffL<<24)
2268
2269 #define BNX2_RPM_DEBUG9                                 0x000019a8
2270 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                    (0x7L<<0)
2271 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                     (1L<<3)
2272 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                  (0x7L<<4)
2273 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED         (1L<<28)
2274 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
2275 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
2276 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
2277
2278 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
2279 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
2280 #define BNX2_RPM_ACPI_DBG_BUF_W02                       0x000019c8
2281 #define BNX2_RPM_ACPI_DBG_BUF_W03                       0x000019cc
2282 #define BNX2_RPM_ACPI_DBG_BUF_W10                       0x000019d0
2283 #define BNX2_RPM_ACPI_DBG_BUF_W11                       0x000019d4
2284 #define BNX2_RPM_ACPI_DBG_BUF_W12                       0x000019d8
2285 #define BNX2_RPM_ACPI_DBG_BUF_W13                       0x000019dc
2286 #define BNX2_RPM_ACPI_DBG_BUF_W20                       0x000019e0
2287 #define BNX2_RPM_ACPI_DBG_BUF_W21                       0x000019e4
2288 #define BNX2_RPM_ACPI_DBG_BUF_W22                       0x000019e8
2289 #define BNX2_RPM_ACPI_DBG_BUF_W23                       0x000019ec
2290 #define BNX2_RPM_ACPI_DBG_BUF_W30                       0x000019f0
2291 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
2292 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
2293 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
2294
2295
2296 /*
2297  *  rbuf_reg definition
2298  *  offset: 0x200000
2299  */
2300 #define BNX2_RBUF_COMMAND                               0x00200000
2301 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
2302 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
2303 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
2304 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
2305 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
2306
2307 #define BNX2_RBUF_STATUS1                               0x00200004
2308 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
2309
2310 #define BNX2_RBUF_STATUS2                               0x00200008
2311 #define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
2312 #define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
2313
2314 #define BNX2_RBUF_CONFIG                                0x0020000c
2315 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
2316 #define BNX2_RBUF_CONFIG_XON_TRIP                        (0x3ffL<<16)
2317
2318 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
2319 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
2320
2321 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
2322 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
2323 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
2324 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
2325
2326 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
2327 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
2328 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
2329 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
2330
2331 #define BNX2_RBUF_CONFIG2                               0x0020001c
2332 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
2333 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                  (0x3ffL<<16)
2334
2335 #define BNX2_RBUF_CONFIG3                               0x00200020
2336 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                   (0x3ffL<<0)
2337 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                   (0x3ffL<<16)
2338
2339 #define BNX2_RBUF_PKT_DATA                              0x00208000
2340 #define BNX2_RBUF_CLIST_DATA                            0x00210000
2341 #define BNX2_RBUF_BUF_DATA                              0x00220000
2342
2343
2344 /*
2345  *  rv2p_reg definition
2346  *  offset: 0x2800
2347  */
2348 #define BNX2_RV2P_COMMAND                               0x00002800
2349 #define BNX2_RV2P_COMMAND_ENABLED                        (1L<<0)
2350 #define BNX2_RV2P_COMMAND_PROC1_INTRPT                   (1L<<1)
2351 #define BNX2_RV2P_COMMAND_PROC2_INTRPT                   (1L<<2)
2352 #define BNX2_RV2P_COMMAND_ABORT0                         (1L<<4)
2353 #define BNX2_RV2P_COMMAND_ABORT1                         (1L<<5)
2354 #define BNX2_RV2P_COMMAND_ABORT2                         (1L<<6)
2355 #define BNX2_RV2P_COMMAND_ABORT3                         (1L<<7)
2356 #define BNX2_RV2P_COMMAND_ABORT4                         (1L<<8)
2357 #define BNX2_RV2P_COMMAND_ABORT5                         (1L<<9)
2358 #define BNX2_RV2P_COMMAND_PROC1_RESET                    (1L<<16)
2359 #define BNX2_RV2P_COMMAND_PROC2_RESET                    (1L<<17)
2360 #define BNX2_RV2P_COMMAND_CTXIF_RESET                    (1L<<18)
2361
2362 #define BNX2_RV2P_STATUS                                0x00002804
2363 #define BNX2_RV2P_STATUS_ALWAYS_0                        (1L<<0)
2364 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT              (1L<<8)
2365 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT              (1L<<9)
2366 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT              (1L<<10)
2367 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT              (1L<<11)
2368 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT              (1L<<12)
2369 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT              (1L<<13)
2370
2371 #define BNX2_RV2P_CONFIG                                0x00002808
2372 #define BNX2_RV2P_CONFIG_STALL_PROC1                     (1L<<0)
2373 #define BNX2_RV2P_CONFIG_STALL_PROC2                     (1L<<1)
2374 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0           (1L<<8)
2375 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1           (1L<<9)
2376 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2           (1L<<10)
2377 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3           (1L<<11)
2378 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4           (1L<<12)
2379 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5           (1L<<13)
2380 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0           (1L<<16)
2381 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1           (1L<<17)
2382 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2           (1L<<18)
2383 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3           (1L<<19)
2384 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4           (1L<<20)
2385 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5           (1L<<21)
2386 #define BNX2_RV2P_CONFIG_PAGE_SIZE                       (0xfL<<24)
2387 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256                   (0L<<24)
2388 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512                   (1L<<24)
2389 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                    (2L<<24)
2390 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                    (3L<<24)
2391 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                    (4L<<24)
2392 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                    (5L<<24)
2393 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                   (6L<<24)
2394 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                   (7L<<24)
2395 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                   (8L<<24)
2396 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                  (9L<<24)
2397 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                  (10L<<24)
2398 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                  (11L<<24)
2399 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                    (12L<<24)
2400
2401 #define BNX2_RV2P_GEN_BFR_ADDR_0                        0x00002810
2402 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                   (0xffffL<<16)
2403
2404 #define BNX2_RV2P_GEN_BFR_ADDR_1                        0x00002814
2405 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                   (0xffffL<<16)
2406
2407 #define BNX2_RV2P_GEN_BFR_ADDR_2                        0x00002818
2408 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                   (0xffffL<<16)
2409
2410 #define BNX2_RV2P_GEN_BFR_ADDR_3                        0x0000281c
2411 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                   (0xffffL<<16)
2412
2413 #define BNX2_RV2P_INSTR_HIGH                            0x00002830
2414 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
2415
2416 #define BNX2_RV2P_INSTR_LOW                             0x00002834
2417 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
2418 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
2419 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
2420
2421 #define BNX2_RV2P_PROC2_ADDR_CMD                        0x0000283c
2422 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD                     (0x3ffL<<0)
2423 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                    (1L<<31)
2424
2425 #define BNX2_RV2P_PROC1_GRC_DEBUG                       0x00002840
2426 #define BNX2_RV2P_PROC2_GRC_DEBUG                       0x00002844
2427 #define BNX2_RV2P_GRC_PROC_DEBUG                        0x00002848
2428 #define BNX2_RV2P_DEBUG_VECT_PEEK                       0x0000284c
2429 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
2430 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
2431 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
2432 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
2433 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
2434 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
2435
2436 #define BNX2_RV2P_PFTQ_DATA                             0x00002b40
2437 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
2438 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
2439 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
2440 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                      (0L<<10)
2441 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                      (1L<<10)
2442 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET                     (1L<<25)
2443 #define BNX2_RV2P_PFTQ_CMD_RD_DATA                       (1L<<26)
2444 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2445 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA                      (1L<<28)
2446 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2447 #define BNX2_RV2P_PFTQ_CMD_POP                           (1L<<30)
2448 #define BNX2_RV2P_PFTQ_CMD_BUSY                          (1L<<31)
2449
2450 #define BNX2_RV2P_PFTQ_CTL                              0x00002b7c
2451 #define BNX2_RV2P_PFTQ_CTL_INTERVENE                     (1L<<0)
2452 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW                      (1L<<1)
2453 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2454 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2455 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2456
2457 #define BNX2_RV2P_TFTQ_DATA                             0x00002b80
2458 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
2459 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
2460 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
2461 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                      (0L<<10)
2462 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                      (1L<<10)
2463 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET                     (1L<<25)
2464 #define BNX2_RV2P_TFTQ_CMD_RD_DATA                       (1L<<26)
2465 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2466 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA                      (1L<<28)
2467 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2468 #define BNX2_RV2P_TFTQ_CMD_POP                           (1L<<30)
2469 #define BNX2_RV2P_TFTQ_CMD_BUSY                          (1L<<31)
2470
2471 #define BNX2_RV2P_TFTQ_CTL                              0x00002bbc
2472 #define BNX2_RV2P_TFTQ_CTL_INTERVENE                     (1L<<0)
2473 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW                      (1L<<1)
2474 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2475 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2476 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2477
2478 #define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
2479 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
2480 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
2481 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
2482 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                      (0L<<10)
2483 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                      (1L<<10)
2484 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET                     (1L<<25)
2485 #define BNX2_RV2P_MFTQ_CMD_RD_DATA                       (1L<<26)
2486 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2487 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA                      (1L<<28)
2488 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2489 #define BNX2_RV2P_MFTQ_CMD_POP                           (1L<<30)
2490 #define BNX2_RV2P_MFTQ_CMD_BUSY                          (1L<<31)
2491
2492 #define BNX2_RV2P_MFTQ_CTL                              0x00002bfc
2493 #define BNX2_RV2P_MFTQ_CTL_INTERVENE                     (1L<<0)
2494 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW                      (1L<<1)
2495 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2496 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2497 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2498
2499
2500
2501 /*
2502  *  mq_reg definition
2503  *  offset: 0x3c00
2504  */
2505 #define BNX2_MQ_COMMAND                                 0x00003c00
2506 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
2507 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
2508 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
2509 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
2510
2511 #define BNX2_MQ_STATUS                                  0x00003c04
2512 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
2513 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
2514 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
2515
2516 #define BNX2_MQ_CONFIG                                  0x00003c08
2517 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
2518 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
2519 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
2520 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
2521 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
2522 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K               (2L<<4)
2523 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K               (3L<<4)
2524 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K               (4L<<4)
2525 #define BNX2_MQ_CONFIG_MAX_DEPTH                         (0x7fL<<8)
2526 #define BNX2_MQ_CONFIG_CUR_DEPTH                         (0x7fL<<20)
2527
2528 #define BNX2_MQ_ENQUEUE1                                0x00003c0c
2529 #define BNX2_MQ_ENQUEUE1_OFFSET                          (0x3fL<<2)
2530 #define BNX2_MQ_ENQUEUE1_CID                             (0x3fffL<<8)
2531 #define BNX2_MQ_ENQUEUE1_BYTE_MASK                       (0xfL<<24)
2532 #define BNX2_MQ_ENQUEUE1_KNL_MODE                        (1L<<28)
2533
2534 #define BNX2_MQ_ENQUEUE2                                0x00003c10
2535 #define BNX2_MQ_BAD_WR_ADDR                             0x00003c14
2536 #define BNX2_MQ_BAD_RD_ADDR                             0x00003c18
2537 #define BNX2_MQ_KNL_BYP_WIND_START                      0x00003c1c
2538 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE                 (0xfffffL<<12)
2539
2540 #define BNX2_MQ_KNL_WIND_END                            0x00003c20
2541 #define BNX2_MQ_KNL_WIND_END_VALUE                       (0xffffffL<<8)
2542
2543 #define BNX2_MQ_KNL_WRITE_MASK1                         0x00003c24
2544 #define BNX2_MQ_KNL_TX_MASK1                            0x00003c28
2545 #define BNX2_MQ_KNL_CMD_MASK1                           0x00003c2c
2546 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                  0x00003c30
2547 #define BNX2_MQ_KNL_RX_V2P_MASK1                        0x00003c34
2548 #define BNX2_MQ_KNL_WRITE_MASK2                         0x00003c38
2549 #define BNX2_MQ_KNL_TX_MASK2                            0x00003c3c
2550 #define BNX2_MQ_KNL_CMD_MASK2                           0x00003c40
2551 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                  0x00003c44
2552 #define BNX2_MQ_KNL_RX_V2P_MASK2                        0x00003c48
2553 #define BNX2_MQ_KNL_BYP_WRITE_MASK1                     0x00003c4c
2554 #define BNX2_MQ_KNL_BYP_TX_MASK1                        0x00003c50
2555 #define BNX2_MQ_KNL_BYP_CMD_MASK1                       0x00003c54
2556 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1              0x00003c58
2557 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                    0x00003c5c
2558 #define BNX2_MQ_KNL_BYP_WRITE_MASK2                     0x00003c60
2559 #define BNX2_MQ_KNL_BYP_TX_MASK2                        0x00003c64
2560 #define BNX2_MQ_KNL_BYP_CMD_MASK2                       0x00003c68
2561 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2              0x00003c6c
2562 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                    0x00003c70
2563 #define BNX2_MQ_MEM_WR_ADDR                             0x00003c74
2564 #define BNX2_MQ_MEM_WR_ADDR_VALUE                        (0x3fL<<0)
2565
2566 #define BNX2_MQ_MEM_WR_DATA0                            0x00003c78
2567 #define BNX2_MQ_MEM_WR_DATA0_VALUE                       (0xffffffffL<<0)
2568
2569 #define BNX2_MQ_MEM_WR_DATA1                            0x00003c7c
2570 #define BNX2_MQ_MEM_WR_DATA1_VALUE                       (0xffffffffL<<0)
2571
2572 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
2573 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
2574
2575 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
2576 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
2577
2578 #define BNX2_MQ_MEM_RD_DATA0                            0x00003c88
2579 #define BNX2_MQ_MEM_RD_DATA0_VALUE                       (0xffffffffL<<0)
2580
2581 #define BNX2_MQ_MEM_RD_DATA1                            0x00003c8c
2582 #define BNX2_MQ_MEM_RD_DATA1_VALUE                       (0xffffffffL<<0)
2583
2584 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
2585 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
2586
2587
2588
2589 /*
2590  *  tbdr_reg definition
2591  *  offset: 0x5000
2592  */
2593 #define BNX2_TBDR_COMMAND                               0x00005000
2594 #define BNX2_TBDR_COMMAND_ENABLE                         (1L<<0)
2595 #define BNX2_TBDR_COMMAND_SOFT_RST                       (1L<<1)
2596 #define BNX2_TBDR_COMMAND_MSTR_ABORT                     (1L<<4)
2597
2598 #define BNX2_TBDR_STATUS                                0x00005004
2599 #define BNX2_TBDR_STATUS_DMA_WAIT                        (1L<<0)
2600 #define BNX2_TBDR_STATUS_FTQ_WAIT                        (1L<<1)
2601 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW                   (1L<<2)
2602 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                  (1L<<3)
2603 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR                (1L<<4)
2604 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                   (1L<<5)
2605 #define BNX2_TBDR_STATUS_BURST_CNT                       (1L<<6)
2606
2607 #define BNX2_TBDR_CONFIG                                0x00005008
2608 #define BNX2_TBDR_CONFIG_MAX_BDS                         (0xffL<<0)
2609 #define BNX2_TBDR_CONFIG_SWAP_MODE                       (1L<<8)
2610 #define BNX2_TBDR_CONFIG_PRIORITY                        (1L<<9)
2611 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS            (1L<<10)
2612 #define BNX2_TBDR_CONFIG_PAGE_SIZE                       (0xfL<<24)
2613 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256                   (0L<<24)
2614 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512                   (1L<<24)
2615 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                    (2L<<24)
2616 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                    (3L<<24)
2617 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                    (4L<<24)
2618 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                    (5L<<24)
2619 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                   (6L<<24)
2620 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                   (7L<<24)
2621 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                   (8L<<24)
2622 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                  (9L<<24)
2623 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                  (10L<<24)
2624 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                  (11L<<24)
2625 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                    (12L<<24)
2626
2627 #define BNX2_TBDR_DEBUG_VECT_PEEK                       0x0000500c
2628 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
2629 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
2630 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
2631 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
2632 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
2633 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
2634
2635 #define BNX2_TBDR_FTQ_DATA                              0x000053c0
2636 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
2637 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
2638 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
2639 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0                       (0L<<10)
2640 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1                       (1L<<10)
2641 #define BNX2_TBDR_FTQ_CMD_SFT_RESET                      (1L<<25)
2642 #define BNX2_TBDR_FTQ_CMD_RD_DATA                        (1L<<26)
2643 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
2644 #define BNX2_TBDR_FTQ_CMD_ADD_DATA                       (1L<<28)
2645 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
2646 #define BNX2_TBDR_FTQ_CMD_POP                            (1L<<30)
2647 #define BNX2_TBDR_FTQ_CMD_BUSY                           (1L<<31)
2648
2649 #define BNX2_TBDR_FTQ_CTL                               0x000053fc
2650 #define BNX2_TBDR_FTQ_CTL_INTERVENE                      (1L<<0)
2651 #define BNX2_TBDR_FTQ_CTL_OVERFLOW                       (1L<<1)
2652 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
2653 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
2654 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
2655
2656
2657
2658 /*
2659  *  tdma_reg definition
2660  *  offset: 0x5c00
2661  */
2662 #define BNX2_TDMA_COMMAND                               0x00005c00
2663 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
2664 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
2665 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
2666
2667 #define BNX2_TDMA_STATUS                                0x00005c04
2668 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
2669 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT                    (1L<<1)
2670 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                  (1L<<2)
2671 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
2672 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
2673 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
2674
2675 #define BNX2_TDMA_CONFIG                                0x00005c08
2676 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
2677 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
2678 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
2679 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
2680 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
2681 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256                    (0x6L<<4)
2682 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512                    (0x8L<<4)
2683 #define BNX2_TDMA_CONFIG_LINE_SZ                         (0xfL<<8)
2684 #define BNX2_TDMA_CONFIG_LINE_SZ_64                      (0L<<8)
2685 #define BNX2_TDMA_CONFIG_LINE_SZ_128                     (4L<<8)
2686 #define BNX2_TDMA_CONFIG_LINE_SZ_256                     (6L<<8)
2687 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
2688 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
2689 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
2690 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
2691
2692 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
2693 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
2694
2695 #define BNX2_TDMA_DBG_WATCHDOG                          0x00005c10
2696 #define BNX2_TDMA_DBG_TRIGGER                           0x00005c14
2697 #define BNX2_TDMA_DMAD_FSM                              0x00005c80
2698 #define BNX2_TDMA_DMAD_FSM_BD_INVLD                      (1L<<0)
2699 #define BNX2_TDMA_DMAD_FSM_PUSH                          (0xfL<<4)
2700 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC                      (0x3L<<8)
2701 #define BNX2_TDMA_DMAD_FSM_ARB_CTX                       (1L<<12)
2702 #define BNX2_TDMA_DMAD_FSM_DR_INTF                       (1L<<16)
2703 #define BNX2_TDMA_DMAD_FSM_DMAD                          (0x7L<<20)
2704 #define BNX2_TDMA_DMAD_FSM_BD                            (0xfL<<24)
2705
2706 #define BNX2_TDMA_DMAD_STATUS                           0x00005c84
2707 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY           (0x3L<<0)
2708 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY           (0x3L<<4)
2709 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY             (0x3L<<8)
2710 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                  (0xfL<<12)
2711
2712 #define BNX2_TDMA_DR_INTF_FSM                           0x00005c88
2713 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP                    (0x3L<<0)
2714 #define BNX2_TDMA_DR_INTF_FSM_TPATQ                      (0x7L<<4)
2715 #define BNX2_TDMA_DR_INTF_FSM_TPBUF                      (0x3L<<8)
2716 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF                     (0x7L<<12)
2717 #define BNX2_TDMA_DR_INTF_FSM_DMAD                       (0x7L<<16)
2718
2719 #define BNX2_TDMA_DR_INTF_STATUS                        0x00005c8c
2720 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE              (0x7L<<0)
2721 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL              (0x3L<<4)
2722 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR              (0x7L<<8)
2723 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
2724 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
2725
2726 #define BNX2_TDMA_FTQ_DATA                              0x00005fc0
2727 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
2728 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
2729 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
2730 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0                       (0L<<10)
2731 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1                       (1L<<10)
2732 #define BNX2_TDMA_FTQ_CMD_SFT_RESET                      (1L<<25)
2733 #define BNX2_TDMA_FTQ_CMD_RD_DATA                        (1L<<26)
2734 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
2735 #define BNX2_TDMA_FTQ_CMD_ADD_DATA                       (1L<<28)
2736 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
2737 #define BNX2_TDMA_FTQ_CMD_POP                            (1L<<30)
2738 #define BNX2_TDMA_FTQ_CMD_BUSY                           (1L<<31)
2739
2740 #define BNX2_TDMA_FTQ_CTL                               0x00005ffc
2741 #define BNX2_TDMA_FTQ_CTL_INTERVENE                      (1L<<0)
2742 #define BNX2_TDMA_FTQ_CTL_OVERFLOW                       (1L<<1)
2743 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
2744 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
2745 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
2746
2747
2748
2749 /*
2750  *  hc_reg definition
2751  *  offset: 0x6800
2752  */
2753 #define BNX2_HC_COMMAND                                 0x00006800
2754 #define BNX2_HC_COMMAND_ENABLE                           (1L<<0)
2755 #define BNX2_HC_COMMAND_SKIP_ABORT                       (1L<<4)
2756 #define BNX2_HC_COMMAND_COAL_NOW                         (1L<<16)
2757 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT                  (1L<<17)
2758 #define BNX2_HC_COMMAND_STATS_NOW                        (1L<<18)
2759 #define BNX2_HC_COMMAND_FORCE_INT                        (0x3L<<19)
2760 #define BNX2_HC_COMMAND_FORCE_INT_NULL                   (0L<<19)
2761 #define BNX2_HC_COMMAND_FORCE_INT_HIGH                   (1L<<19)
2762 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
2763 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
2764 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
2765
2766 #define BNX2_HC_STATUS                                  0x00006804
2767 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
2768 #define BNX2_HC_STATUS_PARITY_ERROR_STATE                (1L<<1)
2769 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT                  (1L<<16)
2770 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT                 (1L<<17)
2771 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT            (1L<<18)
2772 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT                  (1L<<19)
2773 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT              (1L<<20)
2774 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT       (1L<<23)
2775 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT       (1L<<24)
2776 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT   (1L<<25)
2777
2778 #define BNX2_HC_CONFIG                                  0x00006808
2779 #define BNX2_HC_CONFIG_COLLECT_STATS                     (1L<<0)
2780 #define BNX2_HC_CONFIG_RX_TMR_MODE                       (1L<<1)
2781 #define BNX2_HC_CONFIG_TX_TMR_MODE                       (1L<<2)
2782 #define BNX2_HC_CONFIG_COM_TMR_MODE                      (1L<<3)
2783 #define BNX2_HC_CONFIG_CMD_TMR_MODE                      (1L<<4)
2784 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
2785 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
2786 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
2787
2788 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
2789 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
2790 #define BNX2_HC_STATUS_ADDR_H                           0x00006814
2791 #define BNX2_HC_STATISTICS_ADDR_L                       0x00006818
2792 #define BNX2_HC_STATISTICS_ADDR_H                       0x0000681c
2793 #define BNX2_HC_TX_QUICK_CONS_TRIP                      0x00006820
2794 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
2795 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
2796
2797 #define BNX2_HC_COMP_PROD_TRIP                          0x00006824
2798 #define BNX2_HC_COMP_PROD_TRIP_VALUE                     (0xffL<<0)
2799 #define BNX2_HC_COMP_PROD_TRIP_INT                       (0xffL<<16)
2800
2801 #define BNX2_HC_RX_QUICK_CONS_TRIP                      0x00006828
2802 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
2803 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
2804
2805 #define BNX2_HC_RX_TICKS                                0x0000682c
2806 #define BNX2_HC_RX_TICKS_VALUE                           (0x3ffL<<0)
2807 #define BNX2_HC_RX_TICKS_INT                             (0x3ffL<<16)
2808
2809 #define BNX2_HC_TX_TICKS                                0x00006830
2810 #define BNX2_HC_TX_TICKS_VALUE                           (0x3ffL<<0)
2811 #define BNX2_HC_TX_TICKS_INT                             (0x3ffL<<16)
2812
2813 #define BNX2_HC_COM_TICKS                               0x00006834
2814 #define BNX2_HC_COM_TICKS_VALUE                          (0x3ffL<<0)
2815 #define BNX2_HC_COM_TICKS_INT                            (0x3ffL<<16)
2816
2817 #define BNX2_HC_CMD_TICKS                               0x00006838
2818 #define BNX2_HC_CMD_TICKS_VALUE                          (0x3ffL<<0)
2819 #define BNX2_HC_CMD_TICKS_INT                            (0x3ffL<<16)
2820
2821 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
2822 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
2823
2824 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
2825 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
2826
2827 #define BNX2_HC_STATS_TICKS                             0x00006844
2828 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
2829
2830 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
2831 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
2832 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
2833 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0       (0L<<0)
2834 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1       (1L<<0)
2835 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2       (2L<<0)
2836 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3       (3L<<0)
2837 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4       (4L<<0)
2838 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5       (5L<<0)
2839 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6       (6L<<0)
2840 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7       (7L<<0)
2841 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8       (8L<<0)
2842 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9       (9L<<0)
2843 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10      (10L<<0)
2844 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11      (11L<<0)
2845 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0       (12L<<0)
2846 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1       (13L<<0)
2847 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2       (14L<<0)
2848 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3       (15L<<0)
2849 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4       (16L<<0)
2850 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5       (17L<<0)
2851 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6       (18L<<0)
2852 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7       (19L<<0)
2853 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0       (20L<<0)
2854 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1       (21L<<0)
2855 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2       (22L<<0)
2856 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3       (23L<<0)
2857 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4       (24L<<0)
2858 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5       (25L<<0)
2859 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6       (26L<<0)
2860 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7       (27L<<0)
2861 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8       (28L<<0)
2862 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9       (29L<<0)
2863 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10      (30L<<0)
2864 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11      (31L<<0)
2865 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0      (32L<<0)
2866 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1      (33L<<0)
2867 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2      (34L<<0)
2868 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3      (35L<<0)
2869 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0        (36L<<0)
2870 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1        (37L<<0)
2871 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2        (38L<<0)
2872 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3        (39L<<0)
2873 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4        (40L<<0)
2874 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5        (41L<<0)
2875 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6        (42L<<0)
2876 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7        (43L<<0)
2877 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0       (44L<<0)
2878 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1       (45L<<0)
2879 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2       (46L<<0)
2880 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3       (47L<<0)
2881 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4       (48L<<0)
2882 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5       (49L<<0)
2883 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6       (50L<<0)
2884 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7       (51L<<0)
2885 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT     (52L<<0)
2886 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT    (53L<<0)
2887 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS    (54L<<0)
2888 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN  (55L<<0)
2889 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR      (56L<<0)
2890 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK       (59L<<0)
2891 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK       (60L<<0)
2892 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK   (61L<<0)
2893 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT    (62L<<0)
2894 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT   (63L<<0)
2895 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT    (64L<<0)
2896 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT   (65L<<0)
2897 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT         (66L<<0)
2898 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT  (67L<<0)
2899 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT         (68L<<0)
2900 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT        (69L<<0)
2901 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT        (70L<<0)
2902 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT        (71L<<0)
2903 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT         (72L<<0)
2904 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT         (73L<<0)
2905 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT         (74L<<0)
2906 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT  (75L<<0)
2907 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT         (76L<<0)
2908 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT         (77L<<0)
2909 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT  (78L<<0)
2910 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT   (79L<<0)
2911 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT   (80L<<0)
2912 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT         (81L<<0)
2913 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT         (82L<<0)
2914 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT  (83L<<0)
2915 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT  (84L<<0)
2916 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT         (85L<<0)
2917 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT    (86L<<0)
2918 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT     (87L<<0)
2919 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT        (88L<<0)
2920 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT      (89L<<0)
2921 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT        (90L<<0)
2922 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT   (91L<<0)
2923 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT    (92L<<0)
2924 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT       (93L<<0)
2925 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT     (94L<<0)
2926 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64    (95L<<0)
2927 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64    (96L<<0)
2928 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS      (97L<<0)
2929 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS     (98L<<0)
2930 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT     (99L<<0)
2931 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT   (100L<<0)
2932 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT      (101L<<0)
2933 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT      (102L<<0)
2934 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT  (103L<<0)
2935 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT      (104L<<0)
2936 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT  (105L<<0)
2937 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT      (106L<<0)
2938 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT  (107L<<0)
2939 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT  (108L<<0)
2940 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT       (109L<<0)
2941 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT    (110L<<0)
2942 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT    (111L<<0)
2943 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT    (112L<<0)
2944 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT    (113L<<0)
2945 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT    (114L<<0)
2946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0      (115L<<0)
2947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1      (116L<<0)
2948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2      (117L<<0)
2949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3      (118L<<0)
2950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4      (119L<<0)
2951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5      (120L<<0)
2952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS         (121L<<0)
2953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS         (122L<<0)
2954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT  (127L<<0)
2955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
2956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
2957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
2958
2959 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
2960 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
2961 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
2962 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
2963 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
2964
2965 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
2966 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
2967 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
2968 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
2969 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
2970
2971 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
2972 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
2973 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
2974 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
2975 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
2976
2977 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
2978 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
2979 #define BNX2_HC_STAT_GEN_STAT2                          0x00006890
2980 #define BNX2_HC_STAT_GEN_STAT3                          0x00006894
2981 #define BNX2_HC_STAT_GEN_STAT4                          0x00006898
2982 #define BNX2_HC_STAT_GEN_STAT5                          0x0000689c
2983 #define BNX2_HC_STAT_GEN_STAT6                          0x000068a0
2984 #define BNX2_HC_STAT_GEN_STAT7                          0x000068a4
2985 #define BNX2_HC_STAT_GEN_STAT8                          0x000068a8
2986 #define BNX2_HC_STAT_GEN_STAT9                          0x000068ac
2987 #define BNX2_HC_STAT_GEN_STAT10                         0x000068b0
2988 #define BNX2_HC_STAT_GEN_STAT11                         0x000068b4
2989 #define BNX2_HC_STAT_GEN_STAT12                         0x000068b8
2990 #define BNX2_HC_STAT_GEN_STAT13                         0x000068bc
2991 #define BNX2_HC_STAT_GEN_STAT14                         0x000068c0
2992 #define BNX2_HC_STAT_GEN_STAT15                         0x000068c4
2993 #define BNX2_HC_STAT_GEN_STAT_AC0                       0x000068c8
2994 #define BNX2_HC_STAT_GEN_STAT_AC1                       0x000068cc
2995 #define BNX2_HC_STAT_GEN_STAT_AC2                       0x000068d0
2996 #define BNX2_HC_STAT_GEN_STAT_AC3                       0x000068d4
2997 #define BNX2_HC_STAT_GEN_STAT_AC4                       0x000068d8
2998 #define BNX2_HC_STAT_GEN_STAT_AC5                       0x000068dc
2999 #define BNX2_HC_STAT_GEN_STAT_AC6                       0x000068e0
3000 #define BNX2_HC_STAT_GEN_STAT_AC7                       0x000068e4
3001 #define BNX2_HC_STAT_GEN_STAT_AC8                       0x000068e8
3002 #define BNX2_HC_STAT_GEN_STAT_AC9                       0x000068ec
3003 #define BNX2_HC_STAT_GEN_STAT_AC10                      0x000068f0
3004 #define BNX2_HC_STAT_GEN_STAT_AC11                      0x000068f4
3005 #define BNX2_HC_STAT_GEN_STAT_AC12                      0x000068f8
3006 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
3007 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
3008 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
3009 #define BNX2_HC_VIS                                     0x00006908
3010 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
3011 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
3012 #define BNX2_HC_VIS_STAT_BUILD_STATE_START               (1L<<0)
3013 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST             (2L<<0)
3014 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64            (3L<<0)
3015 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32            (4L<<0)
3016 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE         (5L<<0)
3017 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA                 (6L<<0)
3018 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL         (7L<<0)
3019 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW             (8L<<0)
3020 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH            (9L<<0)
3021 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA            (10L<<0)
3022 #define BNX2_HC_VIS_DMA_STAT_STATE                       (0xfL<<8)
3023 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE                  (0L<<8)
3024 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM          (1L<<8)
3025 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA            (2L<<8)
3026 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP            (3L<<8)
3027 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP                  (4L<<8)
3028 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM       (5L<<8)
3029 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA         (6L<<8)
3030 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1          (7L<<8)
3031 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2          (8L<<8)
3032 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT                  (9L<<8)
3033 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT                 (15L<<8)
3034 #define BNX2_HC_VIS_DMA_MSI_STATE                        (0x7L<<12)
3035 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE               (0x3L<<15)
3036 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE          (0L<<15)
3037 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT         (1L<<15)
3038 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START         (2L<<15)
3039
3040 #define BNX2_HC_VIS_1                                   0x0000690c
3041 #define BNX2_HC_VIS_1_HW_INTACK_STATE                    (1L<<4)
3042 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE               (0L<<4)
3043 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT              (1L<<4)
3044 #define BNX2_HC_VIS_1_SW_INTACK_STATE                    (1L<<5)
3045 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE               (0L<<5)
3046 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT              (1L<<5)
3047 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE             (1L<<6)
3048 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE        (0L<<6)
3049 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT       (1L<<6)
3050 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE                (1L<<7)
3051 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE           (0L<<7)
3052 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT          (1L<<7)
3053 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE                   (0xfL<<17)
3054 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE              (0L<<17)
3055 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA               (1L<<17)
3056 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE            (2L<<17)
3057 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN            (3L<<17)
3058 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT              (4L<<17)
3059 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE        (5L<<17)
3060 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN        (6L<<17)
3061 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT          (7L<<17)
3062 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE                   (0x3L<<21)
3063 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL            (0L<<21)
3064 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR             (1L<<21)
3065 #define BNX2_HC_VIS_1_INT_GEN_STATE                      (1L<<23)
3066 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE                  (0L<<23)
3067 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT             (1L<<23)
3068 #define BNX2_HC_VIS_1_STAT_CHAN_ID                       (0x7L<<24)
3069 #define BNX2_HC_VIS_1_INT_B                              (1L<<27)
3070
3071 #define BNX2_HC_DEBUG_VECT_PEEK                         0x00006910
3072 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE                  (0x7ffL<<0)
3073 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN                (1L<<11)
3074 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL                    (0xfL<<12)
3075 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE                  (0x7ffL<<16)
3076 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
3077 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
3078
3079
3080
3081 /*
3082  *  txp_reg definition
3083  *  offset: 0x40000
3084  */
3085 #define BNX2_TXP_CPU_MODE                               0x00045000
3086 #define BNX2_TXP_CPU_MODE_LOCAL_RST                      (1L<<0)
3087 #define BNX2_TXP_CPU_MODE_STEP_ENA                       (1L<<1)
3088 #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
3089 #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
3090 #define BNX2_TXP_CPU_MODE_MSG_BIT1                       (1L<<6)
3091 #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
3092 #define BNX2_TXP_CPU_MODE_SOFT_HALT                      (1L<<10)
3093 #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
3094 #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
3095 #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
3096 #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
3097
3098 #define BNX2_TXP_CPU_STATE                              0x00045004
3099 #define BNX2_TXP_CPU_STATE_BREAKPOINT                    (1L<<0)
3100 #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
3101 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
3102 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
3103 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
3104 #define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
3105 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
3106 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
3107 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
3108 #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
3109 #define BNX2_TXP_CPU_STATE_INTERRRUPT                    (1L<<12)
3110 #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
3111 #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
3112 #define BNX2_TXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
3113
3114 #define BNX2_TXP_CPU_EVENT_MASK                         0x00045008
3115 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
3116 #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
3117 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
3118 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
3119 #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
3120 #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
3121 #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
3122 #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
3123 #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
3124 #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
3125 #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
3126
3127 #define BNX2_TXP_CPU_PROGRAM_COUNTER                    0x0004501c
3128 #define BNX2_TXP_CPU_INSTRUCTION                        0x00045020
3129 #define BNX2_TXP_CPU_DATA_ACCESS                        0x00045024
3130 #define BNX2_TXP_CPU_INTERRUPT_ENABLE                   0x00045028
3131 #define BNX2_TXP_CPU_INTERRUPT_VECTOR                   0x0004502c
3132 #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC                 0x00045030
3133 #define BNX2_TXP_CPU_HW_BREAKPOINT                      0x00045034
3134 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
3135 #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
3136
3137 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK                    0x00045038
3138 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
3139 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
3140 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
3141 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
3142 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
3143 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
3144
3145 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR                   0x00045048
3146 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
3147 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
3148 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
3149 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
3150
3151 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
3152 #define BNX2_TXP_FTQ_DATA                               0x000453c0
3153 #define BNX2_TXP_FTQ_CMD                                0x000453f8
3154 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
3155 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
3156 #define BNX2_TXP_FTQ_CMD_WR_TOP_0                        (0L<<10)
3157 #define BNX2_TXP_FTQ_CMD_WR_TOP_1                        (1L<<10)
3158 #define BNX2_TXP_FTQ_CMD_SFT_RESET                       (1L<<25)
3159 #define BNX2_TXP_FTQ_CMD_RD_DATA                         (1L<<26)
3160 #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
3161 #define BNX2_TXP_FTQ_CMD_ADD_DATA                        (1L<<28)
3162 #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
3163 #define BNX2_TXP_FTQ_CMD_POP                             (1L<<30)
3164 #define BNX2_TXP_FTQ_CMD_BUSY                            (1L<<31)
3165
3166 #define BNX2_TXP_FTQ_CTL                                0x000453fc
3167 #define BNX2_TXP_FTQ_CTL_INTERVENE                       (1L<<0)
3168 #define BNX2_TXP_FTQ_CTL_OVERFLOW                        (1L<<1)
3169 #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
3170 #define BNX2_TXP_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
3171 #define BNX2_TXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
3172
3173 #define BNX2_TXP_SCRATCH                                0x00060000
3174
3175
3176 /*
3177  *  tpat_reg definition
3178  *  offset: 0x80000
3179  */
3180 #define BNX2_TPAT_CPU_MODE                              0x00085000
3181 #define BNX2_TPAT_CPU_MODE_LOCAL_RST                     (1L<<0)
3182 #define BNX2_TPAT_CPU_MODE_STEP_ENA                      (1L<<1)
3183 #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
3184 #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
3185 #define BNX2_TPAT_CPU_MODE_MSG_BIT1                      (1L<<6)
3186 #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA                 (1L<<7)
3187 #define BNX2_TPAT_CPU_MODE_SOFT_HALT                     (1L<<10)
3188 #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
3189 #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
3190 #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
3191 #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
3192
3193 #define BNX2_TPAT_CPU_STATE                             0x00085004
3194 #define BNX2_TPAT_CPU_STATE_BREAKPOINT                   (1L<<0)
3195 #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED              (1L<<2)
3196 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
3197 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
3198 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
3199 #define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED                (1L<<6)
3200 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
3201 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
3202 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
3203 #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
3204 #define BNX2_TPAT_CPU_STATE_INTERRRUPT                   (1L<<12)
3205 #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
3206 #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL             (1L<<15)
3207 #define BNX2_TPAT_CPU_STATE_BLOCKED_READ                 (1L<<31)
3208
3209 #define BNX2_TPAT_CPU_EVENT_MASK                        0x00085008
3210 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK         (1L<<0)
3211 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
3212 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
3213 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
3214 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
3215 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
3216 #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
3217 #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
3218 #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
3219 #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
3220 #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
3221
3222 #define BNX2_TPAT_CPU_PROGRAM_COUNTER                   0x0008501c
3223 #define BNX2_TPAT_CPU_INSTRUCTION                       0x00085020
3224 #define BNX2_TPAT_CPU_DATA_ACCESS                       0x00085024
3225 #define BNX2_TPAT_CPU_INTERRUPT_ENABLE                  0x00085028
3226 #define BNX2_TPAT_CPU_INTERRUPT_VECTOR                  0x0008502c
3227 #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC                0x00085030
3228 #define BNX2_TPAT_CPU_HW_BREAKPOINT                     0x00085034
3229 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
3230 #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
3231
3232 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK                   0x00085038
3233 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
3234 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
3235 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
3236 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
3237 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
3238 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
3239
3240 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR                  0x00085048
3241 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
3242 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP         (0L<<1)
3243 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
3244 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
3245
3246 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
3247 #define BNX2_TPAT_FTQ_DATA                              0x000853c0
3248 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
3249 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
3250 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
3251 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0                       (0L<<10)
3252 #define BNX2_TPAT_FTQ_CMD_WR_TOP_1                       (1L<<10)
3253 #define BNX2_TPAT_FTQ_CMD_SFT_RESET                      (1L<<25)
3254 #define BNX2_TPAT_FTQ_CMD_RD_DATA                        (1L<<26)
3255 #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
3256 #define BNX2_TPAT_FTQ_CMD_ADD_DATA                       (1L<<28)
3257 #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
3258 #define BNX2_TPAT_FTQ_CMD_POP                            (1L<<30)
3259 #define BNX2_TPAT_FTQ_CMD_BUSY                           (1L<<31)
3260
3261 #define BNX2_TPAT_FTQ_CTL                               0x000853fc
3262 #define BNX2_TPAT_FTQ_CTL_INTERVENE                      (1L<<0)
3263 #define BNX2_TPAT_FTQ_CTL_OVERFLOW                       (1L<<1)
3264 #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
3265 #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
3266 #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
3267
3268 #define BNX2_TPAT_SCRATCH                               0x000a0000
3269
3270
3271 /*
3272  *  rxp_reg definition
3273  *  offset: 0xc0000
3274  */
3275 #define BNX2_RXP_CPU_MODE                               0x000c5000
3276 #define BNX2_RXP_CPU_MODE_LOCAL_RST                      (1L<<0)
3277 #define BNX2_RXP_CPU_MODE_STEP_ENA                       (1L<<1)
3278 #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
3279 #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
3280 #define BNX2_RXP_CPU_MODE_MSG_BIT1                       (1L<<6)
3281 #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
3282 #define BNX2_RXP_CPU_MODE_SOFT_HALT                      (1L<<10)
3283 #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
3284 #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
3285 #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
3286 #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
3287
3288 #define BNX2_RXP_CPU_STATE                              0x000c5004
3289 #define BNX2_RXP_CPU_STATE_BREAKPOINT                    (1L<<0)
3290 #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
3291 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
3292 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
3293 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
3294 #define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
3295 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
3296 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
3297 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
3298 #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
3299 #define BNX2_RXP_CPU_STATE_INTERRRUPT                    (1L<<12)
3300 #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
3301 #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
3302 #define BNX2_RXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
3303
3304 #define BNX2_RXP_CPU_EVENT_MASK                         0x000c5008
3305 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
3306 #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
3307 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
3308 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
3309 #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
3310 #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
3311 #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
3312 #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
3313 #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
3314 #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
3315 #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
3316
3317 #define BNX2_RXP_CPU_PROGRAM_COUNTER                    0x000c501c
3318 #define BNX2_RXP_CPU_INSTRUCTION                        0x000c5020
3319 #define BNX2_RXP_CPU_DATA_ACCESS                        0x000c5024