drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #include "bnx2.h"
  13 #include "bnx2_fw.h"
  14
  15 #define DRV_MODULE_NAME         "bnx2"
  16 #define PFX DRV_MODULE_NAME     ": "
  17 #define DRV_MODULE_VERSION      "1.4.31"
  18 #define DRV_MODULE_RELDATE      "January 19, 2006"
  19
  20 #define RUN_AT(x) (jiffies + (x))
  21
  22 /* Time in jiffies before concluding the transmitter is hung. */
  23 #define TX_TIMEOUT  (5*HZ)
  24
  25 static char version[] __devinitdata =
  26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  27
  28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_VERSION(DRV_MODULE_VERSION);
  32
  33 static int disable_msi = 0;
  34
  35 module_param(disable_msi, int, 0);
  36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  37
  38 typedef enum {
  39         BCM5706 = 0,
  40         NC370T,
  41         NC370I,
  42         BCM5706S,
  43         NC370F,
  44         BCM5708,
  45         BCM5708S,
  46 } board_t;
  47
  48 /* indexed by board_t, above */
  49 static struct {
  50         char *name;
  51 } board_info[] __devinitdata = {
  52         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  53         { "HP NC370T Multifunction Gigabit Server Adapter" },
  54         { "HP NC370i Multifunction Gigabit Server Adapter" },
  55         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  56         { "HP NC370F Multifunction Gigabit Server Adapter" },
  57         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  58         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  59         };
  60
  61 static struct pci_device_id bnx2_pci_tbl[] = {
  62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  63           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  65           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  70         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  71           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  72         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  74         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  76         { 0, }
  77 };
  78
  79 static struct flash_spec flash_table[] =
  80 {
  81         /* Slow EEPROM */
  82         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  83          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  84          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  85          "EEPROM - slow"},
  86         /* Expansion entry 0001 */
  87         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  88          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  89          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  90          "Entry 0001"},
  91         /* Saifun SA25F010 (non-buffered flash) */
  92         /* strap, cfg1, & write1 need updates */
  93         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  94          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  95          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  96          "Non-buffered flash (128kB)"},
  97         /* Saifun SA25F020 (non-buffered flash) */
  98         /* strap, cfg1, & write1 need updates */
  99         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 100          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 101          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 102          "Non-buffered flash (256kB)"},
 103         /* Expansion entry 0100 */
 104         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 105          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 106          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 107          "Entry 0100"},
 108         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 109         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 110          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 111          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 112          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 113         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 114         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 115          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 116          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 117          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 118         /* Saifun SA25F005 (non-buffered flash) */
 119         /* strap, cfg1, & write1 need updates */
 120         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 121          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 122          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 123          "Non-buffered flash (64kB)"},
 124         /* Fast EEPROM */
 125         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 126          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 127          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 128          "EEPROM - fast"},
 129         /* Expansion entry 1001 */
 130         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 131          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 132          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 133          "Entry 1001"},
 134         /* Expansion entry 1010 */
 135         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 136          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 137          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 138          "Entry 1010"},
 139         /* ATMEL AT45DB011B (buffered flash) */
 140         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 141          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 142          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 143          "Buffered flash (128kB)"},
 144         /* Expansion entry 1100 */
 145         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 146          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 148          "Entry 1100"},
 149         /* Expansion entry 1101 */
 150         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 151          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 153          "Entry 1101"},
 154         /* Ateml Expansion entry 1110 */
 155         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 156          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 157          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 158          "Entry 1110 (Atmel)"},
 159         /* ATMEL AT45DB021B (buffered flash) */
 160         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 161          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 162          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 163          "Buffered flash (256kB)"},
 164 };
 165
 166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 167
 168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 169 {
 170         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
 171
 172         if (diff > MAX_TX_DESC_CNT)
 173                 diff = (diff & MAX_TX_DESC_CNT) - 1;
 174         return (bp->tx_ring_size - diff);
 175 }
 176
 177 static u32
 178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 179 {
 180         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 181         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 182 }
 183
 184 static void
 185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 186 {
 187         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 188         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 189 }
 190
 191 static void
 192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 193 {
 194         offset += cid_addr;
 195         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 196         REG_WR(bp, BNX2_CTX_DATA, val);
 197 }
 198
 199 static int
 200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 201 {
 202         u32 val1;
 203         int i, ret;
 204
 205         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 206                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 207                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 208
 209                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 210                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 211
 212                 udelay(40);
 213         }
 214
 215         val1 = (bp->phy_addr << 21) | (reg << 16) |
 216                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 217                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 218         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 219
 220         for (i = 0; i < 50; i++) {
 221                 udelay(10);
 222
 223                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 224                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 225                         udelay(5);
 226
 227                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 228                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 229
 230                         break;
 231                 }
 232         }
 233
 234         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 235                 *val = 0x0;
 236                 ret = -EBUSY;
 237         }
 238         else {
 239                 *val = val1;
 240                 ret = 0;
 241         }
 242
 243         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 244                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 245                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 246
 247                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 248                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 249
 250                 udelay(40);
 251         }
 252
 253         return ret;
 254 }
 255
 256 static int
 257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 258 {
 259         u32 val1;
 260         int i, ret;
 261
 262         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 263                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 264                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 265
 266                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 267                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 268
 269                 udelay(40);
 270         }
 271
 272         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 273                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 274                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 275         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 276
 277         for (i = 0; i < 50; i++) {
 278                 udelay(10);
 279
 280                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 281                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 282                         udelay(5);
 283                         break;
 284                 }
 285         }
 286
 287         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 288                 ret = -EBUSY;
 289         else
 290                 ret = 0;
 291
 292         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 293                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 294                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 295
 296                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 297                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 298
 299                 udelay(40);
 300         }
 301
 302         return ret;
 303 }
 304
 305 static void
 306 bnx2_disable_int(struct bnx2 *bp)
 307 {
 308         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 309                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 310         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 311 }
 312
 313 static void
 314 bnx2_enable_int(struct bnx2 *bp)
 315 {
 316         u32 val;
 317
 318         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 319                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 320                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 321
 322         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 323                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 324
 325         val = REG_RD(bp, BNX2_HC_COMMAND);
 326         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 327 }
 328
 329 static void
 330 bnx2_disable_int_sync(struct bnx2 *bp)
 331 {
 332         atomic_inc(&bp->intr_sem);
 333         bnx2_disable_int(bp);
 334         synchronize_irq(bp->pdev->irq);
 335 }
 336
 337 static void
 338 bnx2_netif_stop(struct bnx2 *bp)
 339 {
 340         bnx2_disable_int_sync(bp);
 341         if (netif_running(bp->dev)) {
 342                 netif_poll_disable(bp->dev);
 343                 netif_tx_disable(bp->dev);
 344                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 345         }
 346 }
 347
 348 static void
 349 bnx2_netif_start(struct bnx2 *bp)
 350 {
 351         if (atomic_dec_and_test(&bp->intr_sem)) {
 352                 if (netif_running(bp->dev)) {
 353                         netif_wake_queue(bp->dev);
 354                         netif_poll_enable(bp->dev);
 355                         bnx2_enable_int(bp);
 356                 }
 357         }
 358 }
 359
 360 static void
 361 bnx2_free_mem(struct bnx2 *bp)
 362 {
 363         if (bp->stats_blk) {
 364                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
 365                                     bp->stats_blk, bp->stats_blk_mapping);
 366                 bp->stats_blk = NULL;
 367         }
 368         if (bp->status_blk) {
 369                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
 370                                     bp->status_blk, bp->status_blk_mapping);
 371                 bp->status_blk = NULL;
 372         }
 373         if (bp->tx_desc_ring) {
 374                 pci_free_consistent(bp->pdev,
 375                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 376                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 377                 bp->tx_desc_ring = NULL;
 378         }
 379         kfree(bp->tx_buf_ring);
 380         bp->tx_buf_ring = NULL;
 381         if (bp->rx_desc_ring) {
 382                 pci_free_consistent(bp->pdev,
 383                                     sizeof(struct rx_bd) * RX_DESC_CNT,
 384                                     bp->rx_desc_ring, bp->rx_desc_mapping);
 385                 bp->rx_desc_ring = NULL;
 386         }
 387         kfree(bp->rx_buf_ring);
 388         bp->rx_buf_ring = NULL;
 389 }
 390
 391 static int
 392 bnx2_alloc_mem(struct bnx2 *bp)
 393 {
 394         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 395                                      GFP_KERNEL);
 396         if (bp->tx_buf_ring == NULL)
 397                 return -ENOMEM;
 398
 399         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
 400         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 401                                                 sizeof(struct tx_bd) *
 402                                                 TX_DESC_CNT,
 403                                                 &bp->tx_desc_mapping);
 404         if (bp->tx_desc_ring == NULL)
 405                 goto alloc_mem_err;
 406
 407         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
 408                                      GFP_KERNEL);
 409         if (bp->rx_buf_ring == NULL)
 410                 goto alloc_mem_err;
 411
 412         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
 413         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
 414                                                 sizeof(struct rx_bd) *
 415                                                 RX_DESC_CNT,
 416                                                 &bp->rx_desc_mapping);
 417         if (bp->rx_desc_ring == NULL)
 418                 goto alloc_mem_err;
 419
 420         bp->status_blk = pci_alloc_consistent(bp->pdev,
 421                                               sizeof(struct status_block),
 422                                               &bp->status_blk_mapping);
 423         if (bp->status_blk == NULL)
 424                 goto alloc_mem_err;
 425
 426         memset(bp->status_blk, 0, sizeof(struct status_block));
 427
 428         bp->stats_blk = pci_alloc_consistent(bp->pdev,
 429                                              sizeof(struct statistics_block),
 430                                              &bp->stats_blk_mapping);
 431         if (bp->stats_blk == NULL)
 432                 goto alloc_mem_err;
 433
 434         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
 435
 436         return 0;
 437
 438 alloc_mem_err:
 439         bnx2_free_mem(bp);
 440         return -ENOMEM;
 441 }
 442
 443 static void
 444 bnx2_report_fw_link(struct bnx2 *bp)
 445 {
 446         u32 fw_link_status = 0;
 447
 448         if (bp->link_up) {
 449                 u32 bmsr;
 450
 451                 switch (bp->line_speed) {
 452                 case SPEED_10:
 453                         if (bp->duplex == DUPLEX_HALF)
 454                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 455                         else
 456                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 457                         break;
 458                 case SPEED_100:
 459                         if (bp->duplex == DUPLEX_HALF)
 460                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 461                         else
 462                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 463                         break;
 464                 case SPEED_1000:
 465                         if (bp->duplex == DUPLEX_HALF)
 466                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 467                         else
 468                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 469                         break;
 470                 case SPEED_2500:
 471                         if (bp->duplex == DUPLEX_HALF)
 472                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 473                         else
 474                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 475                         break;
 476                 }
 477
 478                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 479
 480                 if (bp->autoneg) {
 481                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 482
 483                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 484                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 485
 486                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 487                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 488                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 489                         else
 490                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 491                 }
 492         }
 493         else
 494                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 495
 496         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 497 }
 498
 499 static void
 500 bnx2_report_link(struct bnx2 *bp)
 501 {
 502         if (bp->link_up) {
 503                 netif_carrier_on(bp->dev);
 504                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 505
 506                 printk("%d Mbps ", bp->line_speed);
 507
 508                 if (bp->duplex == DUPLEX_FULL)
 509                         printk("full duplex");
 510                 else
 511                         printk("half duplex");
 512
 513                 if (bp->flow_ctrl) {
 514                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 515                                 printk(", receive ");
 516                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 517                                         printk("& transmit ");
 518                         }
 519                         else {
 520                                 printk(", transmit ");
 521                         }
 522                         printk("flow control ON");
 523                 }
 524                 printk("\n");
 525         }
 526         else {
 527                 netif_carrier_off(bp->dev);
 528                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 529         }
 530
 531         bnx2_report_fw_link(bp);
 532 }
 533
 534 static void
 535 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 536 {
 537         u32 local_adv, remote_adv;
 538
 539         bp->flow_ctrl = 0;
 540         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 541                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 542
 543                 if (bp->duplex == DUPLEX_FULL) {
 544                         bp->flow_ctrl = bp->req_flow_ctrl;
 545                 }
 546                 return;
 547         }
 548
 549         if (bp->duplex != DUPLEX_FULL) {
 550                 return;
 551         }
 552
 553         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 554             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 555                 u32 val;
 556
 557                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 558                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 559                         bp->flow_ctrl |= FLOW_CTRL_TX;
 560                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 561                         bp->flow_ctrl |= FLOW_CTRL_RX;
 562                 return;
 563         }
 564
 565         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 566         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 567
 568         if (bp->phy_flags & PHY_SERDES_FLAG) {
 569                 u32 new_local_adv = 0;
 570                 u32 new_remote_adv = 0;
 571
 572                 if (local_adv & ADVERTISE_1000XPAUSE)
 573                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 574                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 575                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 576                 if (remote_adv & ADVERTISE_1000XPAUSE)
 577                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 578                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 579                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 580
 581                 local_adv = new_local_adv;
 582                 remote_adv = new_remote_adv;
 583         }
 584
 585         /* See Table 28B-3 of 802.3ab-1999 spec. */
 586         if (local_adv & ADVERTISE_PAUSE_CAP) {
 587                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 588                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 589                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 590                         }
 591                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 592                                 bp->flow_ctrl = FLOW_CTRL_RX;
 593                         }
 594                 }
 595                 else {
 596                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 597                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 598                         }
 599                 }
 600         }
 601         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 602                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 603                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 604
 605                         bp->flow_ctrl = FLOW_CTRL_TX;
 606                 }
 607         }
 608 }
 609
 610 static int
 611 bnx2_5708s_linkup(struct bnx2 *bp)
 612 {
 613         u32 val;
 614
 615         bp->link_up = 1;
 616         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 617         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 618                 case BCM5708S_1000X_STAT1_SPEED_10:
 619                         bp->line_speed = SPEED_10;
 620                         break;
 621                 case BCM5708S_1000X_STAT1_SPEED_100:
 622                         bp->line_speed = SPEED_100;
 623                         break;
 624                 case BCM5708S_1000X_STAT1_SPEED_1G:
 625                         bp->line_speed = SPEED_1000;
 626                         break;
 627                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 628                         bp->line_speed = SPEED_2500;
 629                         break;
 630         }
 631         if (val & BCM5708S_1000X_STAT1_FD)
 632                 bp->duplex = DUPLEX_FULL;
 633         else
 634                 bp->duplex = DUPLEX_HALF;
 635
 636         return 0;
 637 }
 638
 639 static int
 640 bnx2_5706s_linkup(struct bnx2 *bp)
 641 {
 642         u32 bmcr, local_adv, remote_adv, common;
 643
 644         bp->link_up = 1;
 645         bp->line_speed = SPEED_1000;
 646
 647         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 648         if (bmcr & BMCR_FULLDPLX) {
 649                 bp->duplex = DUPLEX_FULL;
 650         }
 651         else {
 652                 bp->duplex = DUPLEX_HALF;
 653         }
 654
 655         if (!(bmcr & BMCR_ANENABLE)) {
 656                 return 0;
 657         }
 658
 659         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 660         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 661
 662         common = local_adv & remote_adv;
 663         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 664
 665                 if (common & ADVERTISE_1000XFULL) {
 666                         bp->duplex = DUPLEX_FULL;
 667                 }
 668                 else {
 669                         bp->duplex = DUPLEX_HALF;
 670                 }
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int
 677 bnx2_copper_linkup(struct bnx2 *bp)
 678 {
 679         u32 bmcr;
 680
 681         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 682         if (bmcr & BMCR_ANENABLE) {
 683                 u32 local_adv, remote_adv, common;
 684
 685                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 686                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 687
 688                 common = local_adv & (remote_adv >> 2);
 689                 if (common & ADVERTISE_1000FULL) {
 690                         bp->line_speed = SPEED_1000;
 691                         bp->duplex = DUPLEX_FULL;
 692                 }
 693                 else if (common & ADVERTISE_1000HALF) {
 694                         bp->line_speed = SPEED_1000;
 695                         bp->duplex = DUPLEX_HALF;
 696                 }
 697                 else {
 698                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 699                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 700
 701                         common = local_adv & remote_adv;
 702                         if (common & ADVERTISE_100FULL) {
 703                                 bp->line_speed = SPEED_100;
 704                                 bp->duplex = DUPLEX_FULL;
 705                         }
 706                         else if (common & ADVERTISE_100HALF) {
 707                                 bp->line_speed = SPEED_100;
 708                                 bp->duplex = DUPLEX_HALF;
 709                         }
 710                         else if (common & ADVERTISE_10FULL) {
 711                                 bp->line_speed = SPEED_10;
 712                                 bp->duplex = DUPLEX_FULL;
 713                         }
 714                         else if (common & ADVERTISE_10HALF) {
 715                                 bp->line_speed = SPEED_10;
 716                                 bp->duplex = DUPLEX_HALF;
 717                         }
 718                         else {
 719                                 bp->line_speed = 0;
 720                                 bp->link_up = 0;
 721                         }
 722                 }
 723         }
 724         else {
 725                 if (bmcr & BMCR_SPEED100) {
 726                         bp->line_speed = SPEED_100;
 727                 }
 728                 else {
 729                         bp->line_speed = SPEED_10;
 730                 }
 731                 if (bmcr & BMCR_FULLDPLX) {
 732                         bp->duplex = DUPLEX_FULL;
 733                 }
 734                 else {
 735                         bp->duplex = DUPLEX_HALF;
 736                 }
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int
 743 bnx2_set_mac_link(struct bnx2 *bp)
 744 {
 745         u32 val;
 746
 747         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 748         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 749                 (bp->duplex == DUPLEX_HALF)) {
 750                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 751         }
 752
 753         /* Configure the EMAC mode register. */
 754         val = REG_RD(bp, BNX2_EMAC_MODE);
 755
 756         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 757                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 758                 BNX2_EMAC_MODE_25G);
 759
 760         if (bp->link_up) {
 761                 switch (bp->line_speed) {
 762                         case SPEED_10:
 763                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 764                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
 765                                         break;
 766                                 }
 767                                 /* fall through */
 768                         case SPEED_100:
 769                                 val |= BNX2_EMAC_MODE_PORT_MII;
 770                                 break;
 771                         case SPEED_2500:
 772                                 val |= BNX2_EMAC_MODE_25G;
 773                                 /* fall through */
 774                         case SPEED_1000:
 775                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 776                                 break;
 777                 }
 778         }
 779         else {
 780                 val |= BNX2_EMAC_MODE_PORT_GMII;
 781         }
 782
 783         /* Set the MAC to operate in the appropriate duplex mode. */
 784         if (bp->duplex == DUPLEX_HALF)
 785                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 786         REG_WR(bp, BNX2_EMAC_MODE, val);
 787
 788         /* Enable/disable rx PAUSE. */
 789         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 790
 791         if (bp->flow_ctrl & FLOW_CTRL_RX)
 792                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 793         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 794
 795         /* Enable/disable tx PAUSE. */
 796         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 797         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 798
 799         if (bp->flow_ctrl & FLOW_CTRL_TX)
 800                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 801         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 802
 803         /* Acknowledge the interrupt. */
 804         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 805
 806         return 0;
 807 }
 808
 809 static int
 810 bnx2_set_link(struct bnx2 *bp)
 811 {
 812         u32 bmsr;
 813         u8 link_up;
 814
 815         if (bp->loopback == MAC_LOOPBACK) {
 816                 bp->link_up = 1;
 817                 return 0;
 818         }
 819
 820         link_up = bp->link_up;
 821
 822         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 823         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 824
 825         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 826             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 827                 u32 val;
 828
 829                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 830                 if (val & BNX2_EMAC_STATUS_LINK)
 831                         bmsr |= BMSR_LSTATUS;
 832                 else
 833                         bmsr &= ~BMSR_LSTATUS;
 834         }
 835
 836         if (bmsr & BMSR_LSTATUS) {
 837                 bp->link_up = 1;
 838
 839                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 840                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
 841                                 bnx2_5706s_linkup(bp);
 842                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
 843                                 bnx2_5708s_linkup(bp);
 844                 }
 845                 else {
 846                         bnx2_copper_linkup(bp);
 847                 }
 848                 bnx2_resolve_flow_ctrl(bp);
 849         }
 850         else {
 851                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 852                         (bp->autoneg & AUTONEG_SPEED)) {
 853
 854                         u32 bmcr;
 855
 856                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 857                         if (!(bmcr & BMCR_ANENABLE)) {
 858                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 859                                         BMCR_ANENABLE);
 860                         }
 861                 }
 862                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 863                 bp->link_up = 0;
 864         }
 865
 866         if (bp->link_up != link_up) {
 867                 bnx2_report_link(bp);
 868         }
 869
 870         bnx2_set_mac_link(bp);
 871
 872         return 0;
 873 }
 874
 875 static int
 876 bnx2_reset_phy(struct bnx2 *bp)
 877 {
 878         int i;
 879         u32 reg;
 880
 881         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 882
 883 #define PHY_RESET_MAX_WAIT 100
 884         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 885                 udelay(10);
 886
 887                 bnx2_read_phy(bp, MII_BMCR, &reg);
 888                 if (!(reg & BMCR_RESET)) {
 889                         udelay(20);
 890                         break;
 891                 }
 892         }
 893         if (i == PHY_RESET_MAX_WAIT) {
 894                 return -EBUSY;
 895         }
 896         return 0;
 897 }
 898
 899 static u32
 900 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 901 {
 902         u32 adv = 0;
 903
 904         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
 905                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 906
 907                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 908                         adv = ADVERTISE_1000XPAUSE;
 909                 }
 910                 else {
 911                         adv = ADVERTISE_PAUSE_CAP;
 912                 }
 913         }
 914         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
 915                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 916                         adv = ADVERTISE_1000XPSE_ASYM;
 917                 }
 918                 else {
 919                         adv = ADVERTISE_PAUSE_ASYM;
 920                 }
 921         }
 922         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
 923                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 924                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
 925                 }
 926                 else {
 927                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 928                 }
 929         }
 930         return adv;
 931 }
 932
 933 static int
 934 bnx2_setup_serdes_phy(struct bnx2 *bp)
 935 {
 936         u32 adv, bmcr, up1;
 937         u32 new_adv = 0;
 938
 939         if (!(bp->autoneg & AUTONEG_SPEED)) {
 940                 u32 new_bmcr;
 941                 int force_link_down = 0;
 942
 943                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 944                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 945                         if (up1 & BCM5708S_UP1_2G5) {
 946                                 up1 &= ~BCM5708S_UP1_2G5;
 947                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 948                                 force_link_down = 1;
 949                         }
 950                 }
 951
 952                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 953                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
 954
 955                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
 956                 new_bmcr = bmcr & ~BMCR_ANENABLE;
 957                 new_bmcr |= BMCR_SPEED1000;
 958                 if (bp->req_duplex == DUPLEX_FULL) {
 959                         adv |= ADVERTISE_1000XFULL;
 960                         new_bmcr |= BMCR_FULLDPLX;
 961                 }
 962                 else {
 963                         adv |= ADVERTISE_1000XHALF;
 964                         new_bmcr &= ~BMCR_FULLDPLX;
 965                 }
 966                 if ((new_bmcr != bmcr) || (force_link_down)) {
 967                         /* Force a link down visible on the other side */
 968                         if (bp->link_up) {
 969                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
 970                                                ~(ADVERTISE_1000XFULL |
 971                                                  ADVERTISE_1000XHALF));
 972                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 973                                         BMCR_ANRESTART | BMCR_ANENABLE);
 974
 975                                 bp->link_up = 0;
 976                                 netif_carrier_off(bp->dev);
 977                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 978                         }
 979                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
 980                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 981                 }
 982                 return 0;
 983         }
 984
 985         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
 986                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 987                 up1 |= BCM5708S_UP1_2G5;
 988                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 989         }
 990
 991         if (bp->advertising & ADVERTISED_1000baseT_Full)
 992                 new_adv |= ADVERTISE_1000XFULL;
 993
 994         new_adv |= bnx2_phy_get_pause_adv(bp);
 995
 996         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 997         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 998
 999         bp->serdes_an_pending = 0;
1000         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1001                 /* Force a link down visible on the other side */
1002                 if (bp->link_up) {
1003                         int i;
1004
1005                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1006                         for (i = 0; i < 110; i++) {
1007                                 udelay(100);
1008                         }
1009                 }
1010
1011                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1012                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1013                         BMCR_ANENABLE);
1014                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1015                         /* Speed up link-up time when the link partner
1016                          * does not autonegotiate which is very common
1017                          * in blade servers. Some blade servers use
1018                          * IPMI for kerboard input and it's important
1019                          * to minimize link disruptions. Autoneg. involves
1020                          * exchanging base pages plus 3 next pages and
1021                          * normally completes in about 120 msec.
1022                          */
1023                         bp->current_interval = SERDES_AN_TIMEOUT;
1024                         bp->serdes_an_pending = 1;
1025                         mod_timer(&bp->timer, jiffies + bp->current_interval);
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1033         (ADVERTISED_1000baseT_Full)
1034
1035 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1036         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1037         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1038         ADVERTISED_1000baseT_Full)
1039
1040 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1041         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1042
1043 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1044
1045 static int
1046 bnx2_setup_copper_phy(struct bnx2 *bp)
1047 {
1048         u32 bmcr;
1049         u32 new_bmcr;
1050
1051         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1052
1053         if (bp->autoneg & AUTONEG_SPEED) {
1054                 u32 adv_reg, adv1000_reg;
1055                 u32 new_adv_reg = 0;
1056                 u32 new_adv1000_reg = 0;
1057
1058                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1059                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1060                         ADVERTISE_PAUSE_ASYM);
1061
1062                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1063                 adv1000_reg &= PHY_ALL_1000_SPEED;
1064
1065                 if (bp->advertising & ADVERTISED_10baseT_Half)
1066                         new_adv_reg |= ADVERTISE_10HALF;
1067                 if (bp->advertising & ADVERTISED_10baseT_Full)
1068                         new_adv_reg |= ADVERTISE_10FULL;
1069                 if (bp->advertising & ADVERTISED_100baseT_Half)
1070                         new_adv_reg |= ADVERTISE_100HALF;
1071                 if (bp->advertising & ADVERTISED_100baseT_Full)
1072                         new_adv_reg |= ADVERTISE_100FULL;
1073                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1074                         new_adv1000_reg |= ADVERTISE_1000FULL;
1075
1076                 new_adv_reg |= ADVERTISE_CSMA;
1077
1078                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1079
1080                 if ((adv1000_reg != new_adv1000_reg) ||
1081                         (adv_reg != new_adv_reg) ||
1082                         ((bmcr & BMCR_ANENABLE) == 0)) {
1083
1084                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1085                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1086                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1087                                 BMCR_ANENABLE);
1088                 }
1089                 else if (bp->link_up) {
1090                         /* Flow ctrl may have changed from auto to forced */
1091                         /* or vice-versa. */
1092
1093                         bnx2_resolve_flow_ctrl(bp);
1094                         bnx2_set_mac_link(bp);
1095                 }
1096                 return 0;
1097         }
1098
1099         new_bmcr = 0;
1100         if (bp->req_line_speed == SPEED_100) {
1101                 new_bmcr |= BMCR_SPEED100;
1102         }
1103         if (bp->req_duplex == DUPLEX_FULL) {
1104                 new_bmcr |= BMCR_FULLDPLX;
1105         }
1106         if (new_bmcr != bmcr) {
1107                 u32 bmsr;
1108                 int i = 0;
1109
1110                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1111                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1112
1113                 if (bmsr & BMSR_LSTATUS) {
1114                         /* Force link down */
1115                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1116                         do {
1117                                 udelay(100);
1118                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1119                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1120                                 i++;
1121                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1122                 }
1123
1124                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1125
1126                 /* Normally, the new speed is setup after the link has
1127                  * gone down and up again. In some cases, link will not go
1128                  * down so we need to set up the new speed here.
1129                  */
1130                 if (bmsr & BMSR_LSTATUS) {
1131                         bp->line_speed = bp->req_line_speed;
1132                         bp->duplex = bp->req_duplex;
1133                         bnx2_resolve_flow_ctrl(bp);
1134                         bnx2_set_mac_link(bp);
1135                 }
1136         }
1137         return 0;
1138 }
1139
1140 static int
1141 bnx2_setup_phy(struct bnx2 *bp)
1142 {
1143         if (bp->loopback == MAC_LOOPBACK)
1144                 return 0;
1145
1146         if (bp->phy_flags & PHY_SERDES_FLAG) {
1147                 return (bnx2_setup_serdes_phy(bp));
1148         }
1149         else {
1150                 return (bnx2_setup_copper_phy(bp));
1151         }
1152 }
1153
1154 static int
1155 bnx2_init_5708s_phy(struct bnx2 *bp)
1156 {
1157         u32 val;
1158
1159         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1160         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1161         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1162
1163         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1164         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1165         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1166
1167         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1168         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1169         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1170
1171         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1172                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1173                 val |= BCM5708S_UP1_2G5;
1174                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1175         }
1176
1177         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1178             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1179             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1180                 /* increase tx signal amplitude */
1181                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1182                                BCM5708S_BLK_ADDR_TX_MISC);
1183                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1184                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1185                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1186                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1187         }
1188
1189         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1190               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1191
1192         if (val) {
1193                 u32 is_backplane;
1194
1195                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1196                                           BNX2_SHARED_HW_CFG_CONFIG);
1197                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1198                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1199                                        BCM5708S_BLK_ADDR_TX_MISC);
1200                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1201                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1202                                        BCM5708S_BLK_ADDR_DIG);
1203                 }
1204         }
1205         return 0;
1206 }
1207
1208 static int
1209 bnx2_init_5706s_phy(struct bnx2 *bp)
1210 {
1211         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1212
1213         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1214                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1215         }
1216
1217         if (bp->dev->mtu > 1500) {
1218                 u32 val;
1219
1220                 /* Set extended packet length bit */
1221                 bnx2_write_phy(bp, 0x18, 0x7);
1222                 bnx2_read_phy(bp, 0x18, &val);
1223                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1224
1225                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1226                 bnx2_read_phy(bp, 0x1c, &val);
1227                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1228         }
1229         else {
1230                 u32 val;
1231
1232                 bnx2_write_phy(bp, 0x18, 0x7);
1233                 bnx2_read_phy(bp, 0x18, &val);
1234                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1235
1236                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1237                 bnx2_read_phy(bp, 0x1c, &val);
1238                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int
1245 bnx2_init_copper_phy(struct bnx2 *bp)
1246 {
1247         u32 val;
1248
1249         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1250
1251         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1252                 bnx2_write_phy(bp, 0x18, 0x0c00);
1253                 bnx2_write_phy(bp, 0x17, 0x000a);
1254                 bnx2_write_phy(bp, 0x15, 0x310b);
1255                 bnx2_write_phy(bp, 0x17, 0x201f);
1256                 bnx2_write_phy(bp, 0x15, 0x9506);
1257                 bnx2_write_phy(bp, 0x17, 0x401f);
1258                 bnx2_write_phy(bp, 0x15, 0x14e2);
1259                 bnx2_write_phy(bp, 0x18, 0x0400);
1260         }
1261
1262         if (bp->dev->mtu > 1500) {
1263                 /* Set extended packet length bit */
1264                 bnx2_write_phy(bp, 0x18, 0x7);
1265                 bnx2_read_phy(bp, 0x18, &val);
1266                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1267
1268                 bnx2_read_phy(bp, 0x10, &val);
1269                 bnx2_write_phy(bp, 0x10, val | 0x1);
1270         }
1271         else {
1272                 bnx2_write_phy(bp, 0x18, 0x7);
1273                 bnx2_read_phy(bp, 0x18, &val);
1274                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1275
1276                 bnx2_read_phy(bp, 0x10, &val);
1277                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1278         }
1279
1280         /* ethernet@wirespeed */
1281         bnx2_write_phy(bp, 0x18, 0x7007);
1282         bnx2_read_phy(bp, 0x18, &val);
1283         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1284         return 0;
1285 }
1286
1287
1288 static int
1289 bnx2_init_phy(struct bnx2 *bp)
1290 {
1291         u32 val;
1292         int rc = 0;
1293
1294         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1295         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1296
1297         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1298
1299         bnx2_reset_phy(bp);
1300
1301         bnx2_read_phy(bp, MII_PHYSID1, &val);
1302         bp->phy_id = val << 16;
1303         bnx2_read_phy(bp, MII_PHYSID2, &val);
1304         bp->phy_id |= val & 0xffff;
1305
1306         if (bp->phy_flags & PHY_SERDES_FLAG) {
1307                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1308                         rc = bnx2_init_5706s_phy(bp);
1309                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1310                         rc = bnx2_init_5708s_phy(bp);
1311         }
1312         else {
1313                 rc = bnx2_init_copper_phy(bp);
1314         }
1315
1316         bnx2_setup_phy(bp);
1317
1318         return rc;
1319 }
1320
1321 static int
1322 bnx2_set_mac_loopback(struct bnx2 *bp)
1323 {
1324         u32 mac_mode;
1325
1326         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1327         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1328         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1329         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1330         bp->link_up = 1;
1331         return 0;
1332 }
1333
1334 static int bnx2_test_link(struct bnx2 *);
1335
1336 static int
1337 bnx2_set_phy_loopback(struct bnx2 *bp)
1338 {
1339         u32 mac_mode;
1340         int rc, i;
1341
1342         spin_lock_bh(&bp->phy_lock);
1343         rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1344                             BMCR_SPEED1000);
1345         spin_unlock_bh(&bp->phy_lock);
1346         if (rc)
1347                 return rc;
1348
1349         for (i = 0; i < 10; i++) {
1350                 if (bnx2_test_link(bp) == 0)
1351                         break;
1352                 udelay(10);
1353         }
1354
1355         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1356         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1357                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1358                       BNX2_EMAC_MODE_25G);
1359
1360         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1361         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1362         bp->link_up = 1;
1363         return 0;
1364 }
1365
1366 static int
1367 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1368 {
1369         int i;
1370         u32 val;
1371
1372         bp->fw_wr_seq++;
1373         msg_data |= bp->fw_wr_seq;
1374
1375         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1376
1377         /* wait for an acknowledgement. */
1378         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1379                 msleep(10);
1380
1381                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1382
1383                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1384                         break;
1385         }
1386         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1387                 return 0;
1388
1389         /* If we timed out, inform the firmware that this is the case. */
1390         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1391                 if (!silent)
1392                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1393                                             "%x\n", msg_data);
1394
1395                 msg_data &= ~BNX2_DRV_MSG_CODE;
1396                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1397
1398                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1399
1400                 return -EBUSY;
1401         }
1402
1403         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1404                 return -EIO;
1405
1406         return 0;
1407 }
1408
1409 static void
1410 bnx2_init_context(struct bnx2 *bp)
1411 {
1412         u32 vcid;
1413
1414         vcid = 96;
1415         while (vcid) {
1416                 u32 vcid_addr, pcid_addr, offset;
1417
1418                 vcid--;
1419
1420                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1421                         u32 new_vcid;
1422
1423                         vcid_addr = GET_PCID_ADDR(vcid);
1424                         if (vcid & 0x8) {
1425                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1426                         }
1427                         else {
1428                                 new_vcid = vcid;
1429                         }
1430                         pcid_addr = GET_PCID_ADDR(new_vcid);
1431                 }
1432                 else {
1433                         vcid_addr = GET_CID_ADDR(vcid);
1434                         pcid_addr = vcid_addr;
1435                 }
1436
1437                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1438                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1439
1440                 /* Zero out the context. */
1441                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1442                         CTX_WR(bp, 0x00, offset, 0);
1443                 }
1444
1445                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1446                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1447         }
1448 }
1449
1450 static int
1451 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1452 {
1453         u16 *good_mbuf;
1454         u32 good_mbuf_cnt;
1455         u32 val;
1456
1457         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1458         if (good_mbuf == NULL) {
1459                 printk(KERN_ERR PFX "Failed to allocate memory in "
1460                                     "bnx2_alloc_bad_rbuf\n");
1461                 return -ENOMEM;
1462         }
1463
1464         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1465                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1466
1467         good_mbuf_cnt = 0;
1468
1469         /* Allocate a bunch of mbufs and save the good ones in an array. */
1470         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1471         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1472                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1473
1474                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1475
1476                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1477
1478                 /* The addresses with Bit 9 set are bad memory blocks. */
1479                 if (!(val & (1 << 9))) {
1480                         good_mbuf[good_mbuf_cnt] = (u16) val;
1481                         good_mbuf_cnt++;
1482                 }
1483
1484                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1485         }
1486
1487         /* Free the good ones back to the mbuf pool thus discarding
1488          * all the bad ones. */
1489         while (good_mbuf_cnt) {
1490                 good_mbuf_cnt--;
1491
1492                 val = good_mbuf[good_mbuf_cnt];
1493                 val = (val << 9) | val | 1;
1494
1495                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1496         }
1497         kfree(good_mbuf);
1498         return 0;
1499 }
1500
1501 static void
1502 bnx2_set_mac_addr(struct bnx2 *bp)
1503 {
1504         u32 val;
1505         u8 *mac_addr = bp->dev->dev_addr;
1506
1507         val = (mac_addr[0] << 8) | mac_addr[1];
1508
1509         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1510
1511         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1512                 (mac_addr[4] << 8) | mac_addr[5];
1513
1514         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1515 }
1516
1517 static inline int
1518 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1519 {
1520         struct sk_buff *skb;
1521         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1522         dma_addr_t mapping;
1523         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1524         unsigned long align;
1525
1526         skb = dev_alloc_skb(bp->rx_buf_size);
1527         if (skb == NULL) {
1528                 return -ENOMEM;
1529         }
1530
1531         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1532                 skb_reserve(skb, 8 - align);
1533         }
1534
1535         skb->dev = bp->dev;
1536         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1537                 PCI_DMA_FROMDEVICE);
1538
1539         rx_buf->skb = skb;
1540         pci_unmap_addr_set(rx_buf, mapping, mapping);
1541
1542         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1543         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1544
1545         bp->rx_prod_bseq += bp->rx_buf_use_size;
1546
1547         return 0;
1548 }
1549
1550 static void
1551 bnx2_phy_int(struct bnx2 *bp)
1552 {
1553         u32 new_link_state, old_link_state;
1554
1555         new_link_state = bp->status_blk->status_attn_bits &
1556                 STATUS_ATTN_BITS_LINK_STATE;
1557         old_link_state = bp->status_blk->status_attn_bits_ack &
1558                 STATUS_ATTN_BITS_LINK_STATE;
1559         if (new_link_state != old_link_state) {
1560                 if (new_link_state) {
1561                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1562                                 STATUS_ATTN_BITS_LINK_STATE);
1563                 }
1564                 else {
1565                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1566                                 STATUS_ATTN_BITS_LINK_STATE);
1567                 }
1568                 bnx2_set_link(bp);
1569         }
1570 }
1571
1572 static void
1573 bnx2_tx_int(struct bnx2 *bp)
1574 {
1575         struct status_block *sblk = bp->status_blk;
1576         u16 hw_cons, sw_cons, sw_ring_cons;
1577         int tx_free_bd = 0;
1578
1579         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1580         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1581                 hw_cons++;
1582         }
1583         sw_cons = bp->tx_cons;
1584
1585         while (sw_cons != hw_cons) {
1586                 struct sw_bd *tx_buf;
1587                 struct sk_buff *skb;
1588                 int i, last;
1589
1590                 sw_ring_cons = TX_RING_IDX(sw_cons);
1591
1592                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1593                 skb = tx_buf->skb;
1594 #ifdef BCM_TSO
1595                 /* partial BD completions possible with TSO packets */
1596                 if (skb_shinfo(skb)->tso_size) {
1597                         u16 last_idx, last_ring_idx;
1598
1599                         last_idx = sw_cons +
1600                                 skb_shinfo(skb)->nr_frags + 1;
1601                         last_ring_idx = sw_ring_cons +
1602                                 skb_shinfo(skb)->nr_frags + 1;
1603                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1604                                 last_idx++;
1605                         }
1606                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1607                                 break;
1608                         }
1609                 }
1610 #endif
1611                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1612                         skb_headlen(skb), PCI_DMA_TODEVICE);
1613
1614                 tx_buf->skb = NULL;
1615                 last = skb_shinfo(skb)->nr_frags;
1616
1617                 for (i = 0; i < last; i++) {
1618                         sw_cons = NEXT_TX_BD(sw_cons);
1619
1620                         pci_unmap_page(bp->pdev,
1621                                 pci_unmap_addr(
1622                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1623                                         mapping),
1624                                 skb_shinfo(skb)->frags[i].size,
1625                                 PCI_DMA_TODEVICE);
1626                 }
1627
1628                 sw_cons = NEXT_TX_BD(sw_cons);
1629
1630                 tx_free_bd += last + 1;
1631
1632                 dev_kfree_skb_irq(skb);
1633
1634                 hw_cons = bp->hw_tx_cons =
1635                         sblk->status_tx_quick_consumer_index0;
1636
1637                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1638                         hw_cons++;
1639                 }
1640         }
1641
1642         bp->tx_cons = sw_cons;
1643
1644         if (unlikely(netif_queue_stopped(bp->dev))) {
1645                 spin_lock(&bp->tx_lock);
1646                 if ((netif_queue_stopped(bp->dev)) &&
1647                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1648
1649                         netif_wake_queue(bp->dev);
1650                 }
1651                 spin_unlock(&bp->tx_lock);
1652         }
1653 }
1654
1655 static inline void
1656 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1657         u16 cons, u16 prod)
1658 {
1659         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1660         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1661         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1662         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1663
1664         pci_dma_sync_single_for_device(bp->pdev,
1665                 pci_unmap_addr(cons_rx_buf, mapping),
1666                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1667
1668         prod_rx_buf->skb = cons_rx_buf->skb;
1669         pci_unmap_addr_set(prod_rx_buf, mapping,
1670                         pci_unmap_addr(cons_rx_buf, mapping));
1671
1672         memcpy(prod_bd, cons_bd, 8);
1673
1674         bp->rx_prod_bseq += bp->rx_buf_use_size;
1675
1676 }
1677
1678 static int
1679 bnx2_rx_int(struct bnx2 *bp, int budget)
1680 {
1681         struct status_block *sblk = bp->status_blk;
1682         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1683         struct l2_fhdr *rx_hdr;
1684         int rx_pkt = 0;
1685
1686         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1687         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1688                 hw_cons++;
1689         }
1690         sw_cons = bp->rx_cons;
1691         sw_prod = bp->rx_prod;
1692
1693         /* Memory barrier necessary as speculative reads of the rx
1694          * buffer can be ahead of the index in the status block
1695          */
1696         rmb();
1697         while (sw_cons != hw_cons) {
1698                 unsigned int len;
1699                 u32 status;
1700                 struct sw_bd *rx_buf;
1701                 struct sk_buff *skb;
1702
1703                 sw_ring_cons = RX_RING_IDX(sw_cons);
1704                 sw_ring_prod = RX_RING_IDX(sw_prod);
1705
1706                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1707                 skb = rx_buf->skb;
1708                 pci_dma_sync_single_for_cpu(bp->pdev,
1709                         pci_unmap_addr(rx_buf, mapping),
1710                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1711
1712                 rx_hdr = (struct l2_fhdr *) skb->data;
1713                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1714
1715                 if ((status = rx_hdr->l2_fhdr_status) &
1716                         (L2_FHDR_ERRORS_BAD_CRC |
1717                         L2_FHDR_ERRORS_PHY_DECODE |
1718                         L2_FHDR_ERRORS_ALIGNMENT |
1719                         L2_FHDR_ERRORS_TOO_SHORT |
1720                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1721
1722                         goto reuse_rx;
1723                 }
1724
1725                 /* Since we don't have a jumbo ring, copy small packets
1726                  * if mtu > 1500
1727                  */
1728                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1729                         struct sk_buff *new_skb;
1730
1731                         new_skb = dev_alloc_skb(len + 2);
1732                         if (new_skb == NULL)
1733                                 goto reuse_rx;
1734
1735                         /* aligned copy */
1736                         memcpy(new_skb->data,
1737                                 skb->data + bp->rx_offset - 2,
1738                                 len + 2);
1739
1740                         skb_reserve(new_skb, 2);
1741                         skb_put(new_skb, len);
1742                         new_skb->dev = bp->dev;
1743
1744                         bnx2_reuse_rx_skb(bp, skb,
1745                                 sw_ring_cons, sw_ring_prod);
1746
1747                         skb = new_skb;
1748                 }
1749                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1750                         pci_unmap_single(bp->pdev,
1751                                 pci_unmap_addr(rx_buf, mapping),
1752                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1753
1754                         skb_reserve(skb, bp->rx_offset);
1755                         skb_put(skb, len);
1756                 }
1757                 else {
1758 reuse_rx:
1759                         bnx2_reuse_rx_skb(bp, skb,
1760                                 sw_ring_cons, sw_ring_prod);
1761                         goto next_rx;
1762                 }
1763
1764                 skb->protocol = eth_type_trans(skb, bp->dev);
1765
1766                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1767                         (htons(skb->protocol) != 0x8100)) {
1768
1769                         dev_kfree_skb_irq(skb);
1770                         goto next_rx;
1771
1772                 }
1773
1774                 skb->ip_summed = CHECKSUM_NONE;
1775                 if (bp->rx_csum &&
1776                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1777                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1778
1779                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1780                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1781                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1782                 }
1783
1784 #ifdef BCM_VLAN
1785                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1786                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1787                                 rx_hdr->l2_fhdr_vlan_tag);
1788                 }
1789                 else
1790 #endif
1791                         netif_receive_skb(skb);
1792
1793                 bp->dev->last_rx = jiffies;
1794                 rx_pkt++;
1795
1796 next_rx:
1797                 rx_buf->skb = NULL;
1798
1799                 sw_cons = NEXT_RX_BD(sw_cons);
1800                 sw_prod = NEXT_RX_BD(sw_prod);
1801
1802                 if ((rx_pkt == budget))
1803                         break;
1804
1805                 /* Refresh hw_cons to see if there is new work */
1806                 if (sw_cons == hw_cons) {
1807                         hw_cons = bp->hw_rx_cons =
1808                                 sblk->status_rx_quick_consumer_index0;
1809                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1810                                 hw_cons++;
1811                         rmb();
1812                 }
1813         }
1814         bp->rx_cons = sw_cons;
1815         bp->rx_prod = sw_prod;
1816
1817         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1818
1819         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1820
1821         mmiowb();
1822
1823         return rx_pkt;
1824
1825 }
1826
1827 /* MSI ISR - The only difference between this and the INTx ISR
1828  * is that the MSI interrupt is always serviced.
1829  */
1830 static irqreturn_t
1831 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1832 {
1833         struct net_device *dev = dev_instance;
1834         struct bnx2 *bp = netdev_priv(dev);
1835
1836         prefetch(bp->status_blk);
1837         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1838                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1839                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1840
1841         /* Return here if interrupt is disabled. */
1842         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1843                 return IRQ_HANDLED;
1844
1845         netif_rx_schedule(dev);
1846
1847         return IRQ_HANDLED;
1848 }
1849
1850 static irqreturn_t
1851 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1852 {
1853         struct net_device *dev = dev_instance;
1854         struct bnx2 *bp = netdev_priv(dev);
1855
1856         /* When using INTx, it is possible for the interrupt to arrive
1857          * at the CPU before the status block posted prior to the
1858          * interrupt. Reading a register will flush the status block.
1859          * When using MSI, the MSI message will always complete after
1860          * the status block write.
1861          */
1862         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1863             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1864              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1865                 return IRQ_NONE;
1866
1867         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1868                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1869                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1870
1871         /* Return here if interrupt is shared and is disabled. */
1872         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1873                 return IRQ_HANDLED;
1874
1875         netif_rx_schedule(dev);
1876
1877         return IRQ_HANDLED;
1878 }
1879
1880 static inline int
1881 bnx2_has_work(struct bnx2 *bp)
1882 {
1883         struct status_block *sblk = bp->status_blk;
1884
1885         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1886             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1887                 return 1;
1888
1889         if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1890             bp->link_up)
1891                 return 1;
1892
1893         return 0;
1894 }
1895
1896 static int
1897 bnx2_poll(struct net_device *dev, int *budget)
1898 {
1899         struct bnx2 *bp = netdev_priv(dev);
1900
1901         if ((bp->status_blk->status_attn_bits &
1902                 STATUS_ATTN_BITS_LINK_STATE) !=
1903                 (bp->status_blk->status_attn_bits_ack &
1904                 STATUS_ATTN_BITS_LINK_STATE)) {
1905
1906                 spin_lock(&bp->phy_lock);
1907                 bnx2_phy_int(bp);
1908                 spin_unlock(&bp->phy_lock);
1909         }
1910
1911         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1912                 bnx2_tx_int(bp);
1913
1914         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1915                 int orig_budget = *budget;
1916                 int work_done;
1917
1918                 if (orig_budget > dev->quota)
1919                         orig_budget = dev->quota;
1920
1921                 work_done = bnx2_rx_int(bp, orig_budget);
1922                 *budget -= work_done;
1923                 dev->quota -= work_done;
1924         }
1925
1926         bp->last_status_idx = bp->status_blk->status_idx;
1927         rmb();
1928
1929         if (!bnx2_has_work(bp)) {
1930                 netif_rx_complete(dev);
1931                 if (likely(bp->flags & USING_MSI_FLAG)) {
1932                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1933                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1934                                bp->last_status_idx);
1935                         return 0;
1936                 }
1937                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1938                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1939                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
1940                        bp->last_status_idx);
1941
1942                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1943                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1944                        bp->last_status_idx);
1945                 return 0;
1946         }
1947
1948         return 1;
1949 }
1950
1951 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1952  * from set_multicast.
1953  */
1954 static void
1955 bnx2_set_rx_mode(struct net_device *dev)
1956 {
1957         struct bnx2 *bp = netdev_priv(dev);
1958         u32 rx_mode, sort_mode;
1959         int i;
1960
1961         spin_lock_bh(&bp->phy_lock);
1962
1963         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1964                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1965         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1966 #ifdef BCM_VLAN
1967         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1968                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1969 #else
1970         if (!(bp->flags & ASF_ENABLE_FLAG))
1971                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1972 #endif
1973         if (dev->flags & IFF_PROMISC) {
1974                 /* Promiscuous mode. */
1975                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1976                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1977         }
1978         else if (dev->flags & IFF_ALLMULTI) {
1979                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1980                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1981                                0xffffffff);
1982                 }
1983                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1984         }
1985         else {
1986                 /* Accept one or more multicast(s). */
1987                 struct dev_mc_list *mclist;
1988                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1989                 u32 regidx;
1990                 u32 bit;
1991                 u32 crc;
1992
1993                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1994
1995                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1996                      i++, mclist = mclist->next) {
1997
1998                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1999                         bit = crc & 0xff;
2000                         regidx = (bit & 0xe0) >> 5;
2001                         bit &= 0x1f;
2002                         mc_filter[regidx] |= (1 << bit);
2003                 }
2004
2005                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2006                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2007                                mc_filter[i]);
2008                 }
2009
2010                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2011         }
2012
2013         if (rx_mode != bp->rx_mode) {
2014                 bp->rx_mode = rx_mode;
2015                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2016         }
2017
2018         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2019         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2020         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2021
2022         spin_unlock_bh(&bp->phy_lock);
2023 }
2024
2025 static void
2026 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2027         u32 rv2p_proc)
2028 {
2029         int i;
2030         u32 val;
2031
2032
2033         for (i = 0; i < rv2p_code_len; i += 8) {
2034                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
2035                 rv2p_code++;
2036                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
2037                 rv2p_code++;
2038
2039                 if (rv2p_proc == RV2P_PROC1) {
2040                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2041                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2042                 }
2043                 else {
2044                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2045                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2046                 }
2047         }
2048
2049         /* Reset the processor, un-stall is done later. */
2050         if (rv2p_proc == RV2P_PROC1) {
2051                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2052         }
2053         else {
2054                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2055         }
2056 }
2057
2058 static void
2059 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2060 {
2061         u32 offset;
2062         u32 val;
2063
2064         /* Halt the CPU. */
2065         val = REG_RD_IND(bp, cpu_reg->mode);
2066         val |= cpu_reg->mode_value_halt;
2067         REG_WR_IND(bp, cpu_reg->mode, val);
2068         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2069
2070         /* Load the Text area. */
2071         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2072         if (fw->text) {
2073                 int j;
2074
2075                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2076                         REG_WR_IND(bp, offset, fw->text[j]);
2077                 }
2078         }
2079
2080         /* Load the Data area. */
2081         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2082         if (fw->data) {
2083                 int j;
2084
2085                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2086                         REG_WR_IND(bp, offset, fw->data[j]);
2087                 }
2088         }
2089
2090         /* Load the SBSS area. */
2091         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2092         if (fw->sbss) {
2093                 int j;
2094
2095                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2096                         REG_WR_IND(bp, offset, fw->sbss[j]);
2097                 }
2098         }
2099
2100         /* Load the BSS area. */
2101         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2102         if (fw->bss) {
2103                 int j;
2104
2105                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2106                         REG_WR_IND(bp, offset, fw->bss[j]);
2107                 }
2108         }
2109
2110         /* Load the Read-Only area. */
2111         offset = cpu_reg->spad_base +
2112                 (fw->rodata_addr - cpu_reg->mips_view_base);
2113         if (fw->rodata) {
2114                 int j;
2115
2116                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2117                         REG_WR_IND(bp, offset, fw->rodata[j]);
2118                 }
2119         }
2120
2121         /* Clear the pre-fetch instruction. */
2122         REG_WR_IND(bp, cpu_reg->inst, 0);
2123         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2124
2125         /* Start the CPU. */
2126         val = REG_RD_IND(bp, cpu_reg->mode);
2127         val &= ~cpu_reg->mode_value_halt;
2128         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2129         REG_WR_IND(bp, cpu_reg->mode, val);
2130 }
2131
2132 static void
2133 bnx2_init_cpus(struct bnx2 *bp)
2134 {
2135         struct cpu_reg cpu_reg;
2136         struct fw_info fw;
2137
2138         /* Initialize the RV2P processor. */
2139         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2140         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2141
2142         /* Initialize the RX Processor. */
2143         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2144         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2145         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2146         cpu_reg.state = BNX2_RXP_CPU_STATE;
2147         cpu_reg.state_value_clear = 0xffffff;
2148         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2149         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2150         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2151         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2152         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2153         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2154         cpu_reg.mips_view_base = 0x8000000;
2155
2156         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2157         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2158         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2159         fw.start_addr = bnx2_RXP_b06FwStartAddr;
2160
2161         fw.text_addr = bnx2_RXP_b06FwTextAddr;
2162         fw.text_len = bnx2_RXP_b06FwTextLen;
2163         fw.text_index = 0;
2164         fw.text = bnx2_RXP_b06FwText;
2165
2166         fw.data_addr = bnx2_RXP_b06FwDataAddr;
2167         fw.data_len = bnx2_RXP_b06FwDataLen;
2168         fw.data_index = 0;
2169         fw.data = bnx2_RXP_b06FwData;
2170
2171         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2172         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2173         fw.sbss_index = 0;
2174         fw.sbss = bnx2_RXP_b06FwSbss;
2175
2176         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2177         fw.bss_len = bnx2_RXP_b06FwBssLen;
2178         fw.bss_index = 0;
2179         fw.bss = bnx2_RXP_b06FwBss;
2180
2181         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2182         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2183         fw.rodata_index = 0;
2184         fw.rodata = bnx2_RXP_b06FwRodata;
2185
2186         load_cpu_fw(bp, &cpu_reg, &fw);
2187
2188         /* Initialize the TX Processor. */
2189         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2190         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2191         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2192         cpu_reg.state = BNX2_TXP_CPU_STATE;
2193         cpu_reg.state_value_clear = 0xffffff;
2194         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2195         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2196         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2197         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2198         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2199         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2200         cpu_reg.mips_view_base = 0x8000000;
2201
2202         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2203         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2204         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2205         fw.start_addr = bnx2_TXP_b06FwStartAddr;
2206
2207         fw.text_addr = bnx2_TXP_b06FwTextAddr;
2208         fw.text_len = bnx2_TXP_b06FwTextLen;
2209         fw.text_index = 0;
2210         fw.text = bnx2_TXP_b06FwText;
2211
2212         fw.data_addr = bnx2_TXP_b06FwDataAddr;
2213         fw.data_len = bnx2_TXP_b06FwDataLen;
2214         fw.data_index = 0;
2215         fw.data = bnx2_TXP_b06FwData;
2216
2217         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2218         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2219         fw.sbss_index = 0;
2220         fw.sbss = bnx2_TXP_b06FwSbss;
2221
2222         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2223         fw.bss_len = bnx2_TXP_b06FwBssLen;
2224         fw.bss_index = 0;
2225         fw.bss = bnx2_TXP_b06FwBss;
2226
2227         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2228         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2229         fw.rodata_index = 0;
2230         fw.rodata = bnx2_TXP_b06FwRodata;
2231
2232         load_cpu_fw(bp, &cpu_reg, &fw);
2233
2234         /* Initialize the TX Patch-up Processor. */
2235         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2236         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2237         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2238         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2239         cpu_reg.state_value_clear = 0xffffff;
2240         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2241         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2242         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2243         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2244         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2245         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2246         cpu_reg.mips_view_base = 0x8000000;
2247
2248         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2249         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2250         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2251         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2252
2253         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2254         fw.text_len = bnx2_TPAT_b06FwTextLen;
2255         fw.text_index = 0;
2256         fw.text = bnx2_TPAT_b06FwText;
2257
2258         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2259         fw.data_len = bnx2_TPAT_b06FwDataLen;
2260         fw.data_index = 0;
2261         fw.data = bnx2_TPAT_b06FwData;
2262
2263         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2264         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2265         fw.sbss_index = 0;
2266         fw.sbss = bnx2_TPAT_b06FwSbss;
2267
2268         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2269         fw.bss_len = bnx2_TPAT_b06FwBssLen;
2270         fw.bss_index = 0;
2271         fw.bss = bnx2_TPAT_b06FwBss;
2272
2273         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2274         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2275         fw.rodata_index = 0;
2276         fw.rodata = bnx2_TPAT_b06FwRodata;
2277
2278         load_cpu_fw(bp, &cpu_reg, &fw);
2279
2280         /* Initialize the Completion Processor. */
2281         cpu_reg.mode = BNX2_COM_CPU_MODE;
2282         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2283         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2284         cpu_reg.state = BNX2_COM_CPU_STATE;
2285         cpu_reg.state_value_clear = 0xffffff;
2286         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2287         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2288         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2289         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2290         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2291         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2292         cpu_reg.mips_view_base = 0x8000000;
2293
2294         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2295         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2296         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2297         fw.start_addr = bnx2_COM_b06FwStartAddr;
2298
2299         fw.text_addr = bnx2_COM_b06FwTextAddr;
2300         fw.text_len = bnx2_COM_b06FwTextLen;
2301         fw.text_index = 0;
2302         fw.text = bnx2_COM_b06FwText;
2303
2304         fw.data_addr = bnx2_COM_b06FwDataAddr;
2305         fw.data_len = bnx2_COM_b06FwDataLen;
2306         fw.data_index = 0;
2307         fw.data = bnx2_COM_b06FwData;
2308
2309         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2310         fw.sbss_len = bnx2_COM_b06FwSbssLen;
2311         fw.sbss_index = 0;
2312         fw.sbss = bnx2_COM_b06FwSbss;
2313
2314         fw.bss_addr = bnx2_COM_b06FwBssAddr;
2315         fw.bss_len = bnx2_COM_b06FwBssLen;
2316         fw.bss_index = 0;
2317         fw.bss = bnx2_COM_b06FwBss;
2318
2319         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2320         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2321         fw.rodata_index = 0;
2322         fw.rodata = bnx2_COM_b06FwRodata;
2323
2324         load_cpu_fw(bp, &cpu_reg, &fw);
2325
2326 }
2327
2328 static int
2329 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2330 {
2331         u16 pmcsr;
2332
2333         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2334
2335         switch (state) {
2336         case PCI_D0: {
2337                 u32 val;
2338
2339                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2340                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2341                         PCI_PM_CTRL_PME_STATUS);
2342
2343                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2344                         /* delay required during transition out of D3hot */
2345                         msleep(20);
2346
2347                 val = REG_RD(bp, BNX2_EMAC_MODE);
2348                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2349                 val &= ~BNX2_EMAC_MODE_MPKT;
2350                 REG_WR(bp, BNX2_EMAC_MODE, val);
2351
2352                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2353                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2354                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2355                 break;
2356         }
2357         case PCI_D3hot: {
2358                 int i;
2359                 u32 val, wol_msg;
2360
2361                 if (bp->wol) {
2362                         u32 advertising;
2363                         u8 autoneg;
2364
2365                         autoneg = bp->autoneg;
2366                         advertising = bp->advertising;
2367
2368                         bp->autoneg = AUTONEG_SPEED;
2369                         bp->advertising = ADVERTISED_10baseT_Half |
2370                                 ADVERTISED_10baseT_Full |
2371                                 ADVERTISED_100baseT_Half |
2372                                 ADVERTISED_100baseT_Full |
2373                                 ADVERTISED_Autoneg;
2374
2375                         bnx2_setup_copper_phy(bp);
2376
2377                         bp->autoneg = autoneg;
2378                         bp->advertising = advertising;
2379
2380                         bnx2_set_mac_addr(bp);
2381
2382                         val = REG_RD(bp, BNX2_EMAC_MODE);
2383
2384                         /* Enable port mode. */
2385                         val &= ~BNX2_EMAC_MODE_PORT;
2386                         val |= BNX2_EMAC_MODE_PORT_MII |
2387                                BNX2_EMAC_MODE_MPKT_RCVD |
2388                                BNX2_EMAC_MODE_ACPI_RCVD |
2389                                BNX2_EMAC_MODE_MPKT;
2390
2391                         REG_WR(bp, BNX2_EMAC_MODE, val);
2392
2393                         /* receive all multicast */
2394                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2395                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2396                                        0xffffffff);
2397                         }
2398                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2399                                BNX2_EMAC_RX_MODE_SORT_MODE);
2400
2401                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2402                               BNX2_RPM_SORT_USER0_MC_EN;
2403                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2404                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2405                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2406                                BNX2_RPM_SORT_USER0_ENA);
2407
2408                         /* Need to enable EMAC and RPM for WOL. */
2409                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2410                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2411                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2412                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2413
2414                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2415                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2416                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2417
2418                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2419                 }
2420                 else {
2421                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2422                 }
2423
2424                 if (!(bp->flags & NO_WOL_FLAG))
2425                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2426
2427                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2428                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2429                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2430
2431                         if (bp->wol)
2432                                 pmcsr |= 3;
2433                 }
2434                 else {
2435                         pmcsr |= 3;
2436                 }
2437                 if (bp->wol) {
2438                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2439                 }
2440                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2441                                       pmcsr);
2442
2443                 /* No more memory access after this point until
2444                  * device is brought back to D0.
2445                  */
2446                 udelay(50);
2447                 break;
2448         }
2449         default:
2450                 return -EINVAL;
2451         }
2452         return 0;
2453 }
2454
2455 static int
2456 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2457 {
2458         u32 val;
2459         int j;
2460
2461         /* Request access to the flash interface. */
2462         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2463         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2464                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2465                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2466                         break;
2467
2468                 udelay(5);
2469         }
2470
2471         if (j >= NVRAM_TIMEOUT_COUNT)
2472                 return -EBUSY;
2473
2474         return 0;
2475 }
2476
2477 static int
2478 bnx2_release_nvram_lock(struct bnx2 *bp)
2479 {
2480         int j;
2481         u32 val;
2482
2483         /* Relinquish nvram interface. */
2484         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2485
2486         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2487                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2488                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2489                         break;
2490
2491                 udelay(5);
2492         }
2493
2494         if (j >= NVRAM_TIMEOUT_COUNT)
2495                 return -EBUSY;
2496
2497         return 0;
2498 }
2499
2500
2501 static int
2502 bnx2_enable_nvram_write(struct bnx2 *bp)
2503 {
2504         u32 val;
2505
2506         val = REG_RD(bp, BNX2_MISC_CFG);
2507         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2508
2509         if (!bp->flash_info->buffered) {
2510                 int j;
2511
2512                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2513                 REG_WR(bp, BNX2_NVM_COMMAND,
2514                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2515
2516                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2517                         udelay(5);
2518
2519                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2520                         if (val & BNX2_NVM_COMMAND_DONE)
2521                                 break;
2522                 }
2523
2524                 if (j >= NVRAM_TIMEOUT_COUNT)
2525                         return -EBUSY;
2526         }
2527         return 0;
2528 }
2529
2530 static void
2531 bnx2_disable_nvram_write(struct bnx2 *bp)
2532 {
2533         u32 val;
2534
2535         val = REG_RD(bp, BNX2_MISC_CFG);
2536         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2537 }
2538
2539
2540 static void
2541 bnx2_enable_nvram_access(struct bnx2 *bp)
2542 {
2543         u32 val;
2544
2545         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2546         /* Enable both bits, even on read. */
2547         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2548                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2549 }
2550
2551 static void
2552 bnx2_disable_nvram_access(struct bnx2 *bp)
2553 {
2554         u32 val;
2555
2556         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2557         /* Disable both bits, even after read. */
2558         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2559                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2560                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2561 }
2562
2563 static int
2564 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2565 {
2566         u32 cmd;
2567         int j;
2568
2569         if (bp->flash_info->buffered)
2570                 /* Buffered flash, no erase needed */
2571                 return 0;
2572
2573         /* Build an erase command */
2574         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2575               BNX2_NVM_COMMAND_DOIT;
2576
2577         /* Need to clear DONE bit separately. */
2578         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2579
2580         /* Address of the NVRAM to read from. */
2581         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2582
2583         /* Issue an erase command. */
2584         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2585
2586         /* Wait for completion. */
2587         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2588                 u32 val;
2589
2590                 udelay(5);
2591
2592                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2593                 if (val & BNX2_NVM_COMMAND_DONE)
2594                         break;
2595         }
2596
2597         if (j >= NVRAM_TIMEOUT_COUNT)
2598                 return -EBUSY;
2599
2600         return 0;
2601 }
2602
2603 static int
2604 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2605 {
2606         u32 cmd;
2607         int j;
2608
2609         /* Build the command word. */
2610         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2611
2612         /* Calculate an offset of a buffered flash. */
2613         if (bp->flash_info->buffered) {
2614                 offset = ((offset / bp->flash_info->page_size) <<
2615                            bp->flash_info->page_bits) +
2616                           (offset % bp->flash_info->page_size);
2617         }
2618
2619         /* Need to clear DONE bit separately. */
2620         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2621
2622         /* Address of the NVRAM to read from. */
2623         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2624
2625         /* Issue a read command. */
2626         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2627
2628         /* Wait for completion. */
2629         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2630                 u32 val;
2631
2632                 udelay(5);
2633
2634                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2635                 if (val & BNX2_NVM_COMMAND_DONE) {
2636                         val = REG_RD(bp, BNX2_NVM_READ);
2637
2638                         val = be32_to_cpu(val);
2639                         memcpy(ret_val, &val, 4);
2640                         break;
2641                 }
2642         }
2643         if (j >= NVRAM_TIMEOUT_COUNT)
2644                 return -EBUSY;
2645
2646         return 0;
2647 }
2648
2649
2650 static int
2651 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2652 {
2653         u32 cmd, val32;
2654         int j;
2655
2656         /* Build the command word. */
2657         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2658
2659         /* Calculate an offset of a buffered flash. */
2660         if (bp->flash_info->buffered) {
2661                 offset = ((offset / bp->flash_info->page_size) <<
2662                           bp->flash_info->page_bits) +
2663                          (offset % bp->flash_info->page_size);
2664         }
2665
2666         /* Need to clear DONE bit separately. */
2667         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2668
2669         memcpy(&val32, val, 4);
2670         val32 = cpu_to_be32(val32);
2671
2672         /* Write the data. */
2673         REG_WR(bp, BNX2_NVM_WRITE, val32);
2674
2675         /* Address of the NVRAM to write to. */
2676         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2677
2678         /* Issue the write command. */
2679         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2680
2681         /* Wait for completion. */
2682         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2683                 udelay(5);
2684
2685                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2686                         break;
2687         }
2688         if (j >= NVRAM_TIMEOUT_COUNT)
2689                 return -EBUSY;
2690
2691         return 0;
2692 }
2693
2694 static int
2695 bnx2_init_nvram(struct bnx2 *bp)
2696 {
2697         u32 val;
2698         int j, entry_count, rc;
2699         struct flash_spec *flash;
2700
2701         /* Determine the selected interface. */
2702         val = REG_RD(bp, BNX2_NVM_CFG1);
2703
2704         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2705
2706         rc = 0;
2707         if (val & 0x40000000) {
2708
2709                 /* Flash interface has been reconfigured */
2710                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2711                      j++, flash++) {
2712                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2713                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2714                                 bp->flash_info = flash;
2715                                 break;
2716                         }
2717                 }
2718         }
2719         else {
2720                 u32 mask;
2721                 /* Not yet been reconfigured */
2722
2723                 if (val & (1 << 23))
2724                         mask = FLASH_BACKUP_STRAP_MASK;
2725                 else
2726                         mask = FLASH_STRAP_MASK;
2727
2728                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2729                         j++, flash++) {
2730
2731                         if ((val & mask) == (flash->strapping & mask)) {
2732                                 bp->flash_info = flash;
2733
2734                                 /* Request access to the flash interface. */
2735                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2736                                         return rc;
2737
2738                                 /* Enable access to flash interface */
2739                                 bnx2_enable_nvram_access(bp);
2740
2741                                 /* Reconfigure the flash interface */
2742                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2743                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2744                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2745                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2746
2747                                 /* Disable access to flash interface */
2748                                 bnx2_disable_nvram_access(bp);
2749                                 bnx2_release_nvram_lock(bp);
2750
2751                                 break;
2752                         }
2753                 }
2754         } /* if (val & 0x40000000) */
2755
2756         if (j == entry_count) {
2757                 bp->flash_info = NULL;
2758                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2759                 return -ENODEV;
2760         }
2761
2762         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2763         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2764         if (val)
2765                 bp->flash_size = val;
2766         else
2767                 bp->flash_size = bp->flash_info->total_size;
2768
2769         return rc;
2770 }
2771
2772 static int
2773 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2774                 int buf_size)
2775 {
2776         int rc = 0;
2777         u32 cmd_flags, offset32, len32, extra;
2778
2779         if (buf_size == 0)
2780                 return 0;
2781
2782         /* Request access to the flash interface. */
2783         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2784                 return rc;
2785
2786         /* Enable access to flash interface */
2787         bnx2_enable_nvram_access(bp);
2788
2789         len32 = buf_size;
2790         offset32 = offset;
2791         extra = 0;
2792
2793         cmd_flags = 0;
2794
2795         if (offset32 & 3) {
2796                 u8 buf[4];
2797                 u32 pre_len;
2798
2799                 offset32 &= ~3;
2800                 pre_len = 4 - (offset & 3);
2801
2802                 if (pre_len >= len32) {
2803                         pre_len = len32;
2804                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2805                                     BNX2_NVM_COMMAND_LAST;
2806                 }
2807                 else {
2808                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2809                 }
2810
2811                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2812
2813                 if (rc)
2814                         return rc;
2815
2816                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2817
2818                 offset32 += 4;
2819                 ret_buf += pre_len;
2820                 len32 -= pre_len;
2821         }
2822         if (len32 & 3) {
2823                 extra = 4 - (len32 & 3);
2824                 len32 = (len32 + 4) & ~3;
2825         }
2826
2827         if (len32 == 4) {
2828                 u8 buf[4];
2829
2830                 if (cmd_flags)
2831                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2832                 else
2833                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2834                                     BNX2_NVM_COMMAND_LAST;
2835
2836                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2837
2838                 memcpy(ret_buf, buf, 4 - extra);
2839         }
2840         else if (len32 > 0) {
2841                 u8 buf[4];
2842
2843                 /* Read the first word. */
2844                 if (cmd_flags)
2845                         cmd_flags = 0;
2846                 else
2847                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2848
2849                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2850
2851                 /* Advance to the next dword. */
2852                 offset32 += 4;
2853                 ret_buf += 4;
2854                 len32 -= 4;
2855
2856                 while (len32 > 4 && rc == 0) {
2857                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2858
2859                         /* Advance to the next dword. */
2860                         offset32 += 4;
2861                         ret_buf += 4;
2862                         len32 -= 4;
2863                 }
2864
2865                 if (rc)
2866                         return rc;
2867
2868                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2869                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2870
2871                 memcpy(ret_buf, buf, 4 - extra);
2872         }
2873
2874         /* Disable access to flash interface */
2875         bnx2_disable_nvram_access(bp);
2876
2877         bnx2_release_nvram_lock(bp);
2878
2879         return rc;
2880 }
2881
2882 static int
2883 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2884                 int buf_size)
2885 {
2886         u32 written, offset32, len32;
2887         u8 *buf, start[4], end[4];
2888         int rc = 0;
2889         int align_start, align_end;
2890
2891         buf = data_buf;
2892         offset32 = offset;
2893         len32 = buf_size;
2894         align_start = align_end = 0;
2895
2896         if ((align_start = (offset32 & 3))) {
2897                 offset32 &= ~3;
2898                 len32 += align_start;
2899                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2900                         return rc;
2901         }
2902
2903         if (len32 & 3) {
2904                 if ((len32 > 4) || !align_start) {
2905                         align_end = 4 - (len32 & 3);
2906                         len32 += align_end;
2907                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2908                                 end, 4))) {
2909                                 return rc;
2910                         }
2911                 }
2912         }
2913
2914         if (align_start || align_end) {
2915                 buf = kmalloc(len32, GFP_KERNEL);
2916                 if (buf == 0)
2917                         return -ENOMEM;
2918                 if (align_start) {
2919                         memcpy(buf, start, 4);
2920                 }
2921                 if (align_end) {
2922                         memcpy(buf + len32 - 4, end, 4);
2923                 }
2924                 memcpy(buf + align_start, data_buf, buf_size);
2925         }
2926
2927         written = 0;
2928         while ((written < len32) && (rc == 0)) {
2929                 u32 page_start, page_end, data_start, data_end;
2930                 u32 addr, cmd_flags;
2931                 int i;
2932                 u8 flash_buffer[264];
2933
2934                 /* Find the page_start addr */
2935                 page_start = offset32 + written;
2936                 page_start -= (page_start % bp->flash_info->page_size);
2937                 /* Find the page_end addr */
2938                 page_end = page_start + bp->flash_info->page_size;
2939                 /* Find the data_start addr */
2940                 data_start = (written == 0) ? offset32 : page_start;
2941                 /* Find the data_end addr */
2942                 data_end = (page_end > offset32 + len32) ?
2943                         (offset32 + len32) : page_end;
2944
2945                 /* Request access to the flash interface. */
2946                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2947                         goto nvram_write_end;
2948
2949                 /* Enable access to flash interface */
2950                 bnx2_enable_nvram_access(bp);
2951
2952                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2953                 if (bp->flash_info->buffered == 0) {
2954                         int j;
2955
2956                         /* Read the whole page into the buffer
2957                          * (non-buffer flash only) */
2958                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2959                                 if (j == (bp->flash_info->page_size - 4)) {
2960                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2961                                 }
2962                                 rc = bnx2_nvram_read_dword(bp,
2963                                         page_start + j,
2964                                         &flash_buffer[j],
2965                                         cmd_flags);
2966
2967                                 if (rc)
2968                                         goto nvram_write_end;
2969
2970                                 cmd_flags = 0;
2971                         }
2972                 }
2973
2974                 /* Enable writes to flash interface (unlock write-protect) */
2975                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2976                         goto nvram_write_end;
2977
2978                 /* Erase the page */
2979                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2980                         goto nvram_write_end;
2981
2982                 /* Re-enable the write again for the actual write */
2983                 bnx2_enable_nvram_write(bp);
2984
2985                 /* Loop to write back the buffer data from page_start to
2986                  * data_start */
2987                 i = 0;
2988                 if (bp->flash_info->buffered == 0) {
2989                         for (addr = page_start; addr < data_start;
2990                                 addr += 4, i += 4) {
2991
2992                                 rc = bnx2_nvram_write_dword(bp, addr,
2993                                         &flash_buffer[i], cmd_flags);
2994
2995                                 if (rc != 0)
2996                                         goto nvram_write_end;
2997
2998                                 cmd_flags = 0;
2999                         }
3000                 }
3001
3002                 /* Loop to write the new data from data_start to data_end */
3003                 for (addr = data_start; addr < data_end; addr += 4, i++) {
3004                         if ((addr == page_end - 4) ||
3005                                 ((bp->flash_info->buffered) &&
3006                                  (addr == data_end - 4))) {
3007
3008                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3009                         }
3010                         rc = bnx2_nvram_write_dword(bp, addr, buf,
3011                                 cmd_flags);
3012
3013                         if (rc != 0)
3014                                 goto nvram_write_end;
3015
3016                         cmd_flags = 0;
3017                         buf += 4;
3018                 }
3019
3020                 /* Loop to write back the buffer data from data_end
3021                  * to page_end */
3022                 if (bp->flash_info->buffered == 0) {
3023                         for (addr = data_end; addr < page_end;
3024                                 addr += 4, i += 4) {
3025
3026                                 if (addr == page_end-4) {
3027                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3028                                 }
3029                                 rc = bnx2_nvram_write_dword(bp, addr,
3030                                         &flash_buffer[i], cmd_flags);
3031
3032                                 if (rc != 0)
3033                                         goto nvram_write_end;
3034
3035                                 cmd_flags = 0;
3036                         }
3037                 }
3038
3039                 /* Disable writes to flash interface (lock write-protect) */
3040                 bnx2_disable_nvram_write(bp);
3041
3042                 /* Disable access to flash interface */
3043                 bnx2_disable_nvram_access(bp);
3044                 bnx2_release_nvram_lock(bp);
3045
3046                 /* Increment written */
3047                 written += data_end - data_start;
3048         }
3049
3050 nvram_write_end:
3051         if (align_start || align_end)
3052                 kfree(buf);
3053         return rc;
3054 }
3055
3056 static int
3057 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3058 {
3059         u32 val;
3060         int i, rc = 0;
3061
3062         /* Wait for the current PCI transaction to complete before
3063          * issuing a reset. */
3064         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3065                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3066                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3067                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3068                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3069         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3070         udelay(5);
3071
3072         /* Wait for the firmware to tell us it is ok to issue a reset. */
3073         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3074
3075         /* Deposit a driver reset signature so the firmware knows that
3076          * this is a soft reset. */
3077         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3078                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3079
3080         /* Do a dummy read to force the chip to complete all current transaction
3081          * before we issue a reset. */
3082         val = REG_RD(bp, BNX2_MISC_ID);
3083
3084         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3085               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3086               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3087
3088         /* Chip reset. */
3089         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3090
3091         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3092             (CHIP_ID(bp) == CHIP_ID_5706_A1))
3093                 msleep(15);
3094
3095         /* Reset takes approximate 30 usec */
3096         for (i = 0; i < 10; i++) {
3097                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3098                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3099                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3100                         break;
3101                 }
3102                 udelay(10);
3103         }
3104
3105         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3106                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3107                 printk(KERN_ERR PFX "Chip reset did not complete\n");
3108                 return -EBUSY;
3109         }
3110
3111         /* Make sure byte swapping is properly configured. */
3112         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3113         if (val != 0x01020304) {
3114                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3115                 return -ENODEV;
3116         }
3117
3118         /* Wait for the firmware to finish its initialization. */
3119         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3120         if (rc)
3121                 return rc;
3122
3123         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3124                 /* Adjust the voltage regular to two steps lower.  The default
3125                  * of this register is 0x0000000e. */
3126                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3127
3128                 /* Remove bad rbuf memory from the free pool. */
3129                 rc = bnx2_alloc_bad_rbuf(bp);
3130         }
3131
3132         return rc;
3133 }
3134
3135 static int
3136 bnx2_init_chip(struct bnx2 *bp)
3137 {
3138         u32 val;
3139         int rc;
3140
3141         /* Make sure the interrupt is not active. */
3142         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3143
3144         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3145               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3146 #ifdef __BIG_ENDIAN
3147               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3148 #endif
3149               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3150               DMA_READ_CHANS << 12 |
3151               DMA_WRITE_CHANS << 16;
3152
3153         val |= (0x2 << 20) | (1 << 11);
3154
3155         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3156                 val |= (1 << 23);
3157
3158         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3159             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3160                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3161
3162         REG_WR(bp, BNX2_DMA_CONFIG, val);
3163
3164         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3165                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3166                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3167                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3168         }
3169
3170         if (bp->flags & PCIX_FLAG) {
3171                 u16 val16;
3172
3173                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3174                                      &val16);
3175                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3176                                       val16 & ~PCI_X_CMD_ERO);
3177         }
3178
3179         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3180                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3181                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3182                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3183
3184         /* Initialize context mapping and zero out the quick contexts.  The
3185          * context block must have already been enabled. */
3186         bnx2_init_context(bp);
3187
3188         bnx2_init_cpus(bp);
3189         bnx2_init_nvram(bp);
3190
3191         bnx2_set_mac_addr(bp);
3192
3193         val = REG_RD(bp, BNX2_MQ_CONFIG);
3194         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3195         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3196         REG_WR(bp, BNX2_MQ_CONFIG, val);
3197
3198         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3199         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3200         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3201
3202         val = (BCM_PAGE_BITS - 8) << 24;
3203         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3204
3205         /* Configure page size. */
3206         val = REG_RD(bp, BNX2_TBDR_CONFIG);
3207         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3208         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3209         REG_WR(bp, BNX2_TBDR_CONFIG, val);
3210
3211         val = bp->mac_addr[0] +
3212               (bp->mac_addr[1] << 8) +
3213               (bp->mac_addr[2] << 16) +
3214               bp->mac_addr[3] +
3215               (bp->mac_addr[4] << 8) +
3216               (bp->mac_addr[5] << 16);
3217         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3218
3219         /* Program the MTU.  Also include 4 bytes for CRC32. */
3220         val = bp->dev->mtu + ETH_HLEN + 4;
3221         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3222                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3223         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3224
3225         bp->last_status_idx = 0;
3226         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3227
3228         /* Set up how to generate a link change interrupt. */
3229         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3230
3231         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3232                (u64) bp->status_blk_mapping & 0xffffffff);
3233         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3234
3235         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3236                (u64) bp->stats_blk_mapping & 0xffffffff);
3237         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3238                (u64) bp->stats_blk_mapping >> 32);
3239
3240         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3241                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3242
3243         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3244                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3245
3246         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3247                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3248
3249         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3250
3251         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3252
3253         REG_WR(bp, BNX2_HC_COM_TICKS,
3254                (bp->com_ticks_int << 16) | bp->com_ticks);
3255
3256         REG_WR(bp, BNX2_HC_CMD_TICKS,
3257                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3258
3259         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3260         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
3261
3262         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3263                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3264         else {
3265                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3266                        BNX2_HC_CONFIG_TX_TMR_MODE |
3267                        BNX2_HC_CONFIG_COLLECT_STATS);
3268         }
3269
3270         /* Clear internal stats counters. */
3271         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3272
3273         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3274
3275         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3276             BNX2_PORT_FEATURE_ASF_ENABLED)
3277                 bp->flags |= ASF_ENABLE_FLAG;
3278
3279         /* Initialize the receive filter. */
3280         bnx2_set_rx_mode(bp->dev);
3281
3282         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3283                           0);
3284
3285         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3286         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3287
3288         udelay(20);
3289
3290         return rc;
3291 }
3292
3293
3294 static void
3295 bnx2_init_tx_ring(struct bnx2 *bp)
3296 {
3297         struct tx_bd *txbd;
3298         u32 val;
3299
3300         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3301
3302         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3303         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3304
3305         bp->tx_prod = 0;
3306         bp->tx_cons = 0;
3307         bp->hw_tx_cons = 0;
3308         bp->tx_prod_bseq = 0;
3309
3310         val = BNX2_L2CTX_TYPE_TYPE_L2;
3311         val |= BNX2_L2CTX_TYPE_SIZE_L2;
3312         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3313
3314         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3315         val |= 8 << 16;
3316         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3317
3318         val = (u64) bp->tx_desc_mapping >> 32;
3319         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3320
3321         val = (u64) bp->tx_desc_mapping & 0xffffffff;
3322         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3323 }
3324
3325 static void
3326 bnx2_init_rx_ring(struct bnx2 *bp)
3327 {
3328         struct rx_bd *rxbd;
3329         int i;
3330         u16 prod, ring_prod;
3331         u32 val;
3332
3333         /* 8 for CRC and VLAN */
3334         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3335         /* 8 for alignment */
3336         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3337
3338         ring_prod = prod = bp->rx_prod = 0;
3339         bp->rx_cons = 0;
3340         bp->hw_rx_cons = 0;
3341         bp->rx_prod_bseq = 0;
3342
3343         rxbd = &bp->rx_desc_ring[0];
3344         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3345                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3346             &nbs