1e5407d44dfd5610aa3e3ce1546cf01c62b12b56
[linux-2.6.git] / drivers / mmc / omap.c
1 /*
2  *  linux/drivers/media/mmc/omap.c
3  *
4  *  Copyright (C) 2004 Nokia Corporation
5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7  *  Other hacks (DMA, SD, etc) by David Brownell
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/protocol.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28
29 #include <asm/io.h>
30 #include <asm/irq.h>
31 #include <asm/scatterlist.h>
32 #include <asm/mach-types.h>
33
34 #include <asm/arch/board.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/dma.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/fpga.h>
39 #include <asm/arch/tps65010.h>
40
41 #define OMAP_MMC_REG_CMD        0x00
42 #define OMAP_MMC_REG_ARGL       0x04
43 #define OMAP_MMC_REG_ARGH       0x08
44 #define OMAP_MMC_REG_CON        0x0c
45 #define OMAP_MMC_REG_STAT       0x10
46 #define OMAP_MMC_REG_IE         0x14
47 #define OMAP_MMC_REG_CTO        0x18
48 #define OMAP_MMC_REG_DTO        0x1c
49 #define OMAP_MMC_REG_DATA       0x20
50 #define OMAP_MMC_REG_BLEN       0x24
51 #define OMAP_MMC_REG_NBLK       0x28
52 #define OMAP_MMC_REG_BUF        0x2c
53 #define OMAP_MMC_REG_SDIO       0x34
54 #define OMAP_MMC_REG_REV        0x3c
55 #define OMAP_MMC_REG_RSP0       0x40
56 #define OMAP_MMC_REG_RSP1       0x44
57 #define OMAP_MMC_REG_RSP2       0x48
58 #define OMAP_MMC_REG_RSP3       0x4c
59 #define OMAP_MMC_REG_RSP4       0x50
60 #define OMAP_MMC_REG_RSP5       0x54
61 #define OMAP_MMC_REG_RSP6       0x58
62 #define OMAP_MMC_REG_RSP7       0x5c
63 #define OMAP_MMC_REG_IOSR       0x60
64 #define OMAP_MMC_REG_SYSC       0x64
65 #define OMAP_MMC_REG_SYSS       0x68
66
67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
80
81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
83
84 /*
85  * Command types
86  */
87 #define OMAP_MMC_CMDTYPE_BC     0
88 #define OMAP_MMC_CMDTYPE_BCR    1
89 #define OMAP_MMC_CMDTYPE_AC     2
90 #define OMAP_MMC_CMDTYPE_ADTC   3
91
92
93 #define DRIVER_NAME "mmci-omap"
94
95 /* Specifies how often in millisecs to poll for card status changes
96  * when the cover switch is open */
97 #define OMAP_MMC_SWITCH_POLL_DELAY      500
98
99 static int mmc_omap_enable_poll = 1;
100
101 struct mmc_omap_host {
102         int                     initialized;
103         int                     suspended;
104         struct mmc_request *    mrq;
105         struct mmc_command *    cmd;
106         struct mmc_data *       data;
107         struct mmc_host *       mmc;
108         struct device *         dev;
109         unsigned char           id; /* 16xx chips have 2 MMC blocks */
110         struct clk *            iclk;
111         struct clk *            fclk;
112         struct resource         *mem_res;
113         void __iomem            *virt_base;
114         unsigned int            phys_base;
115         int                     irq;
116         unsigned char           bus_mode;
117         unsigned char           hw_bus_mode;
118
119         unsigned int            sg_len;
120         int                     sg_idx;
121         u16 *                   buffer;
122         u32                     buffer_bytes_left;
123         u32                     total_bytes_left;
124
125         unsigned                use_dma:1;
126         unsigned                brs_received:1, dma_done:1;
127         unsigned                dma_is_read:1;
128         unsigned                dma_in_use:1;
129         int                     dma_ch;
130         spinlock_t              dma_lock;
131         struct timer_list       dma_timer;
132         unsigned                dma_len;
133
134         short                   power_pin;
135         short                   wp_pin;
136
137         int                     switch_pin;
138         struct work_struct      switch_work;
139         struct timer_list       switch_timer;
140         int                     switch_last_state;
141 };
142
143 static inline int
144 mmc_omap_cover_is_open(struct mmc_omap_host *host)
145 {
146         if (host->switch_pin < 0)
147                 return 0;
148         return omap_get_gpio_datain(host->switch_pin);
149 }
150
151 static ssize_t
152 mmc_omap_show_cover_switch(struct device *dev,
153         struct device_attribute *attr, char *buf)
154 {
155         struct mmc_omap_host *host = dev_get_drvdata(dev);
156
157         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
158                         "closed");
159 }
160
161 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
162
163 static ssize_t
164 mmc_omap_show_enable_poll(struct device *dev,
165         struct device_attribute *attr, char *buf)
166 {
167         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
168 }
169
170 static ssize_t
171 mmc_omap_store_enable_poll(struct device *dev,
172         struct device_attribute *attr, const char *buf,
173         size_t size)
174 {
175         int enable_poll;
176
177         if (sscanf(buf, "%10d", &enable_poll) != 1)
178                 return -EINVAL;
179
180         if (enable_poll != mmc_omap_enable_poll) {
181                 struct mmc_omap_host *host = dev_get_drvdata(dev);
182
183                 mmc_omap_enable_poll = enable_poll;
184                 if (enable_poll && host->switch_pin >= 0)
185                         schedule_work(&host->switch_work);
186         }
187         return size;
188 }
189
190 static DEVICE_ATTR(enable_poll, 0664,
191                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
192
193 static void
194 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
195 {
196         u32 cmdreg;
197         u32 resptype;
198         u32 cmdtype;
199
200         host->cmd = cmd;
201
202         resptype = 0;
203         cmdtype = 0;
204
205         /* Our hardware needs to know exact type */
206         switch (mmc_resp_type(cmd)) {
207         case MMC_RSP_NONE:
208                 break;
209         case MMC_RSP_R1:
210         case MMC_RSP_R1B:
211                 /* resp 1, resp 1b */
212                 resptype = 1;
213                 break;
214         case MMC_RSP_R2:
215                 resptype = 2;
216                 break;
217         case MMC_RSP_R3:
218                 resptype = 3;
219                 break;
220         case MMC_RSP_R6:
221                 resptype = 6;
222                 break;
223         default:
224                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
225                 break;
226         }
227
228         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
229                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
230         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
231                 cmdtype = OMAP_MMC_CMDTYPE_BC;
232         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
233                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
234         } else {
235                 cmdtype = OMAP_MMC_CMDTYPE_AC;
236         }
237
238         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
239
240         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
241                 cmdreg |= 1 << 6;
242
243         if (cmd->flags & MMC_RSP_BUSY)
244                 cmdreg |= 1 << 11;
245
246         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
247                 cmdreg |= 1 << 15;
248
249         clk_enable(host->fclk);
250
251         OMAP_MMC_WRITE(host, CTO, 200);
252         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
253         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
254         OMAP_MMC_WRITE(host, IE,
255                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
256                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
257                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
258                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
259                        OMAP_MMC_STAT_END_OF_DATA);
260         OMAP_MMC_WRITE(host, CMD, cmdreg);
261 }
262
263 static void
264 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
265 {
266         if (host->dma_in_use) {
267                 enum dma_data_direction dma_data_dir;
268
269                 BUG_ON(host->dma_ch < 0);
270                 if (data->error != MMC_ERR_NONE)
271                         omap_stop_dma(host->dma_ch);
272                 /* Release DMA channel lazily */
273                 mod_timer(&host->dma_timer, jiffies + HZ);
274                 if (data->flags & MMC_DATA_WRITE)
275                         dma_data_dir = DMA_TO_DEVICE;
276                 else
277                         dma_data_dir = DMA_FROM_DEVICE;
278                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
279                              dma_data_dir);
280         }
281         host->data = NULL;
282         host->sg_len = 0;
283         clk_disable(host->fclk);
284
285         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
286          * dozens of requests until the card finishes writing data.
287          * It'd be cheaper to just wait till an EOFB interrupt arrives...
288          */
289
290         if (!data->stop) {
291                 host->mrq = NULL;
292                 mmc_request_done(host->mmc, data->mrq);
293                 return;
294         }
295
296         mmc_omap_start_command(host, data->stop);
297 }
298
299 static void
300 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
301 {
302         unsigned long flags;
303         int done;
304
305         if (!host->dma_in_use) {
306                 mmc_omap_xfer_done(host, data);
307                 return;
308         }
309         done = 0;
310         spin_lock_irqsave(&host->dma_lock, flags);
311         if (host->dma_done)
312                 done = 1;
313         else
314                 host->brs_received = 1;
315         spin_unlock_irqrestore(&host->dma_lock, flags);
316         if (done)
317                 mmc_omap_xfer_done(host, data);
318 }
319
320 static void
321 mmc_omap_dma_timer(unsigned long data)
322 {
323         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
324
325         BUG_ON(host->dma_ch < 0);
326         omap_free_dma(host->dma_ch);
327         host->dma_ch = -1;
328 }
329
330 static void
331 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
332 {
333         unsigned long flags;
334         int done;
335
336         done = 0;
337         spin_lock_irqsave(&host->dma_lock, flags);
338         if (host->brs_received)
339                 done = 1;
340         else
341                 host->dma_done = 1;
342         spin_unlock_irqrestore(&host->dma_lock, flags);
343         if (done)
344                 mmc_omap_xfer_done(host, data);
345 }
346
347 static void
348 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
349 {
350         host->cmd = NULL;
351
352         if (cmd->flags & MMC_RSP_PRESENT) {
353                 if (cmd->flags & MMC_RSP_136) {
354                         /* response type 2 */
355                         cmd->resp[3] =
356                                 OMAP_MMC_READ(host, RSP0) |
357                                 (OMAP_MMC_READ(host, RSP1) << 16);
358                         cmd->resp[2] =
359                                 OMAP_MMC_READ(host, RSP2) |
360                                 (OMAP_MMC_READ(host, RSP3) << 16);
361                         cmd->resp[1] =
362                                 OMAP_MMC_READ(host, RSP4) |
363                                 (OMAP_MMC_READ(host, RSP5) << 16);
364                         cmd->resp[0] =
365                                 OMAP_MMC_READ(host, RSP6) |
366                                 (OMAP_MMC_READ(host, RSP7) << 16);
367                 } else {
368                         /* response types 1, 1b, 3, 4, 5, 6 */
369                         cmd->resp[0] =
370                                 OMAP_MMC_READ(host, RSP6) |
371                                 (OMAP_MMC_READ(host, RSP7) << 16);
372                 }
373         }
374
375         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
376                 host->mrq = NULL;
377                 clk_disable(host->fclk);
378                 mmc_request_done(host->mmc, cmd->mrq);
379         }
380 }
381
382 /* PIO only */
383 static void
384 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
385 {
386         struct scatterlist *sg;
387
388         sg = host->data->sg + host->sg_idx;
389         host->buffer_bytes_left = sg->length;
390         host->buffer = page_address(sg->page) + sg->offset;
391         if (host->buffer_bytes_left > host->total_bytes_left)
392                 host->buffer_bytes_left = host->total_bytes_left;
393 }
394
395 /* PIO only */
396 static void
397 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
398 {
399         int n;
400
401         if (host->buffer_bytes_left == 0) {
402                 host->sg_idx++;
403                 BUG_ON(host->sg_idx == host->sg_len);
404                 mmc_omap_sg_to_buf(host);
405         }
406         n = 64;
407         if (n > host->buffer_bytes_left)
408                 n = host->buffer_bytes_left;
409         host->buffer_bytes_left -= n;
410         host->total_bytes_left -= n;
411         host->data->bytes_xfered += n;
412
413         if (write) {
414                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
415         } else {
416                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
417         }
418 }
419
420 static inline void mmc_omap_report_irq(u16 status)
421 {
422         static const char *mmc_omap_status_bits[] = {
423                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
424                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
425         };
426         int i, c = 0;
427
428         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
429                 if (status & (1 << i)) {
430                         if (c)
431                                 printk(" ");
432                         printk("%s", mmc_omap_status_bits[i]);
433                         c++;
434                 }
435 }
436
437 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
438 {
439         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
440         u16 status;
441         int end_command;
442         int end_transfer;
443         int transfer_error;
444
445         if (host->cmd == NULL && host->data == NULL) {
446                 status = OMAP_MMC_READ(host, STAT);
447                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
448                 if (status != 0) {
449                         OMAP_MMC_WRITE(host, STAT, status);
450                         OMAP_MMC_WRITE(host, IE, 0);
451                 }
452                 return IRQ_HANDLED;
453         }
454
455         end_command = 0;
456         end_transfer = 0;
457         transfer_error = 0;
458
459         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
460                 OMAP_MMC_WRITE(host, STAT, status);
461 #ifdef CONFIG_MMC_DEBUG
462                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
463                         status, host->cmd != NULL ? host->cmd->opcode : -1);
464                 mmc_omap_report_irq(status);
465                 printk("\n");
466 #endif
467                 if (host->total_bytes_left) {
468                         if ((status & OMAP_MMC_STAT_A_FULL) ||
469                             (status & OMAP_MMC_STAT_END_OF_DATA))
470                                 mmc_omap_xfer_data(host, 0);
471                         if (status & OMAP_MMC_STAT_A_EMPTY)
472                                 mmc_omap_xfer_data(host, 1);
473                 }
474
475                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
476                         end_transfer = 1;
477                 }
478
479                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
480                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
481                         if (host->data) {
482                                 host->data->error |= MMC_ERR_TIMEOUT;
483                                 transfer_error = 1;
484                         }
485                 }
486
487                 if (status & OMAP_MMC_STAT_DATA_CRC) {
488                         if (host->data) {
489                                 host->data->error |= MMC_ERR_BADCRC;
490                                 dev_dbg(mmc_dev(host->mmc),
491                                          "data CRC error, bytes left %d\n",
492                                         host->total_bytes_left);
493                                 transfer_error = 1;
494                         } else {
495                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
496                         }
497                 }
498
499                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
500                         /* Timeouts are routine with some commands */
501                         if (host->cmd) {
502                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
503                                                 host->cmd->opcode !=
504                                                 MMC_SEND_OP_COND &&
505                                                 host->cmd->opcode !=
506                                                 MMC_APP_CMD &&
507                                                 !mmc_omap_cover_is_open(host))
508                                         dev_err(mmc_dev(host->mmc),
509                                                 "command timeout, CMD %d\n",
510                                                 host->cmd->opcode);
511                                 host->cmd->error = MMC_ERR_TIMEOUT;
512                                 end_command = 1;
513                         }
514                 }
515
516                 if (status & OMAP_MMC_STAT_CMD_CRC) {
517                         if (host->cmd) {
518                                 dev_err(mmc_dev(host->mmc),
519                                         "command CRC error (CMD%d, arg 0x%08x)\n",
520                                         host->cmd->opcode, host->cmd->arg);
521                                 host->cmd->error = MMC_ERR_BADCRC;
522                                 end_command = 1;
523                         } else
524                                 dev_err(mmc_dev(host->mmc),
525                                         "command CRC error without cmd?\n");
526                 }
527
528                 if (status & OMAP_MMC_STAT_CARD_ERR) {
529                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
530                                 u32 response = OMAP_MMC_READ(host, RSP6)
531                                         | (OMAP_MMC_READ(host, RSP7) << 16);
532                                 /* STOP sometimes sets must-ignore bits */
533                                 if (!(response & (R1_CC_ERROR
534                                                                 | R1_ILLEGAL_COMMAND
535                                                                 | R1_COM_CRC_ERROR))) {
536                                         end_command = 1;
537                                         continue;
538                                 }
539                         }
540
541                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
542                                 host->cmd->opcode);
543                         if (host->cmd) {
544                                 host->cmd->error = MMC_ERR_FAILED;
545                                 end_command = 1;
546                         }
547                         if (host->data) {
548                                 host->data->error = MMC_ERR_FAILED;
549                                 transfer_error = 1;
550                         }
551                 }
552
553                 /*
554                  * NOTE: On 1610 the END_OF_CMD may come too early when
555                  * starting a write 
556                  */
557                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
558                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
559                         end_command = 1;
560                 }
561         }
562
563         if (end_command) {
564                 mmc_omap_cmd_done(host, host->cmd);
565         }
566         if (transfer_error)
567                 mmc_omap_xfer_done(host, host->data);
568         else if (end_transfer)
569                 mmc_omap_end_of_data(host, host->data);
570
571         return IRQ_HANDLED;
572 }
573
574 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
575 {
576         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
577
578         schedule_work(&host->switch_work);
579
580         return IRQ_HANDLED;
581 }
582
583 static void mmc_omap_switch_timer(unsigned long arg)
584 {
585         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
586
587         schedule_work(&host->switch_work);
588 }
589
590 static void mmc_omap_switch_handler(struct work_struct *work)
591 {
592         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
593         struct mmc_card *card;
594         static int complained = 0;
595         int cards = 0, cover_open;
596
597         if (host->switch_pin == -1)
598                 return;
599         cover_open = mmc_omap_cover_is_open(host);
600         if (cover_open != host->switch_last_state) {
601                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
602                 host->switch_last_state = cover_open;
603         }
604         mmc_detect_change(host->mmc, 0);
605         list_for_each_entry(card, &host->mmc->cards, node) {
606                 if (mmc_card_present(card))
607                         cards++;
608         }
609         if (mmc_omap_cover_is_open(host)) {
610                 if (!complained) {
611                         dev_info(mmc_dev(host->mmc), "cover is open");
612                         complained = 1;
613                 }
614                 if (mmc_omap_enable_poll)
615                         mod_timer(&host->switch_timer, jiffies +
616                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
617         } else {
618                 complained = 0;
619         }
620 }
621
622 /* Prepare to transfer the next segment of a scatterlist */
623 static void
624 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
625 {
626         int dma_ch = host->dma_ch;
627         unsigned long data_addr;
628         u16 buf, frame;
629         u32 count;
630         struct scatterlist *sg = &data->sg[host->sg_idx];
631         int src_port = 0;
632         int dst_port = 0;
633         int sync_dev = 0;
634
635         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
636         frame = data->blksz;
637         count = sg_dma_len(sg);
638
639         if ((data->blocks == 1) && (count > data->blksz))
640                 count = frame;
641
642         host->dma_len = count;
643
644         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
645          * Use 16 or 32 word frames when the blocksize is at least that large.
646          * Blocksize is usually 512 bytes; but not for some SD reads.
647          */
648         if (cpu_is_omap15xx() && frame > 32)
649                 frame = 32;
650         else if (frame > 64)
651                 frame = 64;
652         count /= frame;
653         frame >>= 1;
654
655         if (!(data->flags & MMC_DATA_WRITE)) {
656                 buf = 0x800f | ((frame - 1) << 8);
657
658                 if (cpu_class_is_omap1()) {
659                         src_port = OMAP_DMA_PORT_TIPB;
660                         dst_port = OMAP_DMA_PORT_EMIFF;
661                 }
662                 if (cpu_is_omap24xx())
663                         sync_dev = OMAP24XX_DMA_MMC1_RX;
664
665                 omap_set_dma_src_params(dma_ch, src_port,
666                                         OMAP_DMA_AMODE_CONSTANT,
667                                         data_addr, 0, 0);
668                 omap_set_dma_dest_params(dma_ch, dst_port,
669                                          OMAP_DMA_AMODE_POST_INC,
670                                          sg_dma_address(sg), 0, 0);
671                 omap_set_dma_dest_data_pack(dma_ch, 1);
672                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
673         } else {
674                 buf = 0x0f80 | ((frame - 1) << 0);
675
676                 if (cpu_class_is_omap1()) {
677                         src_port = OMAP_DMA_PORT_EMIFF;
678                         dst_port = OMAP_DMA_PORT_TIPB;
679                 }
680                 if (cpu_is_omap24xx())
681                         sync_dev = OMAP24XX_DMA_MMC1_TX;
682
683                 omap_set_dma_dest_params(dma_ch, dst_port,
684                                          OMAP_DMA_AMODE_CONSTANT,
685                                          data_addr, 0, 0);
686                 omap_set_dma_src_params(dma_ch, src_port,
687                                         OMAP_DMA_AMODE_POST_INC,
688                                         sg_dma_address(sg), 0, 0);
689                 omap_set_dma_src_data_pack(dma_ch, 1);
690                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
691         }
692
693         /* Max limit for DMA frame count is 0xffff */
694         BUG_ON(count > 0xffff);
695
696         OMAP_MMC_WRITE(host, BUF, buf);
697         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
698                                      frame, count, OMAP_DMA_SYNC_FRAME,
699                                      sync_dev, 0);
700 }
701
702 /* A scatterlist segment completed */
703 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
704 {
705         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
706         struct mmc_data *mmcdat = host->data;
707
708         if (unlikely(host->dma_ch < 0)) {
709                 dev_err(mmc_dev(host->mmc),
710                         "DMA callback while DMA not enabled\n");
711                 return;
712         }
713         /* FIXME: We really should do something to _handle_ the errors */
714         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
715                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
716                 return;
717         }
718         if (ch_status & OMAP_DMA_DROP_IRQ) {
719                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
720                 return;
721         }
722         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
723                 return;
724         }
725         mmcdat->bytes_xfered += host->dma_len;
726         host->sg_idx++;
727         if (host->sg_idx < host->sg_len) {
728                 mmc_omap_prepare_dma(host, host->data);
729                 omap_start_dma(host->dma_ch);
730         } else
731                 mmc_omap_dma_done(host, host->data);
732 }
733
734 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
735 {
736         const char *dev_name;
737         int sync_dev, dma_ch, is_read, r;
738
739         is_read = !(data->flags & MMC_DATA_WRITE);
740         del_timer_sync(&host->dma_timer);
741         if (host->dma_ch >= 0) {
742                 if (is_read == host->dma_is_read)
743                         return 0;
744                 omap_free_dma(host->dma_ch);
745                 host->dma_ch = -1;
746         }
747
748         if (is_read) {
749                 if (host->id == 1) {
750                         sync_dev = OMAP_DMA_MMC_RX;
751                         dev_name = "MMC1 read";
752                 } else {
753                         sync_dev = OMAP_DMA_MMC2_RX;
754                         dev_name = "MMC2 read";
755                 }
756         } else {
757                 if (host->id == 1) {
758                         sync_dev = OMAP_DMA_MMC_TX;
759                         dev_name = "MMC1 write";
760                 } else {
761                         sync_dev = OMAP_DMA_MMC2_TX;
762                         dev_name = "MMC2 write";
763                 }
764         }
765         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
766                              host, &dma_ch);
767         if (r != 0) {
768                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
769                 return r;
770         }
771         host->dma_ch = dma_ch;
772         host->dma_is_read = is_read;
773
774         return 0;
775 }
776
777 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
778 {
779         u16 reg;
780
781         reg = OMAP_MMC_READ(host, SDIO);
782         reg &= ~(1 << 5);
783         OMAP_MMC_WRITE(host, SDIO, reg);
784         /* Set maximum timeout */
785         OMAP_MMC_WRITE(host, CTO, 0xff);
786 }
787
788 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
789 {
790         int timeout;
791         u16 reg;
792
793         /* Convert ns to clock cycles by assuming 20MHz frequency
794          * 1 cycle at 20MHz = 500 ns
795          */
796         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
797
798         /* Check if we need to use timeout multiplier register */
799         reg = OMAP_MMC_READ(host, SDIO);
800         if (timeout > 0xffff) {
801                 reg |= (1 << 5);
802                 timeout /= 1024;
803         } else
804                 reg &= ~(1 << 5);
805         OMAP_MMC_WRITE(host, SDIO, reg);
806         OMAP_MMC_WRITE(host, DTO, timeout);
807 }
808
809 static void
810 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
811 {
812         struct mmc_data *data = req->data;
813         int i, use_dma, block_size;
814         unsigned sg_len;
815
816         host->data = data;
817         if (data == NULL) {
818                 OMAP_MMC_WRITE(host, BLEN, 0);
819                 OMAP_MMC_WRITE(host, NBLK, 0);
820                 OMAP_MMC_WRITE(host, BUF, 0);
821                 host->dma_in_use = 0;
822                 set_cmd_timeout(host, req);
823                 return;
824         }
825
826         block_size = data->blksz;
827
828         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
829         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
830         set_data_timeout(host, req);
831
832         /* cope with calling layer confusion; it issues "single
833          * block" writes using multi-block scatterlists.
834          */
835         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
836
837         /* Only do DMA for entire blocks */
838         use_dma = host->use_dma;
839         if (use_dma) {
840                 for (i = 0; i < sg_len; i++) {
841                         if ((data->sg[i].length % block_size) != 0) {
842                                 use_dma = 0;
843                                 break;
844                         }
845                 }
846         }
847
848         host->sg_idx = 0;
849         if (use_dma) {
850                 if (mmc_omap_get_dma_channel(host, data) == 0) {
851                         enum dma_data_direction dma_data_dir;
852
853                         if (data->flags & MMC_DATA_WRITE)
854                                 dma_data_dir = DMA_TO_DEVICE;
855                         else
856                                 dma_data_dir = DMA_FROM_DEVICE;
857
858                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
859                                                 sg_len, dma_data_dir);
860                         host->total_bytes_left = 0;
861                         mmc_omap_prepare_dma(host, req->data);
862                         host->brs_received = 0;
863                         host->dma_done = 0;
864                         host->dma_in_use = 1;
865                 } else
866                         use_dma = 0;
867         }
868
869         /* Revert to PIO? */
870         if (!use_dma) {
871                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
872                 host->total_bytes_left = data->blocks * block_size;
873                 host->sg_len = sg_len;
874                 mmc_omap_sg_to_buf(host);
875                 host->dma_in_use = 0;
876         }
877 }
878
879 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
880 {
881         struct mmc_omap_host *host = mmc_priv(mmc);
882
883         WARN_ON(host->mrq != NULL);
884
885         host->mrq = req;
886
887         /* only touch fifo AFTER the controller readies it */
888         mmc_omap_prepare_data(host, req);
889         mmc_omap_start_command(host, req->cmd);
890         if (host->dma_in_use)
891                 omap_start_dma(host->dma_ch);
892 }
893
894 static void innovator_fpga_socket_power(int on)
895 {
896 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
897         if (on) {
898                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
899                      OMAP1510_FPGA_POWER);
900         } else {
901                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
902                      OMAP1510_FPGA_POWER);
903         }
904 #endif
905 }
906
907 /*
908  * Turn the socket power on/off. Innovator uses FPGA, most boards
909  * probably use GPIO.
910  */
911 static void mmc_omap_power(struct mmc_omap_host *host, int on)
912 {
913         if (on) {
914                 if (machine_is_omap_innovator())
915                         innovator_fpga_socket_power(1);
916                 else if (machine_is_omap_h2())
917                         tps65010_set_gpio_out_value(GPIO3, HIGH);
918                 else if (machine_is_omap_h3())
919                         /* GPIO 4 of TPS65010 sends SD_EN signal */
920                         tps65010_set_gpio_out_value(GPIO4, HIGH);
921                 else if (cpu_is_omap24xx()) {
922                         u16 reg = OMAP_MMC_READ(host, CON);
923                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
924                 } else
925                         if (host->power_pin >= 0)
926                                 omap_set_gpio_dataout(host->power_pin, 1);
927         } else {
928                 if (machine_is_omap_innovator())
929                         innovator_fpga_socket_power(0);
930                 else if (machine_is_omap_h2())
931                         tps65010_set_gpio_out_value(GPIO3, LOW);
932                 else if (machine_is_omap_h3())
933                         tps65010_set_gpio_out_value(GPIO4, LOW);
934                 else if (cpu_is_omap24xx()) {
935                         u16 reg = OMAP_MMC_READ(host, CON);
936                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
937                 } else
938                         if (host->power_pin >= 0)
939                                 omap_set_gpio_dataout(host->power_pin, 0);
940         }
941 }
942
943 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
944 {
945         struct mmc_omap_host *host = mmc_priv(mmc);
946         int dsor;
947         int realclock, i;
948
949         realclock = ios->clock;
950
951         if (ios->clock == 0)
952                 dsor = 0;
953         else {
954                 int func_clk_rate = clk_get_rate(host->fclk);
955
956                 dsor = func_clk_rate / realclock;
957                 if (dsor < 1)
958                         dsor = 1;
959
960                 if (func_clk_rate / dsor > realclock)
961                         dsor++;
962
963                 if (dsor > 250)
964                         dsor = 250;
965                 dsor++;
966
967                 if (ios->bus_width == MMC_BUS_WIDTH_4)
968                         dsor |= 1 << 15;
969         }
970
971         switch (ios->power_mode) {
972         case MMC_POWER_OFF:
973                 mmc_omap_power(host, 0);
974                 break;
975         case MMC_POWER_UP:
976         case MMC_POWER_ON:
977                 mmc_omap_power(host, 1);
978                 dsor |= 1 << 11;
979                 break;
980         }
981
982         host->bus_mode = ios->bus_mode;
983         host->hw_bus_mode = host->bus_mode;
984
985         clk_enable(host->fclk);
986
987         /* On insanely high arm_per frequencies something sometimes
988          * goes somehow out of sync, and the POW bit is not being set,
989          * which results in the while loop below getting stuck.
990          * Writing to the CON register twice seems to do the trick. */
991         for (i = 0; i < 2; i++)
992                 OMAP_MMC_WRITE(host, CON, dsor);
993         if (ios->power_mode == MMC_POWER_UP) {
994                 /* Send clock cycles, poll completion */
995                 OMAP_MMC_WRITE(host, IE, 0);
996                 OMAP_MMC_WRITE(host, STAT, 0xffff);
997                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
998                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
999                 OMAP_MMC_WRITE(host, STAT, 1);
1000         }
1001         clk_disable(host->fclk);
1002 }
1003
1004 static int mmc_omap_get_ro(struct mmc_host *mmc)
1005 {
1006         struct mmc_omap_host *host = mmc_priv(mmc);
1007
1008         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1009 }
1010
1011 static const struct mmc_host_ops mmc_omap_ops = {
1012         .request        = mmc_omap_request,
1013         .set_ios        = mmc_omap_set_ios,
1014         .get_ro         = mmc_omap_get_ro,
1015 };
1016
1017 static int __init mmc_omap_probe(struct platform_device *pdev)
1018 {
1019         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1020         struct mmc_host *mmc;
1021         struct mmc_omap_host *host = NULL;
1022         struct resource *res;
1023         int ret = 0;
1024         int irq;
1025
1026         if (minfo == NULL) {
1027                 dev_err(&pdev->dev, "platform data missing\n");
1028                 return -ENXIO;
1029         }
1030
1031         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032         irq = platform_get_irq(pdev, 0);
1033         if (res == NULL || irq < 0)
1034                 return -ENXIO;
1035
1036         res = request_mem_region(res->start, res->end - res->start + 1,
1037                                  pdev->name);
1038         if (res == NULL)
1039                 return -EBUSY;
1040
1041         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1042         if (mmc == NULL) {
1043                 ret = -ENOMEM;
1044                 goto err_free_mem_region;
1045         }
1046
1047         host = mmc_priv(mmc);
1048         host->mmc = mmc;
1049
1050         spin_lock_init(&host->dma_lock);
1051         init_timer(&host->dma_timer);
1052         host->dma_timer.function = mmc_omap_dma_timer;
1053         host->dma_timer.data = (unsigned long) host;
1054
1055         host->id = pdev->id;
1056         host->mem_res = res;
1057         host->irq = irq;
1058
1059         if (cpu_is_omap24xx()) {
1060                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1061                 if (IS_ERR(host->iclk))
1062                         goto err_free_mmc_host;
1063                 clk_enable(host->iclk);
1064         }
1065
1066         if (!cpu_is_omap24xx())
1067                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1068         else
1069                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1070
1071         if (IS_ERR(host->fclk)) {
1072                 ret = PTR_ERR(host->fclk);
1073                 goto err_free_iclk;
1074         }
1075
1076         /* REVISIT:
1077          * Also, use minfo->cover to decide how to manage
1078          * the card detect sensing.
1079          */
1080         host->power_pin = minfo->power_pin;
1081         host->switch_pin = minfo->switch_pin;
1082         host->wp_pin = minfo->wp_pin;
1083         host->use_dma = 1;
1084         host->dma_ch = -1;
1085
1086         host->irq = irq;
1087         host->phys_base = host->mem_res->start;
1088         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1089
1090         mmc->ops = &mmc_omap_ops;
1091         mmc->f_min = 400000;
1092         mmc->f_max = 24000000;
1093         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1094         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1095
1096         if (minfo->wire4)
1097                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1098
1099         /* Use scatterlist DMA to reduce per-transfer costs.
1100          * NOTE max_seg_size assumption that small blocks aren't
1101          * normally used (except e.g. for reading SD registers).
1102          */
1103         mmc->max_phys_segs = 32;
1104         mmc->max_hw_segs = 32;
1105         mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1106         mmc->max_seg_size = mmc->max_sectors * 512;
1107
1108         if (host->power_pin >= 0) {
1109                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1110                         dev_err(mmc_dev(host->mmc),
1111                                 "Unable to get GPIO pin for MMC power\n");
1112                         goto err_free_fclk;
1113                 }
1114                 omap_set_gpio_direction(host->power_pin, 0);
1115         }
1116
1117         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1118         if (ret)
1119                 goto err_free_power_gpio;
1120
1121         host->dev = &pdev->dev;
1122         platform_set_drvdata(pdev, host);
1123
1124         if (host->switch_pin >= 0) {
1125                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1126                 init_timer(&host->switch_timer);
1127                 host->switch_timer.function = mmc_omap_switch_timer;
1128                 host->switch_timer.data = (unsigned long) host;
1129                 if (omap_request_gpio(host->switch_pin) != 0) {
1130                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1131                         host->switch_pin = -1;
1132                         goto no_switch;
1133                 }
1134
1135                 omap_set_gpio_direction(host->switch_pin, 1);
1136                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1137                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1138                 if (ret) {
1139                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1140                         omap_free_gpio(host->switch_pin);
1141                         host->switch_pin = -1;
1142                         goto no_switch;
1143                 }
1144                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1145                 if (ret == 0) {
1146                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1147                         if (ret != 0)
1148                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1149                 }
1150                 if (ret) {
1151                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1152                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1153                         omap_free_gpio(host->switch_pin);
1154                         host->switch_pin = -1;
1155                         goto no_switch;
1156                 }
1157                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1158                         schedule_work(&host->switch_work);
1159         }
1160
1161         mmc_add_host(mmc);
1162
1163         return 0;
1164
1165 no_switch:
1166         /* FIXME: Free other resources too. */
1167         if (host) {
1168                 if (host->iclk && !IS_ERR(host->iclk))
1169                         clk_put(host->iclk);
1170                 if (host->fclk && !IS_ERR(host->fclk))
1171                         clk_put(host->fclk);
1172                 mmc_free_host(host->mmc);
1173         }
1174 err_free_power_gpio:
1175         if (host->power_pin >= 0)
1176                 omap_free_gpio(host->power_pin);
1177 err_free_fclk:
1178         clk_put(host->fclk);
1179 err_free_iclk:
1180         if (host->iclk != NULL) {
1181                 clk_disable(host->iclk);
1182                 clk_put(host->iclk);
1183         }
1184 err_free_mmc_host:
1185         mmc_free_host(host->mmc);
1186 err_free_mem_region:
1187         release_mem_region(res->start, res->end - res->start + 1);
1188         return ret;
1189 }
1190
1191 static int mmc_omap_remove(struct platform_device *pdev)
1192 {
1193         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1194
1195         platform_set_drvdata(pdev, NULL);
1196
1197         BUG_ON(host == NULL);
1198
1199         mmc_remove_host(host->mmc);
1200         free_irq(host->irq, host);
1201
1202         if (host->power_pin >= 0)
1203                 omap_free_gpio(host->power_pin);
1204         if (host->switch_pin >= 0) {
1205                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1206                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1207                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1208                 omap_free_gpio(host->switch_pin);
1209                 host->switch_pin = -1;
1210                 del_timer_sync(&host->switch_timer);
1211                 flush_scheduled_work();
1212         }
1213         if (host->iclk && !IS_ERR(host->iclk))
1214                 clk_put(host->iclk);
1215         if (host->fclk && !IS_ERR(host->fclk))
1216                 clk_put(host->fclk);
1217
1218         release_mem_region(pdev->resource[0].start,
1219                            pdev->resource[0].end - pdev->resource[0].start + 1);
1220
1221         mmc_free_host(host->mmc);
1222
1223         return 0;
1224 }
1225
1226 #ifdef CONFIG_PM
1227 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1228 {
1229         int ret = 0;
1230         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1231
1232         if (host && host->suspended)
1233                 return 0;
1234
1235         if (host) {
1236                 ret = mmc_suspend_host(host->mmc, mesg);
1237                 if (ret == 0)
1238                         host->suspended = 1;
1239         }
1240         return ret;
1241 }
1242
1243 static int mmc_omap_resume(struct platform_device *pdev)
1244 {
1245         int ret = 0;
1246         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1247
1248         if (host && !host->suspended)
1249                 return 0;
1250
1251         if (host) {
1252                 ret = mmc_resume_host(host->mmc);
1253                 if (ret == 0)
1254                         host->suspended = 0;
1255         }
1256
1257         return ret;
1258 }
1259 #else
1260 #define mmc_omap_suspend        NULL
1261 #define mmc_omap_resume         NULL
1262 #endif
1263
1264 static struct platform_driver mmc_omap_driver = {
1265         .probe          = mmc_omap_probe,
1266         .remove         = mmc_omap_remove,
1267         .suspend        = mmc_omap_suspend,
1268         .resume         = mmc_omap_resume,
1269         .driver         = {
1270                 .name   = DRIVER_NAME,
1271         },
1272 };
1273
1274 static int __init mmc_omap_init(void)
1275 {
1276         return platform_driver_register(&mmc_omap_driver);
1277 }
1278
1279 static void __exit mmc_omap_exit(void)
1280 {
1281         platform_driver_unregister(&mmc_omap_driver);
1282 }
1283
1284 module_init(mmc_omap_init);
1285 module_exit(mmc_omap_exit);
1286
1287 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1288 MODULE_LICENSE("GPL");
1289 MODULE_ALIAS(DRIVER_NAME);
1290 MODULE_AUTHOR("Juha Yrjölä");