mmc: Correct definition of R6
[linux-2.6.git] / drivers / mmc / imxmmc.c
1 /*
2  *  linux/drivers/mmc/imxmmc.c - Motorola i.MX MMCI driver
3  *
4  *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6  *
7  *  derived from pxamci.c by Russell King
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14  *             Changed to conform redesigned i.MX scatter gather DMA interface
15  *
16  *  2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17  *             Updated for 2.6.14 kernel
18  *
19  *  2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20  *             Found and corrected problems in the write path
21  *
22  *  2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23  *             The event handling rewritten right way in softirq.
24  *             Added many ugly hacks and delays to overcome SDHC
25  *             deficiencies
26  *
27  */
28
29 #ifdef CONFIG_MMC_DEBUG
30 #define DEBUG
31 #else
32 #undef  DEBUG
33 #endif
34
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/blkdev.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/protocol.h>
45 #include <linux/delay.h>
46
47 #include <asm/dma.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/sizes.h>
51 #include <asm/arch/mmc.h>
52 #include <asm/arch/imx-dma.h>
53
54 #include "imxmmc.h"
55
56 #define DRIVER_NAME "imx-mmc"
57
58 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
59                       INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
60                       INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
61
62 struct imxmci_host {
63         struct mmc_host         *mmc;
64         spinlock_t              lock;
65         struct resource         *res;
66         int                     irq;
67         imx_dmach_t             dma;
68         unsigned int            clkrt;
69         unsigned int            cmdat;
70         volatile unsigned int   imask;
71         unsigned int            power_mode;
72         unsigned int            present;
73         struct imxmmc_platform_data *pdata;
74
75         struct mmc_request      *req;
76         struct mmc_command      *cmd;
77         struct mmc_data         *data;
78
79         struct timer_list       timer;
80         struct tasklet_struct   tasklet;
81         unsigned int            status_reg;
82         unsigned long           pending_events;
83         /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
84         u16                     *data_ptr;
85         unsigned int            data_cnt;
86         atomic_t                stuck_timeout;
87
88         unsigned int            dma_nents;
89         unsigned int            dma_size;
90         unsigned int            dma_dir;
91         int                     dma_allocated;
92
93         unsigned char           actual_bus_width;
94
95         int                     prev_cmd_code;
96 };
97
98 #define IMXMCI_PEND_IRQ_b       0
99 #define IMXMCI_PEND_DMA_END_b   1
100 #define IMXMCI_PEND_DMA_ERR_b   2
101 #define IMXMCI_PEND_WAIT_RESP_b 3
102 #define IMXMCI_PEND_DMA_DATA_b  4
103 #define IMXMCI_PEND_CPU_DATA_b  5
104 #define IMXMCI_PEND_CARD_XCHG_b 6
105 #define IMXMCI_PEND_SET_INIT_b  7
106 #define IMXMCI_PEND_STARTED_b   8
107
108 #define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
109 #define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
110 #define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
111 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
112 #define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
113 #define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
114 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
115 #define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
116 #define IMXMCI_PEND_STARTED_m   (1 << IMXMCI_PEND_STARTED_b)
117
118 static void imxmci_stop_clock(struct imxmci_host *host)
119 {
120         int i = 0;
121         MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
122         while(i < 0x1000) {
123                 if(!(i & 0x7f))
124                         MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
125
126                 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
127                         /* Check twice before cut */
128                         if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
129                                 return;
130                 }
131
132                 i++;
133         }
134         dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
135 }
136
137 static int imxmci_start_clock(struct imxmci_host *host)
138 {
139         unsigned int trials = 0;
140         unsigned int delay_limit = 128;
141         unsigned long flags;
142
143         MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
144
145         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
146
147         /*
148          * Command start of the clock, this usually succeeds in less
149          * then 6 delay loops, but during card detection (low clockrate)
150          * it takes up to 5000 delay loops and sometimes fails for the first time
151          */
152         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
153
154         do {
155                 unsigned int delay = delay_limit;
156
157                 while(delay--){
158                         if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
159                                 /* Check twice before cut */
160                                 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
161                                         return 0;
162
163                         if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
164                                 return 0;
165                 }
166
167                 local_irq_save(flags);
168                 /*
169                  * Ensure, that request is not doubled under all possible circumstances.
170                  * It is possible, that cock running state is missed, because some other
171                  * IRQ or schedule delays this function execution and the clocks has
172                  * been already stopped by other means (response processing, SDHC HW)
173                  */
174                 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
175                         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
176                 local_irq_restore(flags);
177
178         } while(++trials<256);
179
180         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
181
182         return -1;
183 }
184
185 static void imxmci_softreset(void)
186 {
187         /* reset sequence */
188         MMC_STR_STP_CLK = 0x8;
189         MMC_STR_STP_CLK = 0xD;
190         MMC_STR_STP_CLK = 0x5;
191         MMC_STR_STP_CLK = 0x5;
192         MMC_STR_STP_CLK = 0x5;
193         MMC_STR_STP_CLK = 0x5;
194         MMC_STR_STP_CLK = 0x5;
195         MMC_STR_STP_CLK = 0x5;
196         MMC_STR_STP_CLK = 0x5;
197         MMC_STR_STP_CLK = 0x5;
198
199         MMC_RES_TO = 0xff;
200         MMC_BLK_LEN = 512;
201         MMC_NOB = 1;
202 }
203
204 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
205                         unsigned int *pstat, unsigned int stat_mask,
206                         int timeout, const char *where)
207 {
208         int loops=0;
209         while(!(*pstat & stat_mask)) {
210                 loops+=2;
211                 if(loops >= timeout) {
212                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
213                                 where, *pstat, stat_mask);
214                         return -1;
215                 }
216                 udelay(2);
217                 *pstat |= MMC_STATUS;
218         }
219         if(!loops)
220                 return 0;
221
222         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
223         if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
224                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
225                         loops, where, *pstat, stat_mask);
226         return loops;
227 }
228
229 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
230 {
231         unsigned int nob = data->blocks;
232         unsigned int blksz = data->blksz;
233         unsigned int datasz = nob * blksz;
234         int i;
235
236         if (data->flags & MMC_DATA_STREAM)
237                 nob = 0xffff;
238
239         host->data = data;
240         data->bytes_xfered = 0;
241
242         MMC_NOB = nob;
243         MMC_BLK_LEN = blksz;
244
245         /*
246          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
247          * We are in big troubles for non-512 byte transfers according to note in the paragraph
248          * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
249          * The situation is even more complex in reality. The SDHC in not able to handle wll
250          * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
251          * This is required for SCR read at least.
252          */
253         if (datasz < 512) {
254                 host->dma_size = datasz;
255                 if (data->flags & MMC_DATA_READ) {
256                         host->dma_dir = DMA_FROM_DEVICE;
257
258                         /* Hack to enable read SCR */
259                         MMC_NOB = 1;
260                         MMC_BLK_LEN = 512;
261                 } else {
262                         host->dma_dir = DMA_TO_DEVICE;
263                 }
264
265                 /* Convert back to virtual address */
266                 host->data_ptr = (u16*)(page_address(data->sg->page) + data->sg->offset);
267                 host->data_cnt = 0;
268
269                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
270                 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
271
272                 return;
273         }
274
275         if (data->flags & MMC_DATA_READ) {
276                 host->dma_dir = DMA_FROM_DEVICE;
277                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
278                                                 data->sg_len,  host->dma_dir);
279
280                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
281                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
282
283                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
284                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
285         } else {
286                 host->dma_dir = DMA_TO_DEVICE;
287
288                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
289                                                 data->sg_len,  host->dma_dir);
290
291                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
292                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
293
294                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
295                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
296         }
297
298 #if 1   /* This code is there only for consistency checking and can be disabled in future */
299         host->dma_size = 0;
300         for(i=0; i<host->dma_nents; i++)
301                 host->dma_size+=data->sg[i].length;
302
303         if (datasz > host->dma_size) {
304                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
305                        datasz, host->dma_size);
306         }
307 #endif
308
309         host->dma_size = datasz;
310
311         wmb();
312
313         if(host->actual_bus_width == MMC_BUS_WIDTH_4)
314                 BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
315         else
316                 BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
317
318         RSSR(host->dma) = DMA_REQ_SDHC;
319
320         set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
321         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
322
323         /* start DMA engine for read, write is delayed after initial response */
324         if (host->dma_dir == DMA_FROM_DEVICE) {
325                 imx_dma_enable(host->dma);
326         }
327 }
328
329 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
330 {
331         unsigned long flags;
332         u32 imask;
333
334         WARN_ON(host->cmd != NULL);
335         host->cmd = cmd;
336
337         /* Ensure, that clock are stopped else command programming and start fails */
338         imxmci_stop_clock(host);
339
340         if (cmd->flags & MMC_RSP_BUSY)
341                 cmdat |= CMD_DAT_CONT_BUSY;
342
343         switch (mmc_resp_type(cmd)) {
344         case MMC_RSP_R1: /* short CRC, OPCODE */
345         case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
346                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
347                 break;
348         case MMC_RSP_R2: /* long 136 bit + CRC */
349                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
350                 break;
351         case MMC_RSP_R3: /* short */
352                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
353                 break;
354         default:
355                 break;
356         }
357
358         if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
359                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
360
361         if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
362                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
363
364         MMC_CMD = cmd->opcode;
365         MMC_ARGH = cmd->arg >> 16;
366         MMC_ARGL = cmd->arg & 0xffff;
367         MMC_CMD_DAT_CONT = cmdat;
368
369         atomic_set(&host->stuck_timeout, 0);
370         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
371
372
373         imask = IMXMCI_INT_MASK_DEFAULT;
374         imask &= ~INT_MASK_END_CMD_RES;
375         if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
376                 /*imask &= ~INT_MASK_BUF_READY;*/
377                 imask &= ~INT_MASK_DATA_TRAN;
378                 if ( cmdat & CMD_DAT_CONT_WRITE )
379                         imask &= ~INT_MASK_WRITE_OP_DONE;
380                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
381                         imask &= ~INT_MASK_BUF_READY;
382         }
383
384         spin_lock_irqsave(&host->lock, flags);
385         host->imask = imask;
386         MMC_INT_MASK = host->imask;
387         spin_unlock_irqrestore(&host->lock, flags);
388
389         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
390                 cmd->opcode, cmd->opcode, imask);
391
392         imxmci_start_clock(host);
393 }
394
395 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
396 {
397         unsigned long flags;
398
399         spin_lock_irqsave(&host->lock, flags);
400
401         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
402                         IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
403
404         host->imask = IMXMCI_INT_MASK_DEFAULT;
405         MMC_INT_MASK = host->imask;
406
407         spin_unlock_irqrestore(&host->lock, flags);
408
409         if(req && req->cmd)
410                 host->prev_cmd_code = req->cmd->opcode;
411
412         host->req = NULL;
413         host->cmd = NULL;
414         host->data = NULL;
415         mmc_request_done(host->mmc, req);
416 }
417
418 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
419 {
420         struct mmc_data *data = host->data;
421         int data_error;
422
423         if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
424                 imx_dma_disable(host->dma);
425                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
426                              host->dma_dir);
427         }
428
429         if ( stat & STATUS_ERR_MASK ) {
430                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
431                 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
432                         data->error = MMC_ERR_BADCRC;
433                 else if(stat & STATUS_TIME_OUT_READ)
434                         data->error = MMC_ERR_TIMEOUT;
435                 else
436                         data->error = MMC_ERR_FAILED;
437         } else {
438                 data->bytes_xfered = host->dma_size;
439         }
440
441         data_error = data->error;
442
443         host->data = NULL;
444
445         return data_error;
446 }
447
448 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
449 {
450         struct mmc_command *cmd = host->cmd;
451         int i;
452         u32 a,b,c;
453         struct mmc_data *data = host->data;
454
455         if (!cmd)
456                 return 0;
457
458         host->cmd = NULL;
459
460         if (stat & STATUS_TIME_OUT_RESP) {
461                 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
462                 cmd->error = MMC_ERR_TIMEOUT;
463         } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
464                 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
465                 cmd->error = MMC_ERR_BADCRC;
466         }
467
468         if(cmd->flags & MMC_RSP_PRESENT) {
469                 if(cmd->flags & MMC_RSP_136) {
470                         for (i = 0; i < 4; i++) {
471                                 u32 a = MMC_RES_FIFO & 0xffff;
472                                 u32 b = MMC_RES_FIFO & 0xffff;
473                                 cmd->resp[i] = a<<16 | b;
474                         }
475                 } else {
476                         a = MMC_RES_FIFO & 0xffff;
477                         b = MMC_RES_FIFO & 0xffff;
478                         c = MMC_RES_FIFO & 0xffff;
479                         cmd->resp[0] = a<<24 | b<<8 | c>>8;
480                 }
481         }
482
483         dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
484                 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
485
486         if (data && (cmd->error == MMC_ERR_NONE) && !(stat & STATUS_ERR_MASK)) {
487                 if (host->req->data->flags & MMC_DATA_WRITE) {
488
489                         /* Wait for FIFO to be empty before starting DMA write */
490
491                         stat = MMC_STATUS;
492                         if(imxmci_busy_wait_for_status(host, &stat,
493                                 STATUS_APPL_BUFF_FE,
494                                 40, "imxmci_cmd_done DMA WR") < 0) {
495                                 cmd->error = MMC_ERR_FIFO;
496                                 imxmci_finish_data(host, stat);
497                                 if(host->req)
498                                         imxmci_finish_request(host, host->req);
499                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
500                                        stat);
501                                 return 0;
502                         }
503
504                         if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
505                                 imx_dma_enable(host->dma);
506                         }
507                 }
508         } else {
509                 struct mmc_request *req;
510                 imxmci_stop_clock(host);
511                 req = host->req;
512
513                 if(data)
514                         imxmci_finish_data(host, stat);
515
516                 if( req ) {
517                         imxmci_finish_request(host, req);
518                 } else {
519                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
520                 }
521         }
522
523         return 1;
524 }
525
526 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
527 {
528         struct mmc_data *data = host->data;
529         int data_error;
530
531         if (!data)
532                 return 0;
533
534         data_error = imxmci_finish_data(host, stat);
535
536         if (host->req->stop) {
537                 imxmci_stop_clock(host);
538                 imxmci_start_cmd(host, host->req->stop, 0);
539         } else {
540                 struct mmc_request *req;
541                 req = host->req;
542                 if( req ) {
543                         imxmci_finish_request(host, req);
544                 } else {
545                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
546                 }
547         }
548
549         return 1;
550 }
551
552 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
553 {
554         int i;
555         int burst_len;
556         int trans_done = 0;
557         unsigned int stat = *pstat;
558
559         if(host->actual_bus_width != MMC_BUS_WIDTH_4)
560                 burst_len = 16;
561         else
562                 burst_len = 64;
563
564         /* This is unfortunately required */
565         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
566                 stat);
567
568         udelay(20);     /* required for clocks < 8MHz*/
569
570         if(host->dma_dir == DMA_FROM_DEVICE) {
571                 imxmci_busy_wait_for_status(host, &stat,
572                                 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE,
573                                 50, "imxmci_cpu_driven_data read");
574
575                 while((stat & (STATUS_APPL_BUFF_FF |  STATUS_DATA_TRANS_DONE)) &&
576                       (host->data_cnt < 512)) {
577
578                         udelay(20);     /* required for clocks < 8MHz*/
579
580                         for(i = burst_len; i>=2 ; i-=2) {
581                                 u16 data;
582                                 data = MMC_BUFFER_ACCESS;
583                                 udelay(10);     /* required for clocks < 8MHz*/
584                                 if(host->data_cnt+2 <= host->dma_size) {
585                                         *(host->data_ptr++) = data;
586                                 } else {
587                                         if(host->data_cnt < host->dma_size)
588                                                 *(u8*)(host->data_ptr) = data;
589                                 }
590                                 host->data_cnt += 2;
591                         }
592
593                         stat = MMC_STATUS;
594
595                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
596                                 host->data_cnt, burst_len, stat);
597                 }
598
599                 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
600                         trans_done = 1;
601
602                 if(host->dma_size & 0x1ff)
603                         stat &= ~STATUS_CRC_READ_ERR;
604
605         } else {
606                 imxmci_busy_wait_for_status(host, &stat,
607                                 STATUS_APPL_BUFF_FE,
608                                 20, "imxmci_cpu_driven_data write");
609
610                 while((stat & STATUS_APPL_BUFF_FE) &&
611                       (host->data_cnt < host->dma_size)) {
612                         if(burst_len >= host->dma_size - host->data_cnt) {
613                                 burst_len = host->dma_size - host->data_cnt;
614                                 host->data_cnt = host->dma_size;
615                                 trans_done = 1;
616                         } else {
617                                 host->data_cnt += burst_len;
618                         }
619
620                         for(i = burst_len; i>0 ; i-=2)
621                                 MMC_BUFFER_ACCESS = *(host->data_ptr++);
622
623                         stat = MMC_STATUS;
624
625                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
626                                 burst_len, stat);
627                 }
628         }
629
630         *pstat = stat;
631
632         return trans_done;
633 }
634
635 static void imxmci_dma_irq(int dma, void *devid)
636 {
637         struct imxmci_host *host = devid;
638         uint32_t stat = MMC_STATUS;
639
640         atomic_set(&host->stuck_timeout, 0);
641         host->status_reg = stat;
642         set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
643         tasklet_schedule(&host->tasklet);
644 }
645
646 static irqreturn_t imxmci_irq(int irq, void *devid)
647 {
648         struct imxmci_host *host = devid;
649         uint32_t stat = MMC_STATUS;
650         int handled = 1;
651
652         MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
653
654         atomic_set(&host->stuck_timeout, 0);
655         host->status_reg = stat;
656         set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
657         set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
658         tasklet_schedule(&host->tasklet);
659
660         return IRQ_RETVAL(handled);;
661 }
662
663 static void imxmci_tasklet_fnc(unsigned long data)
664 {
665         struct imxmci_host *host = (struct imxmci_host *)data;
666         u32 stat;
667         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
668         int timeout = 0;
669
670         if(atomic_read(&host->stuck_timeout) > 4) {
671                 char *what;
672                 timeout = 1;
673                 stat = MMC_STATUS;
674                 host->status_reg = stat;
675                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
676                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
677                                 what = "RESP+DMA";
678                         else
679                                 what = "RESP";
680                 else
681                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
682                                 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
683                                         what = "DATA";
684                                 else
685                                         what = "DMA";
686                         else
687                                 what = "???";
688
689                 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
690                        what, stat, MMC_INT_MASK);
691                 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
692                        MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
693                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
694                        host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
695         }
696
697         if(!host->present || timeout)
698                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
699                                     STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
700
701         if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
702                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
703
704                 stat = MMC_STATUS;
705                 /*
706                  * This is not required in theory, but there is chance to miss some flag
707                  * which clears automatically by mask write, FreeScale original code keeps
708                  * stat from IRQ time so do I
709                  */
710                 stat |= host->status_reg;
711
712                 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
713                         imxmci_busy_wait_for_status(host, &stat,
714                                         STATUS_END_CMD_RESP | STATUS_ERR_MASK,
715                                         20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
716                 }
717
718                 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
719                         if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
720                                 imxmci_cmd_done(host, stat);
721                         if(host->data && (stat & STATUS_ERR_MASK))
722                                 imxmci_data_done(host, stat);
723                 }
724
725                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
726                         stat |= MMC_STATUS;
727                         if(imxmci_cpu_driven_data(host, &stat)){
728                                 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
729                                         imxmci_cmd_done(host, stat);
730                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
731                                                         &host->pending_events);
732                                 imxmci_data_done(host, stat);
733                         }
734                 }
735         }
736
737         if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
738            !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
739
740                 stat = MMC_STATUS;
741                 /* Same as above */
742                 stat |= host->status_reg;
743
744                 if(host->dma_dir == DMA_TO_DEVICE) {
745                         data_dir_mask = STATUS_WRITE_OP_DONE;
746                 } else {
747                         data_dir_mask = STATUS_DATA_TRANS_DONE;
748                 }
749
750                 if(stat & data_dir_mask) {
751                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
752                         imxmci_data_done(host, stat);
753                 }
754         }
755
756         if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
757
758                 if(host->cmd)
759                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
760
761                 if(host->data)
762                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
763                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
764
765                 if(host->req)
766                         imxmci_finish_request(host, host->req);
767
768                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
769
770         }
771 }
772
773 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
774 {
775         struct imxmci_host *host = mmc_priv(mmc);
776         unsigned int cmdat;
777
778         WARN_ON(host->req != NULL);
779
780         host->req = req;
781
782         cmdat = 0;
783
784         if (req->data) {
785                 imxmci_setup_data(host, req->data);
786
787                 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
788
789                 if (req->data->flags & MMC_DATA_WRITE)
790                         cmdat |= CMD_DAT_CONT_WRITE;
791
792                 if (req->data->flags & MMC_DATA_STREAM) {
793                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
794                 }
795         }
796
797         imxmci_start_cmd(host, req->cmd, cmdat);
798 }
799
800 #define CLK_RATE 19200000
801
802 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
803 {
804         struct imxmci_host *host = mmc_priv(mmc);
805         int prescaler;
806
807         if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
808                 host->actual_bus_width = MMC_BUS_WIDTH_4;
809                 imx_gpio_mode(PB11_PF_SD_DAT3);
810         }else{
811                 host->actual_bus_width = MMC_BUS_WIDTH_1;
812                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
813         }
814
815         if ( host->power_mode != ios->power_mode ) {
816                 switch (ios->power_mode) {
817                 case MMC_POWER_OFF:
818                         break;
819                 case MMC_POWER_UP:
820                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
821                         break;
822                 case MMC_POWER_ON:
823                         break;
824                 }
825                 host->power_mode = ios->power_mode;
826         }
827
828         if ( ios->clock ) {
829                 unsigned int clk;
830
831                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
832                  * then 96MHz / 5 = 19.2 MHz
833                  */
834                 clk=imx_get_perclk2();
835                 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
836                 switch(prescaler) {
837                 case 0:
838                 case 1: prescaler = 0;
839                         break;
840                 case 2: prescaler = 1;
841                         break;
842                 case 3: prescaler = 2;
843                         break;
844                 case 4: prescaler = 4;
845                         break;
846                 default:
847                 case 5: prescaler = 5;
848                         break;
849                 }
850
851                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
852                         clk, prescaler);
853
854                 for(clk=0; clk<8; clk++) {
855                         int x;
856                         x = CLK_RATE / (1<<clk);
857                         if( x <= ios->clock)
858                                 break;
859                 }
860
861                 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
862
863                 imxmci_stop_clock(host);
864                 MMC_CLK_RATE = (prescaler<<3) | clk;
865                 /*
866                  * Under my understanding, clock should not be started there, because it would
867                  * initiate SDHC sequencer and send last or random command into card
868                  */
869                 /*imxmci_start_clock(host);*/
870
871                 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
872         } else {
873                 imxmci_stop_clock(host);
874         }
875 }
876
877 static const struct mmc_host_ops imxmci_ops = {
878         .request        = imxmci_request,
879         .set_ios        = imxmci_set_ios,
880 };
881
882 static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr)
883 {
884         int i;
885
886         for (i = 0; i < dev->num_resources; i++)
887                 if (dev->resource[i].flags == mask && nr-- == 0)
888                         return &dev->resource[i];
889         return NULL;
890 }
891
892 static int platform_device_irq(struct platform_device *dev, int nr)
893 {
894         int i;
895
896         for (i = 0; i < dev->num_resources; i++)
897                 if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0)
898                         return dev->resource[i].start;
899         return NO_IRQ;
900 }
901
902 static void imxmci_check_status(unsigned long data)
903 {
904         struct imxmci_host *host = (struct imxmci_host *)data;
905
906         if( host->pdata->card_present() != host->present ) {
907                 host->present ^= 1;
908                 dev_info(mmc_dev(host->mmc), "card %s\n",
909                       host->present ? "inserted" : "removed");
910
911                 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
912                 tasklet_schedule(&host->tasklet);
913         }
914
915         if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
916            test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
917                 atomic_inc(&host->stuck_timeout);
918                 if(atomic_read(&host->stuck_timeout) > 4)
919                         tasklet_schedule(&host->tasklet);
920         } else {
921                 atomic_set(&host->stuck_timeout, 0);
922
923         }
924
925         mod_timer(&host->timer, jiffies + (HZ>>1));
926 }
927
928 static int imxmci_probe(struct platform_device *pdev)
929 {
930         struct mmc_host *mmc;
931         struct imxmci_host *host = NULL;
932         struct resource *r;
933         int ret = 0, irq;
934
935         printk(KERN_INFO "i.MX mmc driver\n");
936
937         r = platform_device_resource(pdev, IORESOURCE_MEM, 0);
938         irq = platform_device_irq(pdev, 0);
939         if (!r || irq == NO_IRQ)
940                 return -ENXIO;
941
942         r = request_mem_region(r->start, 0x100, "IMXMCI");
943         if (!r)
944                 return -EBUSY;
945
946         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
947         if (!mmc) {
948                 ret = -ENOMEM;
949                 goto out;
950         }
951
952         mmc->ops = &imxmci_ops;
953         mmc->f_min = 150000;
954         mmc->f_max = CLK_RATE/2;
955         mmc->ocr_avail = MMC_VDD_32_33;
956         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_BYTEBLOCK;
957
958         /* MMC core transfer sizes tunable parameters */
959         mmc->max_hw_segs = 64;
960         mmc->max_phys_segs = 64;
961         mmc->max_sectors = 64;          /* default 1 << (PAGE_CACHE_SHIFT - 9) */
962         mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
963
964         host = mmc_priv(mmc);
965         host->mmc = mmc;
966         host->dma_allocated = 0;
967         host->pdata = pdev->dev.platform_data;
968
969         spin_lock_init(&host->lock);
970         host->res = r;
971         host->irq = irq;
972
973         imx_gpio_mode(PB8_PF_SD_DAT0);
974         imx_gpio_mode(PB9_PF_SD_DAT1);
975         imx_gpio_mode(PB10_PF_SD_DAT2);
976         /* Configured as GPIO with pull-up to ensure right MCC card mode */
977         /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
978         imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
979         /* imx_gpio_mode(PB11_PF_SD_DAT3); */
980         imx_gpio_mode(PB12_PF_SD_CLK);
981         imx_gpio_mode(PB13_PF_SD_CMD);
982
983         imxmci_softreset();
984
985         if ( MMC_REV_NO != 0x390 ) {
986                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
987                         MMC_REV_NO);
988                 goto out;
989         }
990
991         MMC_READ_TO = 0x2db4; /* recommended in data sheet */
992
993         host->imask = IMXMCI_INT_MASK_DEFAULT;
994         MMC_INT_MASK = host->imask;
995
996
997         if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){
998                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
999                 ret = -EBUSY;
1000                 goto out;
1001         }
1002         host->dma_allocated=1;
1003         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1004
1005         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1006         host->status_reg=0;
1007         host->pending_events=0;
1008
1009         ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1010         if (ret)
1011                 goto out;
1012
1013         host->present = host->pdata->card_present();
1014         init_timer(&host->timer);
1015         host->timer.data = (unsigned long)host;
1016         host->timer.function = imxmci_check_status;
1017         add_timer(&host->timer);
1018         mod_timer(&host->timer, jiffies + (HZ>>1));
1019
1020         platform_set_drvdata(pdev, mmc);
1021
1022         mmc_add_host(mmc);
1023
1024         return 0;
1025
1026 out:
1027         if (host) {
1028                 if(host->dma_allocated){
1029                         imx_dma_free(host->dma);
1030                         host->dma_allocated=0;
1031                 }
1032         }
1033         if (mmc)
1034                 mmc_free_host(mmc);
1035         release_resource(r);
1036         return ret;
1037 }
1038
1039 static int imxmci_remove(struct platform_device *pdev)
1040 {
1041         struct mmc_host *mmc = platform_get_drvdata(pdev);
1042
1043         platform_set_drvdata(pdev, NULL);
1044
1045         if (mmc) {
1046                 struct imxmci_host *host = mmc_priv(mmc);
1047
1048                 tasklet_disable(&host->tasklet);
1049
1050                 del_timer_sync(&host->timer);
1051                 mmc_remove_host(mmc);
1052
1053                 free_irq(host->irq, host);
1054                 if(host->dma_allocated){
1055                         imx_dma_free(host->dma);
1056                         host->dma_allocated=0;
1057                 }
1058
1059                 tasklet_kill(&host->tasklet);
1060
1061                 release_resource(host->res);
1062
1063                 mmc_free_host(mmc);
1064         }
1065         return 0;
1066 }
1067
1068 #ifdef CONFIG_PM
1069 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1070 {
1071         struct mmc_host *mmc = platform_get_drvdata(dev);
1072         int ret = 0;
1073
1074         if (mmc)
1075                 ret = mmc_suspend_host(mmc, state);
1076
1077         return ret;
1078 }
1079
1080 static int imxmci_resume(struct platform_device *dev)
1081 {
1082         struct mmc_host *mmc = platform_get_drvdata(dev);
1083         struct imxmci_host *host;
1084         int ret = 0;
1085
1086         if (mmc) {
1087                 host = mmc_priv(mmc);
1088                 if(host)
1089                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1090                 ret = mmc_resume_host(mmc);
1091         }
1092
1093         return ret;
1094 }
1095 #else
1096 #define imxmci_suspend  NULL
1097 #define imxmci_resume   NULL
1098 #endif /* CONFIG_PM */
1099
1100 static struct platform_driver imxmci_driver = {
1101         .probe          = imxmci_probe,
1102         .remove         = imxmci_remove,
1103         .suspend        = imxmci_suspend,
1104         .resume         = imxmci_resume,
1105         .driver         = {
1106                 .name           = DRIVER_NAME,
1107         }
1108 };
1109
1110 static int __init imxmci_init(void)
1111 {
1112         return platform_driver_register(&imxmci_driver);
1113 }
1114
1115 static void __exit imxmci_exit(void)
1116 {
1117         platform_driver_unregister(&imxmci_driver);
1118 }
1119
1120 module_init(imxmci_init);
1121 module_exit(imxmci_exit);
1122
1123 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1124 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1125 MODULE_LICENSE("GPL");