06e7fcd192217317bef3d0159c5823144ca6619a
[linux-2.6.git] / drivers / mmc / imxmmc.c
1 /*
2  *  linux/drivers/mmc/imxmmc.c - Motorola i.MX MMCI driver
3  *
4  *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6  *
7  *  derived from pxamci.c by Russell King
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14  *             Changed to conform redesigned i.MX scatter gather DMA interface
15  *
16  *  2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17  *             Updated for 2.6.14 kernel
18  *
19  *  2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20  *             Found and corrected problems in the write path
21  *
22  *  2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23  *             The event handling rewritten right way in softirq.
24  *             Added many ugly hacks and delays to overcome SDHC
25  *             deficiencies
26  *
27  */
28
29 #ifdef CONFIG_MMC_DEBUG
30 #define DEBUG
31 #else
32 #undef  DEBUG
33 #endif
34
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/blkdev.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/protocol.h>
45 #include <linux/delay.h>
46
47 #include <asm/dma.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/sizes.h>
51 #include <asm/arch/mmc.h>
52 #include <asm/arch/imx-dma.h>
53
54 #include "imxmmc.h"
55
56 #define DRIVER_NAME "imx-mmc"
57
58 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
59                       INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
60                       INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
61
62 struct imxmci_host {
63         struct mmc_host         *mmc;
64         spinlock_t              lock;
65         struct resource         *res;
66         int                     irq;
67         imx_dmach_t             dma;
68         unsigned int            clkrt;
69         unsigned int            cmdat;
70         volatile unsigned int   imask;
71         unsigned int            power_mode;
72         unsigned int            present;
73         struct imxmmc_platform_data *pdata;
74
75         struct mmc_request      *req;
76         struct mmc_command      *cmd;
77         struct mmc_data         *data;
78
79         struct timer_list       timer;
80         struct tasklet_struct   tasklet;
81         unsigned int            status_reg;
82         unsigned long           pending_events;
83         /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
84         u16                     *data_ptr;
85         unsigned int            data_cnt;
86         atomic_t                stuck_timeout;
87
88         unsigned int            dma_nents;
89         unsigned int            dma_size;
90         unsigned int            dma_dir;
91         int                     dma_allocated;
92
93         unsigned char           actual_bus_width;
94
95         int                     prev_cmd_code;
96 };
97
98 #define IMXMCI_PEND_IRQ_b       0
99 #define IMXMCI_PEND_DMA_END_b   1
100 #define IMXMCI_PEND_DMA_ERR_b   2
101 #define IMXMCI_PEND_WAIT_RESP_b 3
102 #define IMXMCI_PEND_DMA_DATA_b  4
103 #define IMXMCI_PEND_CPU_DATA_b  5
104 #define IMXMCI_PEND_CARD_XCHG_b 6
105 #define IMXMCI_PEND_SET_INIT_b  7
106 #define IMXMCI_PEND_STARTED_b   8
107
108 #define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
109 #define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
110 #define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
111 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
112 #define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
113 #define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
114 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
115 #define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
116 #define IMXMCI_PEND_STARTED_m   (1 << IMXMCI_PEND_STARTED_b)
117
118 static void imxmci_stop_clock(struct imxmci_host *host)
119 {
120         int i = 0;
121         MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
122         while(i < 0x1000) {
123                 if(!(i & 0x7f))
124                         MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
125
126                 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
127                         /* Check twice before cut */
128                         if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
129                                 return;
130                 }
131
132                 i++;
133         }
134         dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
135 }
136
137 static int imxmci_start_clock(struct imxmci_host *host)
138 {
139         unsigned int trials = 0;
140         unsigned int delay_limit = 128;
141         unsigned long flags;
142
143         MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
144
145         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
146
147         /*
148          * Command start of the clock, this usually succeeds in less
149          * then 6 delay loops, but during card detection (low clockrate)
150          * it takes up to 5000 delay loops and sometimes fails for the first time
151          */
152         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
153
154         do {
155                 unsigned int delay = delay_limit;
156
157                 while(delay--){
158                         if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
159                                 /* Check twice before cut */
160                                 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
161                                         return 0;
162
163                         if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
164                                 return 0;
165                 }
166
167                 local_irq_save(flags);
168                 /*
169                  * Ensure, that request is not doubled under all possible circumstances.
170                  * It is possible, that cock running state is missed, because some other
171                  * IRQ or schedule delays this function execution and the clocks has
172                  * been already stopped by other means (response processing, SDHC HW)
173                  */
174                 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
175                         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
176                 local_irq_restore(flags);
177
178         } while(++trials<256);
179
180         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
181
182         return -1;
183 }
184
185 static void imxmci_softreset(void)
186 {
187         /* reset sequence */
188         MMC_STR_STP_CLK = 0x8;
189         MMC_STR_STP_CLK = 0xD;
190         MMC_STR_STP_CLK = 0x5;
191         MMC_STR_STP_CLK = 0x5;
192         MMC_STR_STP_CLK = 0x5;
193         MMC_STR_STP_CLK = 0x5;
194         MMC_STR_STP_CLK = 0x5;
195         MMC_STR_STP_CLK = 0x5;
196         MMC_STR_STP_CLK = 0x5;
197         MMC_STR_STP_CLK = 0x5;
198
199         MMC_RES_TO = 0xff;
200         MMC_BLK_LEN = 512;
201         MMC_NOB = 1;
202 }
203
204 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
205                         unsigned int *pstat, unsigned int stat_mask,
206                         int timeout, const char *where)
207 {
208         int loops=0;
209         while(!(*pstat & stat_mask)) {
210                 loops+=2;
211                 if(loops >= timeout) {
212                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
213                                 where, *pstat, stat_mask);
214                         return -1;
215                 }
216                 udelay(2);
217                 *pstat |= MMC_STATUS;
218         }
219         if(!loops)
220                 return 0;
221
222         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
223         if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
224                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
225                         loops, where, *pstat, stat_mask);
226         return loops;
227 }
228
229 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
230 {
231         unsigned int nob = data->blocks;
232         unsigned int blksz = data->blksz;
233         unsigned int datasz = nob * blksz;
234         int i;
235
236         if (data->flags & MMC_DATA_STREAM)
237                 nob = 0xffff;
238
239         host->data = data;
240         data->bytes_xfered = 0;
241
242         MMC_NOB = nob;
243         MMC_BLK_LEN = blksz;
244
245         /*
246          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
247          * We are in big troubles for non-512 byte transfers according to note in the paragraph
248          * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
249          * The situation is even more complex in reality. The SDHC in not able to handle wll
250          * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
251          * This is required for SCR read at least.
252          */
253         if (datasz < 512) {
254                 host->dma_size = datasz;
255                 if (data->flags & MMC_DATA_READ) {
256                         host->dma_dir = DMA_FROM_DEVICE;
257
258                         /* Hack to enable read SCR */
259                         MMC_NOB = 1;
260                         MMC_BLK_LEN = 512;
261                 } else {
262                         host->dma_dir = DMA_TO_DEVICE;
263                 }
264
265                 /* Convert back to virtual address */
266                 host->data_ptr = (u16*)(page_address(data->sg->page) + data->sg->offset);
267                 host->data_cnt = 0;
268
269                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
270                 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
271
272                 return;
273         }
274
275         if (data->flags & MMC_DATA_READ) {
276                 host->dma_dir = DMA_FROM_DEVICE;
277                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
278                                                 data->sg_len,  host->dma_dir);
279
280                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
281                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
282
283                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
284                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
285         } else {
286                 host->dma_dir = DMA_TO_DEVICE;
287
288                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
289                                                 data->sg_len,  host->dma_dir);
290
291                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
292                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
293
294                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
295                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
296         }
297
298 #if 1   /* This code is there only for consistency checking and can be disabled in future */
299         host->dma_size = 0;
300         for(i=0; i<host->dma_nents; i++)
301                 host->dma_size+=data->sg[i].length;
302
303         if (datasz > host->dma_size) {
304                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
305                        datasz, host->dma_size);
306         }
307 #endif
308
309         host->dma_size = datasz;
310
311         wmb();
312
313         if(host->actual_bus_width == MMC_BUS_WIDTH_4)
314                 BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
315         else
316                 BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
317
318         RSSR(host->dma) = DMA_REQ_SDHC;
319
320         set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
321         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
322
323         /* start DMA engine for read, write is delayed after initial response */
324         if (host->dma_dir == DMA_FROM_DEVICE) {
325                 imx_dma_enable(host->dma);
326         }
327 }
328
329 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
330 {
331         unsigned long flags;
332         u32 imask;
333
334         WARN_ON(host->cmd != NULL);
335         host->cmd = cmd;
336
337         /* Ensure, that clock are stopped else command programming and start fails */
338         imxmci_stop_clock(host);
339
340         if (cmd->flags & MMC_RSP_BUSY)
341                 cmdat |= CMD_DAT_CONT_BUSY;
342
343         switch (mmc_resp_type(cmd)) {
344         case MMC_RSP_R1: /* short CRC, OPCODE */
345         case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
346                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
347                 break;
348         case MMC_RSP_R2: /* long 136 bit + CRC */
349                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
350                 break;
351         case MMC_RSP_R3: /* short */
352                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
353                 break;
354         case MMC_RSP_R6: /* short CRC */
355                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R6;
356                 break;
357         default:
358                 break;
359         }
360
361         if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
362                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
363
364         if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
365                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
366
367         MMC_CMD = cmd->opcode;
368         MMC_ARGH = cmd->arg >> 16;
369         MMC_ARGL = cmd->arg & 0xffff;
370         MMC_CMD_DAT_CONT = cmdat;
371
372         atomic_set(&host->stuck_timeout, 0);
373         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
374
375
376         imask = IMXMCI_INT_MASK_DEFAULT;
377         imask &= ~INT_MASK_END_CMD_RES;
378         if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
379                 /*imask &= ~INT_MASK_BUF_READY;*/
380                 imask &= ~INT_MASK_DATA_TRAN;
381                 if ( cmdat & CMD_DAT_CONT_WRITE )
382                         imask &= ~INT_MASK_WRITE_OP_DONE;
383                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
384                         imask &= ~INT_MASK_BUF_READY;
385         }
386
387         spin_lock_irqsave(&host->lock, flags);
388         host->imask = imask;
389         MMC_INT_MASK = host->imask;
390         spin_unlock_irqrestore(&host->lock, flags);
391
392         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
393                 cmd->opcode, cmd->opcode, imask);
394
395         imxmci_start_clock(host);
396 }
397
398 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
399 {
400         unsigned long flags;
401
402         spin_lock_irqsave(&host->lock, flags);
403
404         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
405                         IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
406
407         host->imask = IMXMCI_INT_MASK_DEFAULT;
408         MMC_INT_MASK = host->imask;
409
410         spin_unlock_irqrestore(&host->lock, flags);
411
412         if(req && req->cmd)
413                 host->prev_cmd_code = req->cmd->opcode;
414
415         host->req = NULL;
416         host->cmd = NULL;
417         host->data = NULL;
418         mmc_request_done(host->mmc, req);
419 }
420
421 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
422 {
423         struct mmc_data *data = host->data;
424         int data_error;
425
426         if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
427                 imx_dma_disable(host->dma);
428                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
429                              host->dma_dir);
430         }
431
432         if ( stat & STATUS_ERR_MASK ) {
433                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
434                 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
435                         data->error = MMC_ERR_BADCRC;
436                 else if(stat & STATUS_TIME_OUT_READ)
437                         data->error = MMC_ERR_TIMEOUT;
438                 else
439                         data->error = MMC_ERR_FAILED;
440         } else {
441                 data->bytes_xfered = host->dma_size;
442         }
443
444         data_error = data->error;
445
446         host->data = NULL;
447
448         return data_error;
449 }
450
451 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
452 {
453         struct mmc_command *cmd = host->cmd;
454         int i;
455         u32 a,b,c;
456         struct mmc_data *data = host->data;
457
458         if (!cmd)
459                 return 0;
460
461         host->cmd = NULL;
462
463         if (stat & STATUS_TIME_OUT_RESP) {
464                 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
465                 cmd->error = MMC_ERR_TIMEOUT;
466         } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
467                 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
468                 cmd->error = MMC_ERR_BADCRC;
469         }
470
471         if(cmd->flags & MMC_RSP_PRESENT) {
472                 if(cmd->flags & MMC_RSP_136) {
473                         for (i = 0; i < 4; i++) {
474                                 u32 a = MMC_RES_FIFO & 0xffff;
475                                 u32 b = MMC_RES_FIFO & 0xffff;
476                                 cmd->resp[i] = a<<16 | b;
477                         }
478                 } else {
479                         a = MMC_RES_FIFO & 0xffff;
480                         b = MMC_RES_FIFO & 0xffff;
481                         c = MMC_RES_FIFO & 0xffff;
482                         cmd->resp[0] = a<<24 | b<<8 | c>>8;
483                 }
484         }
485
486         dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
487                 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
488
489         if (data && (cmd->error == MMC_ERR_NONE) && !(stat & STATUS_ERR_MASK)) {
490                 if (host->req->data->flags & MMC_DATA_WRITE) {
491
492                         /* Wait for FIFO to be empty before starting DMA write */
493
494                         stat = MMC_STATUS;
495                         if(imxmci_busy_wait_for_status(host, &stat,
496                                 STATUS_APPL_BUFF_FE,
497                                 40, "imxmci_cmd_done DMA WR") < 0) {
498                                 cmd->error = MMC_ERR_FIFO;
499                                 imxmci_finish_data(host, stat);
500                                 if(host->req)
501                                         imxmci_finish_request(host, host->req);
502                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
503                                        stat);
504                                 return 0;
505                         }
506
507                         if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
508                                 imx_dma_enable(host->dma);
509                         }
510                 }
511         } else {
512                 struct mmc_request *req;
513                 imxmci_stop_clock(host);
514                 req = host->req;
515
516                 if(data)
517                         imxmci_finish_data(host, stat);
518
519                 if( req ) {
520                         imxmci_finish_request(host, req);
521                 } else {
522                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
523                 }
524         }
525
526         return 1;
527 }
528
529 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
530 {
531         struct mmc_data *data = host->data;
532         int data_error;
533
534         if (!data)
535                 return 0;
536
537         data_error = imxmci_finish_data(host, stat);
538
539         if (host->req->stop) {
540                 imxmci_stop_clock(host);
541                 imxmci_start_cmd(host, host->req->stop, 0);
542         } else {
543                 struct mmc_request *req;
544                 req = host->req;
545                 if( req ) {
546                         imxmci_finish_request(host, req);
547                 } else {
548                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
549                 }
550         }
551
552         return 1;
553 }
554
555 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
556 {
557         int i;
558         int burst_len;
559         int trans_done = 0;
560         unsigned int stat = *pstat;
561
562         if(host->actual_bus_width != MMC_BUS_WIDTH_4)
563                 burst_len = 16;
564         else
565                 burst_len = 64;
566
567         /* This is unfortunately required */
568         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
569                 stat);
570
571         udelay(20);     /* required for clocks < 8MHz*/
572
573         if(host->dma_dir == DMA_FROM_DEVICE) {
574                 imxmci_busy_wait_for_status(host, &stat,
575                                 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE,
576                                 50, "imxmci_cpu_driven_data read");
577
578                 while((stat & (STATUS_APPL_BUFF_FF |  STATUS_DATA_TRANS_DONE)) &&
579                       (host->data_cnt < 512)) {
580
581                         udelay(20);     /* required for clocks < 8MHz*/
582
583                         for(i = burst_len; i>=2 ; i-=2) {
584                                 u16 data;
585                                 data = MMC_BUFFER_ACCESS;
586                                 udelay(10);     /* required for clocks < 8MHz*/
587                                 if(host->data_cnt+2 <= host->dma_size) {
588                                         *(host->data_ptr++) = data;
589                                 } else {
590                                         if(host->data_cnt < host->dma_size)
591                                                 *(u8*)(host->data_ptr) = data;
592                                 }
593                                 host->data_cnt += 2;
594                         }
595
596                         stat = MMC_STATUS;
597
598                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
599                                 host->data_cnt, burst_len, stat);
600                 }
601
602                 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
603                         trans_done = 1;
604
605                 if(host->dma_size & 0x1ff)
606                         stat &= ~STATUS_CRC_READ_ERR;
607
608         } else {
609                 imxmci_busy_wait_for_status(host, &stat,
610                                 STATUS_APPL_BUFF_FE,
611                                 20, "imxmci_cpu_driven_data write");
612
613                 while((stat & STATUS_APPL_BUFF_FE) &&
614                       (host->data_cnt < host->dma_size)) {
615                         if(burst_len >= host->dma_size - host->data_cnt) {
616                                 burst_len = host->dma_size - host->data_cnt;
617                                 host->data_cnt = host->dma_size;
618                                 trans_done = 1;
619                         } else {
620                                 host->data_cnt += burst_len;
621                         }
622
623                         for(i = burst_len; i>0 ; i-=2)
624                                 MMC_BUFFER_ACCESS = *(host->data_ptr++);
625
626                         stat = MMC_STATUS;
627
628                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
629                                 burst_len, stat);
630                 }
631         }
632
633         *pstat = stat;
634
635         return trans_done;
636 }
637
638 static void imxmci_dma_irq(int dma, void *devid)
639 {
640         struct imxmci_host *host = devid;
641         uint32_t stat = MMC_STATUS;
642
643         atomic_set(&host->stuck_timeout, 0);
644         host->status_reg = stat;
645         set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
646         tasklet_schedule(&host->tasklet);
647 }
648
649 static irqreturn_t imxmci_irq(int irq, void *devid)
650 {
651         struct imxmci_host *host = devid;
652         uint32_t stat = MMC_STATUS;
653         int handled = 1;
654
655         MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
656
657         atomic_set(&host->stuck_timeout, 0);
658         host->status_reg = stat;
659         set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
660         set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
661         tasklet_schedule(&host->tasklet);
662
663         return IRQ_RETVAL(handled);;
664 }
665
666 static void imxmci_tasklet_fnc(unsigned long data)
667 {
668         struct imxmci_host *host = (struct imxmci_host *)data;
669         u32 stat;
670         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
671         int timeout = 0;
672
673         if(atomic_read(&host->stuck_timeout) > 4) {
674                 char *what;
675                 timeout = 1;
676                 stat = MMC_STATUS;
677                 host->status_reg = stat;
678                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
679                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
680                                 what = "RESP+DMA";
681                         else
682                                 what = "RESP";
683                 else
684                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
685                                 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
686                                         what = "DATA";
687                                 else
688                                         what = "DMA";
689                         else
690                                 what = "???";
691
692                 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
693                        what, stat, MMC_INT_MASK);
694                 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
695                        MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
696                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
697                        host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
698         }
699
700         if(!host->present || timeout)
701                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
702                                     STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
703
704         if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
705                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
706
707                 stat = MMC_STATUS;
708                 /*
709                  * This is not required in theory, but there is chance to miss some flag
710                  * which clears automatically by mask write, FreeScale original code keeps
711                  * stat from IRQ time so do I
712                  */
713                 stat |= host->status_reg;
714
715                 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
716                         imxmci_busy_wait_for_status(host, &stat,
717                                         STATUS_END_CMD_RESP | STATUS_ERR_MASK,
718                                         20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
719                 }
720
721                 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
722                         if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
723                                 imxmci_cmd_done(host, stat);
724                         if(host->data && (stat & STATUS_ERR_MASK))
725                                 imxmci_data_done(host, stat);
726                 }
727
728                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
729                         stat |= MMC_STATUS;
730                         if(imxmci_cpu_driven_data(host, &stat)){
731                                 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
732                                         imxmci_cmd_done(host, stat);
733                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
734                                                         &host->pending_events);
735                                 imxmci_data_done(host, stat);
736                         }
737                 }
738         }
739
740         if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
741            !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
742
743                 stat = MMC_STATUS;
744                 /* Same as above */
745                 stat |= host->status_reg;
746
747                 if(host->dma_dir == DMA_TO_DEVICE) {
748                         data_dir_mask = STATUS_WRITE_OP_DONE;
749                 } else {
750                         data_dir_mask = STATUS_DATA_TRANS_DONE;
751                 }
752
753                 if(stat & data_dir_mask) {
754                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
755                         imxmci_data_done(host, stat);
756                 }
757         }
758
759         if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
760
761                 if(host->cmd)
762                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
763
764                 if(host->data)
765                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
766                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
767
768                 if(host->req)
769                         imxmci_finish_request(host, host->req);
770
771                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
772
773         }
774 }
775
776 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
777 {
778         struct imxmci_host *host = mmc_priv(mmc);
779         unsigned int cmdat;
780
781         WARN_ON(host->req != NULL);
782
783         host->req = req;
784
785         cmdat = 0;
786
787         if (req->data) {
788                 imxmci_setup_data(host, req->data);
789
790                 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
791
792                 if (req->data->flags & MMC_DATA_WRITE)
793                         cmdat |= CMD_DAT_CONT_WRITE;
794
795                 if (req->data->flags & MMC_DATA_STREAM) {
796                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
797                 }
798         }
799
800         imxmci_start_cmd(host, req->cmd, cmdat);
801 }
802
803 #define CLK_RATE 19200000
804
805 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
806 {
807         struct imxmci_host *host = mmc_priv(mmc);
808         int prescaler;
809
810         if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
811                 host->actual_bus_width = MMC_BUS_WIDTH_4;
812                 imx_gpio_mode(PB11_PF_SD_DAT3);
813         }else{
814                 host->actual_bus_width = MMC_BUS_WIDTH_1;
815                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
816         }
817
818         if ( host->power_mode != ios->power_mode ) {
819                 switch (ios->power_mode) {
820                 case MMC_POWER_OFF:
821                         break;
822                 case MMC_POWER_UP:
823                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
824                         break;
825                 case MMC_POWER_ON:
826                         break;
827                 }
828                 host->power_mode = ios->power_mode;
829         }
830
831         if ( ios->clock ) {
832                 unsigned int clk;
833
834                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
835                  * then 96MHz / 5 = 19.2 MHz
836                  */
837                 clk=imx_get_perclk2();
838                 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
839                 switch(prescaler) {
840                 case 0:
841                 case 1: prescaler = 0;
842                         break;
843                 case 2: prescaler = 1;
844                         break;
845                 case 3: prescaler = 2;
846                         break;
847                 case 4: prescaler = 4;
848                         break;
849                 default:
850                 case 5: prescaler = 5;
851                         break;
852                 }
853
854                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
855                         clk, prescaler);
856
857                 for(clk=0; clk<8; clk++) {
858                         int x;
859                         x = CLK_RATE / (1<<clk);
860                         if( x <= ios->clock)
861                                 break;
862                 }
863
864                 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
865
866                 imxmci_stop_clock(host);
867                 MMC_CLK_RATE = (prescaler<<3) | clk;
868                 /*
869                  * Under my understanding, clock should not be started there, because it would
870                  * initiate SDHC sequencer and send last or random command into card
871                  */
872                 /*imxmci_start_clock(host);*/
873
874                 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
875         } else {
876                 imxmci_stop_clock(host);
877         }
878 }
879
880 static const struct mmc_host_ops imxmci_ops = {
881         .request        = imxmci_request,
882         .set_ios        = imxmci_set_ios,
883 };
884
885 static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr)
886 {
887         int i;
888
889         for (i = 0; i < dev->num_resources; i++)
890                 if (dev->resource[i].flags == mask && nr-- == 0)
891                         return &dev->resource[i];
892         return NULL;
893 }
894
895 static int platform_device_irq(struct platform_device *dev, int nr)
896 {
897         int i;
898
899         for (i = 0; i < dev->num_resources; i++)
900                 if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0)
901                         return dev->resource[i].start;
902         return NO_IRQ;
903 }
904
905 static void imxmci_check_status(unsigned long data)
906 {
907         struct imxmci_host *host = (struct imxmci_host *)data;
908
909         if( host->pdata->card_present() != host->present ) {
910                 host->present ^= 1;
911                 dev_info(mmc_dev(host->mmc), "card %s\n",
912                       host->present ? "inserted" : "removed");
913
914                 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
915                 tasklet_schedule(&host->tasklet);
916         }
917
918         if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
919            test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
920                 atomic_inc(&host->stuck_timeout);
921                 if(atomic_read(&host->stuck_timeout) > 4)
922                         tasklet_schedule(&host->tasklet);
923         } else {
924                 atomic_set(&host->stuck_timeout, 0);
925
926         }
927
928         mod_timer(&host->timer, jiffies + (HZ>>1));
929 }
930
931 static int imxmci_probe(struct platform_device *pdev)
932 {
933         struct mmc_host *mmc;
934         struct imxmci_host *host = NULL;
935         struct resource *r;
936         int ret = 0, irq;
937
938         printk(KERN_INFO "i.MX mmc driver\n");
939
940         r = platform_device_resource(pdev, IORESOURCE_MEM, 0);
941         irq = platform_device_irq(pdev, 0);
942         if (!r || irq == NO_IRQ)
943                 return -ENXIO;
944
945         r = request_mem_region(r->start, 0x100, "IMXMCI");
946         if (!r)
947                 return -EBUSY;
948
949         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
950         if (!mmc) {
951                 ret = -ENOMEM;
952                 goto out;
953         }
954
955         mmc->ops = &imxmci_ops;
956         mmc->f_min = 150000;
957         mmc->f_max = CLK_RATE/2;
958         mmc->ocr_avail = MMC_VDD_32_33;
959         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_BYTEBLOCK;
960
961         /* MMC core transfer sizes tunable parameters */
962         mmc->max_hw_segs = 64;
963         mmc->max_phys_segs = 64;
964         mmc->max_sectors = 64;          /* default 1 << (PAGE_CACHE_SHIFT - 9) */
965         mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
966
967         host = mmc_priv(mmc);
968         host->mmc = mmc;
969         host->dma_allocated = 0;
970         host->pdata = pdev->dev.platform_data;
971
972         spin_lock_init(&host->lock);
973         host->res = r;
974         host->irq = irq;
975
976         imx_gpio_mode(PB8_PF_SD_DAT0);
977         imx_gpio_mode(PB9_PF_SD_DAT1);
978         imx_gpio_mode(PB10_PF_SD_DAT2);
979         /* Configured as GPIO with pull-up to ensure right MCC card mode */
980         /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
981         imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
982         /* imx_gpio_mode(PB11_PF_SD_DAT3); */
983         imx_gpio_mode(PB12_PF_SD_CLK);
984         imx_gpio_mode(PB13_PF_SD_CMD);
985
986         imxmci_softreset();
987
988         if ( MMC_REV_NO != 0x390 ) {
989                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
990                         MMC_REV_NO);
991                 goto out;
992         }
993
994         MMC_READ_TO = 0x2db4; /* recommended in data sheet */
995
996         host->imask = IMXMCI_INT_MASK_DEFAULT;
997         MMC_INT_MASK = host->imask;
998
999
1000         if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){
1001                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1002                 ret = -EBUSY;
1003                 goto out;
1004         }
1005         host->dma_allocated=1;
1006         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1007
1008         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1009         host->status_reg=0;
1010         host->pending_events=0;
1011
1012         ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1013         if (ret)
1014                 goto out;
1015
1016         host->present = host->pdata->card_present();
1017         init_timer(&host->timer);
1018         host->timer.data = (unsigned long)host;
1019         host->timer.function = imxmci_check_status;
1020         add_timer(&host->timer);
1021         mod_timer(&host->timer, jiffies + (HZ>>1));
1022
1023         platform_set_drvdata(pdev, mmc);
1024
1025         mmc_add_host(mmc);
1026
1027         return 0;
1028
1029 out:
1030         if (host) {
1031                 if(host->dma_allocated){
1032                         imx_dma_free(host->dma);
1033                         host->dma_allocated=0;
1034                 }
1035         }
1036         if (mmc)
1037                 mmc_free_host(mmc);
1038         release_resource(r);
1039         return ret;
1040 }
1041
1042 static int imxmci_remove(struct platform_device *pdev)
1043 {
1044         struct mmc_host *mmc = platform_get_drvdata(pdev);
1045
1046         platform_set_drvdata(pdev, NULL);
1047
1048         if (mmc) {
1049                 struct imxmci_host *host = mmc_priv(mmc);
1050
1051                 tasklet_disable(&host->tasklet);
1052
1053                 del_timer_sync(&host->timer);
1054                 mmc_remove_host(mmc);
1055
1056                 free_irq(host->irq, host);
1057                 if(host->dma_allocated){
1058                         imx_dma_free(host->dma);
1059                         host->dma_allocated=0;
1060                 }
1061
1062                 tasklet_kill(&host->tasklet);
1063
1064                 release_resource(host->res);
1065
1066                 mmc_free_host(mmc);
1067         }
1068         return 0;
1069 }
1070
1071 #ifdef CONFIG_PM
1072 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1073 {
1074         struct mmc_host *mmc = platform_get_drvdata(dev);
1075         int ret = 0;
1076
1077         if (mmc)
1078                 ret = mmc_suspend_host(mmc, state);
1079
1080         return ret;
1081 }
1082
1083 static int imxmci_resume(struct platform_device *dev)
1084 {
1085         struct mmc_host *mmc = platform_get_drvdata(dev);
1086         struct imxmci_host *host;
1087         int ret = 0;
1088
1089         if (mmc) {
1090                 host = mmc_priv(mmc);
1091                 if(host)
1092                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1093                 ret = mmc_resume_host(mmc);
1094         }
1095
1096         return ret;
1097 }
1098 #else
1099 #define imxmci_suspend  NULL
1100 #define imxmci_resume   NULL
1101 #endif /* CONFIG_PM */
1102
1103 static struct platform_driver imxmci_driver = {
1104         .probe          = imxmci_probe,
1105         .remove         = imxmci_remove,
1106         .suspend        = imxmci_suspend,
1107         .resume         = imxmci_resume,
1108         .driver         = {
1109                 .name           = DRIVER_NAME,
1110         }
1111 };
1112
1113 static int __init imxmci_init(void)
1114 {
1115         return platform_driver_register(&imxmci_driver);
1116 }
1117
1118 static void __exit imxmci_exit(void)
1119 {
1120         platform_driver_unregister(&imxmci_driver);
1121 }
1122
1123 module_init(imxmci_init);
1124 module_exit(imxmci_exit);
1125
1126 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1127 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1128 MODULE_LICENSE("GPL");