Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
[linux-2.6.git] / drivers / mmc / au1xmmc.c
1 /*
2  * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
3  *
4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
5  *
6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
7  *  the following copyright notices:
8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
9  *     Portions Copyright (C) 2002 Embedix, Inc
10  *     Copyright 2002 Hewlett-Packard Company
11
12  *  2.6 version of this driver inspired by:
13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14  *     All Rights Reserved.
15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16  *     All Rights Reserved.
17  *
18
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  */
23
24 /* Why is a timer used to detect insert events?
25  *
26  * From the AU1100 MMC application guide:
27  * If the Au1100-based design is intended to support both MultiMediaCards
28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30  * In doing so, a MMC card never enters SPI-mode communications,
31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32  * (the low to high transition will not occur).
33  *
34  * So we use the timer to check the status manually.
35  */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
40 #include <linux/mm.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43
44 #include <linux/mmc/host.h>
45 #include <linux/mmc/protocol.h>
46 #include <asm/io.h>
47 #include <asm/mach-au1x00/au1000.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49 #include <asm/mach-au1x00/au1100_mmc.h>
50 #include <asm/scatterlist.h>
51
52 #include <au1xxx.h>
53 #include "au1xmmc.h"
54
55 #define DRIVER_NAME "au1xxx-mmc"
56
57 /* Set this to enable special debugging macros */
58
59 #ifdef DEBUG
60 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
61 #else
62 #define DBG(fmt, idx, args...)
63 #endif
64
65 const struct {
66         u32 iobase;
67         u32 tx_devid, rx_devid;
68         u16 bcsrpwr;
69         u16 bcsrstatus;
70         u16 wpstatus;
71 } au1xmmc_card_table[] = {
72         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
73           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
74 #ifndef CONFIG_MIPS_DB1200
75         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
76           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
77 #endif
78 };
79
80 #define AU1XMMC_CONTROLLER_COUNT \
81         (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
82
83 /* This array stores pointers for the hosts (used by the IRQ handler) */
84 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
85 static int dma = 1;
86
87 #ifdef MODULE
88 module_param(dma, bool, 0);
89 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
90 #endif
91
92 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
93 {
94         u32 val = au_readl(HOST_CONFIG(host));
95         val |= mask;
96         au_writel(val, HOST_CONFIG(host));
97         au_sync();
98 }
99
100 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
101 {
102         u32 val = au_readl(HOST_CONFIG2(host));
103
104         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
105         au_sync_delay(1);
106
107         /* SEND_STOP will turn off clock control - this re-enables it */
108         val &= ~SD_CONFIG2_DF;
109
110         au_writel(val, HOST_CONFIG2(host));
111         au_sync();
112 }
113
114 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
115 {
116         u32 val = au_readl(HOST_CONFIG(host));
117         val &= ~mask;
118         au_writel(val, HOST_CONFIG(host));
119         au_sync();
120 }
121
122 static inline void SEND_STOP(struct au1xmmc_host *host)
123 {
124
125         /* We know the value of CONFIG2, so avoid a read we don't need */
126         u32 mask = SD_CONFIG2_EN;
127
128         WARN_ON(host->status != HOST_S_DATA);
129         host->status = HOST_S_STOP;
130
131         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
132         au_sync();
133
134         /* Send the stop commmand */
135         au_writel(STOP_CMD, HOST_CMD(host));
136 }
137
138 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
139 {
140
141         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
142
143         bcsr->board &= ~val;
144         if (state) bcsr->board |= val;
145
146         au_sync_delay(1);
147 }
148
149 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
150 {
151         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
152                 ? 1 : 0;
153 }
154
155 static int au1xmmc_card_readonly(struct mmc_host *mmc)
156 {
157         struct au1xmmc_host *host = mmc_priv(mmc);
158         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
159                 ? 1 : 0;
160 }
161
162 static void au1xmmc_finish_request(struct au1xmmc_host *host)
163 {
164
165         struct mmc_request *mrq = host->mrq;
166
167         host->mrq = NULL;
168         host->flags &= HOST_F_ACTIVE;
169
170         host->dma.len = 0;
171         host->dma.dir = 0;
172
173         host->pio.index  = 0;
174         host->pio.offset = 0;
175         host->pio.len = 0;
176
177         host->status = HOST_S_IDLE;
178
179         bcsr->disk_leds |= (1 << 8);
180
181         mmc_request_done(host->mmc, mrq);
182 }
183
184 static void au1xmmc_tasklet_finish(unsigned long param)
185 {
186         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
187         au1xmmc_finish_request(host);
188 }
189
190 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
191                                 struct mmc_command *cmd)
192 {
193
194         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
195
196         switch (mmc_resp_type(cmd)) {
197         case MMC_RSP_NONE:
198                 break;
199         case MMC_RSP_R1:
200                 mmccmd |= SD_CMD_RT_1;
201                 break;
202         case MMC_RSP_R1B:
203                 mmccmd |= SD_CMD_RT_1B;
204                 break;
205         case MMC_RSP_R2:
206                 mmccmd |= SD_CMD_RT_2;
207                 break;
208         case MMC_RSP_R3:
209                 mmccmd |= SD_CMD_RT_3;
210                 break;
211         default:
212                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
213                         mmc_resp_type(cmd));
214                 return MMC_ERR_INVALID;
215         }
216
217         switch(cmd->opcode) {
218         case MMC_READ_SINGLE_BLOCK:
219         case SD_APP_SEND_SCR:
220                 mmccmd |= SD_CMD_CT_2;
221                 break;
222         case MMC_READ_MULTIPLE_BLOCK:
223                 mmccmd |= SD_CMD_CT_4;
224                 break;
225         case MMC_WRITE_BLOCK:
226                 mmccmd |= SD_CMD_CT_1;
227                 break;
228
229         case MMC_WRITE_MULTIPLE_BLOCK:
230                 mmccmd |= SD_CMD_CT_3;
231                 break;
232         case MMC_STOP_TRANSMISSION:
233                 mmccmd |= SD_CMD_CT_7;
234                 break;
235         }
236
237         au_writel(cmd->arg, HOST_CMDARG(host));
238         au_sync();
239
240         if (wait)
241                 IRQ_OFF(host, SD_CONFIG_CR);
242
243         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
244         au_sync();
245
246         /* Wait for the command to go on the line */
247
248         while(1) {
249                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
250                         break;
251         }
252
253         /* Wait for the command to come back */
254
255         if (wait) {
256                 u32 status = au_readl(HOST_STATUS(host));
257
258                 while(!(status & SD_STATUS_CR))
259                         status = au_readl(HOST_STATUS(host));
260
261                 /* Clear the CR status */
262                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
263
264                 IRQ_ON(host, SD_CONFIG_CR);
265         }
266
267         return MMC_ERR_NONE;
268 }
269
270 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
271 {
272
273         struct mmc_request *mrq = host->mrq;
274         struct mmc_data *data;
275         u32 crc;
276
277         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
278
279         if (host->mrq == NULL)
280                 return;
281
282         data = mrq->cmd->data;
283
284         if (status == 0)
285                 status = au_readl(HOST_STATUS(host));
286
287         /* The transaction is really over when the SD_STATUS_DB bit is clear */
288
289         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
290                 status = au_readl(HOST_STATUS(host));
291
292         data->error = MMC_ERR_NONE;
293         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
294
295         /* Process any errors */
296
297         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
298         if (host->flags & HOST_F_XMIT)
299                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
300
301         if (crc)
302                 data->error = MMC_ERR_BADCRC;
303
304         /* Clear the CRC bits */
305         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
306
307         data->bytes_xfered = 0;
308
309         if (data->error == MMC_ERR_NONE) {
310                 if (host->flags & HOST_F_DMA) {
311                         u32 chan = DMA_CHANNEL(host);
312
313                         chan_tab_t *c = *((chan_tab_t **) chan);
314                         au1x_dma_chan_t *cp = c->chan_ptr;
315                         data->bytes_xfered = cp->ddma_bytecnt;
316                 }
317                 else
318                         data->bytes_xfered =
319                                 (data->blocks * data->blksz) -
320                                 host->pio.len;
321         }
322
323         au1xmmc_finish_request(host);
324 }
325
326 static void au1xmmc_tasklet_data(unsigned long param)
327 {
328         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
329
330         u32 status = au_readl(HOST_STATUS(host));
331         au1xmmc_data_complete(host, status);
332 }
333
334 #define AU1XMMC_MAX_TRANSFER 8
335
336 static void au1xmmc_send_pio(struct au1xmmc_host *host)
337 {
338
339         struct mmc_data *data = 0;
340         int sg_len, max, count = 0;
341         unsigned char *sg_ptr;
342         u32 status = 0;
343         struct scatterlist *sg;
344
345         data = host->mrq->data;
346
347         if (!(host->flags & HOST_F_XMIT))
348                 return;
349
350         /* This is the pointer to the data buffer */
351         sg = &data->sg[host->pio.index];
352         sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
353
354         /* This is the space left inside the buffer */
355         sg_len = data->sg[host->pio.index].length - host->pio.offset;
356
357         /* Check to if we need less then the size of the sg_buffer */
358
359         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
360         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
361
362         for(count = 0; count < max; count++ ) {
363                 unsigned char val;
364
365                 status = au_readl(HOST_STATUS(host));
366
367                 if (!(status & SD_STATUS_TH))
368                         break;
369
370                 val = *sg_ptr++;
371
372                 au_writel((unsigned long) val, HOST_TXPORT(host));
373                 au_sync();
374         }
375
376         host->pio.len -= count;
377         host->pio.offset += count;
378
379         if (count == sg_len) {
380                 host->pio.index++;
381                 host->pio.offset = 0;
382         }
383
384         if (host->pio.len == 0) {
385                 IRQ_OFF(host, SD_CONFIG_TH);
386
387                 if (host->flags & HOST_F_STOP)
388                         SEND_STOP(host);
389
390                 tasklet_schedule(&host->data_task);
391         }
392 }
393
394 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
395 {
396
397         struct mmc_data *data = 0;
398         int sg_len = 0, max = 0, count = 0;
399         unsigned char *sg_ptr = 0;
400         u32 status = 0;
401         struct scatterlist *sg;
402
403         data = host->mrq->data;
404
405         if (!(host->flags & HOST_F_RECV))
406                 return;
407
408         max = host->pio.len;
409
410         if (host->pio.index < host->dma.len) {
411                 sg = &data->sg[host->pio.index];
412                 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
413
414                 /* This is the space left inside the buffer */
415                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
416
417                 /* Check to if we need less then the size of the sg_buffer */
418                 if (sg_len < max) max = sg_len;
419         }
420
421         if (max > AU1XMMC_MAX_TRANSFER)
422                 max = AU1XMMC_MAX_TRANSFER;
423
424         for(count = 0; count < max; count++ ) {
425                 u32 val;
426                 status = au_readl(HOST_STATUS(host));
427
428                 if (!(status & SD_STATUS_NE))
429                         break;
430
431                 if (status & SD_STATUS_RC) {
432                         DBG("RX CRC Error [%d + %d].\n", host->id,
433                                         host->pio.len, count);
434                         break;
435                 }
436
437                 if (status & SD_STATUS_RO) {
438                         DBG("RX Overrun [%d + %d]\n", host->id,
439                                         host->pio.len, count);
440                         break;
441                 }
442                 else if (status & SD_STATUS_RU) {
443                         DBG("RX Underrun [%d + %d]\n", host->id,
444                                         host->pio.len,  count);
445                         break;
446                 }
447
448                 val = au_readl(HOST_RXPORT(host));
449
450                 if (sg_ptr)
451                         *sg_ptr++ = (unsigned char) (val & 0xFF);
452         }
453
454         host->pio.len -= count;
455         host->pio.offset += count;
456
457         if (sg_len && count == sg_len) {
458                 host->pio.index++;
459                 host->pio.offset = 0;
460         }
461
462         if (host->pio.len == 0) {
463                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
464                 IRQ_OFF(host, SD_CONFIG_NE);
465
466                 if (host->flags & HOST_F_STOP)
467                         SEND_STOP(host);
468
469                 tasklet_schedule(&host->data_task);
470         }
471 }
472
473 /* static void au1xmmc_cmd_complete
474    This is called when a command has been completed - grab the response
475    and check for errors.  Then start the data transfer if it is indicated.
476 */
477
478 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
479 {
480
481         struct mmc_request *mrq = host->mrq;
482         struct mmc_command *cmd;
483         int trans;
484
485         if (!host->mrq)
486                 return;
487
488         cmd = mrq->cmd;
489         cmd->error = MMC_ERR_NONE;
490
491         if (cmd->flags & MMC_RSP_PRESENT) {
492                 if (cmd->flags & MMC_RSP_136) {
493                         u32 r[4];
494                         int i;
495
496                         r[0] = au_readl(host->iobase + SD_RESP3);
497                         r[1] = au_readl(host->iobase + SD_RESP2);
498                         r[2] = au_readl(host->iobase + SD_RESP1);
499                         r[3] = au_readl(host->iobase + SD_RESP0);
500
501                         /* The CRC is omitted from the response, so really
502                          * we only got 120 bytes, but the engine expects
503                          * 128 bits, so we have to shift things up
504                          */
505
506                         for(i = 0; i < 4; i++) {
507                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
508                                 if (i != 3)
509                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
510                         }
511                 } else {
512                         /* Techincally, we should be getting all 48 bits of
513                          * the response (SD_RESP1 + SD_RESP2), but because
514                          * our response omits the CRC, our data ends up
515                          * being shifted 8 bits to the right.  In this case,
516                          * that means that the OSR data starts at bit 31,
517                          * so we can just read RESP0 and return that
518                          */
519                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
520                 }
521         }
522
523         /* Figure out errors */
524
525         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
526                 cmd->error = MMC_ERR_BADCRC;
527
528         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
529
530         if (!trans || cmd->error != MMC_ERR_NONE) {
531
532                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
533                 tasklet_schedule(&host->finish_task);
534                 return;
535         }
536
537         host->status = HOST_S_DATA;
538
539         if (host->flags & HOST_F_DMA) {
540                 u32 channel = DMA_CHANNEL(host);
541
542                 /* Start the DMA as soon as the buffer gets something in it */
543
544                 if (host->flags & HOST_F_RECV) {
545                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
546
547                         while((status & mask) != mask)
548                                 status = au_readl(HOST_STATUS(host));
549                 }
550
551                 au1xxx_dbdma_start(channel);
552         }
553 }
554
555 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
556 {
557
558         unsigned int pbus = get_au1x00_speed();
559         unsigned int divisor;
560         u32 config;
561
562         /* From databook:
563            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
564         */
565
566         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
567         pbus /= 2;
568
569         divisor = ((pbus / rate) / 2) - 1;
570
571         config = au_readl(HOST_CONFIG(host));
572
573         config &= ~(SD_CONFIG_DIV);
574         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
575
576         au_writel(config, HOST_CONFIG(host));
577         au_sync();
578 }
579
580 static int
581 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
582 {
583
584         int datalen = data->blocks * data->blksz;
585
586         if (dma != 0)
587                 host->flags |= HOST_F_DMA;
588
589         if (data->flags & MMC_DATA_READ)
590                 host->flags |= HOST_F_RECV;
591         else
592                 host->flags |= HOST_F_XMIT;
593
594         if (host->mrq->stop)
595                 host->flags |= HOST_F_STOP;
596
597         host->dma.dir = DMA_BIDIRECTIONAL;
598
599         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
600                                    data->sg_len, host->dma.dir);
601
602         if (host->dma.len == 0)
603                 return MMC_ERR_TIMEOUT;
604
605         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
606
607         if (host->flags & HOST_F_DMA) {
608                 int i;
609                 u32 channel = DMA_CHANNEL(host);
610
611                 au1xxx_dbdma_stop(channel);
612
613                 for(i = 0; i < host->dma.len; i++) {
614                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
615                         struct scatterlist *sg = &data->sg[i];
616                         int sg_len = sg->length;
617
618                         int len = (datalen > sg_len) ? sg_len : datalen;
619
620                         if (i == host->dma.len - 1)
621                                 flags = DDMA_FLAGS_IE;
622
623                         if (host->flags & HOST_F_XMIT){
624                                 ret = au1xxx_dbdma_put_source_flags(channel,
625                                         (void *) (page_address(sg->page) +
626                                                   sg->offset),
627                                         len, flags);
628                         }
629                         else {
630                                 ret = au1xxx_dbdma_put_dest_flags(channel,
631                                         (void *) (page_address(sg->page) +
632                                                   sg->offset),
633                                         len, flags);
634                         }
635
636                         if (!ret)
637                                 goto dataerr;
638
639                         datalen -= len;
640                 }
641         }
642         else {
643                 host->pio.index = 0;
644                 host->pio.offset = 0;
645                 host->pio.len = datalen;
646
647                 if (host->flags & HOST_F_XMIT)
648                         IRQ_ON(host, SD_CONFIG_TH);
649                 else
650                         IRQ_ON(host, SD_CONFIG_NE);
651                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
652         }
653
654         return MMC_ERR_NONE;
655
656  dataerr:
657         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
658         return MMC_ERR_TIMEOUT;
659 }
660
661 /* static void au1xmmc_request
662    This actually starts a command or data transaction
663 */
664
665 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
666 {
667
668         struct au1xmmc_host *host = mmc_priv(mmc);
669         int ret = MMC_ERR_NONE;
670
671         WARN_ON(irqs_disabled());
672         WARN_ON(host->status != HOST_S_IDLE);
673
674         host->mrq = mrq;
675         host->status = HOST_S_CMD;
676
677         bcsr->disk_leds &= ~(1 << 8);
678
679         if (mrq->data) {
680                 FLUSH_FIFO(host);
681                 ret = au1xmmc_prepare_data(host, mrq->data);
682         }
683
684         if (ret == MMC_ERR_NONE)
685                 ret = au1xmmc_send_command(host, 0, mrq->cmd);
686
687         if (ret != MMC_ERR_NONE) {
688                 mrq->cmd->error = ret;
689                 au1xmmc_finish_request(host);
690         }
691 }
692
693 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
694 {
695
696         /* Apply the clock */
697         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
698         au_sync_delay(1);
699
700         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
701         au_sync_delay(5);
702
703         au_writel(~0, HOST_STATUS(host));
704         au_sync();
705
706         au_writel(0, HOST_BLKSIZE(host));
707         au_writel(0x001fffff, HOST_TIMEOUT(host));
708         au_sync();
709
710         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
711         au_sync();
712
713         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
714         au_sync_delay(1);
715
716         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
717         au_sync();
718
719         /* Configure interrupts */
720         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
721         au_sync();
722 }
723
724
725 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
726 {
727         struct au1xmmc_host *host = mmc_priv(mmc);
728
729         if (ios->power_mode == MMC_POWER_OFF)
730                 au1xmmc_set_power(host, 0);
731         else if (ios->power_mode == MMC_POWER_ON) {
732                 au1xmmc_set_power(host, 1);
733         }
734
735         if (ios->clock && ios->clock != host->clock) {
736                 au1xmmc_set_clock(host, ios->clock);
737                 host->clock = ios->clock;
738         }
739 }
740
741 static void au1xmmc_dma_callback(int irq, void *dev_id)
742 {
743         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
744
745         /* Avoid spurious interrupts */
746
747         if (!host->mrq)
748                 return;
749
750         if (host->flags & HOST_F_STOP)
751                 SEND_STOP(host);
752
753         tasklet_schedule(&host->data_task);
754 }
755
756 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
757 #define STATUS_DATA_IN  (SD_STATUS_NE)
758 #define STATUS_DATA_OUT (SD_STATUS_TH)
759
760 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
761 {
762
763         u32 status;
764         int i, ret = 0;
765
766         disable_irq(AU1100_SD_IRQ);
767
768         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
769                 struct au1xmmc_host * host = au1xmmc_hosts[i];
770                 u32 handled = 1;
771
772                 status = au_readl(HOST_STATUS(host));
773
774                 if (host->mrq && (status & STATUS_TIMEOUT)) {
775                         if (status & SD_STATUS_RAT)
776                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
777
778                         else if (status & SD_STATUS_DT)
779                                 host->mrq->data->error = MMC_ERR_TIMEOUT;
780
781                         /* In PIO mode, interrupts might still be enabled */
782                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
783
784                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
785                         tasklet_schedule(&host->finish_task);
786                 }
787 #if 0
788                 else if (status & SD_STATUS_DD) {
789
790                         /* Sometimes we get a DD before a NE in PIO mode */
791
792                         if (!(host->flags & HOST_F_DMA) &&
793                                         (status & SD_STATUS_NE))
794                                 au1xmmc_receive_pio(host);
795                         else {
796                                 au1xmmc_data_complete(host, status);
797                                 //tasklet_schedule(&host->data_task);
798                         }
799                 }
800 #endif
801                 else if (status & (SD_STATUS_CR)) {
802                         if (host->status == HOST_S_CMD)
803                                 au1xmmc_cmd_complete(host,status);
804                 }
805                 else if (!(host->flags & HOST_F_DMA)) {
806                         if ((host->flags & HOST_F_XMIT) &&
807                             (status & STATUS_DATA_OUT))
808                                 au1xmmc_send_pio(host);
809                         else if ((host->flags & HOST_F_RECV) &&
810                             (status & STATUS_DATA_IN))
811                                 au1xmmc_receive_pio(host);
812                 }
813                 else if (status & 0x203FBC70) {
814                         DBG("Unhandled status %8.8x\n", host->id, status);
815                         handled = 0;
816                 }
817
818                 au_writel(status, HOST_STATUS(host));
819                 au_sync();
820
821                 ret |= handled;
822         }
823
824         enable_irq(AU1100_SD_IRQ);
825         return ret;
826 }
827
828 static void au1xmmc_poll_event(unsigned long arg)
829 {
830         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
831
832         int card = au1xmmc_card_inserted(host);
833         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
834
835         if (card != controller) {
836                 host->flags &= ~HOST_F_ACTIVE;
837                 if (card) host->flags |= HOST_F_ACTIVE;
838                 mmc_detect_change(host->mmc, 0);
839         }
840
841         if (host->mrq != NULL) {
842                 u32 status = au_readl(HOST_STATUS(host));
843                 DBG("PENDING - %8.8x\n", host->id, status);
844         }
845
846         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
847 }
848
849 static dbdev_tab_t au1xmmc_mem_dbdev =
850 {
851         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
852 };
853
854 static void au1xmmc_init_dma(struct au1xmmc_host *host)
855 {
856
857         u32 rxchan, txchan;
858
859         int txid = au1xmmc_card_table[host->id].tx_devid;
860         int rxid = au1xmmc_card_table[host->id].rx_devid;
861
862         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
863            of 8 bits.  And since devices are shared, we need to create
864            our own to avoid freaking out other devices
865         */
866
867         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
868
869         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
870                                          au1xmmc_dma_callback, (void *) host);
871
872         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
873                                          au1xmmc_dma_callback, (void *) host);
874
875         au1xxx_dbdma_set_devwidth(txchan, 8);
876         au1xxx_dbdma_set_devwidth(rxchan, 8);
877
878         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
879         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
880
881         host->tx_chan = txchan;
882         host->rx_chan = rxchan;
883 }
884
885 static const struct mmc_host_ops au1xmmc_ops = {
886         .request        = au1xmmc_request,
887         .set_ios        = au1xmmc_set_ios,
888         .get_ro         = au1xmmc_card_readonly,
889 };
890
891 static int __devinit au1xmmc_probe(struct platform_device *pdev)
892 {
893
894         int i, ret = 0;
895
896         /* THe interrupt is shared among all controllers */
897         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
898
899         if (ret) {
900                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
901                                 AU1100_SD_IRQ, ret);
902                 return -ENXIO;
903         }
904
905         disable_irq(AU1100_SD_IRQ);
906
907         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
908                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
909                 struct au1xmmc_host *host = 0;
910
911                 if (!mmc) {
912                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
913                         au1xmmc_hosts[i] = 0;
914                         continue;
915                 }
916
917                 mmc->ops = &au1xmmc_ops;
918
919                 mmc->f_min =   450000;
920                 mmc->f_max = 24000000;
921
922                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
923                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
924
925                 mmc->max_blk_size = 2048;
926                 mmc->max_blk_count = 512;
927
928                 mmc->ocr_avail = AU1XMMC_OCR;
929
930                 host = mmc_priv(mmc);
931                 host->mmc = mmc;
932
933                 host->id = i;
934                 host->iobase = au1xmmc_card_table[host->id].iobase;
935                 host->clock = 0;
936                 host->power_mode = MMC_POWER_OFF;
937
938                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
939                 host->status = HOST_S_IDLE;
940
941                 init_timer(&host->timer);
942
943                 host->timer.function = au1xmmc_poll_event;
944                 host->timer.data = (unsigned long) host;
945                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
946
947                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
948                                 (unsigned long) host);
949
950                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
951                                 (unsigned long) host);
952
953                 spin_lock_init(&host->lock);
954
955                 if (dma != 0)
956                         au1xmmc_init_dma(host);
957
958                 au1xmmc_reset_controller(host);
959
960                 mmc_add_host(mmc);
961                 au1xmmc_hosts[i] = host;
962
963                 add_timer(&host->timer);
964
965                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
966                        host->id, host->iobase, dma ? "dma" : "pio");
967         }
968
969         enable_irq(AU1100_SD_IRQ);
970
971         return 0;
972 }
973
974 static int __devexit au1xmmc_remove(struct platform_device *pdev)
975 {
976
977         int i;
978
979         disable_irq(AU1100_SD_IRQ);
980
981         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
982                 struct au1xmmc_host *host = au1xmmc_hosts[i];
983                 if (!host) continue;
984
985                 tasklet_kill(&host->data_task);
986                 tasklet_kill(&host->finish_task);
987
988                 del_timer_sync(&host->timer);
989                 au1xmmc_set_power(host, 0);
990
991                 mmc_remove_host(host->mmc);
992
993                 au1xxx_dbdma_chan_free(host->tx_chan);
994                 au1xxx_dbdma_chan_free(host->rx_chan);
995
996                 au_writel(0x0, HOST_ENABLE(host));
997                 au_sync();
998         }
999
1000         free_irq(AU1100_SD_IRQ, 0);
1001         return 0;
1002 }
1003
1004 static struct platform_driver au1xmmc_driver = {
1005         .probe         = au1xmmc_probe,
1006         .remove        = au1xmmc_remove,
1007         .suspend       = NULL,
1008         .resume        = NULL,
1009         .driver        = {
1010                 .name  = DRIVER_NAME,
1011         },
1012 };
1013
1014 static int __init au1xmmc_init(void)
1015 {
1016         return platform_driver_register(&au1xmmc_driver);
1017 }
1018
1019 static void __exit au1xmmc_exit(void)
1020 {
1021         platform_driver_unregister(&au1xmmc_driver);
1022 }
1023
1024 module_init(au1xmmc_init);
1025 module_exit(au1xmmc_exit);
1026
1027 #ifdef MODULE
1028 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1029 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1030 MODULE_LICENSE("GPL");
1031 #endif
1032