Merge branch 'for-linus' of git://git390.osdl.marist.edu/pub/scm/linux-2.6
[linux-2.6.git] / drivers / mmc / au1xmmc.c
1 /*
2  * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
3  *
4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
5  *
6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
7  *  the following copyright notices:
8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
9  *     Portions Copyright (C) 2002 Embedix, Inc
10  *     Copyright 2002 Hewlett-Packard Company
11
12  *  2.6 version of this driver inspired by:
13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14  *     All Rights Reserved.
15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16  *     All Rights Reserved.
17  *
18
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  */
23
24 /* Why is a timer used to detect insert events?
25  *
26  * From the AU1100 MMC application guide:
27  * If the Au1100-based design is intended to support both MultiMediaCards
28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30  * In doing so, a MMC card never enters SPI-mode communications,
31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32  * (the low to high transition will not occur).
33  *
34  * So we use the timer to check the status manually.
35  */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
40 #include <linux/mm.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43
44 #include <linux/mmc/host.h>
45 #include <linux/mmc/protocol.h>
46 #include <asm/io.h>
47 #include <asm/mach-au1x00/au1000.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49 #include <asm/mach-au1x00/au1100_mmc.h>
50 #include <asm/scatterlist.h>
51
52 #include <au1xxx.h>
53 #include "au1xmmc.h"
54
55 #define DRIVER_NAME "au1xxx-mmc"
56
57 /* Set this to enable special debugging macros */
58
59 #ifdef DEBUG
60 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
61 #else
62 #define DBG(fmt, idx, args...)
63 #endif
64
65 const struct {
66         u32 iobase;
67         u32 tx_devid, rx_devid;
68         u16 bcsrpwr;
69         u16 bcsrstatus;
70         u16 wpstatus;
71 } au1xmmc_card_table[] = {
72         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
73           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
74 #ifndef CONFIG_MIPS_DB1200
75         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
76           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
77 #endif
78 };
79
80 #define AU1XMMC_CONTROLLER_COUNT \
81         (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
82
83 /* This array stores pointers for the hosts (used by the IRQ handler) */
84 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
85 static int dma = 1;
86
87 #ifdef MODULE
88 module_param(dma, bool, 0);
89 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
90 #endif
91
92 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
93 {
94         u32 val = au_readl(HOST_CONFIG(host));
95         val |= mask;
96         au_writel(val, HOST_CONFIG(host));
97         au_sync();
98 }
99
100 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
101 {
102         u32 val = au_readl(HOST_CONFIG2(host));
103
104         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
105         au_sync_delay(1);
106
107         /* SEND_STOP will turn off clock control - this re-enables it */
108         val &= ~SD_CONFIG2_DF;
109
110         au_writel(val, HOST_CONFIG2(host));
111         au_sync();
112 }
113
114 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
115 {
116         u32 val = au_readl(HOST_CONFIG(host));
117         val &= ~mask;
118         au_writel(val, HOST_CONFIG(host));
119         au_sync();
120 }
121
122 static inline void SEND_STOP(struct au1xmmc_host *host)
123 {
124
125         /* We know the value of CONFIG2, so avoid a read we don't need */
126         u32 mask = SD_CONFIG2_EN;
127
128         WARN_ON(host->status != HOST_S_DATA);
129         host->status = HOST_S_STOP;
130
131         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
132         au_sync();
133
134         /* Send the stop commmand */
135         au_writel(STOP_CMD, HOST_CMD(host));
136 }
137
138 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
139 {
140
141         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
142
143         bcsr->board &= ~val;
144         if (state) bcsr->board |= val;
145
146         au_sync_delay(1);
147 }
148
149 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
150 {
151         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
152                 ? 1 : 0;
153 }
154
155 static inline int au1xmmc_card_readonly(struct au1xmmc_host *host)
156 {
157         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
158                 ? 1 : 0;
159 }
160
161 static void au1xmmc_finish_request(struct au1xmmc_host *host)
162 {
163
164         struct mmc_request *mrq = host->mrq;
165
166         host->mrq = NULL;
167         host->flags &= HOST_F_ACTIVE;
168
169         host->dma.len = 0;
170         host->dma.dir = 0;
171
172         host->pio.index  = 0;
173         host->pio.offset = 0;
174         host->pio.len = 0;
175
176         host->status = HOST_S_IDLE;
177
178         bcsr->disk_leds |= (1 << 8);
179
180         mmc_request_done(host->mmc, mrq);
181 }
182
183 static void au1xmmc_tasklet_finish(unsigned long param)
184 {
185         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
186         au1xmmc_finish_request(host);
187 }
188
189 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
190                                 struct mmc_command *cmd)
191 {
192
193         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
194
195         switch (mmc_resp_type(cmd)) {
196         case MMC_RSP_R1:
197                 mmccmd |= SD_CMD_RT_1;
198                 break;
199         case MMC_RSP_R1B:
200                 mmccmd |= SD_CMD_RT_1B;
201                 break;
202         case MMC_RSP_R2:
203                 mmccmd |= SD_CMD_RT_2;
204                 break;
205         case MMC_RSP_R3:
206                 mmccmd |= SD_CMD_RT_3;
207                 break;
208         }
209
210         switch(cmd->opcode) {
211         case MMC_READ_SINGLE_BLOCK:
212         case SD_APP_SEND_SCR:
213                 mmccmd |= SD_CMD_CT_2;
214                 break;
215         case MMC_READ_MULTIPLE_BLOCK:
216                 mmccmd |= SD_CMD_CT_4;
217                 break;
218         case MMC_WRITE_BLOCK:
219                 mmccmd |= SD_CMD_CT_1;
220                 break;
221
222         case MMC_WRITE_MULTIPLE_BLOCK:
223                 mmccmd |= SD_CMD_CT_3;
224                 break;
225         case MMC_STOP_TRANSMISSION:
226                 mmccmd |= SD_CMD_CT_7;
227                 break;
228         }
229
230         au_writel(cmd->arg, HOST_CMDARG(host));
231         au_sync();
232
233         if (wait)
234                 IRQ_OFF(host, SD_CONFIG_CR);
235
236         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
237         au_sync();
238
239         /* Wait for the command to go on the line */
240
241         while(1) {
242                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
243                         break;
244         }
245
246         /* Wait for the command to come back */
247
248         if (wait) {
249                 u32 status = au_readl(HOST_STATUS(host));
250
251                 while(!(status & SD_STATUS_CR))
252                         status = au_readl(HOST_STATUS(host));
253
254                 /* Clear the CR status */
255                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
256
257                 IRQ_ON(host, SD_CONFIG_CR);
258         }
259
260         return MMC_ERR_NONE;
261 }
262
263 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
264 {
265
266         struct mmc_request *mrq = host->mrq;
267         struct mmc_data *data;
268         u32 crc;
269
270         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
271
272         if (host->mrq == NULL)
273                 return;
274
275         data = mrq->cmd->data;
276
277         if (status == 0)
278                 status = au_readl(HOST_STATUS(host));
279
280         /* The transaction is really over when the SD_STATUS_DB bit is clear */
281
282         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
283                 status = au_readl(HOST_STATUS(host));
284
285         data->error = MMC_ERR_NONE;
286         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
287
288         /* Process any errors */
289
290         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
291         if (host->flags & HOST_F_XMIT)
292                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
293
294         if (crc)
295                 data->error = MMC_ERR_BADCRC;
296
297         /* Clear the CRC bits */
298         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
299
300         data->bytes_xfered = 0;
301
302         if (data->error == MMC_ERR_NONE) {
303                 if (host->flags & HOST_F_DMA) {
304                         u32 chan = DMA_CHANNEL(host);
305
306                         chan_tab_t *c = *((chan_tab_t **) chan);
307                         au1x_dma_chan_t *cp = c->chan_ptr;
308                         data->bytes_xfered = cp->ddma_bytecnt;
309                 }
310                 else
311                         data->bytes_xfered =
312                                 (data->blocks * data->blksz) -
313                                 host->pio.len;
314         }
315
316         au1xmmc_finish_request(host);
317 }
318
319 static void au1xmmc_tasklet_data(unsigned long param)
320 {
321         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
322
323         u32 status = au_readl(HOST_STATUS(host));
324         au1xmmc_data_complete(host, status);
325 }
326
327 #define AU1XMMC_MAX_TRANSFER 8
328
329 static void au1xmmc_send_pio(struct au1xmmc_host *host)
330 {
331
332         struct mmc_data *data = 0;
333         int sg_len, max, count = 0;
334         unsigned char *sg_ptr;
335         u32 status = 0;
336         struct scatterlist *sg;
337
338         data = host->mrq->data;
339
340         if (!(host->flags & HOST_F_XMIT))
341                 return;
342
343         /* This is the pointer to the data buffer */
344         sg = &data->sg[host->pio.index];
345         sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
346
347         /* This is the space left inside the buffer */
348         sg_len = data->sg[host->pio.index].length - host->pio.offset;
349
350         /* Check to if we need less then the size of the sg_buffer */
351
352         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
353         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
354
355         for(count = 0; count < max; count++ ) {
356                 unsigned char val;
357
358                 status = au_readl(HOST_STATUS(host));
359
360                 if (!(status & SD_STATUS_TH))
361                         break;
362
363                 val = *sg_ptr++;
364
365                 au_writel((unsigned long) val, HOST_TXPORT(host));
366                 au_sync();
367         }
368
369         host->pio.len -= count;
370         host->pio.offset += count;
371
372         if (count == sg_len) {
373                 host->pio.index++;
374                 host->pio.offset = 0;
375         }
376
377         if (host->pio.len == 0) {
378                 IRQ_OFF(host, SD_CONFIG_TH);
379
380                 if (host->flags & HOST_F_STOP)
381                         SEND_STOP(host);
382
383                 tasklet_schedule(&host->data_task);
384         }
385 }
386
387 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
388 {
389
390         struct mmc_data *data = 0;
391         int sg_len = 0, max = 0, count = 0;
392         unsigned char *sg_ptr = 0;
393         u32 status = 0;
394         struct scatterlist *sg;
395
396         data = host->mrq->data;
397
398         if (!(host->flags & HOST_F_RECV))
399                 return;
400
401         max = host->pio.len;
402
403         if (host->pio.index < host->dma.len) {
404                 sg = &data->sg[host->pio.index];
405                 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
406
407                 /* This is the space left inside the buffer */
408                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
409
410                 /* Check to if we need less then the size of the sg_buffer */
411                 if (sg_len < max) max = sg_len;
412         }
413
414         if (max > AU1XMMC_MAX_TRANSFER)
415                 max = AU1XMMC_MAX_TRANSFER;
416
417         for(count = 0; count < max; count++ ) {
418                 u32 val;
419                 status = au_readl(HOST_STATUS(host));
420
421                 if (!(status & SD_STATUS_NE))
422                         break;
423
424                 if (status & SD_STATUS_RC) {
425                         DBG("RX CRC Error [%d + %d].\n", host->id,
426                                         host->pio.len, count);
427                         break;
428                 }
429
430                 if (status & SD_STATUS_RO) {
431                         DBG("RX Overrun [%d + %d]\n", host->id,
432                                         host->pio.len, count);
433                         break;
434                 }
435                 else if (status & SD_STATUS_RU) {
436                         DBG("RX Underrun [%d + %d]\n", host->id,
437                                         host->pio.len,  count);
438                         break;
439                 }
440
441                 val = au_readl(HOST_RXPORT(host));
442
443                 if (sg_ptr)
444                         *sg_ptr++ = (unsigned char) (val & 0xFF);
445         }
446
447         host->pio.len -= count;
448         host->pio.offset += count;
449
450         if (sg_len && count == sg_len) {
451                 host->pio.index++;
452                 host->pio.offset = 0;
453         }
454
455         if (host->pio.len == 0) {
456                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
457                 IRQ_OFF(host, SD_CONFIG_NE);
458
459                 if (host->flags & HOST_F_STOP)
460                         SEND_STOP(host);
461
462                 tasklet_schedule(&host->data_task);
463         }
464 }
465
466 /* static void au1xmmc_cmd_complete
467    This is called when a command has been completed - grab the response
468    and check for errors.  Then start the data transfer if it is indicated.
469 */
470
471 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
472 {
473
474         struct mmc_request *mrq = host->mrq;
475         struct mmc_command *cmd;
476         int trans;
477
478         if (!host->mrq)
479                 return;
480
481         cmd = mrq->cmd;
482         cmd->error = MMC_ERR_NONE;
483
484         if (cmd->flags & MMC_RSP_PRESENT) {
485                 if (cmd->flags & MMC_RSP_136) {
486                         u32 r[4];
487                         int i;
488
489                         r[0] = au_readl(host->iobase + SD_RESP3);
490                         r[1] = au_readl(host->iobase + SD_RESP2);
491                         r[2] = au_readl(host->iobase + SD_RESP1);
492                         r[3] = au_readl(host->iobase + SD_RESP0);
493
494                         /* The CRC is omitted from the response, so really
495                          * we only got 120 bytes, but the engine expects
496                          * 128 bits, so we have to shift things up
497                          */
498
499                         for(i = 0; i < 4; i++) {
500                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
501                                 if (i != 3)
502                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
503                         }
504                 } else {
505                         /* Techincally, we should be getting all 48 bits of
506                          * the response (SD_RESP1 + SD_RESP2), but because
507                          * our response omits the CRC, our data ends up
508                          * being shifted 8 bits to the right.  In this case,
509                          * that means that the OSR data starts at bit 31,
510                          * so we can just read RESP0 and return that
511                          */
512                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
513                 }
514         }
515
516         /* Figure out errors */
517
518         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
519                 cmd->error = MMC_ERR_BADCRC;
520
521         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
522
523         if (!trans || cmd->error != MMC_ERR_NONE) {
524
525                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
526                 tasklet_schedule(&host->finish_task);
527                 return;
528         }
529
530         host->status = HOST_S_DATA;
531
532         if (host->flags & HOST_F_DMA) {
533                 u32 channel = DMA_CHANNEL(host);
534
535                 /* Start the DMA as soon as the buffer gets something in it */
536
537                 if (host->flags & HOST_F_RECV) {
538                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
539
540                         while((status & mask) != mask)
541                                 status = au_readl(HOST_STATUS(host));
542                 }
543
544                 au1xxx_dbdma_start(channel);
545         }
546 }
547
548 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
549 {
550
551         unsigned int pbus = get_au1x00_speed();
552         unsigned int divisor;
553         u32 config;
554
555         /* From databook:
556            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
557         */
558
559         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
560         pbus /= 2;
561
562         divisor = ((pbus / rate) / 2) - 1;
563
564         config = au_readl(HOST_CONFIG(host));
565
566         config &= ~(SD_CONFIG_DIV);
567         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
568
569         au_writel(config, HOST_CONFIG(host));
570         au_sync();
571 }
572
573 static int
574 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
575 {
576
577         int datalen = data->blocks * data->blksz;
578
579         if (dma != 0)
580                 host->flags |= HOST_F_DMA;
581
582         if (data->flags & MMC_DATA_READ)
583                 host->flags |= HOST_F_RECV;
584         else
585                 host->flags |= HOST_F_XMIT;
586
587         if (host->mrq->stop)
588                 host->flags |= HOST_F_STOP;
589
590         host->dma.dir = DMA_BIDIRECTIONAL;
591
592         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
593                                    data->sg_len, host->dma.dir);
594
595         if (host->dma.len == 0)
596                 return MMC_ERR_TIMEOUT;
597
598         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
599
600         if (host->flags & HOST_F_DMA) {
601                 int i;
602                 u32 channel = DMA_CHANNEL(host);
603
604                 au1xxx_dbdma_stop(channel);
605
606                 for(i = 0; i < host->dma.len; i++) {
607                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
608                         struct scatterlist *sg = &data->sg[i];
609                         int sg_len = sg->length;
610
611                         int len = (datalen > sg_len) ? sg_len : datalen;
612
613                         if (i == host->dma.len - 1)
614                                 flags = DDMA_FLAGS_IE;
615
616                         if (host->flags & HOST_F_XMIT){
617                                 ret = au1xxx_dbdma_put_source_flags(channel,
618                                         (void *) (page_address(sg->page) +
619                                                   sg->offset),
620                                         len, flags);
621                         }
622                         else {
623                                 ret = au1xxx_dbdma_put_dest_flags(channel,
624                                         (void *) (page_address(sg->page) +
625                                                   sg->offset),
626                                         len, flags);
627                         }
628
629                         if (!ret)
630                                 goto dataerr;
631
632                         datalen -= len;
633                 }
634         }
635         else {
636                 host->pio.index = 0;
637                 host->pio.offset = 0;
638                 host->pio.len = datalen;
639
640                 if (host->flags & HOST_F_XMIT)
641                         IRQ_ON(host, SD_CONFIG_TH);
642                 else
643                         IRQ_ON(host, SD_CONFIG_NE);
644                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
645         }
646
647         return MMC_ERR_NONE;
648
649  dataerr:
650         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
651         return MMC_ERR_TIMEOUT;
652 }
653
654 /* static void au1xmmc_request
655    This actually starts a command or data transaction
656 */
657
658 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
659 {
660
661         struct au1xmmc_host *host = mmc_priv(mmc);
662         int ret = MMC_ERR_NONE;
663
664         WARN_ON(irqs_disabled());
665         WARN_ON(host->status != HOST_S_IDLE);
666
667         host->mrq = mrq;
668         host->status = HOST_S_CMD;
669
670         bcsr->disk_leds &= ~(1 << 8);
671
672         if (mrq->data) {
673                 FLUSH_FIFO(host);
674                 ret = au1xmmc_prepare_data(host, mrq->data);
675         }
676
677         if (ret == MMC_ERR_NONE)
678                 ret = au1xmmc_send_command(host, 0, mrq->cmd);
679
680         if (ret != MMC_ERR_NONE) {
681                 mrq->cmd->error = ret;
682                 au1xmmc_finish_request(host);
683         }
684 }
685
686 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
687 {
688
689         /* Apply the clock */
690         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
691         au_sync_delay(1);
692
693         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
694         au_sync_delay(5);
695
696         au_writel(~0, HOST_STATUS(host));
697         au_sync();
698
699         au_writel(0, HOST_BLKSIZE(host));
700         au_writel(0x001fffff, HOST_TIMEOUT(host));
701         au_sync();
702
703         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
704         au_sync();
705
706         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
707         au_sync_delay(1);
708
709         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
710         au_sync();
711
712         /* Configure interrupts */
713         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
714         au_sync();
715 }
716
717
718 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
719 {
720         struct au1xmmc_host *host = mmc_priv(mmc);
721
722         if (ios->power_mode == MMC_POWER_OFF)
723                 au1xmmc_set_power(host, 0);
724         else if (ios->power_mode == MMC_POWER_ON) {
725                 au1xmmc_set_power(host, 1);
726         }
727
728         if (ios->clock && ios->clock != host->clock) {
729                 au1xmmc_set_clock(host, ios->clock);
730                 host->clock = ios->clock;
731         }
732 }
733
734 static void au1xmmc_dma_callback(int irq, void *dev_id)
735 {
736         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
737
738         /* Avoid spurious interrupts */
739
740         if (!host->mrq)
741                 return;
742
743         if (host->flags & HOST_F_STOP)
744                 SEND_STOP(host);
745
746         tasklet_schedule(&host->data_task);
747 }
748
749 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
750 #define STATUS_DATA_IN  (SD_STATUS_NE)
751 #define STATUS_DATA_OUT (SD_STATUS_TH)
752
753 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
754 {
755
756         u32 status;
757         int i, ret = 0;
758
759         disable_irq(AU1100_SD_IRQ);
760
761         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
762                 struct au1xmmc_host * host = au1xmmc_hosts[i];
763                 u32 handled = 1;
764
765                 status = au_readl(HOST_STATUS(host));
766
767                 if (host->mrq && (status & STATUS_TIMEOUT)) {
768                         if (status & SD_STATUS_RAT)
769                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
770
771                         else if (status & SD_STATUS_DT)
772                                 host->mrq->data->error = MMC_ERR_TIMEOUT;
773
774                         /* In PIO mode, interrupts might still be enabled */
775                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
776
777                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
778                         tasklet_schedule(&host->finish_task);
779                 }
780 #if 0
781                 else if (status & SD_STATUS_DD) {
782
783                         /* Sometimes we get a DD before a NE in PIO mode */
784
785                         if (!(host->flags & HOST_F_DMA) &&
786                                         (status & SD_STATUS_NE))
787                                 au1xmmc_receive_pio(host);
788                         else {
789                                 au1xmmc_data_complete(host, status);
790                                 //tasklet_schedule(&host->data_task);
791                         }
792                 }
793 #endif
794                 else if (status & (SD_STATUS_CR)) {
795                         if (host->status == HOST_S_CMD)
796                                 au1xmmc_cmd_complete(host,status);
797                 }
798                 else if (!(host->flags & HOST_F_DMA)) {
799                         if ((host->flags & HOST_F_XMIT) &&
800                             (status & STATUS_DATA_OUT))
801                                 au1xmmc_send_pio(host);
802                         else if ((host->flags & HOST_F_RECV) &&
803                             (status & STATUS_DATA_IN))
804                                 au1xmmc_receive_pio(host);
805                 }
806                 else if (status & 0x203FBC70) {
807                         DBG("Unhandled status %8.8x\n", host->id, status);
808                         handled = 0;
809                 }
810
811                 au_writel(status, HOST_STATUS(host));
812                 au_sync();
813
814                 ret |= handled;
815         }
816
817         enable_irq(AU1100_SD_IRQ);
818         return ret;
819 }
820
821 static void au1xmmc_poll_event(unsigned long arg)
822 {
823         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
824
825         int card = au1xmmc_card_inserted(host);
826         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
827
828         if (card != controller) {
829                 host->flags &= ~HOST_F_ACTIVE;
830                 if (card) host->flags |= HOST_F_ACTIVE;
831                 mmc_detect_change(host->mmc, 0);
832         }
833
834         if (host->mrq != NULL) {
835                 u32 status = au_readl(HOST_STATUS(host));
836                 DBG("PENDING - %8.8x\n", host->id, status);
837         }
838
839         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
840 }
841
842 static dbdev_tab_t au1xmmc_mem_dbdev =
843 {
844         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
845 };
846
847 static void au1xmmc_init_dma(struct au1xmmc_host *host)
848 {
849
850         u32 rxchan, txchan;
851
852         int txid = au1xmmc_card_table[host->id].tx_devid;
853         int rxid = au1xmmc_card_table[host->id].rx_devid;
854
855         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
856            of 8 bits.  And since devices are shared, we need to create
857            our own to avoid freaking out other devices
858         */
859
860         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
861
862         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
863                                          au1xmmc_dma_callback, (void *) host);
864
865         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
866                                          au1xmmc_dma_callback, (void *) host);
867
868         au1xxx_dbdma_set_devwidth(txchan, 8);
869         au1xxx_dbdma_set_devwidth(rxchan, 8);
870
871         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
872         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
873
874         host->tx_chan = txchan;
875         host->rx_chan = rxchan;
876 }
877
878 static const struct mmc_host_ops au1xmmc_ops = {
879         .request        = au1xmmc_request,
880         .set_ios        = au1xmmc_set_ios,
881 };
882
883 static int __devinit au1xmmc_probe(struct platform_device *pdev)
884 {
885
886         int i, ret = 0;
887
888         /* THe interrupt is shared among all controllers */
889         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
890
891         if (ret) {
892                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
893                                 AU1100_SD_IRQ, ret);
894                 return -ENXIO;
895         }
896
897         disable_irq(AU1100_SD_IRQ);
898
899         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
900                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
901                 struct au1xmmc_host *host = 0;
902
903                 if (!mmc) {
904                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
905                         au1xmmc_hosts[i] = 0;
906                         continue;
907                 }
908
909                 mmc->ops = &au1xmmc_ops;
910
911                 mmc->f_min =   450000;
912                 mmc->f_max = 24000000;
913
914                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
915                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
916
917                 mmc->ocr_avail = AU1XMMC_OCR;
918
919                 host = mmc_priv(mmc);
920                 host->mmc = mmc;
921
922                 host->id = i;
923                 host->iobase = au1xmmc_card_table[host->id].iobase;
924                 host->clock = 0;
925                 host->power_mode = MMC_POWER_OFF;
926
927                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
928                 host->status = HOST_S_IDLE;
929
930                 init_timer(&host->timer);
931
932                 host->timer.function = au1xmmc_poll_event;
933                 host->timer.data = (unsigned long) host;
934                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
935
936                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
937                                 (unsigned long) host);
938
939                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
940                                 (unsigned long) host);
941
942                 spin_lock_init(&host->lock);
943
944                 if (dma != 0)
945                         au1xmmc_init_dma(host);
946
947                 au1xmmc_reset_controller(host);
948
949                 mmc_add_host(mmc);
950                 au1xmmc_hosts[i] = host;
951
952                 add_timer(&host->timer);
953
954                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
955                        host->id, host->iobase, dma ? "dma" : "pio");
956         }
957
958         enable_irq(AU1100_SD_IRQ);
959
960         return 0;
961 }
962
963 static int __devexit au1xmmc_remove(struct platform_device *pdev)
964 {
965
966         int i;
967
968         disable_irq(AU1100_SD_IRQ);
969
970         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
971                 struct au1xmmc_host *host = au1xmmc_hosts[i];
972                 if (!host) continue;
973
974                 tasklet_kill(&host->data_task);
975                 tasklet_kill(&host->finish_task);
976
977                 del_timer_sync(&host->timer);
978                 au1xmmc_set_power(host, 0);
979
980                 mmc_remove_host(host->mmc);
981
982                 au1xxx_dbdma_chan_free(host->tx_chan);
983                 au1xxx_dbdma_chan_free(host->rx_chan);
984
985                 au_writel(0x0, HOST_ENABLE(host));
986                 au_sync();
987         }
988
989         free_irq(AU1100_SD_IRQ, 0);
990         return 0;
991 }
992
993 static struct platform_driver au1xmmc_driver = {
994         .probe         = au1xmmc_probe,
995         .remove        = au1xmmc_remove,
996         .suspend       = NULL,
997         .resume        = NULL,
998         .driver        = {
999                 .name  = DRIVER_NAME,
1000         },
1001 };
1002
1003 static int __init au1xmmc_init(void)
1004 {
1005         return platform_driver_register(&au1xmmc_driver);
1006 }
1007
1008 static void __exit au1xmmc_exit(void)
1009 {
1010         platform_driver_unregister(&au1xmmc_driver);
1011 }
1012
1013 module_init(au1xmmc_init);
1014 module_exit(au1xmmc_exit);
1015
1016 #ifdef MODULE
1017 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1018 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1019 MODULE_LICENSE("GPL");
1020 #endif
1021