drivers/media/dvb/b2c2/flexcop_ibi_value_be.h

   1 /* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
   2  *
   3  * register descriptions
   4  *
   5  * see flexcop.c for copyright information.
   6  */
   7
   8 /* This file is automatically generated, do not edit things here. */
   9 #ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
  10 #define __FLEXCOP_IBI_VALUE_INCLUDED__
  11
  12 typedef union {
  13         u32 raw;
  14
  15         struct {
  16                 u32 dma_address0                   :30;
  17                 u32 dma_0No_update                 : 1;
  18                 u32 dma_0start                     : 1;
  19         } dma_0x0;
  20
  21         struct {
  22                 u32 dma_addr_size                  :24;
  23                 u32 DMA_maxpackets                 : 8;
  24         } dma_0x4_remap;
  25
  26         struct {
  27                 u32 dma_addr_size                  :24;
  28                 u32 unused                         : 1;
  29                 u32 dma1timer                      : 7;
  30         } dma_0x4_read;
  31
  32         struct {
  33                 u32 dma_addr_size                  :24;
  34                 u32 dmatimer                       : 7;
  35                 u32 unused                         : 1;
  36         } dma_0x4_write;
  37
  38         struct {
  39                 u32 dma_cur_addr                   :30;
  40                 u32 unused                         : 2;
  41         } dma_0x8;
  42
  43         struct {
  44                 u32 dma_address1                   :30;
  45                 u32 remap_enable                   : 1;
  46                 u32 dma_1start                     : 1;
  47         } dma_0xc;
  48
  49         struct {
  50                 u32 st_done                        : 1;
  51                 u32 no_base_addr_ack_error         : 1;
  52                 u32 twoWS_port_reg                 : 2;
  53                 u32 total_bytes                    : 2;
  54                 u32 twoWS_rw                       : 1;
  55                 u32 working_start                  : 1;
  56                 u32 data1_reg                      : 8;
  57                 u32 baseaddr                       : 8;
  58                 u32 reserved1                      : 1;
  59                 u32 chipaddr                       : 7;
  60         } tw_sm_c_100;
  61
  62         struct {
  63                 u32 unused                         : 6;
  64                 u32 force_stop                     : 1;
  65                 u32 exlicit_stops                  : 1;
  66                 u32 data4_reg                      : 8;
  67                 u32 data3_reg                      : 8;
  68                 u32 data2_reg                      : 8;
  69         } tw_sm_c_104;
  70
  71         struct {
  72                 u32 reserved2                      :19;
  73                 u32 tlo1                           : 5;
  74                 u32 reserved1                      : 2;
  75                 u32 thi1                           : 6;
  76         } tw_sm_c_108;
  77
  78         struct {
  79                 u32 reserved2                      :19;
  80                 u32 tlo1                           : 5;
  81                 u32 reserved1                      : 2;
  82                 u32 thi1                           : 6;
  83         } tw_sm_c_10c;
  84
  85         struct {
  86                 u32 reserved2                      :19;
  87                 u32 tlo1                           : 5;
  88                 u32 reserved1                      : 2;
  89                 u32 thi1                           : 6;
  90         } tw_sm_c_110;
  91
  92         struct {
  93                 u32 LNB_CTLPrescaler_sig           : 2;
  94                 u32 LNB_CTLLowCount_sig            :15;
  95                 u32 LNB_CTLHighCount_sig           :15;
  96         } lnb_switch_freq_200;
  97
  98         struct {
  99                 u32 Rev_N_sig_reserved2            : 1;
 100                 u32 Rev_N_sig_caps                 : 1;
 101                 u32 Rev_N_sig_reserved1            : 2;
 102                 u32 Rev_N_sig_revision_hi          : 4;
 103                 u32 reserved                       :20;
 104                 u32 Per_reset_sig                  : 1;
 105                 u32 LNB_L_H_sig                    : 1;
 106                 u32 ACPI3_sig                      : 1;
 107                 u32 ACPI1_sig                      : 1;
 108         } misc_204;
 109
 110         struct {
 111                 u32 unused                         : 9;
 112                 u32 Mailbox_from_V8_Enable_sig     : 1;
 113                 u32 DMA2_Size_IRQ_Enable_sig       : 1;
 114                 u32 DMA1_Size_IRQ_Enable_sig       : 1;
 115                 u32 DMA2_Timer_Enable_sig          : 1;
 116                 u32 DMA2_IRQ_Enable_sig            : 1;
 117                 u32 DMA1_Timer_Enable_sig          : 1;
 118                 u32 DMA1_IRQ_Enable_sig            : 1;
 119                 u32 Rcv_Data_sig                   : 1;
 120                 u32 MAC_filter_Mode_sig            : 1;
 121                 u32 Multi2_Enable_sig              : 1;
 122                 u32 Per_CA_Enable_sig              : 1;
 123                 u32 SMC_Enable_sig                 : 1;
 124                 u32 CA_Enable_sig                  : 1;
 125                 u32 WAN_CA_Enable_sig              : 1;
 126                 u32 WAN_Enable_sig                 : 1;
 127                 u32 Mask_filter_sig                : 1;
 128                 u32 Null_filter_sig                : 1;
 129                 u32 ECM_filter_sig                 : 1;
 130                 u32 EMM_filter_sig                 : 1;
 131                 u32 PMT_filter_sig                 : 1;
 132                 u32 PCR_filter_sig                 : 1;
 133                 u32 Stream2_filter_sig             : 1;
 134                 u32 Stream1_filter_sig             : 1;
 135         } ctrl_208;
 136
 137         struct {
 138                 u32 reserved                       :21;
 139                 u32 Transport_Error                : 1;
 140                 u32 LLC_SNAP_FLAG_set              : 1;
 141                 u32 Continuity_error_flag          : 1;
 142                 u32 Data_receiver_error            : 1;
 143                 u32 Mailbox_from_V8_Status_sig     : 1;
 144                 u32 DMA2_Size_IRQ_Status           : 1;
 145                 u32 DMA1_Size_IRQ_Status           : 1;
 146                 u32 DMA2_Timer_Status              : 1;
 147                 u32 DMA2_IRQ_Status                : 1;
 148                 u32 DMA1_Timer_Status              : 1;
 149                 u32 DMA1_IRQ_Status                : 1;
 150         } irq_20c;
 151
 152         struct {
 153                 u32 Special_controls               :16;
 154                 u32 Block_reset_enable             : 8;
 155                 u32 reset_blocks                   : 8;
 156         } sw_reset_210;
 157
 158         struct {
 159                 u32 unused2                        :20;
 160                 u32 polarity_PS_ERR_sig            : 1;
 161                 u32 polarity_PS_SYNC_sig           : 1;
 162                 u32 polarity_PS_VALID_sig          : 1;
 163                 u32 polarity_PS_CLK_sig            : 1;
 164                 u32 unused1                        : 3;
 165                 u32 s2p_sel_sig                    : 1;
 166                 u32 section_pkg_enable_sig         : 1;
 167                 u32 halt_V8_sig                    : 1;
 168                 u32 v2WS_oe_sig                    : 1;
 169                 u32 vuart_oe_sig                   : 1;
 170         } misc_214;
 171
 172         struct {
 173                 u32 Mailbox_from_V8                :32;
 174         } mbox_v8_to_host_218;
 175
 176         struct {
 177                 u32 sysramaccess_busmuster         : 1;
 178                 u32 sysramaccess_write             : 1;
 179                 u32 unused                         : 7;
 180                 u32 sysramaccess_addr              :15;
 181                 u32 sysramaccess_data              : 8;
 182         } mbox_host_to_v8_21c;
 183
 184         struct {
 185                 u32 debug_fifo_problem             : 1;
 186                 u32 debug_flag_write_status00      : 1;
 187                 u32 Stream2_trans                  : 1;
 188                 u32 Stream2_PID                    :13;
 189                 u32 debug_flag_pid_saved           : 1;
 190                 u32 MAC_Multicast_filter           : 1;
 191                 u32 Stream1_trans                  : 1;
 192                 u32 Stream1_PID                    :13;
 193         } pid_filter_300;
 194
 195         struct {
 196                 u32 reserved                       : 2;
 197                 u32 PMT_trans                      : 1;
 198                 u32 PMT_PID                        :13;
 199                 u32 debug_overrun2                 : 1;
 200                 u32 debug_overrun3                 : 1;
 201                 u32 PCR_trans                      : 1;
 202                 u32 PCR_PID                        :13;
 203         } pid_filter_304;
 204
 205         struct {
 206                 u32 reserved                       : 2;
 207                 u32 ECM_trans                      : 1;
 208                 u32 ECM_PID                        :13;
 209                 u32 EMM_filter_6                   : 1;
 210                 u32 EMM_filter_4                   : 1;
 211                 u32 EMM_trans                      : 1;
 212                 u32 EMM_PID                        :13;
 213         } pid_filter_308;
 214
 215         struct {
 216                 u32 unused2                        : 3;
 217                 u32 Group_mask                     :13;
 218                 u32 unused1                        : 2;
 219                 u32 Group_trans                    : 1;
 220                 u32 Group_PID                      :13;
 221         } pid_filter_30c_ext_ind_0_7;
 222
 223         struct {
 224                 u32 unused                         :15;
 225                 u32 net_master_read                :17;
 226         } pid_filter_30c_ext_ind_1;
 227
 228         struct {
 229                 u32 unused                         :15;
 230                 u32 net_master_write               :17;
 231         } pid_filter_30c_ext_ind_2;
 232
 233         struct {
 234                 u32 unused                         :15;
 235                 u32 next_net_master_write          :17;
 236         } pid_filter_30c_ext_ind_3;
 237
 238         struct {
 239                 u32 reserved2                      : 5;
 240                 u32 stack_read                     :10;
 241                 u32 reserved1                      : 6;
 242                 u32 state_write                    :10;
 243                 u32 unused1                        : 1;
 244         } pid_filter_30c_ext_ind_4;
 245
 246         struct {
 247                 u32 unused                         :22;
 248                 u32 stack_cnt                      :10;
 249         } pid_filter_30c_ext_ind_5;
 250
 251         struct {
 252                 u32 unused                         : 4;
 253                 u32 data_size_reg                  :12;
 254                 u32 write_status4                  : 2;
 255                 u32 write_status1                  : 2;
 256                 u32 pid_fsm_save_reg300            : 2;
 257                 u32 pid_fsm_save_reg4              : 2;
 258                 u32 pid_fsm_save_reg3              : 2;
 259                 u32 pid_fsm_save_reg2              : 2;
 260                 u32 pid_fsm_save_reg1              : 2;
 261                 u32 pid_fsm_save_reg0              : 2;
 262         } pid_filter_30c_ext_ind_6;
 263
 264         struct {
 265                 u32 unused                         :22;
 266                 u32 pass_alltables                 : 1;
 267                 u32 AB_select                      : 1;
 268                 u32 extra_index_reg                : 3;
 269                 u32 index_reg                      : 5;
 270         } index_reg_310;
 271
 272         struct {
 273                 u32 reserved                       :17;
 274                 u32 PID_enable_bit                 : 1;
 275                 u32 PID_trans                      : 1;
 276                 u32 PID                            :13;
 277         } pid_n_reg_314;
 278
 279         struct {
 280                 u32 reserved                       : 6;
 281                 u32 HighAB_bit                     : 1;
 282                 u32 Enable_bit                     : 1;
 283                 u32 A6_byte                        : 8;
 284                 u32 A5_byte                        : 8;
 285                 u32 A4_byte                        : 8;
 286         } mac_low_reg_318;
 287
 288         struct {
 289                 u32 reserved                       : 8;
 290                 u32 A3_byte                        : 8;
 291                 u32 A2_byte                        : 8;
 292                 u32 A1_byte                        : 8;
 293         } mac_high_reg_31c;
 294
 295         struct {
 296                 u32 data_Tag_ID                    :16;
 297                 u32 reserved                       :16;
 298         } data_tag_400;
 299
 300         struct {
 301                 u32 Card_IDbyte3                   : 8;
 302                 u32 Card_IDbyte4                   : 8;
 303                 u32 Card_IDbyte5                   : 8;
 304                 u32 Card_IDbyte6                   : 8;
 305         } card_id_408;
 306
 307         struct {
 308                 u32 Card_IDbyte1                   : 8;
 309                 u32 Card_IDbyte2                   : 8;
 310         } card_id_40c;
 311
 312         struct {
 313                 u32 MAC6                           : 8;
 314                 u32 MAC3                           : 8;
 315                 u32 MAC2                           : 8;
 316                 u32 MAC1                           : 8;
 317         } mac_address_418;
 318
 319         struct {
 320                 u32 reserved                       :16;
 321                 u32 MAC8                           : 8;
 322                 u32 MAC7                           : 8;
 323         } mac_address_41c;
 324
 325         struct {
 326                 u32 reserved                       :21;
 327                 u32 txbuffempty                    : 1;
 328                 u32 ReceiveByteFrameError          : 1;
 329                 u32 ReceiveDataReady               : 1;
 330                 u32 transmitter_data_byte          : 8;
 331         } ci_600;
 332
 333         struct {
 334                 u32 pi_component_reg               : 3;
 335                 u32 pi_rw                          : 1;
 336                 u32 pi_ha                          :20;
 337                 u32 pi_d                           : 8;
 338         } pi_604;
 339
 340         struct {
 341                 u32 pi_busy_n                      : 1;
 342                 u32 pi_wait_n                      : 1;
 343                 u32 pi_timeout_status              : 1;
 344                 u32 pi_CiMax_IRQ_n                 : 1;
 345                 u32 config_cclk                    : 1;
 346                 u32 config_cs_n                    : 1;
 347                 u32 config_wr_n                    : 1;
 348                 u32 config_Prog_n                  : 1;
 349                 u32 config_Init_stat               : 1;
 350                 u32 config_Done_stat               : 1;
 351                 u32 pcmcia_b_mod_pwr_n             : 1;
 352                 u32 pcmcia_a_mod_pwr_n             : 1;
 353                 u32 reserved                       : 3;
 354                 u32 Timer_addr                     : 5;
 355                 u32 unused                         : 1;
 356                 u32 timer_data                     : 7;
 357                 u32 Timer_Load_req                 : 1;
 358                 u32 Timer_Read_req                 : 1;
 359                 u32 oncecycle_read                 : 1;
 360                 u32 serialReset                    : 1;
 361         } pi_608;
 362
 363         struct {
 364                 u32 reserved                       : 6;
 365                 u32 rw_flag                        : 1;
 366                 u32 dvb_en                         : 1;
 367                 u32 key_array_row                  : 5;
 368                 u32 key_array_col                  : 3;
 369                 u32 key_code                       : 2;
 370                 u32 key_enable                     : 1;
 371                 u32 PID                            :13;
 372         } dvb_reg_60c;
 373
 374         struct {
 375                 u32 start_sram_ibi                 : 1;
 376                 u32 reserved2                      : 1;
 377                 u32 ce_pin_reg                     : 1;
 378                 u32 oe_pin_reg                     : 1;
 379                 u32 reserved1                      : 3;
 380                 u32 sc_xfer_bit                    : 1;
 381                 u32 sram_data                      : 8;
 382                 u32 sram_rw                        : 1;
 383                 u32 sram_addr                      :15;
 384         } sram_ctrl_reg_700;
 385
 386         struct {
 387                 u32 net_addr_write                 :16;
 388                 u32 net_addr_read                  :16;
 389         } net_buf_reg_704;
 390
 391         struct {
 392                 u32 cai_cnt                        : 4;
 393                 u32 reserved2                      : 6;
 394                 u32 cai_write                      :11;
 395                 u32 reserved1                      : 5;
 396                 u32 cai_read                       :11;
 397         } cai_buf_reg_708;
 398
 399         struct {
 400                 u32 cao_cnt                        : 4;
 401                 u32 reserved2                      : 6;
 402                 u32 cap_write                      :11;
 403                 u32 reserved1                      : 5;
 404                 u32 cao_read                       :11;
 405         } cao_buf_reg_70c;
 406
 407         struct {
 408                 u32 media_cnt                      : 4;
 409                 u32 reserved2                      : 6;
 410                 u32 media_write                    :11;
 411                 u32 reserved1                      : 5;
 412                 u32 media_read                     :11;
 413         } media_buf_reg_710;
 414
 415         struct {
 416                 u32 reserved                       :17;
 417                 u32 ctrl_maximumfill               : 1;
 418                 u32 ctrl_sramdma                   : 1;
 419                 u32 ctrl_usb_wan                   : 1;
 420                 u32 cao_ovflow_error               : 1;
 421                 u32 cai_ovflow_error               : 1;
 422                 u32 media_ovflow_error             : 1;
 423                 u32 net_ovflow_error               : 1;
 424                 u32 MEDIA_Dest                     : 2;
 425                 u32 CAO_Dest                       : 2;
 426                 u32 CAI_Dest                       : 2;
 427                 u32 NET_Dest                       : 2;
 428         } sram_dest_reg_714;
 429
 430         struct {
 431                 u32 reserved3                      :11;
 432                 u32 net_addr_write                 : 1;
 433                 u32 reserved2                      : 3;
 434                 u32 net_addr_read                  : 1;
 435                 u32 reserved1                      : 4;
 436                 u32 net_cnt                        :12;
 437         } net_buf_reg_718;
 438
 439         struct {
 440                 u32 reserved3                      : 4;
 441                 u32 wan_pkt_frame                  : 4;
 442                 u32 reserved2                      : 4;
 443                 u32 sram_memmap                    : 2;
 444                 u32 sram_chip                      : 2;
 445                 u32 wan_wait_state                 : 8;
 446                 u32 reserved1                      : 6;
 447                 u32 wan_speed_sig                  : 2;
 448         } wan_ctrl_reg_71c;
 449 } flexcop_ibi_value;
 450
 451 #endif