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IB/mthca: Make all device methods truly reentrant
[linux-2.6.git] / drivers / infiniband / hw / mthca / mthca_qp.c
1 /*
2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  *
35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36  */
37
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53         MTHCA_ACK_REQ_FREQ       = 10,
54         MTHCA_FLIGHT_LIMIT       = 9,
55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
58 };
59
60 enum {
61         MTHCA_QP_STATE_RST  = 0,
62         MTHCA_QP_STATE_INIT = 1,
63         MTHCA_QP_STATE_RTR  = 2,
64         MTHCA_QP_STATE_RTS  = 3,
65         MTHCA_QP_STATE_SQE  = 4,
66         MTHCA_QP_STATE_SQD  = 5,
67         MTHCA_QP_STATE_ERR  = 6,
68         MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72         MTHCA_QP_ST_RC  = 0x0,
73         MTHCA_QP_ST_UC  = 0x1,
74         MTHCA_QP_ST_RD  = 0x2,
75         MTHCA_QP_ST_UD  = 0x3,
76         MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80         MTHCA_QP_PM_MIGRATED = 0x3,
81         MTHCA_QP_PM_ARMED    = 0x0,
82         MTHCA_QP_PM_REARM    = 0x1
83 };
84
85 enum {
86         /* qp_context flags */
87         MTHCA_QP_BIT_DE  = 1 <<  8,
88         /* params1 */
89         MTHCA_QP_BIT_SRE = 1 << 15,
90         MTHCA_QP_BIT_SWE = 1 << 14,
91         MTHCA_QP_BIT_SAE = 1 << 13,
92         MTHCA_QP_BIT_SIC = 1 <<  4,
93         MTHCA_QP_BIT_SSC = 1 <<  3,
94         /* params2 */
95         MTHCA_QP_BIT_RRE = 1 << 15,
96         MTHCA_QP_BIT_RWE = 1 << 14,
97         MTHCA_QP_BIT_RAE = 1 << 13,
98         MTHCA_QP_BIT_RIC = 1 <<  4,
99         MTHCA_QP_BIT_RSC = 1 <<  3
100 };
101
102 struct mthca_qp_path {
103         __be32 port_pkey;
104         u8     rnr_retry;
105         u8     g_mylmc;
106         __be16 rlid;
107         u8     ackto;
108         u8     mgid_index;
109         u8     static_rate;
110         u8     hop_limit;
111         __be32 sl_tclass_flowlabel;
112         u8     rgid[16];
113 } __attribute__((packed));
114
115 struct mthca_qp_context {
116         __be32 flags;
117         __be32 tavor_sched_queue; /* Reserved on Arbel */
118         u8     mtu_msgmax;
119         u8     rq_size_stride;  /* Reserved on Tavor */
120         u8     sq_size_stride;  /* Reserved on Tavor */
121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
122         __be32 usr_page;
123         __be32 local_qpn;
124         __be32 remote_qpn;
125         u32    reserved1[2];
126         struct mthca_qp_path pri_path;
127         struct mthca_qp_path alt_path;
128         __be32 rdd;
129         __be32 pd;
130         __be32 wqe_base;
131         __be32 wqe_lkey;
132         __be32 params1;
133         __be32 reserved2;
134         __be32 next_send_psn;
135         __be32 cqn_snd;
136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
137         __be32 snd_db_index;    /* (debugging only entries) */
138         __be32 last_acked_psn;
139         __be32 ssn;
140         __be32 params2;
141         __be32 rnr_nextrecvpsn;
142         __be32 ra_buff_indx;
143         __be32 cqn_rcv;
144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
145         __be32 rcv_db_index;    /* (debugging only entries) */
146         __be32 qkey;
147         __be32 srqn;
148         __be32 rmsn;
149         __be16 rq_wqe_counter;  /* reserved on Tavor */
150         __be16 sq_wqe_counter;  /* reserved on Tavor */
151         u32    reserved3[18];
152 } __attribute__((packed));
153
154 struct mthca_qp_param {
155         __be32 opt_param_mask;
156         u32    reserved1;
157         struct mthca_qp_context context;
158         u32    reserved2[62];
159 } __attribute__((packed));
160
161 enum {
162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
179 };
180
181 static const u8 mthca_opcode[] = {
182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
189 };
190
191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
192 {
193         return qp->qpn >= dev->qp_table.sqp_start &&
194                 qp->qpn <= dev->qp_table.sqp_start + 3;
195 }
196
197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
198 {
199         return qp->qpn >= dev->qp_table.sqp_start &&
200                 qp->qpn <= dev->qp_table.sqp_start + 1;
201 }
202
203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
204 {
205         if (qp->is_direct)
206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
207         else
208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
210 }
211
212 static void *get_send_wqe(struct mthca_qp *qp, int n)
213 {
214         if (qp->is_direct)
215                 return qp->queue.direct.buf + qp->send_wqe_offset +
216                         (n << qp->sq.wqe_shift);
217         else
218                 return qp->queue.page_list[(qp->send_wqe_offset +
219                                             (n << qp->sq.wqe_shift)) >>
220                                            PAGE_SHIFT].buf +
221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
222                          (PAGE_SIZE - 1));
223 }
224
225 static void mthca_wq_init(struct mthca_wq *wq)
226 {
227         spin_lock_init(&wq->lock);
228         wq->next_ind  = 0;
229         wq->last_comp = wq->max - 1;
230         wq->head      = 0;
231         wq->tail      = 0;
232 }
233
234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
235                     enum ib_event_type event_type)
236 {
237         struct mthca_qp *qp;
238         struct ib_event event;
239
240         spin_lock(&dev->qp_table.lock);
241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
242         if (qp)
243                 ++qp->refcount;
244         spin_unlock(&dev->qp_table.lock);
245
246         if (!qp) {
247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
248                 return;
249         }
250
251         if (event_type == IB_EVENT_PATH_MIG)
252                 qp->port = qp->alt_port;
253
254         event.device      = &dev->ib_dev;
255         event.event       = event_type;
256         event.element.qp  = &qp->ibqp;
257         if (qp->ibqp.event_handler)
258                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
259
260         spin_lock(&dev->qp_table.lock);
261         if (!--qp->refcount)
262                 wake_up(&qp->wait);
263         spin_unlock(&dev->qp_table.lock);
264 }
265
266 static int to_mthca_state(enum ib_qp_state ib_state)
267 {
268         switch (ib_state) {
269         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
270         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
271         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
272         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
273         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
274         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
275         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
276         default:                return -1;
277         }
278 }
279
280 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
281
282 static int to_mthca_st(int transport)
283 {
284         switch (transport) {
285         case RC:  return MTHCA_QP_ST_RC;
286         case UC:  return MTHCA_QP_ST_UC;
287         case UD:  return MTHCA_QP_ST_UD;
288         case RD:  return MTHCA_QP_ST_RD;
289         case MLX: return MTHCA_QP_ST_MLX;
290         default:  return -1;
291         }
292 }
293
294 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
295                         int attr_mask)
296 {
297         if (attr_mask & IB_QP_PKEY_INDEX)
298                 sqp->pkey_index = attr->pkey_index;
299         if (attr_mask & IB_QP_QKEY)
300                 sqp->qkey = attr->qkey;
301         if (attr_mask & IB_QP_SQ_PSN)
302                 sqp->send_psn = attr->sq_psn;
303 }
304
305 static void init_port(struct mthca_dev *dev, int port)
306 {
307         int err;
308         u8 status;
309         struct mthca_init_ib_param param;
310
311         memset(&param, 0, sizeof param);
312
313         param.port_width = dev->limits.port_width_cap;
314         param.vl_cap     = dev->limits.vl_cap;
315         param.mtu_cap    = dev->limits.mtu_cap;
316         param.gid_cap    = dev->limits.gid_table_len;
317         param.pkey_cap   = dev->limits.pkey_table_len;
318
319         err = mthca_INIT_IB(dev, &param, port, &status);
320         if (err)
321                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
322         if (status)
323                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
324 }
325
326 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
327                                   int attr_mask)
328 {
329         u8 dest_rd_atomic;
330         u32 access_flags;
331         u32 hw_access_flags = 0;
332
333         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
334                 dest_rd_atomic = attr->max_dest_rd_atomic;
335         else
336                 dest_rd_atomic = qp->resp_depth;
337
338         if (attr_mask & IB_QP_ACCESS_FLAGS)
339                 access_flags = attr->qp_access_flags;
340         else
341                 access_flags = qp->atomic_rd_en;
342
343         if (!dest_rd_atomic)
344                 access_flags &= IB_ACCESS_REMOTE_WRITE;
345
346         if (access_flags & IB_ACCESS_REMOTE_READ)
347                 hw_access_flags |= MTHCA_QP_BIT_RRE;
348         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
349                 hw_access_flags |= MTHCA_QP_BIT_RAE;
350         if (access_flags & IB_ACCESS_REMOTE_WRITE)
351                 hw_access_flags |= MTHCA_QP_BIT_RWE;
352
353         return cpu_to_be32(hw_access_flags);
354 }
355
356 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
357 {
358         switch (mthca_state) {
359         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
360         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
361         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
362         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
363         case MTHCA_QP_STATE_DRAINING:
364         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
365         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
366         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
367         default:                      return -1;
368         }
369 }
370
371 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
372 {
373         switch (mthca_mig_state) {
374         case 0:  return IB_MIG_ARMED;
375         case 1:  return IB_MIG_REARM;
376         case 3:  return IB_MIG_MIGRATED;
377         default: return -1;
378         }
379 }
380
381 static int to_ib_qp_access_flags(int mthca_flags)
382 {
383         int ib_flags = 0;
384
385         if (mthca_flags & MTHCA_QP_BIT_RRE)
386                 ib_flags |= IB_ACCESS_REMOTE_READ;
387         if (mthca_flags & MTHCA_QP_BIT_RWE)
388                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
389         if (mthca_flags & MTHCA_QP_BIT_RAE)
390                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
391
392         return ib_flags;
393 }
394
395 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
396                                 struct mthca_qp_path *path)
397 {
398         memset(ib_ah_attr, 0, sizeof *path);
399         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
400
401         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
402                 return;
403
404         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
405         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
406         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
407         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
408                                                      path->static_rate & 0x7,
409                                                      ib_ah_attr->port_num);
410         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
411         if (ib_ah_attr->ah_flags) {
412                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
413                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
414                 ib_ah_attr->grh.traffic_class =
415                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
416                 ib_ah_attr->grh.flow_label =
417                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
418                 memcpy(ib_ah_attr->grh.dgid.raw,
419                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
420         }
421 }
422
423 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
424                    struct ib_qp_init_attr *qp_init_attr)
425 {
426         struct mthca_dev *dev = to_mdev(ibqp->device);
427         struct mthca_qp *qp = to_mqp(ibqp);
428         int err;
429         struct mthca_mailbox *mailbox;
430         struct mthca_qp_param *qp_param;
431         struct mthca_qp_context *context;
432         int mthca_state;
433         u8 status;
434
435         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
436         if (IS_ERR(mailbox))
437                 return PTR_ERR(mailbox);
438
439         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
440         if (err)
441                 goto out;
442         if (status) {
443                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
444                 err = -EINVAL;
445                 goto out;
446         }
447
448         qp_param    = mailbox->buf;
449         context     = &qp_param->context;
450         mthca_state = be32_to_cpu(context->flags) >> 28;
451
452         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
453         qp_attr->cur_qp_state        = qp_attr->qp_state;
454         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
455         qp_attr->path_mig_state      =
456                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
457         qp_attr->qkey                = be32_to_cpu(context->qkey);
458         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
459         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
460         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
461         qp_attr->qp_access_flags     =
462                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
463         qp_attr->cap.max_send_wr     = qp->sq.max;
464         qp_attr->cap.max_recv_wr     = qp->rq.max;
465         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
466         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
467         qp_attr->cap.max_inline_data = qp->max_inline_data;
468
469         if (qp->transport == RC || qp->transport == UC) {
470                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
471                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
472         }
473
474         qp_attr->pkey_index     = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
475         qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
476
477         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
478         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
479
480         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
481
482         qp_attr->max_dest_rd_atomic =
483                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
484         qp_attr->min_rnr_timer      =
485                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
486         qp_attr->port_num           = qp_attr->ah_attr.port_num;
487         qp_attr->timeout            = context->pri_path.ackto >> 3;
488         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
489         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
490         qp_attr->alt_port_num       = qp_attr->alt_ah_attr.port_num;
491         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
492         qp_init_attr->cap           = qp_attr->cap;
493
494 out:
495         mthca_free_mailbox(dev, mailbox);
496         return err;
497 }
498
499 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
500                           struct mthca_qp_path *path, u8 port)
501 {
502         path->g_mylmc     = ah->src_path_bits & 0x7f;
503         path->rlid        = cpu_to_be16(ah->dlid);
504         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
505
506         if (ah->ah_flags & IB_AH_GRH) {
507                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
508                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
509                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
510                         return -1;
511                 }
512
513                 path->g_mylmc   |= 1 << 7;
514                 path->mgid_index = ah->grh.sgid_index;
515                 path->hop_limit  = ah->grh.hop_limit;
516                 path->sl_tclass_flowlabel =
517                         cpu_to_be32((ah->sl << 28)                |
518                                     (ah->grh.traffic_class << 20) |
519                                     (ah->grh.flow_label));
520                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
521         } else
522                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
523
524         return 0;
525 }
526
527 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
528 {
529         struct mthca_dev *dev = to_mdev(ibqp->device);
530         struct mthca_qp *qp = to_mqp(ibqp);
531         enum ib_qp_state cur_state, new_state;
532         struct mthca_mailbox *mailbox;
533         struct mthca_qp_param *qp_param;
534         struct mthca_qp_context *qp_context;
535         u32 sqd_event = 0;
536         u8 status;
537         int err = -EINVAL;
538
539         mutex_lock(&qp->mutex);
540
541         if (attr_mask & IB_QP_CUR_STATE) {
542                 cur_state = attr->cur_qp_state;
543         } else {
544                 spin_lock_irq(&qp->sq.lock);
545                 spin_lock(&qp->rq.lock);
546                 cur_state = qp->state;
547                 spin_unlock(&qp->rq.lock);
548                 spin_unlock_irq(&qp->sq.lock);
549         }
550
551         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
552
553         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
554                 mthca_dbg(dev, "Bad QP transition (transport %d) "
555                           "%d->%d with attr 0x%08x\n",
556                           qp->transport, cur_state, new_state,
557                           attr_mask);
558                 goto out;
559         }
560
561         if ((attr_mask & IB_QP_PKEY_INDEX) &&
562              attr->pkey_index >= dev->limits.pkey_table_len) {
563                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
564                           attr->pkey_index, dev->limits.pkey_table_len-1);
565                 goto out;
566         }
567
568         if ((attr_mask & IB_QP_PORT) &&
569             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
570                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
571                 goto out;
572         }
573
574         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
575             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
576                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
577                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
578                 goto out;
579         }
580
581         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
582             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
583                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
584                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
585                 goto out;
586         }
587
588         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
589         if (IS_ERR(mailbox)) {
590                 err = PTR_ERR(mailbox);
591                 goto out;
592         }
593         qp_param = mailbox->buf;
594         qp_context = &qp_param->context;
595         memset(qp_param, 0, sizeof *qp_param);
596
597         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
598                                              (to_mthca_st(qp->transport) << 16));
599         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
600         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
601                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
602         else {
603                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
604                 switch (attr->path_mig_state) {
605                 case IB_MIG_MIGRATED:
606                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
607                         break;
608                 case IB_MIG_REARM:
609                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
610                         break;
611                 case IB_MIG_ARMED:
612                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
613                         break;
614                 }
615         }
616
617         /* leave tavor_sched_queue as 0 */
618
619         if (qp->transport == MLX || qp->transport == UD)
620                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
621         else if (attr_mask & IB_QP_PATH_MTU) {
622                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
623                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
624                                   attr->path_mtu);
625                         goto out_mailbox;
626                 }
627                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
628         }
629
630         if (mthca_is_memfree(dev)) {
631                 if (qp->rq.max)
632                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
633                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
634
635                 if (qp->sq.max)
636                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
637                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
638         }
639
640         /* leave arbel_sched_queue as 0 */
641
642         if (qp->ibqp.uobject)
643                 qp_context->usr_page =
644                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
645         else
646                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
647         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
648         if (attr_mask & IB_QP_DEST_QPN) {
649                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
650         }
651
652         if (qp->transport == MLX)
653                 qp_context->pri_path.port_pkey |=
654                         cpu_to_be32(qp->port << 24);
655         else {
656                 if (attr_mask & IB_QP_PORT) {
657                         qp_context->pri_path.port_pkey |=
658                                 cpu_to_be32(attr->port_num << 24);
659                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
660                 }
661         }
662
663         if (attr_mask & IB_QP_PKEY_INDEX) {
664                 qp_context->pri_path.port_pkey |=
665                         cpu_to_be32(attr->pkey_index);
666                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
667         }
668
669         if (attr_mask & IB_QP_RNR_RETRY) {
670                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
671                         attr->rnr_retry << 5;
672                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
673                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
674         }
675
676         if (attr_mask & IB_QP_AV) {
677                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
678                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
679                         goto out_mailbox;
680
681                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
682         }
683
684         if (attr_mask & IB_QP_TIMEOUT) {
685                 qp_context->pri_path.ackto = attr->timeout << 3;
686                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
687         }
688
689         if (attr_mask & IB_QP_ALT_PATH) {
690                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
691                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
692                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
693                         goto out_mailbox;
694                 }
695
696                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
697                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
698                                 attr->alt_port_num);
699                         goto out_mailbox;
700                 }
701
702                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
703                                    attr->alt_ah_attr.port_num))
704                         goto out_mailbox;
705
706                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
707                                                               attr->alt_port_num << 24);
708                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
709                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
710         }
711
712         /* leave rdd as 0 */
713         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
714         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
715         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
716         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
717                                              (MTHCA_FLIGHT_LIMIT << 24) |
718                                              MTHCA_QP_BIT_SWE);
719         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
720                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
721         if (attr_mask & IB_QP_RETRY_CNT) {
722                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
723                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
724         }
725
726         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
727                 if (attr->max_rd_atomic) {
728                         qp_context->params1 |=
729                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
730                                             MTHCA_QP_BIT_SAE);
731                         qp_context->params1 |=
732                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
733                 }
734                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
735         }
736
737         if (attr_mask & IB_QP_SQ_PSN)
738                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
739         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
740
741         if (mthca_is_memfree(dev)) {
742                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
743                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
744         }
745
746         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
747                 if (attr->max_dest_rd_atomic)
748                         qp_context->params2 |=
749                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
750
751                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
752         }
753
754         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
755                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
756                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
757                                                         MTHCA_QP_OPTPAR_RRE |
758                                                         MTHCA_QP_OPTPAR_RAE);
759         }
760
761         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
762
763         if (ibqp->srq)
764                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
765
766         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
767                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
768                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
769         }
770         if (attr_mask & IB_QP_RQ_PSN)
771                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
772
773         qp_context->ra_buff_indx =
774                 cpu_to_be32(dev->qp_table.rdb_base +
775                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
776                              dev->qp_table.rdb_shift));
777
778         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
779
780         if (mthca_is_memfree(dev))
781                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
782
783         if (attr_mask & IB_QP_QKEY) {
784                 qp_context->qkey = cpu_to_be32(attr->qkey);
785                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
786         }
787
788         if (ibqp->srq)
789                 qp_context->srqn = cpu_to_be32(1 << 24 |
790                                                to_msrq(ibqp->srq)->srqn);
791
792         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
793             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
794             attr->en_sqd_async_notify)
795                 sqd_event = 1 << 31;
796
797         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
798                               mailbox, sqd_event, &status);
799         if (err)
800                 goto out_mailbox;
801         if (status) {
802                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
803                            cur_state, new_state, status);
804                 err = -EINVAL;
805                 goto out_mailbox;
806         }
807
808         qp->state = new_state;
809         if (attr_mask & IB_QP_ACCESS_FLAGS)
810                 qp->atomic_rd_en = attr->qp_access_flags;
811         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
812                 qp->resp_depth = attr->max_dest_rd_atomic;
813         if (attr_mask & IB_QP_PORT)
814                 qp->port = attr->port_num;
815         if (attr_mask & IB_QP_ALT_PATH)
816                 qp->alt_port = attr->alt_port_num;
817
818         if (is_sqp(dev, qp))
819                 store_attrs(to_msqp(qp), attr, attr_mask);
820
821         /*
822          * If we moved QP0 to RTR, bring the IB link up; if we moved
823          * QP0 to RESET or ERROR, bring the link back down.
824          */
825         if (is_qp0(dev, qp)) {
826                 if (cur_state != IB_QPS_RTR &&
827                     new_state == IB_QPS_RTR)
828                         init_port(dev, qp->port);
829
830                 if (cur_state != IB_QPS_RESET &&
831                     cur_state != IB_QPS_ERR &&
832                     (new_state == IB_QPS_RESET ||
833                      new_state == IB_QPS_ERR))
834                         mthca_CLOSE_IB(dev, qp->port, &status);
835         }
836
837         /*
838          * If we moved a kernel QP to RESET, clean up all old CQ
839          * entries and reinitialize the QP.
840          */
841         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
842                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
843                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
844                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
845                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
846                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
847
848                 mthca_wq_init(&qp->sq);
849                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
850
851                 mthca_wq_init(&qp->rq);
852                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
853
854                 if (mthca_is_memfree(dev)) {
855                         *qp->sq.db = 0;
856                         *qp->rq.db = 0;
857                 }
858         }
859
860 out_mailbox:
861         mthca_free_mailbox(dev, mailbox);
862
863 out:
864         mutex_unlock(&qp->mutex);
865         return err;
866 }
867
868 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
869 {
870         /*
871          * Calculate the maximum size of WQE s/g segments, excluding
872          * the next segment and other non-data segments.
873          */
874         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
875
876         switch (qp->transport) {
877         case MLX:
878                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
879                 break;
880
881         case UD:
882                 if (mthca_is_memfree(dev))
883                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
884                 else
885                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
886                 break;
887
888         default:
889                 max_data_size -= sizeof (struct mthca_raddr_seg);
890                 break;
891         }
892
893         return max_data_size;
894 }
895
896 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
897 {
898         /* We don't support inline data for kernel QPs (yet). */
899         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
900 }
901
902 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
903                                  struct mthca_pd *pd,
904                                  struct mthca_qp *qp)
905 {
906         int max_data_size = mthca_max_data_size(dev, qp,
907                                                 min(dev->limits.max_desc_sz,
908                                                     1 << qp->sq.wqe_shift));
909
910         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
911
912         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
913                               max_data_size / sizeof (struct mthca_data_seg));
914         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
915                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
916                                 sizeof (struct mthca_next_seg)) /
917                                sizeof (struct mthca_data_seg));
918 }
919
920 /*
921  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
922  * rq.max_gs and sq.max_gs must all be assigned.
923  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
924  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
925  * queue)
926  */
927 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
928                                struct mthca_pd *pd,
929                                struct mthca_qp *qp)
930 {
931         int size;
932         int err = -ENOMEM;
933
934         size = sizeof (struct mthca_next_seg) +
935                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
936
937         if (size > dev->limits.max_desc_sz)
938                 return -EINVAL;
939
940         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
941              qp->rq.wqe_shift++)
942                 ; /* nothing */
943
944         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
945         switch (qp->transport) {
946         case MLX:
947                 size += 2 * sizeof (struct mthca_data_seg);
948                 break;
949
950         case UD:
951                 size += mthca_is_memfree(dev) ?
952                         sizeof (struct mthca_arbel_ud_seg) :
953                         sizeof (struct mthca_tavor_ud_seg);
954                 break;
955
956         case UC:
957                 size += sizeof (struct mthca_raddr_seg);
958                 break;
959
960         case RC:
961                 size += sizeof (struct mthca_raddr_seg);
962                 /*
963                  * An atomic op will require an atomic segment, a
964                  * remote address segment and one scatter entry.
965                  */
966                 size = max_t(int, size,
967                              sizeof (struct mthca_atomic_seg) +
968                              sizeof (struct mthca_raddr_seg) +
969                              sizeof (struct mthca_data_seg));
970                 break;
971
972         default:
973                 break;
974         }
975
976         /* Make sure that we have enough space for a bind request */
977         size = max_t(int, size, sizeof (struct mthca_bind_seg));
978
979         size += sizeof (struct mthca_next_seg);
980
981         if (size > dev->limits.max_desc_sz)
982                 return -EINVAL;
983
984         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
985              qp->sq.wqe_shift++)
986                 ; /* nothing */
987
988         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
989                                     1 << qp->sq.wqe_shift);
990
991         /*
992          * If this is a userspace QP, we don't actually have to
993          * allocate anything.  All we need is to calculate the WQE
994          * sizes and the send_wqe_offset, so we're done now.
995          */
996         if (pd->ibpd.uobject)
997                 return 0;
998
999         size = PAGE_ALIGN(qp->send_wqe_offset +
1000                           (qp->sq.max << qp->sq.wqe_shift));
1001
1002         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1003                            GFP_KERNEL);
1004         if (!qp->wrid)
1005                 goto err_out;
1006
1007         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1008                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1009         if (err)
1010                 goto err_out;
1011
1012         return 0;
1013
1014 err_out:
1015         kfree(qp->wrid);
1016         return err;
1017 }
1018
1019 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1020                                struct mthca_qp *qp)
1021 {
1022         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1023                                        (qp->sq.max << qp->sq.wqe_shift)),
1024                        &qp->queue, qp->is_direct, &qp->mr);
1025         kfree(qp->wrid);
1026 }
1027
1028 static int mthca_map_memfree(struct mthca_dev *dev,
1029                              struct mthca_qp *qp)
1030 {
1031         int ret;
1032
1033         if (mthca_is_memfree(dev)) {
1034                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1035                 if (ret)
1036                         return ret;
1037
1038                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1039                 if (ret)
1040                         goto err_qpc;
1041
1042                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1043                                       qp->qpn << dev->qp_table.rdb_shift);
1044                 if (ret)
1045                         goto err_eqpc;
1046
1047         }
1048
1049         return 0;
1050
1051 err_eqpc:
1052         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1053
1054 err_qpc:
1055         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1056
1057         return ret;
1058 }
1059
1060 static void mthca_unmap_memfree(struct mthca_dev *dev,
1061                                 struct mthca_qp *qp)
1062 {
1063         mthca_table_put(dev, dev->qp_table.rdb_table,
1064                         qp->qpn << dev->qp_table.rdb_shift);
1065         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1066         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1067 }
1068
1069 static int mthca_alloc_memfree(struct mthca_dev *dev,
1070                                struct mthca_qp *qp)
1071 {
1072         int ret = 0;
1073
1074         if (mthca_is_memfree(dev)) {
1075                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1076                                                  qp->qpn, &qp->rq.db);
1077                 if (qp->rq.db_index < 0)
1078                         return ret;
1079
1080                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1081                                                  qp->qpn, &qp->sq.db);
1082                 if (qp->sq.db_index < 0)
1083                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1084         }
1085
1086         return ret;
1087 }
1088
1089 static void mthca_free_memfree(struct mthca_dev *dev,
1090                                struct mthca_qp *qp)
1091 {
1092         if (mthca_is_memfree(dev)) {
1093                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1094                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1095         }
1096 }
1097
1098 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1099                                  struct mthca_pd *pd,
1100                                  struct mthca_cq *send_cq,
1101                                  struct mthca_cq *recv_cq,
1102                                  enum ib_sig_type send_policy,
1103                                  struct mthca_qp *qp)
1104 {
1105         int ret;
1106         int i;
1107
1108         qp->refcount = 1;
1109         init_waitqueue_head(&qp->wait);
1110         mutex_init(&qp->mutex);
1111         qp->state        = IB_QPS_RESET;
1112         qp->atomic_rd_en = 0;
1113         qp->resp_depth   = 0;
1114         qp->sq_policy    = send_policy;
1115         mthca_wq_init(&qp->sq);
1116         mthca_wq_init(&qp->rq);
1117
1118         ret = mthca_map_memfree(dev, qp);
1119         if (ret)
1120                 return ret;
1121
1122         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1123         if (ret) {
1124                 mthca_unmap_memfree(dev, qp);
1125                 return ret;
1126         }
1127
1128         mthca_adjust_qp_caps(dev, pd, qp);
1129
1130         /*
1131          * If this is a userspace QP, we're done now.  The doorbells
1132          * will be allocated and buffers will be initialized in
1133          * userspace.
1134          */
1135         if (pd->ibpd.uobject)
1136                 return 0;
1137
1138         ret = mthca_alloc_memfree(dev, qp);
1139         if (ret) {
1140                 mthca_free_wqe_buf(dev, qp);
1141                 mthca_unmap_memfree(dev, qp);
1142                 return ret;
1143         }
1144
1145         if (mthca_is_memfree(dev)) {
1146                 struct mthca_next_seg *next;
1147                 struct mthca_data_seg *scatter;
1148                 int size = (sizeof (struct mthca_next_seg) +
1149                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1150
1151                 for (i = 0; i < qp->rq.max; ++i) {
1152                         next = get_recv_wqe(qp, i);
1153                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1154                                                    qp->rq.wqe_shift);
1155                         next->ee_nds = cpu_to_be32(size);
1156
1157                         for (scatter = (void *) (next + 1);
1158                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1159                              ++scatter)
1160                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1161                 }
1162
1163                 for (i = 0; i < qp->sq.max; ++i) {
1164                         next = get_send_wqe(qp, i);
1165                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1166                                                     qp->sq.wqe_shift) +
1167                                                    qp->send_wqe_offset);
1168                 }
1169         }
1170
1171         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1172         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1173
1174         return 0;
1175 }
1176
1177 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1178                              struct mthca_pd *pd, struct mthca_qp *qp)
1179 {
1180         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1181
1182         /* Sanity check QP size before proceeding */
1183         if (cap->max_send_wr     > dev->limits.max_wqes ||
1184             cap->max_recv_wr     > dev->limits.max_wqes ||
1185             cap->max_send_sge    > dev->limits.max_sg   ||
1186             cap->max_recv_sge    > dev->limits.max_sg   ||
1187             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1188                 return -EINVAL;
1189
1190         /*
1191          * For MLX transport we need 2 extra S/G entries:
1192          * one for the header and one for the checksum at the end
1193          */
1194         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1195                 return -EINVAL;
1196
1197         if (mthca_is_memfree(dev)) {
1198                 qp->rq.max = cap->max_recv_wr ?
1199                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1200                 qp->sq.max = cap->max_send_wr ?
1201                         roundup_pow_of_two(cap->max_send_wr) : 0;
1202         } else {
1203                 qp->rq.max = cap->max_recv_wr;
1204                 qp->sq.max = cap->max_send_wr;
1205         }
1206
1207         qp->rq.max_gs = cap->max_recv_sge;
1208         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1209                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1210                                     MTHCA_INLINE_CHUNK_SIZE) /
1211                               sizeof (struct mthca_data_seg));
1212
1213         return 0;
1214 }
1215
1216 int mthca_alloc_qp(struct mthca_dev *dev,
1217                    struct mthca_pd *pd,
1218                    struct mthca_cq *send_cq,
1219                    struct mthca_cq *recv_cq,
1220                    enum ib_qp_type type,
1221                    enum ib_sig_type send_policy,
1222                    struct ib_qp_cap *cap,
1223                    struct mthca_qp *qp)
1224 {
1225         int err;
1226
1227         switch (type) {
1228         case IB_QPT_RC: qp->transport = RC; break;
1229         case IB_QPT_UC: qp->transport = UC; break;
1230         case IB_QPT_UD: qp->transport = UD; break;
1231         default: return -EINVAL;
1232         }
1233
1234         err = mthca_set_qp_size(dev, cap, pd, qp);
1235         if (err)
1236                 return err;
1237
1238         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1239         if (qp->qpn == -1)
1240                 return -ENOMEM;
1241
1242         /* initialize port to zero for error-catching. */
1243         qp->port = 0;
1244
1245         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1246                                     send_policy, qp);
1247         if (err) {
1248                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1249                 return err;
1250         }
1251
1252         spin_lock_irq(&dev->qp_table.lock);
1253         mthca_array_set(&dev->qp_table.qp,
1254                         qp->qpn & (dev->limits.num_qps - 1), qp);
1255         spin_unlock_irq(&dev->qp_table.lock);
1256
1257         return 0;
1258 }
1259
1260 int mthca_alloc_sqp(struct mthca_dev *dev,
1261                     struct mthca_pd *pd,
1262                     struct mthca_cq *send_cq,
1263                     struct mthca_cq *recv_cq,
1264                     enum ib_sig_type send_policy,
1265                     struct ib_qp_cap *cap,
1266                     int qpn,
1267                     int port,
1268                     struct mthca_sqp *sqp)
1269 {
1270         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1271         int err;
1272
1273         sqp->qp.transport = MLX;
1274         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1275         if (err)
1276                 return err;
1277
1278         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1279         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1280                                              &sqp->header_dma, GFP_KERNEL);
1281         if (!sqp->header_buf)
1282                 return -ENOMEM;
1283
1284         spin_lock_irq(&dev->qp_table.lock);
1285         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1286                 err = -EBUSY;
1287         else
1288                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1289         spin_unlock_irq(&dev->qp_table.lock);
1290
1291         if (err)
1292                 goto err_out;
1293
1294         sqp->qp.port      = port;
1295         sqp->qp.qpn       = mqpn;
1296         sqp->qp.transport = MLX;
1297
1298         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1299                                     send_policy, &sqp->qp);
1300         if (err)
1301                 goto err_out_free;
1302
1303         atomic_inc(&pd->sqp_count);
1304
1305         return 0;
1306
1307  err_out_free:
1308         /*
1309          * Lock CQs here, so that CQ polling code can do QP lookup
1310          * without taking a lock.
1311          */
1312         spin_lock_irq(&send_cq->lock);
1313         if (send_cq != recv_cq)
1314                 spin_lock(&recv_cq->lock);
1315
1316         spin_lock(&dev->qp_table.lock);
1317         mthca_array_clear(&dev->qp_table.qp, mqpn);
1318         spin_unlock(&dev->qp_table.lock);
1319
1320         if (send_cq != recv_cq)
1321                 spin_unlock(&recv_cq->lock);
1322         spin_unlock_irq(&send_cq->lock);
1323
1324  err_out:
1325         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1326                           sqp->header_buf, sqp->header_dma);
1327
1328         return err;
1329 }
1330
1331 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1332 {
1333         int c;
1334
1335         spin_lock_irq(&dev->qp_table.lock);
1336         c = qp->refcount;
1337         spin_unlock_irq(&dev->qp_table.lock);
1338
1339         return c;
1340 }
1341
1342 void mthca_free_qp(struct mthca_dev *dev,
1343                    struct mthca_qp *qp)
1344 {
1345         u8 status;
1346         struct mthca_cq *send_cq;
1347         struct mthca_cq *recv_cq;
1348
1349         send_cq = to_mcq(qp->ibqp.send_cq);
1350         recv_cq = to_mcq(qp->ibqp.recv_cq);
1351
1352         /*
1353          * Lock CQs here, so that CQ polling code can do QP lookup
1354          * without taking a lock.
1355          */
1356         spin_lock_irq(&send_cq->lock);
1357         if (send_cq != recv_cq)
1358                 spin_lock(&recv_cq->lock);
1359
1360         spin_lock(&dev->qp_table.lock);
1361         mthca_array_clear(&dev->qp_table.qp,
1362                           qp->qpn & (dev->limits.num_qps - 1));
1363         --qp->refcount;
1364         spin_unlock(&dev->qp_table.lock);
1365
1366         if (send_cq != recv_cq)
1367                 spin_unlock(&recv_cq->lock);
1368         spin_unlock_irq(&send_cq->lock);
1369
1370         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1371
1372         if (qp->state != IB_QPS_RESET)
1373                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1374                                 NULL, 0, &status);
1375
1376         /*
1377          * If this is a userspace QP, the buffers, MR, CQs and so on
1378          * will be cleaned up in userspace, so all we have to do is
1379          * unref the mem-free tables and free the QPN in our table.
1380          */
1381         if (!qp->ibqp.uobject) {
1382                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1383                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1384                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1385                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1386                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1387
1388                 mthca_free_memfree(dev, qp);
1389                 mthca_free_wqe_buf(dev, qp);
1390         }
1391
1392         mthca_unmap_memfree(dev, qp);
1393
1394         if (is_sqp(dev, qp)) {
1395                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1396                 dma_free_coherent(&dev->pdev->dev,
1397                                   to_msqp(qp)->header_buf_size,
1398                                   to_msqp(qp)->header_buf,
1399                                   to_msqp(qp)->header_dma);
1400         } else
1401                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1402 }
1403
1404 /* Create UD header for an MLX send and build a data segment for it */
1405 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1406                             int ind, struct ib_send_wr *wr,
1407                             struct mthca_mlx_seg *mlx,
1408                             struct mthca_data_seg *data)
1409 {
1410         int header_size;
1411         int err;
1412         u16 pkey;
1413
1414         ib_ud_header_init(256, /* assume a MAD */
1415                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1416                           &sqp->ud_header);
1417
1418         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1419         if (err)
1420                 return err;
1421         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1422         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1423                                   (sqp->ud_header.lrh.destination_lid ==
1424                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1425                                   (sqp->ud_header.lrh.service_level << 8));
1426         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1427         mlx->vcrc = 0;
1428
1429         switch (wr->opcode) {
1430         case IB_WR_SEND:
1431                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1432                 sqp->ud_header.immediate_present = 0;
1433                 break;
1434         case IB_WR_SEND_WITH_IMM:
1435                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1436                 sqp->ud_header.immediate_present = 1;
1437                 sqp->ud_header.immediate_data = wr->imm_data;
1438                 break;
1439         default:
1440                 return -EINVAL;
1441         }
1442
1443         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1444         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1445                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1446         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1447         if (!sqp->qp.ibqp.qp_num)
1448                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1449                                    sqp->pkey_index, &pkey);
1450         else
1451                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1452                                    wr->wr.ud.pkey_index, &pkey);
1453         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1454         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1455         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1456         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1457                                                sqp->qkey : wr->wr.ud.remote_qkey);
1458         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1459
1460         header_size = ib_ud_header_pack(&sqp->ud_header,
1461                                         sqp->header_buf +
1462                                         ind * MTHCA_UD_HEADER_SIZE);
1463
1464         data->byte_count = cpu_to_be32(header_size);
1465         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1466         data->addr       = cpu_to_be64(sqp->header_dma +
1467                                        ind * MTHCA_UD_HEADER_SIZE);
1468
1469         return 0;
1470 }
1471
1472 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1473                                     struct ib_cq *ib_cq)
1474 {
1475         unsigned cur;
1476         struct mthca_cq *cq;
1477
1478         cur = wq->head - wq->tail;
1479         if (likely(cur + nreq < wq->max))
1480                 return 0;
1481
1482         cq = to_mcq(ib_cq);
1483         spin_lock(&cq->lock);
1484         cur = wq->head - wq->tail;
1485         spin_unlock(&cq->lock);
1486
1487         return cur + nreq >= wq->max;
1488 }
1489
1490 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1491                           struct ib_send_wr **bad_wr)
1492 {
1493         struct mthca_dev *dev = to_mdev(ibqp->device);
1494         struct mthca_qp *qp = to_mqp(ibqp);
1495         void *wqe;
1496         void *prev_wqe;
1497         unsigned long flags;
1498         int err = 0;
1499         int nreq;
1500         int i;
1501         int size;
1502         int size0 = 0;
1503         u32 f0 = 0;
1504         int ind;
1505         u8 op0 = 0;
1506
1507         spin_lock_irqsave(&qp->sq.lock, flags);
1508
1509         /* XXX check that state is OK to post send */
1510
1511         ind = qp->sq.next_ind;
1512
1513         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1514                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1515                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1516                                         " %d max, %d nreq)\n", qp->qpn,
1517                                         qp->sq.head, qp->sq.tail,
1518                                         qp->sq.max, nreq);
1519                         err = -ENOMEM;
1520                         *bad_wr = wr;
1521                         goto out;
1522                 }
1523
1524                 wqe = get_send_wqe(qp, ind);
1525                 prev_wqe = qp->sq.last;
1526                 qp->sq.last = wqe;
1527
1528                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1529                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1530                 ((struct mthca_next_seg *) wqe)->flags =
1531                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1532                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1533                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1534                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1535                         cpu_to_be32(1);
1536                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1537                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1538                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1539
1540                 wqe += sizeof (struct mthca_next_seg);
1541                 size = sizeof (struct mthca_next_seg) / 16;
1542
1543                 switch (qp->transport) {
1544                 case RC:
1545                         switch (wr->opcode) {
1546                         case IB_WR_ATOMIC_CMP_AND_SWP:
1547                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1548                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1549                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1550                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1551                                         cpu_to_be32(wr->wr.atomic.rkey);
1552                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1553
1554                                 wqe += sizeof (struct mthca_raddr_seg);
1555
1556                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1557                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1558                                                 cpu_to_be64(wr->wr.atomic.swap);
1559                                         ((struct mthca_atomic_seg *) wqe)->compare =
1560                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1561                                 } else {
1562                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1563                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1564                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1565                                 }
1566
1567                                 wqe += sizeof (struct mthca_atomic_seg);
1568                                 size += (sizeof (struct mthca_raddr_seg) +
1569                                          sizeof (struct mthca_atomic_seg)) / 16;
1570                                 break;
1571
1572                         case IB_WR_RDMA_WRITE:
1573                         case IB_WR_RDMA_WRITE_WITH_IMM:
1574                         case IB_WR_RDMA_READ:
1575                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1576                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1577                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1578                                         cpu_to_be32(wr->wr.rdma.rkey);
1579                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1580                                 wqe += sizeof (struct mthca_raddr_seg);
1581                                 size += sizeof (struct mthca_raddr_seg) / 16;
1582                                 break;
1583
1584                         default:
1585                                 /* No extra segments required for sends */
1586                                 break;
1587                         }
1588
1589                         break;
1590
1591                 case UC:
1592                         switch (wr->opcode) {
1593                         case IB_WR_RDMA_WRITE:
1594                         case IB_WR_RDMA_WRITE_WITH_IMM:
1595                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1596                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1597                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1598                                         cpu_to_be32(wr->wr.rdma.rkey);
1599                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1600                                 wqe += sizeof (struct mthca_raddr_seg);
1601                                 size += sizeof (struct mthca_raddr_seg) / 16;
1602                                 break;
1603
1604                         default:
1605                                 /* No extra segments required for sends */
1606                                 break;
1607                         }
1608
1609                         break;
1610
1611                 case UD:
1612                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1613                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1614                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1615                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1616                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1617                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1618                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1619                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1620
1621                         wqe += sizeof (struct mthca_tavor_ud_seg);
1622                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1623                         break;
1624
1625                 case MLX:
1626                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1627                                                wqe - sizeof (struct mthca_next_seg),
1628                                                wqe);
1629                         if (err) {
1630                                 *bad_wr = wr;
1631                                 goto out;
1632                         }
1633                         wqe += sizeof (struct mthca_data_seg);
1634                         size += sizeof (struct mthca_data_seg) / 16;
1635                         break;
1636                 }
1637
1638                 if (wr->num_sge > qp->sq.max_gs) {
1639                         mthca_err(dev, "too many gathers\n");
1640                         err = -EINVAL;
1641                         *bad_wr = wr;
1642                         goto out;
1643                 }
1644
1645                 for (i = 0; i < wr->num_sge; ++i) {
1646                         ((struct mthca_data_seg *) wqe)->byte_count =
1647                                 cpu_to_be32(wr->sg_list[i].length);
1648                         ((struct mthca_data_seg *) wqe)->lkey =
1649                                 cpu_to_be32(wr->sg_list[i].lkey);
1650                         ((struct mthca_data_seg *) wqe)->addr =
1651                                 cpu_to_be64(wr->sg_list[i].addr);
1652                         wqe += sizeof (struct mthca_data_seg);
1653                         size += sizeof (struct mthca_data_seg) / 16;
1654                 }
1655
1656                 /* Add one more inline data segment for ICRC */
1657                 if (qp->transport == MLX) {
1658                         ((struct mthca_data_seg *) wqe)->byte_count =
1659                                 cpu_to_be32((1 << 31) | 4);
1660                         ((u32 *) wqe)[1] = 0;
1661                         wqe += sizeof (struct mthca_data_seg);
1662                         size += sizeof (struct mthca_data_seg) / 16;
1663                 }
1664
1665                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1666
1667                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1668                         mthca_err(dev, "opcode invalid\n");
1669                         err = -EINVAL;
1670                         *bad_wr = wr;
1671                         goto out;
1672                 }
1673
1674                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1675                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1676                                      qp->send_wqe_offset) |
1677                                     mthca_opcode[wr->opcode]);
1678                 wmb();
1679                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1680                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1681                                     ((wr->send_flags & IB_SEND_FENCE) ?
1682                                     MTHCA_NEXT_FENCE : 0));
1683
1684                 if (!size0) {
1685                         size0 = size;
1686                         op0   = mthca_opcode[wr->opcode];
1687                 }
1688
1689                 ++ind;
1690                 if (unlikely(ind >= qp->sq.max))
1691                         ind -= qp->sq.max;
1692         }
1693
1694 out:
1695         if (likely(nreq)) {
1696                 __be32 doorbell[2];
1697
1698                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1699                                            qp->send_wqe_offset) | f0 | op0);
1700                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1701
1702                 wmb();
1703
1704                 mthca_write64(doorbell,
1705                               dev->kar + MTHCA_SEND_DOORBELL,
1706                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1707         }
1708
1709         qp->sq.next_ind = ind;
1710         qp->sq.head    += nreq;
1711
1712         spin_unlock_irqrestore(&qp->sq.lock, flags);
1713         return err;
1714 }
1715
1716 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1717                              struct ib_recv_wr **bad_wr)
1718 {
1719         struct mthca_dev *dev = to_mdev(ibqp->device);
1720         struct mthca_qp *qp = to_mqp(ibqp);
1721         __be32 doorbell[2];
1722         unsigned long flags;
1723         int err = 0;
1724         int nreq;
1725         int i;
1726         int size;
1727         int size0 = 0;
1728         int ind;
1729         void *wqe;
1730         void *prev_wqe;
1731
1732         spin_lock_irqsave(&qp->rq.lock, flags);
1733
1734         /* XXX check that state is OK to post receive */
1735
1736         ind = qp->rq.next_ind;
1737
1738         for (nreq = 0; wr; wr = wr->next) {
1739                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1740                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1741                                         " %d max, %d nreq)\n", qp->qpn,
1742                                         qp->rq.head, qp->rq.tail,
1743                                         qp->rq.max, nreq);
1744                         err = -ENOMEM;
1745                         *bad_wr = wr;
1746                         goto out;
1747                 }
1748
1749                 wqe = get_recv_wqe(qp, ind);
1750                 prev_wqe = qp->rq.last;
1751                 qp->rq.last = wqe;
1752
1753                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1754                 ((struct mthca_next_seg *) wqe)->ee_nds =
1755                         cpu_to_be32(MTHCA_NEXT_DBD);
1756                 ((struct mthca_next_seg *) wqe)->flags = 0;
1757
1758                 wqe += sizeof (struct mthca_next_seg);
1759                 size = sizeof (struct mthca_next_seg) / 16;
1760
1761                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1762                         err = -EINVAL;
1763                         *bad_wr = wr;
1764                         goto out;
1765                 }
1766
1767                 for (i = 0; i < wr->num_sge; ++i) {
1768                         ((struct mthca_data_seg *) wqe)->byte_count =
1769                                 cpu_to_be32(wr->sg_list[i].length);
1770                         ((struct mthca_data_seg *) wqe)->lkey =
1771                                 cpu_to_be32(wr->sg_list[i].lkey);
1772                         ((struct mthca_data_seg *) wqe)->addr =
1773                                 cpu_to_be64(wr->sg_list[i].addr);
1774                         wqe += sizeof (struct mthca_data_seg);
1775                         size += sizeof (struct mthca_data_seg) / 16;
1776                 }
1777
1778                 qp->wrid[ind] = wr->wr_id;
1779
1780                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1781                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1782                 wmb();
1783                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1784                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1785
1786                 if (!size0)
1787                         size0 = size;
1788
1789                 ++ind;
1790                 if (unlikely(ind >= qp->rq.max))
1791                         ind -= qp->rq.max;
1792
1793                 ++nreq;
1794                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1795                         nreq = 0;
1796
1797                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1798                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1799
1800                         wmb();
1801
1802                         mthca_write64(doorbell,
1803                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1804                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1805
1806                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1807                         size0 = 0;
1808                 }
1809         }
1810
1811 out:
1812         if (likely(nreq)) {
1813                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1814                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1815
1816                 wmb();
1817
1818                 mthca_write64(doorbell,
1819                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1820                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1821         }
1822
1823         qp->rq.next_ind = ind;
1824         qp->rq.head    += nreq;
1825
1826         spin_unlock_irqrestore(&qp->rq.lock, flags);
1827         return err;
1828 }
1829
1830 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1831                           struct ib_send_wr **bad_wr)
1832 {
1833         struct mthca_dev *dev = to_mdev(ibqp->device);
1834         struct mthca_qp *qp = to_mqp(ibqp);
1835         __be32 doorbell[2];
1836         void *wqe;
1837         void *prev_wqe;
1838         unsigned long flags;
1839         int err = 0;
1840         int nreq;
1841         int i;
1842         int size;
1843         int size0 = 0;
1844         u32 f0 = 0;
1845         int ind;
1846         u8 op0 = 0;
1847
1848         spin_lock_irqsave(&qp->sq.lock, flags);
1849
1850         /* XXX check that state is OK to post send */
1851
1852         ind = qp->sq.head & (qp->sq.max - 1);
1853
1854         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1855                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1856                         nreq = 0;
1857
1858                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1859                                                   ((qp->sq.head & 0xffff) << 8) |
1860                                                   f0 | op0);
1861                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1862
1863                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1864                         size0 = 0;
1865
1866                         /*
1867                          * Make sure that descriptors are written before
1868                          * doorbell record.
1869                          */
1870                         wmb();
1871                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1872
1873                         /*
1874                          * Make sure doorbell record is written before we
1875                          * write MMIO send doorbell.
1876                          */
1877                         wmb();
1878                         mthca_write64(doorbell,
1879                                       dev->kar + MTHCA_SEND_DOORBELL,
1880                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1881                 }
1882
1883                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1884                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1885                                         " %d max, %d nreq)\n", qp->qpn,
1886                                         qp->sq.head, qp->sq.tail,
1887                                         qp->sq.max, nreq);
1888                         err = -ENOMEM;
1889                         *bad_wr = wr;
1890                         goto out;
1891                 }
1892
1893                 wqe = get_send_wqe(qp, ind);
1894                 prev_wqe = qp->sq.last;
1895                 qp->sq.last = wqe;
1896
1897                 ((struct mthca_next_seg *) wqe)->flags =
1898                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1899                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1900                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1901                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1902                         cpu_to_be32(1);
1903                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1904                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1905                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1906
1907                 wqe += sizeof (struct mthca_next_seg);
1908                 size = sizeof (struct mthca_next_seg) / 16;
1909
1910                 switch (qp->transport) {
1911                 case RC:
1912                         switch (wr->opcode) {
1913                         case IB_WR_ATOMIC_CMP_AND_SWP:
1914                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1915                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1916                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1917                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1918                                         cpu_to_be32(wr->wr.atomic.rkey);
1919                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1920
1921                                 wqe += sizeof (struct mthca_raddr_seg);
1922
1923                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1924                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1925                                                 cpu_to_be64(wr->wr.atomic.swap);
1926                                         ((struct mthca_atomic_seg *) wqe)->compare =
1927                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1928                                 } else {
1929                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1930                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1931                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1932                                 }
1933
1934                                 wqe += sizeof (struct mthca_atomic_seg);
1935                                 size += (sizeof (struct mthca_raddr_seg) +
1936                                          sizeof (struct mthca_atomic_seg)) / 16;
1937                                 break;
1938
1939                         case IB_WR_RDMA_READ:
1940                         case IB_WR_RDMA_WRITE:
1941                         case IB_WR_RDMA_WRITE_WITH_IMM:
1942                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1943                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1944                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1945                                         cpu_to_be32(wr->wr.rdma.rkey);
1946                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1947                                 wqe += sizeof (struct mthca_raddr_seg);
1948                                 size += sizeof (struct mthca_raddr_seg) / 16;
1949                                 break;
1950
1951                         default:
1952                                 /* No extra segments required for sends */
1953                                 break;
1954                         }
1955
1956                         break;
1957
1958                 case UC:
1959                         switch (wr->opcode) {
1960                         case IB_WR_RDMA_WRITE:
1961                         case IB_WR_RDMA_WRITE_WITH_IMM:
1962                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1963                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1964                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1965                                         cpu_to_be32(wr->wr.rdma.rkey);
1966                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1967                                 wqe += sizeof (struct mthca_raddr_seg);
1968                                 size += sizeof (struct mthca_raddr_seg) / 16;
1969                                 break;
1970
1971                         default:
1972                                 /* No extra segments required for sends */
1973                                 break;
1974                         }
1975
1976                         break;
1977
1978                 case UD:
1979                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1980                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1981                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1982                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1983                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1984                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1985
1986                         wqe += sizeof (struct mthca_arbel_ud_seg);
1987                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1988                         break;
1989
1990                 case MLX:
1991                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1992                                                wqe - sizeof (struct mthca_next_seg),
1993                                                wqe);
1994                         if (err) {
1995                                 *bad_wr = wr;
1996                                 goto out;
1997                         }
1998                         wqe += sizeof (struct mthca_data_seg);
1999                         size += sizeof (struct mthca_data_seg) / 16;
2000                         break;
2001                 }
2002
2003                 if (wr->num_sge > qp->sq.max_gs) {
2004                         mthca_err(dev, "too many gathers\n");
2005                         err = -EINVAL;
2006                         *bad_wr = wr;
2007                         goto out;
2008                 }
2009
2010                 for (i = 0; i < wr->num_sge; ++i) {
2011                         ((struct mthca_data_seg *) wqe)->byte_count =
2012                                 cpu_to_be32(wr->sg_list[i].length);
2013                         ((struct mthca_data_seg *) wqe)->lkey =
2014                                 cpu_to_be32(wr->sg_list[i].lkey);
2015                         ((struct mthca_data_seg *) wqe)->addr =
2016                                 cpu_to_be64(wr->sg_list[i].addr);
2017                         wqe += sizeof (struct mthca_data_seg);
2018                         size += sizeof (struct mthca_data_seg) / 16;
2019                 }
2020
2021                 /* Add one more inline data segment for ICRC */
2022                 if (qp->transport == MLX) {
2023                         ((struct mthca_data_seg *) wqe)->byte_count =
2024                                 cpu_to_be32((1 << 31) | 4);
2025                         ((u32 *) wqe)[1] = 0;
2026                         wqe += sizeof (struct mthca_data_seg);
2027                         size += sizeof (struct mthca_data_seg) / 16;
2028                 }
2029
2030                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2031
2032                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2033                         mthca_err(dev, "opcode invalid\n");
2034                         err = -EINVAL;
2035                         *bad_wr = wr;
2036                         goto out;
2037                 }
2038
2039                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2040                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2041                                      qp->send_wqe_offset) |
2042                                     mthca_opcode[wr->opcode]);
2043                 wmb();
2044                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2045                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2046                                     ((wr->send_flags & IB_SEND_FENCE) ?
2047                                      MTHCA_NEXT_FENCE : 0));
2048
2049                 if (!size0) {
2050                         size0 = size;
2051                         op0   = mthca_opcode[wr->opcode];
2052                 }
2053
2054                 ++ind;
2055                 if (unlikely(ind >= qp->sq.max))
2056                         ind -= qp->sq.max;
2057         }
2058
2059 out:
2060         if (likely(nreq)) {
2061                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2062                                           ((qp->sq.head & 0xffff) << 8) |
2063                                           f0 | op0);
2064                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2065
2066                 qp->sq.head += nreq;
2067
2068                 /*
2069                  * Make sure that descriptors are written before
2070                  * doorbell record.
2071                  */
2072                 wmb();
2073                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2074
2075                 /*
2076                  * Make sure doorbell record is written before we
2077                  * write MMIO send doorbell.
2078                  */
2079                 wmb();
2080                 mthca_write64(doorbell,
2081                               dev->kar + MTHCA_SEND_DOORBELL,
2082                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2083         }
2084
2085         spin_unlock_irqrestore(&qp->sq.lock, flags);
2086         return err;
2087 }
2088
2089 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2090                              struct ib_recv_wr **bad_wr)
2091 {
2092         struct mthca_dev *dev = to_mdev(ibqp->device);
2093         struct mthca_qp *qp = to_mqp(ibqp);
2094         unsigned long flags;
2095         int err = 0;
2096         int nreq;
2097         int ind;
2098         int i;
2099         void *wqe;
2100
2101         spin_lock_irqsave(&qp->rq.lock, flags);
2102
2103         /* XXX check that state is OK to post receive */
2104
2105         ind = qp->rq.head & (qp->rq.max - 1);
2106
2107         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2108                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2109                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2110                                         " %d max, %d nreq)\n", qp->qpn,
2111                                         qp->rq.head, qp->rq.tail,
2112                                         qp->rq.max, nreq);
2113                         err = -ENOMEM;
2114                         *bad_wr = wr;
2115                         goto out;
2116                 }
2117
2118                 wqe = get_recv_wqe(qp, ind);
2119
2120                 ((struct mthca_next_seg *) wqe)->flags = 0;
2121
2122                 wqe += sizeof (struct mthca_next_seg);
2123
2124                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2125                         err = -EINVAL;
2126                         *bad_wr = wr;
2127                         goto out;
2128                 }
2129
2130                 for (i = 0; i < wr->num_sge; ++i) {
2131                         ((struct mthca_data_seg *) wqe)->byte_count =
2132                                 cpu_to_be32(wr->sg_list[i].length);
2133                         ((struct mthca_data_seg *) wqe)->lkey =
2134                                 cpu_to_be32(wr->sg_list[i].lkey);
2135                         ((struct mthca_data_seg *) wqe)->addr =
2136                                 cpu_to_be64(wr->sg_list[i].addr);
2137                         wqe += sizeof (struct mthca_data_seg);
2138                 }
2139
2140                 if (i < qp->rq.max_gs) {
2141                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2142                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2143                         ((struct mthca_data_seg *) wqe)->addr = 0;
2144                 }
2145
2146                 qp->wrid[ind] = wr->wr_id;
2147
2148                 ++ind;
2149                 if (unlikely(ind >= qp->rq.max))
2150                         ind -= qp->rq.max;
2151         }
2152 out:
2153         if (likely(nreq)) {
2154                 qp->rq.head += nreq;
2155
2156                 /*
2157                  * Make sure that descriptors are written before
2158                  * doorbell record.
2159                  */
2160                 wmb();
2161                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2162         }
2163
2164         spin_unlock_irqrestore(&qp->rq.lock, flags);
2165         return err;
2166 }
2167
2168 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2169                         int index, int *dbd, __be32 *new_wqe)
2170 {
2171         struct mthca_next_seg *next;
2172
2173         /*
2174          * For SRQs, all WQEs generate a CQE, so we're always at the
2175          * end of the doorbell chain.
2176          */
2177         if (qp->ibqp.srq) {
2178                 *new_wqe = 0;
2179                 return;
2180         }
2181
2182         if (is_send)
2183                 next = get_send_wqe(qp, index);
2184         else
2185                 next = get_recv_wqe(qp, index);
2186
2187         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2188         if (next->ee_nds & cpu_to_be32(0x3f))
2189                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2190                         (next->ee_nds & cpu_to_be32(0x3f));
2191         else
2192                 *new_wqe = 0;
2193 }
2194
2195 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2196 {
2197         int err;
2198         u8 status;
2199         int i;
2200
2201         spin_lock_init(&dev->qp_table.lock);
2202
2203         /*
2204          * We reserve 2 extra QPs per port for the special QPs.  The
2205          * special QP for port 1 has to be even, so round up.
2206          */
2207         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2208         err = mthca_alloc_init(&dev->qp_table.alloc,
2209                                dev->limits.num_qps,
2210                                (1 << 24) - 1,
2211                                dev->qp_table.sqp_start +
2212                                MTHCA_MAX_PORTS * 2);
2213         if (err)
2214                 return err;
2215
2216         err = mthca_array_init(&dev->qp_table.qp,
2217                                dev->limits.num_qps);
2218         if (err) {
2219                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2220                 return err;
2221         }
2222
2223         for (i = 0; i < 2; ++i) {
2224                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2225                                             dev->qp_table.sqp_start + i * 2,
2226                                             &status);
2227                 if (err)
2228                         goto err_out;
2229                 if (status) {
2230                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2231                                    "status %02x, aborting.\n",
2232                                    status);
2233                         err = -EINVAL;
2234                         goto err_out;
2235                 }
2236         }
2237         return 0;
2238
2239  err_out:
2240         for (i = 0; i < 2; ++i)
2241                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2242
2243         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2244         mthca_alloc_cleanup(&dev->qp_table.alloc);
2245
2246         return err;
2247 }
2248
2249 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2250 {
2251         int i;
2252         u8 status;
2253
2254         for (i = 0; i < 2; ++i)
2255                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2256
2257         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2258         mthca_alloc_cleanup(&dev->qp_table.alloc);
2259 }