]> nv-tegra.nvidia Code Review - linux-2.6.git/blob - drivers/infiniband/hw/ipath/ipath_iba7220.c
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[linux-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba7220.c
1 /*
2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 /*
34  * This file contains all of the code that is specific to the
35  * InfiniPath 7220 chip (except that specific to the SerDes)
36  */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <rdma/ib_verbs.h>
43
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
46 #include "ipath_7220.h"
47
48 static void ipath_setup_7220_setextled(struct ipath_devdata *, u64, u64);
49
50 static unsigned ipath_compat_ddr_negotiate = 1;
51
52 module_param_named(compat_ddr_negotiate, ipath_compat_ddr_negotiate, uint,
53                         S_IWUSR | S_IRUGO);
54 MODULE_PARM_DESC(compat_ddr_negotiate,
55                 "Attempt pre-IBTA 1.2 DDR speed negotiation");
56
57 static unsigned ipath_sdma_fetch_arb = 1;
58 module_param_named(fetch_arb, ipath_sdma_fetch_arb, uint, S_IRUGO);
59 MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration");
60
61 /*
62  * This file contains almost all the chip-specific register information and
63  * access functions for the QLogic InfiniPath 7220 PCI-Express chip, with the
64  * exception of SerDes support, which in in ipath_sd7220.c.
65  *
66  * This lists the InfiniPath registers, in the actual chip layout.
67  * This structure should never be directly accessed.
68  */
69 struct _infinipath_do_not_use_kernel_regs {
70         unsigned long long Revision;
71         unsigned long long Control;
72         unsigned long long PageAlign;
73         unsigned long long PortCnt;
74         unsigned long long DebugPortSelect;
75         unsigned long long DebugSigsIntSel; /* was Reserved0;*/
76         unsigned long long SendRegBase;
77         unsigned long long UserRegBase;
78         unsigned long long CounterRegBase;
79         unsigned long long Scratch;
80         unsigned long long EEPROMAddrCmd; /* was Reserved1; */
81         unsigned long long EEPROMData; /* was Reserved2; */
82         unsigned long long IntBlocked;
83         unsigned long long IntMask;
84         unsigned long long IntStatus;
85         unsigned long long IntClear;
86         unsigned long long ErrorMask;
87         unsigned long long ErrorStatus;
88         unsigned long long ErrorClear;
89         unsigned long long HwErrMask;
90         unsigned long long HwErrStatus;
91         unsigned long long HwErrClear;
92         unsigned long long HwDiagCtrl;
93         unsigned long long MDIO;
94         unsigned long long IBCStatus;
95         unsigned long long IBCCtrl;
96         unsigned long long ExtStatus;
97         unsigned long long ExtCtrl;
98         unsigned long long GPIOOut;
99         unsigned long long GPIOMask;
100         unsigned long long GPIOStatus;
101         unsigned long long GPIOClear;
102         unsigned long long RcvCtrl;
103         unsigned long long RcvBTHQP;
104         unsigned long long RcvHdrSize;
105         unsigned long long RcvHdrCnt;
106         unsigned long long RcvHdrEntSize;
107         unsigned long long RcvTIDBase;
108         unsigned long long RcvTIDCnt;
109         unsigned long long RcvEgrBase;
110         unsigned long long RcvEgrCnt;
111         unsigned long long RcvBufBase;
112         unsigned long long RcvBufSize;
113         unsigned long long RxIntMemBase;
114         unsigned long long RxIntMemSize;
115         unsigned long long RcvPartitionKey;
116         unsigned long long RcvQPMulticastPort;
117         unsigned long long RcvPktLEDCnt;
118         unsigned long long IBCDDRCtrl;
119         unsigned long long HRTBT_GUID;
120         unsigned long long IB_SDTEST_IF_TX;
121         unsigned long long IB_SDTEST_IF_RX;
122         unsigned long long IBCDDRCtrl2;
123         unsigned long long IBCDDRStatus;
124         unsigned long long JIntReload;
125         unsigned long long IBNCModeCtrl;
126         unsigned long long SendCtrl;
127         unsigned long long SendBufBase;
128         unsigned long long SendBufSize;
129         unsigned long long SendBufCnt;
130         unsigned long long SendAvailAddr;
131         unsigned long long TxIntMemBase;
132         unsigned long long TxIntMemSize;
133         unsigned long long SendDmaBase;
134         unsigned long long SendDmaLenGen;
135         unsigned long long SendDmaTail;
136         unsigned long long SendDmaHead;
137         unsigned long long SendDmaHeadAddr;
138         unsigned long long SendDmaBufMask0;
139         unsigned long long SendDmaBufMask1;
140         unsigned long long SendDmaBufMask2;
141         unsigned long long SendDmaStatus;
142         unsigned long long SendBufferError;
143         unsigned long long SendBufferErrorCONT1;
144         unsigned long long SendBufErr2; /* was Reserved6SBE[0/6] */
145         unsigned long long Reserved6L[2];
146         unsigned long long AvailUpdCount;
147         unsigned long long RcvHdrAddr0;
148         unsigned long long RcvHdrAddrs[16]; /* Why enumerate? */
149         unsigned long long Reserved7hdtl; /* Align next to 300 */
150         unsigned long long RcvHdrTailAddr0; /* 300, like others */
151         unsigned long long RcvHdrTailAddrs[16];
152         unsigned long long Reserved9SW[7]; /* was [8]; we have 17 ports */
153         unsigned long long IbsdEpbAccCtl; /* IB Serdes EPB access control */
154         unsigned long long IbsdEpbTransReg; /* IB Serdes EPB Transaction */
155         unsigned long long Reserved10sds; /* was SerdesStatus on */
156         unsigned long long XGXSConfig;
157         unsigned long long IBSerDesCtrl; /* Was IBPLLCfg on Monty */
158         unsigned long long EEPCtlStat; /* for "boot" EEPROM/FLASH */
159         unsigned long long EEPAddrCmd;
160         unsigned long long EEPData;
161         unsigned long long PcieEpbAccCtl;
162         unsigned long long PcieEpbTransCtl;
163         unsigned long long EfuseCtl; /* E-Fuse control */
164         unsigned long long EfuseData[4];
165         unsigned long long ProcMon;
166         /* this chip moves following two from previous 200, 208 */
167         unsigned long long PCIeRBufTestReg0;
168         unsigned long long PCIeRBufTestReg1;
169         /* added for this chip */
170         unsigned long long PCIeRBufTestReg2;
171         unsigned long long PCIeRBufTestReg3;
172         /* added for this chip, debug only */
173         unsigned long long SPC_JTAG_ACCESS_REG;
174         unsigned long long LAControlReg;
175         unsigned long long GPIODebugSelReg;
176         unsigned long long DebugPortValueReg;
177         /* added for this chip, DMA */
178         unsigned long long SendDmaBufUsed[3];
179         unsigned long long SendDmaReqTagUsed;
180         /*
181          * added for this chip, EFUSE: note that these program 64-bit
182          * words 2 and 3 */
183         unsigned long long efuse_pgm_data[2];
184         unsigned long long Reserved11LAalign[10]; /* Skip 4B0..4F8 */
185         /* we have 30 regs for DDS and RXEQ in IB SERDES */
186         unsigned long long SerDesDDSRXEQ[30];
187         unsigned long long Reserved12LAalign[2]; /* Skip 5F0, 5F8 */
188         /* added for LA debug support */
189         unsigned long long LAMemory[32];
190 };
191
192 struct _infinipath_do_not_use_counters {
193         __u64 LBIntCnt;
194         __u64 LBFlowStallCnt;
195         __u64 TxSDmaDescCnt;    /* was Reserved1 */
196         __u64 TxUnsupVLErrCnt;
197         __u64 TxDataPktCnt;
198         __u64 TxFlowPktCnt;
199         __u64 TxDwordCnt;
200         __u64 TxLenErrCnt;
201         __u64 TxMaxMinLenErrCnt;
202         __u64 TxUnderrunCnt;
203         __u64 TxFlowStallCnt;
204         __u64 TxDroppedPktCnt;
205         __u64 RxDroppedPktCnt;
206         __u64 RxDataPktCnt;
207         __u64 RxFlowPktCnt;
208         __u64 RxDwordCnt;
209         __u64 RxLenErrCnt;
210         __u64 RxMaxMinLenErrCnt;
211         __u64 RxICRCErrCnt;
212         __u64 RxVCRCErrCnt;
213         __u64 RxFlowCtrlErrCnt;
214         __u64 RxBadFormatCnt;
215         __u64 RxLinkProblemCnt;
216         __u64 RxEBPCnt;
217         __u64 RxLPCRCErrCnt;
218         __u64 RxBufOvflCnt;
219         __u64 RxTIDFullErrCnt;
220         __u64 RxTIDValidErrCnt;
221         __u64 RxPKeyMismatchCnt;
222         __u64 RxP0HdrEgrOvflCnt;
223         __u64 RxP1HdrEgrOvflCnt;
224         __u64 RxP2HdrEgrOvflCnt;
225         __u64 RxP3HdrEgrOvflCnt;
226         __u64 RxP4HdrEgrOvflCnt;
227         __u64 RxP5HdrEgrOvflCnt;
228         __u64 RxP6HdrEgrOvflCnt;
229         __u64 RxP7HdrEgrOvflCnt;
230         __u64 RxP8HdrEgrOvflCnt;
231         __u64 RxP9HdrEgrOvflCnt;        /* was Reserved6 */
232         __u64 RxP10HdrEgrOvflCnt;       /* was Reserved7 */
233         __u64 RxP11HdrEgrOvflCnt;       /* new for IBA7220 */
234         __u64 RxP12HdrEgrOvflCnt;       /* new for IBA7220 */
235         __u64 RxP13HdrEgrOvflCnt;       /* new for IBA7220 */
236         __u64 RxP14HdrEgrOvflCnt;       /* new for IBA7220 */
237         __u64 RxP15HdrEgrOvflCnt;       /* new for IBA7220 */
238         __u64 RxP16HdrEgrOvflCnt;       /* new for IBA7220 */
239         __u64 IBStatusChangeCnt;
240         __u64 IBLinkErrRecoveryCnt;
241         __u64 IBLinkDownedCnt;
242         __u64 IBSymbolErrCnt;
243         /* The following are new for IBA7220 */
244         __u64 RxVL15DroppedPktCnt;
245         __u64 RxOtherLocalPhyErrCnt;
246         __u64 PcieRetryBufDiagQwordCnt;
247         __u64 ExcessBufferOvflCnt;
248         __u64 LocalLinkIntegrityErrCnt;
249         __u64 RxVlErrCnt;
250         __u64 RxDlidFltrCnt;
251         __u64 Reserved8[7];
252         __u64 PSStat;
253         __u64 PSStart;
254         __u64 PSInterval;
255         __u64 PSRcvDataCount;
256         __u64 PSRcvPktsCount;
257         __u64 PSXmitDataCount;
258         __u64 PSXmitPktsCount;
259         __u64 PSXmitWaitCount;
260 };
261
262 #define IPATH_KREG_OFFSET(field) (offsetof( \
263         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
264 #define IPATH_CREG_OFFSET(field) (offsetof( \
265         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
266
267 static const struct ipath_kregs ipath_7220_kregs = {
268         .kr_control = IPATH_KREG_OFFSET(Control),
269         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
270         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
271         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
272         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
273         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
274         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
275         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
276         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
277         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
278         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
279         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
280         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
281         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
282         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
283         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
284         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
285         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
286         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
287         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
288         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
289         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
290         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
291         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
292         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
293         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
294         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
295         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
296         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
297         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
298         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
299         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
300         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
301         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
302         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
303         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
304         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
305         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
306         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
307         .kr_revision = IPATH_KREG_OFFSET(Revision),
308         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
309         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
310         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
311         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendAvailAddr),
312         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendBufBase),
313         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendBufCnt),
314         .kr_sendpiosize = IPATH_KREG_OFFSET(SendBufSize),
315         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
316         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
317         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
318         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
319
320         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
321
322         /* send dma related regs */
323         .kr_senddmabase = IPATH_KREG_OFFSET(SendDmaBase),
324         .kr_senddmalengen = IPATH_KREG_OFFSET(SendDmaLenGen),
325         .kr_senddmatail = IPATH_KREG_OFFSET(SendDmaTail),
326         .kr_senddmahead = IPATH_KREG_OFFSET(SendDmaHead),
327         .kr_senddmaheadaddr = IPATH_KREG_OFFSET(SendDmaHeadAddr),
328         .kr_senddmabufmask0 = IPATH_KREG_OFFSET(SendDmaBufMask0),
329         .kr_senddmabufmask1 = IPATH_KREG_OFFSET(SendDmaBufMask1),
330         .kr_senddmabufmask2 = IPATH_KREG_OFFSET(SendDmaBufMask2),
331         .kr_senddmastatus = IPATH_KREG_OFFSET(SendDmaStatus),
332
333         /* SerDes related regs */
334         .kr_ibserdesctrl = IPATH_KREG_OFFSET(IBSerDesCtrl),
335         .kr_ib_epbacc = IPATH_KREG_OFFSET(IbsdEpbAccCtl),
336         .kr_ib_epbtrans = IPATH_KREG_OFFSET(IbsdEpbTransReg),
337         .kr_pcie_epbacc = IPATH_KREG_OFFSET(PcieEpbAccCtl),
338         .kr_pcie_epbtrans = IPATH_KREG_OFFSET(PcieEpbTransCtl),
339         .kr_ib_ddsrxeq = IPATH_KREG_OFFSET(SerDesDDSRXEQ),
340
341         /*
342          * These should not be used directly via ipath_read_kreg64(),
343          * use them with ipath_read_kreg64_port()
344          */
345         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
346         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
347
348         /*
349          * The rcvpktled register controls one of the debug port signals, so
350          * a packet activity LED can be connected to it.
351          */
352         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
353         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
354         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
355
356         .kr_hrtbt_guid = IPATH_KREG_OFFSET(HRTBT_GUID),
357         .kr_ibcddrctrl = IPATH_KREG_OFFSET(IBCDDRCtrl),
358         .kr_ibcddrstatus = IPATH_KREG_OFFSET(IBCDDRStatus),
359         .kr_jintreload = IPATH_KREG_OFFSET(JIntReload)
360 };
361
362 static const struct ipath_cregs ipath_7220_cregs = {
363         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
364         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
365         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
366         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
367         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
368         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
369         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
370         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
371         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
372         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
373         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
374         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
375         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
376         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
377         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
378         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
379         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
380         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
381         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
382         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
383         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
384         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
385         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
386         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
387         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
388         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
389         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
390         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
391         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
392         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
393         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
394         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
395         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt),
396         .cr_vl15droppedpktcnt = IPATH_CREG_OFFSET(RxVL15DroppedPktCnt),
397         .cr_rxotherlocalphyerrcnt =
398                 IPATH_CREG_OFFSET(RxOtherLocalPhyErrCnt),
399         .cr_excessbufferovflcnt = IPATH_CREG_OFFSET(ExcessBufferOvflCnt),
400         .cr_locallinkintegrityerrcnt =
401                 IPATH_CREG_OFFSET(LocalLinkIntegrityErrCnt),
402         .cr_rxvlerrcnt = IPATH_CREG_OFFSET(RxVlErrCnt),
403         .cr_rxdlidfltrcnt = IPATH_CREG_OFFSET(RxDlidFltrCnt),
404         .cr_psstat = IPATH_CREG_OFFSET(PSStat),
405         .cr_psstart = IPATH_CREG_OFFSET(PSStart),
406         .cr_psinterval = IPATH_CREG_OFFSET(PSInterval),
407         .cr_psrcvdatacount = IPATH_CREG_OFFSET(PSRcvDataCount),
408         .cr_psrcvpktscount = IPATH_CREG_OFFSET(PSRcvPktsCount),
409         .cr_psxmitdatacount = IPATH_CREG_OFFSET(PSXmitDataCount),
410         .cr_psxmitpktscount = IPATH_CREG_OFFSET(PSXmitPktsCount),
411         .cr_psxmitwaitcount = IPATH_CREG_OFFSET(PSXmitWaitCount),
412 };
413
414 /* kr_control bits */
415 #define INFINIPATH_C_RESET (1U<<7)
416
417 /* kr_intstatus, kr_intclear, kr_intmask bits */
418 #define INFINIPATH_I_RCVURG_MASK ((1ULL<<17)-1)
419 #define INFINIPATH_I_RCVURG_SHIFT 32
420 #define INFINIPATH_I_RCVAVAIL_MASK ((1ULL<<17)-1)
421 #define INFINIPATH_I_RCVAVAIL_SHIFT 0
422 #define INFINIPATH_I_SERDESTRIMDONE (1ULL<<27)
423
424 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
425 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x00000000000000ffULL
426 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
427 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
428 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
429 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
430 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
431 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
432 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
433 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
434 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
435 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
436 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
437 /* specific to this chip */
438 #define INFINIPATH_HWE_PCIECPLDATAQUEUEERR         0x0000000000000040ULL
439 #define INFINIPATH_HWE_PCIECPLHDRQUEUEERR          0x0000000000000080ULL
440 #define INFINIPATH_HWE_SDMAMEMREADERR              0x0000000010000000ULL
441 #define INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED         0x2000000000000000ULL
442 #define INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT   0x0100000000000000ULL
443 #define INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT   0x0200000000000000ULL
444 #define INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT   0x0400000000000000ULL
445 #define INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT   0x0800000000000000ULL
446 #define INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR      0x0000008000000000ULL
447 #define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR       0x0000004000000000ULL
448 #define INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
449 #define INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
450
451 #define IBA7220_IBCS_LINKTRAININGSTATE_MASK 0x1F
452 #define IBA7220_IBCS_LINKSTATE_SHIFT 5
453 #define IBA7220_IBCS_LINKSPEED_SHIFT 8
454 #define IBA7220_IBCS_LINKWIDTH_SHIFT 9
455
456 #define IBA7220_IBCC_LINKINITCMD_MASK 0x7ULL
457 #define IBA7220_IBCC_LINKCMD_SHIFT 19
458 #define IBA7220_IBCC_MAXPKTLEN_SHIFT 21
459
460 /* kr_ibcddrctrl bits */
461 #define IBA7220_IBC_DLIDLMC_MASK        0xFFFFFFFFUL
462 #define IBA7220_IBC_DLIDLMC_SHIFT       32
463 #define IBA7220_IBC_HRTBT_MASK  3
464 #define IBA7220_IBC_HRTBT_SHIFT 16
465 #define IBA7220_IBC_HRTBT_ENB   0x10000UL
466 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
467 #define IBA7220_IBC_LREV_MASK   1
468 #define IBA7220_IBC_LREV_SHIFT  8
469 #define IBA7220_IBC_RXPOL_MASK  1
470 #define IBA7220_IBC_RXPOL_SHIFT 7
471 #define IBA7220_IBC_WIDTH_SHIFT 5
472 #define IBA7220_IBC_WIDTH_MASK  0x3
473 #define IBA7220_IBC_WIDTH_1X_ONLY       (0<<IBA7220_IBC_WIDTH_SHIFT)
474 #define IBA7220_IBC_WIDTH_4X_ONLY       (1<<IBA7220_IBC_WIDTH_SHIFT)
475 #define IBA7220_IBC_WIDTH_AUTONEG       (2<<IBA7220_IBC_WIDTH_SHIFT)
476 #define IBA7220_IBC_SPEED_AUTONEG       (1<<1)
477 #define IBA7220_IBC_SPEED_SDR           (1<<2)
478 #define IBA7220_IBC_SPEED_DDR           (1<<3)
479 #define IBA7220_IBC_SPEED_AUTONEG_MASK  (0x7<<1)
480 #define IBA7220_IBC_IBTA_1_2_MASK       (1)
481
482 /* kr_ibcddrstatus */
483 /* link latency shift is 0, don't bother defining */
484 #define IBA7220_DDRSTAT_LINKLAT_MASK    0x3ffffff
485
486 /* kr_extstatus bits */
487 #define INFINIPATH_EXTS_FREQSEL 0x2
488 #define INFINIPATH_EXTS_SERDESSEL 0x4
489 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
490 #define INFINIPATH_EXTS_MEMBIST_DISABLED    0x0000000000008000
491
492 /* kr_xgxsconfig bits */
493 #define INFINIPATH_XGXS_RESET          0x5ULL
494 #define INFINIPATH_XGXS_FC_SAFE        (1ULL<<63)
495
496 /* kr_rcvpktledcnt */
497 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
498 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
499
500 #define _IPATH_GPIO_SDA_NUM 1
501 #define _IPATH_GPIO_SCL_NUM 0
502
503 #define IPATH_GPIO_SDA (1ULL << \
504         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
505 #define IPATH_GPIO_SCL (1ULL << \
506         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
507
508 #define IBA7220_R_INTRAVAIL_SHIFT 17
509 #define IBA7220_R_TAILUPD_SHIFT 35
510 #define IBA7220_R_PORTCFG_SHIFT 36
511
512 #define INFINIPATH_JINT_PACKETSHIFT 16
513 #define INFINIPATH_JINT_DEFAULT_IDLE_TICKS  0
514 #define INFINIPATH_JINT_DEFAULT_MAX_PACKETS 0
515
516 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
517
518 /*
519  * the size bits give us 2^N, in KB units.  0 marks as invalid,
520  * and 7 is reserved.  We currently use only 2KB and 4KB
521  */
522 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
523 #define IBA7220_TID_SZ_2K (1UL<<IBA7220_TID_SZ_SHIFT) /* 2KB */
524 #define IBA7220_TID_SZ_4K (2UL<<IBA7220_TID_SZ_SHIFT) /* 4KB */
525 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
526
527 #define IPATH_AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
528
529 static char int_type[16] = "auto";
530 module_param_string(interrupt_type, int_type, sizeof(int_type), 0444);
531 MODULE_PARM_DESC(int_type, " interrupt_type=auto|force_msi|force_intx");
532
533 /* packet rate matching delay; chip has support */
534 static u8 rate_to_delay[2][2] = {
535         /* 1x, 4x */
536         {   8, 2 }, /* SDR */
537         {   4, 1 }  /* DDR */
538 };
539
540 /* 7220 specific hardware errors... */
541 static const struct ipath_hwerror_msgs ipath_7220_hwerror_msgs[] = {
542         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
543         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
544         /*
545          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
546          * parity or memory parity error failures, because most likely we
547          * won't be able to talk to the core of the chip.  Nonetheless, we
548          * might see them, if they are in parts of the PCIe core that aren't
549          * essential.
550          */
551         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
552         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
553         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
554         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
555         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
556         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
557         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
558         INFINIPATH_HWE_MSG(PCIECPLDATAQUEUEERR, "PCIe cpl header queue"),
559         INFINIPATH_HWE_MSG(PCIECPLHDRQUEUEERR, "PCIe cpl data queue"),
560         INFINIPATH_HWE_MSG(SDMAMEMREADERR, "Send DMA memory read"),
561         INFINIPATH_HWE_MSG(CLK_UC_PLLNOTLOCKED, "uC PLL clock not locked"),
562         INFINIPATH_HWE_MSG(PCIESERDESQ0PCLKNOTDETECT,
563                 "PCIe serdes Q0 no clock"),
564         INFINIPATH_HWE_MSG(PCIESERDESQ1PCLKNOTDETECT,
565                 "PCIe serdes Q1 no clock"),
566         INFINIPATH_HWE_MSG(PCIESERDESQ2PCLKNOTDETECT,
567                 "PCIe serdes Q2 no clock"),
568         INFINIPATH_HWE_MSG(PCIESERDESQ3PCLKNOTDETECT,
569                 "PCIe serdes Q3 no clock"),
570         INFINIPATH_HWE_MSG(DDSRXEQMEMORYPARITYERR,
571                 "DDS RXEQ memory parity"),
572         INFINIPATH_HWE_MSG(IB_UC_MEMORYPARITYERR, "IB uC memory parity"),
573         INFINIPATH_HWE_MSG(PCIE_UC_OCT0MEMORYPARITYERR,
574                 "PCIe uC oct0 memory parity"),
575         INFINIPATH_HWE_MSG(PCIE_UC_OCT1MEMORYPARITYERR,
576                 "PCIe uC oct1 memory parity"),
577 };
578
579 static void autoneg_work(struct work_struct *);
580
581 /*
582  * the offset is different for different configured port numbers, since
583  * port0 is fixed in size, but others can vary.   Make it a function to
584  * make the issue more obvious.
585 */
586 static inline u32 port_egrtid_idx(struct ipath_devdata *dd, unsigned port)
587 {
588          return port ? dd->ipath_p0_rcvegrcnt +
589                  (port-1) * dd->ipath_rcvegrcnt : 0;
590 }
591
592 static void ipath_7220_txe_recover(struct ipath_devdata *dd)
593 {
594         ++ipath_stats.sps_txeparity;
595
596         dev_info(&dd->pcidev->dev,
597                 "Recovering from TXE PIO parity error\n");
598         ipath_disarm_senderrbufs(dd);
599 }
600
601
602 /**
603  * ipath_7220_handle_hwerrors - display hardware errors.
604  * @dd: the infinipath device
605  * @msg: the output buffer
606  * @msgl: the size of the output buffer
607  *
608  * Use same msg buffer as regular errors to avoid excessive stack
609  * use.  Most hardware errors are catastrophic, but for right now,
610  * we'll print them and continue.  We reuse the same message buffer as
611  * ipath_handle_errors() to avoid excessive stack usage.
612  */
613 static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
614                                        size_t msgl)
615 {
616         ipath_err_t hwerrs;
617         u32 bits, ctrl;
618         int isfatal = 0;
619         char bitsmsg[64];
620         int log_idx;
621
622         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
623         if (!hwerrs) {
624                 /*
625                  * better than printing cofusing messages
626                  * This seems to be related to clearing the crc error, or
627                  * the pll error during init.
628                  */
629                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
630                 goto bail;
631         } else if (hwerrs == ~0ULL) {
632                 ipath_dev_err(dd, "Read of hardware error status failed "
633                               "(all bits set); ignoring\n");
634                 goto bail;
635         }
636         ipath_stats.sps_hwerrs++;
637
638         /*
639          * Always clear the error status register, except MEMBISTFAIL,
640          * regardless of whether we continue or stop using the chip.
641          * We want that set so we know it failed, even across driver reload.
642          * We'll still ignore it in the hwerrmask.  We do this partly for
643          * diagnostics, but also for support.
644          */
645         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
646                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
647
648         hwerrs &= dd->ipath_hwerrmask;
649
650         /* We log some errors to EEPROM, check if we have any of those. */
651         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
652                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
653                         ipath_inc_eeprom_err(dd, log_idx, 1);
654         /*
655          * Make sure we get this much out, unless told to be quiet,
656          * or it's occurred within the last 5 seconds.
657          */
658         if ((hwerrs & ~(dd->ipath_lasthwerror |
659                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
660                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
661                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
662             (ipath_debug & __IPATH_VERBDBG))
663                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
664                          "(cleared)\n", (unsigned long long) hwerrs);
665         dd->ipath_lasthwerror |= hwerrs;
666
667         if (hwerrs & ~dd->ipath_hwe_bitsextant)
668                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
669                               "%llx set\n", (unsigned long long)
670                               (hwerrs & ~dd->ipath_hwe_bitsextant));
671
672         if (hwerrs & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR)
673                 ipath_sd7220_clr_ibpar(dd);
674
675         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
676         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
677                 /*
678                  * Parity errors in send memory are recoverable by h/w
679                  * just do housekeeping, exit freeze mode and continue.
680                  */
681                 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
682                                INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
683                               << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
684                         ipath_7220_txe_recover(dd);
685                         hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
686                                      INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
687                                     << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
688                 }
689                 if (hwerrs) {
690                         /*
691                          * If any set that we aren't ignoring only make the
692                          * complaint once, in case it's stuck or recurring,
693                          * and we get here multiple times
694                          * Force link down, so switch knows, and
695                          * LEDs are turned off.
696                          */
697                         if (dd->ipath_flags & IPATH_INITTED) {
698                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
699                                 ipath_setup_7220_setextled(dd,
700                                         INFINIPATH_IBCS_L_STATE_DOWN,
701                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
702                                 ipath_dev_err(dd, "Fatal Hardware Error "
703                                               "(freeze mode), no longer"
704                                               " usable, SN %.16s\n",
705                                                   dd->ipath_serial);
706                                 isfatal = 1;
707                         }
708                         /*
709                          * Mark as having had an error for driver, and also
710                          * for /sys and status word mapped to user programs.
711                          * This marks unit as not usable, until reset.
712                          */
713                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
714                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
715                         dd->ipath_flags &= ~IPATH_INITTED;
716                 } else {
717                         ipath_dbg("Clearing freezemode on ignored or "
718                                 "recovered hardware error\n");
719                         ipath_clear_freeze(dd);
720                 }
721         }
722
723         *msg = '\0';
724
725         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
726                 strlcat(msg, "[Memory BIST test failed, "
727                         "InfiniPath hardware unusable]", msgl);
728                 /* ignore from now on, so disable until driver reloaded */
729                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
730                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
731                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
732                                  dd->ipath_hwerrmask);
733         }
734
735         ipath_format_hwerrors(hwerrs,
736                               ipath_7220_hwerror_msgs,
737                               ARRAY_SIZE(ipath_7220_hwerror_msgs),
738                               msg, msgl);
739
740         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
741                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
742                 bits = (u32) ((hwerrs >>
743                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
744                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
745                 snprintf(bitsmsg, sizeof bitsmsg,
746                          "[PCIe Mem Parity Errs %x] ", bits);
747                 strlcat(msg, bitsmsg, msgl);
748         }
749
750 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
751                          INFINIPATH_HWE_COREPLL_RFSLIP)
752
753         if (hwerrs & _IPATH_PLL_FAIL) {
754                 snprintf(bitsmsg, sizeof bitsmsg,
755                          "[PLL failed (%llx), InfiniPath hardware unusable]",
756                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
757                 strlcat(msg, bitsmsg, msgl);
758                 /* ignore from now on, so disable until driver reloaded */
759                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
760                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
761                                  dd->ipath_hwerrmask);
762         }
763
764         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
765                 /*
766                  * If it occurs, it is left masked since the eternal
767                  * interface is unused.
768                  */
769                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
770                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
771                                  dd->ipath_hwerrmask);
772         }
773
774         ipath_dev_err(dd, "%s hardware error\n", msg);
775         /*
776          * For /sys status file. if no trailing } is copied, we'll
777          * know it was truncated.
778          */
779         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
780                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
781                          "{%s}", msg);
782 bail:;
783 }
784
785 /**
786  * ipath_7220_boardname - fill in the board name
787  * @dd: the infinipath device
788  * @name: the output buffer
789  * @namelen: the size of the output buffer
790  *
791  * info is based on the board revision register
792  */
793 static int ipath_7220_boardname(struct ipath_devdata *dd, char *name,
794         size_t namelen)
795 {
796         char *n = NULL;
797         u8 boardrev = dd->ipath_boardrev;
798         int ret;
799
800         if (boardrev == 15) {
801                 /*
802                  * Emulator sometimes comes up all-ones, rather than zero.
803                  */
804                 boardrev = 0;
805                 dd->ipath_boardrev = boardrev;
806         }
807         switch (boardrev) {
808         case 0:
809                 n = "InfiniPath_7220_Emulation";
810                 break;
811         case 1:
812                 n = "InfiniPath_QLE7240";
813                 break;
814         case 2:
815                 n = "InfiniPath_QLE7280";
816                 break;
817         case 3:
818                 n = "InfiniPath_QLE7242";
819                 break;
820         case 4:
821                 n = "InfiniPath_QEM7240";
822                 break;
823         case 5:
824                 n = "InfiniPath_QMI7240";
825                 break;
826         case 6:
827                 n = "InfiniPath_QMI7264";
828                 break;
829         case 7:
830                 n = "InfiniPath_QMH7240";
831                 break;
832         case 8:
833                 n = "InfiniPath_QME7240";
834                 break;
835         case 9:
836                 n = "InfiniPath_QLE7250";
837                 break;
838         case 10:
839                 n = "InfiniPath_QLE7290";
840                 break;
841         case 11:
842                 n = "InfiniPath_QEM7250";
843                 break;
844         case 12:
845                 n = "InfiniPath_QLE-Bringup";
846                 break;
847         default:
848                 ipath_dev_err(dd,
849                               "Don't yet know about board with ID %u\n",
850                               boardrev);
851                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
852                          boardrev);
853                 break;
854         }
855         if (n)
856                 snprintf(name, namelen, "%s", n);
857
858         if (dd->ipath_majrev != 5 || !dd->ipath_minrev ||
859                 dd->ipath_minrev > 2) {
860                 ipath_dev_err(dd, "Unsupported InfiniPath hardware "
861                               "revision %u.%u!\n",
862                               dd->ipath_majrev, dd->ipath_minrev);
863                 ret = 1;
864         } else if (dd->ipath_minrev == 1 &&
865                 !(dd->ipath_flags & IPATH_INITTED)) {
866                 /* Rev1 chips are prototype. Complain at init, but allow use */
867                 ipath_dev_err(dd, "Unsupported hardware "
868                               "revision %u.%u, Contact support@qlogic.com\n",
869                               dd->ipath_majrev, dd->ipath_minrev);
870                 ret = 0;
871         } else
872                 ret = 0;
873
874         /*
875          * Set here not in ipath_init_*_funcs because we have to do
876          * it after we can read chip registers.
877          */
878         dd->ipath_ureg_align = 0x10000;  /* 64KB alignment */
879
880         return ret;
881 }
882
883 /**
884  * ipath_7220_init_hwerrors - enable hardware errors
885  * @dd: the infinipath device
886  *
887  * now that we have finished initializing everything that might reasonably
888  * cause a hardware error, and cleared those errors bits as they occur,
889  * we can enable hardware errors in the mask (potentially enabling
890  * freeze mode), and enable hardware errors as errors (along with
891  * everything else) in errormask
892  */
893 static void ipath_7220_init_hwerrors(struct ipath_devdata *dd)
894 {
895         ipath_err_t val;
896         u64 extsval;
897
898         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
899
900         if (!(extsval & (INFINIPATH_EXTS_MEMBIST_ENDTEST |
901                         INFINIPATH_EXTS_MEMBIST_DISABLED)))
902                 ipath_dev_err(dd, "MemBIST did not complete!\n");
903         if (extsval & INFINIPATH_EXTS_MEMBIST_DISABLED)
904                 dev_info(&dd->pcidev->dev, "MemBIST is disabled.\n");
905
906         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
907
908         if (!dd->ipath_boardrev)        /* no PLL for Emulator */
909                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
910
911         if (dd->ipath_minrev == 1)
912                 val &= ~(1ULL << 42); /* TXE LaunchFIFO Parity rev1 issue */
913
914         val &= ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
915         dd->ipath_hwerrmask = val;
916
917         /*
918          * special trigger "error" is for debugging purposes. It
919          * works around a processor/chipset problem.  The error
920          * interrupt allows us to count occurrences, but we don't
921          * want to pay the overhead for normal use.  Emulation only
922          */
923         if (!dd->ipath_boardrev)
924                 dd->ipath_maskederrs = INFINIPATH_E_SENDSPECIALTRIGGER;
925 }
926
927 /*
928  * All detailed interaction with the SerDes has been moved to ipath_sd7220.c
929  *
930  * The portion of IBA7220-specific bringup_serdes() that actually deals with
931  * registers and memory within the SerDes itself is ipath_sd7220_init().
932  */
933
934 /**
935  * ipath_7220_bringup_serdes - bring up the serdes
936  * @dd: the infinipath device
937  */
938 static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
939 {
940         int ret = 0;
941         u64 val, prev_val, guid;
942         int was_reset;          /* Note whether uC was reset */
943
944         ipath_dbg("Trying to bringup serdes\n");
945
946         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
947             INFINIPATH_HWE_SERDESPLLFAILED) {
948                 ipath_dbg("At start, serdes PLL failed bit set "
949                           "in hwerrstatus, clearing and continuing\n");
950                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
951                                  INFINIPATH_HWE_SERDESPLLFAILED);
952         }
953
954         if (!dd->ipath_ibcddrctrl) {
955                 /* not on re-init after reset */
956                 dd->ipath_ibcddrctrl =
957                         ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrctrl);
958
959                 if (dd->ipath_link_speed_enabled ==
960                         (IPATH_IB_SDR | IPATH_IB_DDR))
961                         dd->ipath_ibcddrctrl |=
962                                 IBA7220_IBC_SPEED_AUTONEG_MASK |
963                                 IBA7220_IBC_IBTA_1_2_MASK;
964                 else
965                         dd->ipath_ibcddrctrl |=
966                                 dd->ipath_link_speed_enabled == IPATH_IB_DDR
967                                 ?  IBA7220_IBC_SPEED_DDR :
968                                 IBA7220_IBC_SPEED_SDR;
969                 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
970                         IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X))
971                         dd->ipath_ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
972                 else
973                         dd->ipath_ibcddrctrl |=
974                                 dd->ipath_link_width_enabled == IB_WIDTH_4X
975                                 ? IBA7220_IBC_WIDTH_4X_ONLY :
976                                 IBA7220_IBC_WIDTH_1X_ONLY;
977
978                 /* always enable these on driver reload, not sticky */
979                 dd->ipath_ibcddrctrl |=
980                         IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
981                 dd->ipath_ibcddrctrl |=
982                         IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
983                 /*
984                  * automatic lane reversal detection for receive
985                  * doesn't work correctly in rev 1, so disable it
986                  * on that rev, otherwise enable (disabling not
987                  * sticky across reload for >rev1)
988                  */
989                 if (dd->ipath_minrev == 1)
990                         dd->ipath_ibcddrctrl &=
991                         ~IBA7220_IBC_LANE_REV_SUPPORTED;
992                 else
993                         dd->ipath_ibcddrctrl |=
994                                 IBA7220_IBC_LANE_REV_SUPPORTED;
995         }
996
997         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
998                         dd->ipath_ibcddrctrl);
999
1000         ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl), 0Ull);
1001
1002         /* IBA7220 has SERDES MPU reset in D0 of what _was_ IBPLLCfg */
1003         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1004         /* remember if uC was in Reset or not, for dactrim */
1005         was_reset = (val & 1);
1006         ipath_cdbg(VERBOSE, "IBReset %s xgxsconfig %llx\n",
1007                    was_reset ? "Asserted" : "Negated", (unsigned long long)
1008                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1009
1010         if (dd->ipath_boardrev) {
1011                 /*
1012                  * Hardware is not emulator, and may have been reset. Init it.
1013                  * Below will release reset, but needs to know if chip was
1014                  * originally in reset, to only trim DACs on first time
1015                  * after chip reset or powercycle (not driver reload)
1016                  */
1017                 ret = ipath_sd7220_init(dd, was_reset);
1018         }
1019
1020         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1021         prev_val = val;
1022         val |= INFINIPATH_XGXS_FC_SAFE;
1023         if (val != prev_val) {
1024                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1025                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1026         }
1027         if (val & INFINIPATH_XGXS_RESET)
1028                 val &= ~INFINIPATH_XGXS_RESET;
1029         if (val != prev_val)
1030                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1031
1032         ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
1033                    (unsigned long long)
1034                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
1035                    (unsigned long long) prev_val);
1036
1037         guid = be64_to_cpu(dd->ipath_guid);
1038
1039         if (!guid) {
1040                 /* have to have something, so use likely unique tsc */
1041                 guid = get_cycles();
1042                 ipath_dbg("No GUID for heartbeat, faking %llx\n",
1043                         (unsigned long long)guid);
1044         } else
1045                 ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n",
1046                         (unsigned long long) guid);
1047         ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
1048         return ret;
1049 }
1050
1051 static void ipath_7220_config_jint(struct ipath_devdata *dd,
1052                                    u16 idle_ticks, u16 max_packets)
1053 {
1054
1055         /*
1056          * We can request a receive interrupt for 1 or more packets
1057          * from current offset.
1058          */
1059         if (idle_ticks == 0 || max_packets == 0)
1060                 /* interrupt after one packet if no mitigation */
1061                 dd->ipath_rhdrhead_intr_off =
1062                         1ULL << IBA7220_HDRHEAD_PKTINT_SHIFT;
1063         else
1064                 /* Turn off RcvHdrHead interrupts if using mitigation */
1065                 dd->ipath_rhdrhead_intr_off = 0ULL;
1066
1067         /* refresh kernel RcvHdrHead registers... */
1068         ipath_write_ureg(dd, ur_rcvhdrhead,
1069                          dd->ipath_rhdrhead_intr_off |
1070                          dd->ipath_pd[0]->port_head, 0);
1071
1072         dd->ipath_jint_max_packets = max_packets;
1073         dd->ipath_jint_idle_ticks = idle_ticks;
1074         ipath_write_kreg(dd, dd->ipath_kregs->kr_jintreload,
1075                          ((u64) max_packets << INFINIPATH_JINT_PACKETSHIFT) |
1076                          idle_ticks);
1077 }
1078
1079 /**
1080  * ipath_7220_quiet_serdes - set serdes to txidle
1081  * @dd: the infinipath device
1082  * Called when driver is being unloaded
1083  */
1084 static void ipath_7220_quiet_serdes(struct ipath_devdata *dd)
1085 {
1086         u64 val;
1087         dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
1088         wake_up(&dd->ipath_autoneg_wait);
1089         cancel_delayed_work(&dd->ipath_autoneg_work);
1090         flush_scheduled_work();
1091         ipath_shutdown_relock_poll(dd);
1092         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1093         val |= INFINIPATH_XGXS_RESET;
1094         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1095 }
1096
1097 static int ipath_7220_intconfig(struct ipath_devdata *dd)
1098 {
1099         ipath_7220_config_jint(dd, dd->ipath_jint_idle_ticks,
1100                                dd->ipath_jint_max_packets);
1101         return 0;
1102 }
1103
1104 /**
1105  * ipath_setup_7220_setextled - set the state of the two external LEDs
1106  * @dd: the infinipath device
1107  * @lst: the L state
1108  * @ltst: the LT state
1109  *
1110  * These LEDs indicate the physical and logical state of IB link.
1111  * For this chip (at least with recommended board pinouts), LED1
1112  * is Yellow (logical state) and LED2 is Green (physical state),
1113  *
1114  * Note:  We try to match the Mellanox HCA LED behavior as best
1115  * we can.  Green indicates physical link state is OK (something is
1116  * plugged in, and we can train).
1117  * Amber indicates the link is logically up (ACTIVE).
1118  * Mellanox further blinks the amber LED to indicate data packet
1119  * activity, but we have no hardware support for that, so it would
1120  * require waking up every 10-20 msecs and checking the counters
1121  * on the chip, and then turning the LED off if appropriate.  That's
1122  * visible overhead, so not something we will do.
1123  *
1124  */
1125 static void ipath_setup_7220_setextled(struct ipath_devdata *dd, u64 lst,
1126                                        u64 ltst)
1127 {
1128         u64 extctl, ledblink = 0;
1129         unsigned long flags = 0;
1130
1131         /* the diags use the LED to indicate diag info, so we leave
1132          * the external LED alone when the diags are running */
1133         if (ipath_diag_inuse)
1134                 return;
1135
1136         /* Allow override of LED display for, e.g. Locating system in rack */
1137         if (dd->ipath_led_override) {
1138                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1139                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1140                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1141                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1142                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1143                         : INFINIPATH_IBCS_L_STATE_DOWN;
1144         }
1145
1146         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1147         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1148                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
1149         if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) {
1150                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1151                 /*
1152                  * counts are in chip clock (4ns) periods.
1153                  * This is 1/16 sec (66.6ms) on,
1154                  * 3/16 sec (187.5 ms) off, with packets rcvd
1155                  */
1156                 ledblink = ((66600*1000UL/4) << IBA7220_LEDBLINK_ON_SHIFT)
1157                         | ((187500*1000UL/4) << IBA7220_LEDBLINK_OFF_SHIFT);
1158         }
1159         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1160                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1161         dd->ipath_extctrl = extctl;
1162         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1163         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1164
1165         if (ledblink) /* blink the LED on packet receive */
1166                 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvpktledcnt,
1167                         ledblink);
1168 }
1169
1170 /*
1171  * Similar to pci_intx(pdev, 1), except that we make sure
1172  * msi is off...
1173  */
1174 static void ipath_enable_intx(struct pci_dev *pdev)
1175 {
1176         u16 cw, new;
1177         int pos;
1178
1179         /* first, turn on INTx */
1180         pci_read_config_word(pdev, PCI_COMMAND, &cw);
1181         new = cw & ~PCI_COMMAND_INTX_DISABLE;
1182         if (new != cw)
1183                 pci_write_config_word(pdev, PCI_COMMAND, new);
1184
1185         /* then turn off MSI */
1186         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1187         if (pos) {
1188                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1189                 new = cw & ~PCI_MSI_FLAGS_ENABLE;
1190                 if (new != cw)
1191                         pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
1192         }
1193 }
1194
1195 static int ipath_msi_enabled(struct pci_dev *pdev)
1196 {
1197         int pos, ret = 0;
1198
1199         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1200         if (pos) {
1201                 u16 cw;
1202
1203                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1204                 ret = !!(cw & PCI_MSI_FLAGS_ENABLE);
1205         }
1206         return ret;
1207 }
1208
1209 /*
1210  * disable msi interrupt if enabled, and clear the flag.
1211  * flag is used primarily for the fallback to INTx, but
1212  * is also used in reinit after reset as a flag.
1213  */
1214 static void ipath_7220_nomsi(struct ipath_devdata *dd)
1215 {
1216         dd->ipath_msi_lo = 0;
1217
1218         if (ipath_msi_enabled(dd->pcidev)) {
1219                 /*
1220                  * free, but don't zero; later kernels require
1221                  * it be freed before disable_msi, so the intx
1222                  * setup has to request it again.
1223                  */
1224                  if (dd->ipath_irq)
1225                         free_irq(dd->ipath_irq, dd);
1226                 pci_disable_msi(dd->pcidev);
1227         }
1228 }
1229
1230 /*
1231  * ipath_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1232  * @dd: the infinipath device
1233  *
1234  * Nothing but msi interrupt cleanup for now.
1235  *
1236  * This is called during driver unload.
1237  */
1238 static void ipath_setup_7220_cleanup(struct ipath_devdata *dd)
1239 {
1240         ipath_7220_nomsi(dd);
1241 }
1242
1243
1244 static void ipath_7220_pcie_params(struct ipath_devdata *dd, u32 boardrev)
1245 {
1246         u16 linkstat, minwidth, speed;
1247         int pos;
1248
1249         pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
1250         if (!pos) {
1251                 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
1252                 goto bail;
1253         }
1254
1255         pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
1256                              &linkstat);
1257         /*
1258          * speed is bits 0-4, linkwidth is bits 4-8
1259          * no defines for them in headers
1260          */
1261         speed = linkstat & 0xf;
1262         linkstat >>= 4;
1263         linkstat &= 0x1f;
1264         dd->ipath_lbus_width = linkstat;
1265         switch (boardrev) {
1266         case 0:
1267         case 2:
1268         case 10:
1269         case 12:
1270                 minwidth = 16; /* x16 capable boards */
1271                 break;
1272         default:
1273                 minwidth = 8; /* x8 capable boards */
1274                 break;
1275         }
1276
1277         switch (speed) {
1278         case 1:
1279                 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
1280                 break;
1281         case 2:
1282                 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
1283                 break;
1284         default: /* not defined, assume gen1 */
1285                 dd->ipath_lbus_speed = 2500;
1286                 break;
1287         }
1288
1289         if (linkstat < minwidth)
1290                 ipath_dev_err(dd,
1291                         "PCIe width %u (x%u HCA), performance "
1292                         "reduced\n", linkstat, minwidth);
1293         else
1294                 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x%u HCA)\n",
1295                         dd->ipath_lbus_speed, linkstat, minwidth);
1296
1297         if (speed != 1)
1298                 ipath_dev_err(dd,
1299                         "PCIe linkspeed %u is incorrect; "
1300                         "should be 1 (2500)!\n", speed);
1301
1302 bail:
1303         /* fill in string, even on errors */
1304         snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
1305                 "PCIe,%uMHz,x%u\n",
1306                 dd->ipath_lbus_speed,
1307                 dd->ipath_lbus_width);
1308         return;
1309 }
1310
1311
1312 /**
1313  * ipath_setup_7220_config - setup PCIe config related stuff
1314  * @dd: the infinipath device
1315  * @pdev: the PCI device
1316  *
1317  * The pci_enable_msi() call will fail on systems with MSI quirks
1318  * such as those with AMD8131, even if the device of interest is not
1319  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1320  * late in 2.6.16).
1321  * All that can be done is to edit the kernel source to remove the quirk
1322  * check until that is fixed.
1323  * We do not need to call enable_msi() for our HyperTransport chip,
1324  * even though it uses MSI, and we want to avoid the quirk warning, so
1325  * So we call enable_msi only for PCIe.  If we do end up needing
1326  * pci_enable_msi at some point in the future for HT, we'll move the
1327  * call back into the main init_one code.
1328  * We save the msi lo and hi values, so we can restore them after
1329  * chip reset (the kernel PCI infrastructure doesn't yet handle that
1330  * correctly).
1331  */
1332 static int ipath_setup_7220_config(struct ipath_devdata *dd,
1333                                    struct pci_dev *pdev)
1334 {
1335         int pos, ret = -1;
1336         u32 boardrev;
1337
1338         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
1339
1340         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1341         if (!strcmp(int_type, "force_msi") || !strcmp(int_type, "auto"))
1342                 ret = pci_enable_msi(pdev);
1343         if (ret) {
1344                 if (!strcmp(int_type, "force_msi")) {
1345                         ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1346                                       "force_msi is on, so not continuing.\n",
1347                                       ret);
1348                         return ret;
1349                 }
1350
1351                 ipath_enable_intx(pdev);
1352                 if (!strcmp(int_type, "auto"))
1353                         ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1354                                       "falling back to INTx\n", ret);
1355         } else if (pos) {
1356                 u16 control;
1357                 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
1358                                       &dd->ipath_msi_lo);
1359                 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
1360                                       &dd->ipath_msi_hi);
1361                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS,
1362                                      &control);
1363                 /* now save the data (vector) info */
1364                 pci_read_config_word(pdev,
1365                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
1366                                             ? PCI_MSI_DATA_64 :
1367                                             PCI_MSI_DATA_32),
1368                                      &dd->ipath_msi_data);
1369         } else
1370                 ipath_dev_err(dd, "Can't find MSI capability, "
1371                               "can't save MSI settings for reset\n");
1372
1373         dd->ipath_irq = pdev->irq;
1374
1375         /*
1376          * We save the cachelinesize also, although it doesn't
1377          * really matter.
1378          */
1379         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1380                              &dd->ipath_pci_cacheline);
1381
1382         /*
1383          * this function called early, ipath_boardrev not set yet.  Can't
1384          * use ipath_read_kreg64() yet, too early in init, so use readq()
1385          */
1386         boardrev = (readq(&dd->ipath_kregbase[dd->ipath_kregs->kr_revision])
1387                  >> INFINIPATH_R_BOARDID_SHIFT) & INFINIPATH_R_BOARDID_MASK;
1388
1389         ipath_7220_pcie_params(dd, boardrev);
1390
1391         dd->ipath_flags |= IPATH_NODMA_RTAIL | IPATH_HAS_SEND_DMA |
1392                 IPATH_HAS_PBC_CNT | IPATH_HAS_THRESH_UPDATE;
1393         dd->ipath_pioupd_thresh = 4U; /* set default update threshold */
1394         return 0;
1395 }
1396
1397 static void ipath_init_7220_variables(struct ipath_devdata *dd)
1398 {
1399         /*
1400          * setup the register offsets, since they are different for each
1401          * chip
1402          */
1403         dd->ipath_kregs = &ipath_7220_kregs;
1404         dd->ipath_cregs = &ipath_7220_cregs;
1405
1406         /*
1407          * bits for selecting i2c direction and values,
1408          * used for I2C serial flash
1409          */
1410         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1411         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1412         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1413         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1414
1415         /*
1416          * Fill in data for field-values that change in IBA7220.
1417          * We dynamically specify only the mask for LINKTRAININGSTATE
1418          * and only the shift for LINKSTATE, as they are the only ones
1419          * that change.  Also precalculate the 3 link states of interest
1420          * and the combined mask.
1421          */
1422         dd->ibcs_ls_shift = IBA7220_IBCS_LINKSTATE_SHIFT;
1423         dd->ibcs_lts_mask = IBA7220_IBCS_LINKTRAININGSTATE_MASK;
1424         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1425                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1426         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1427                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1428                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1429         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1430                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1431                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1432         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1433                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1434                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1435
1436         /*
1437          * Fill in data for ibcc field-values that change in IBA7220.
1438          * We dynamically specify only the mask for LINKINITCMD
1439          * and only the shift for LINKCMD and MAXPKTLEN, as they are
1440          * the only ones that change.
1441          */
1442         dd->ibcc_lic_mask = IBA7220_IBCC_LINKINITCMD_MASK;
1443         dd->ibcc_lc_shift = IBA7220_IBCC_LINKCMD_SHIFT;
1444         dd->ibcc_mpl_shift = IBA7220_IBCC_MAXPKTLEN_SHIFT;
1445
1446         /* Fill in shifts for RcvCtrl. */
1447         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1448         dd->ipath_r_intravail_shift = IBA7220_R_INTRAVAIL_SHIFT;
1449         dd->ipath_r_tailupd_shift = IBA7220_R_TAILUPD_SHIFT;
1450         dd->ipath_r_portcfg_shift = IBA7220_R_PORTCFG_SHIFT;
1451
1452         /* variables for sanity checking interrupt and errors */
1453         dd->ipath_hwe_bitsextant =
1454                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1455                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1456                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1457                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1458                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1459                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1460                 INFINIPATH_HWE_PCIE1PLLFAILED |
1461                 INFINIPATH_HWE_PCIE0PLLFAILED |
1462                 INFINIPATH_HWE_PCIEPOISONEDTLP |
1463                 INFINIPATH_HWE_PCIECPLTIMEOUT |
1464                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1465                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1466                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1467                 INFINIPATH_HWE_MEMBISTFAILED |
1468                 INFINIPATH_HWE_COREPLL_FBSLIP |
1469                 INFINIPATH_HWE_COREPLL_RFSLIP |
1470                 INFINIPATH_HWE_SERDESPLLFAILED |
1471                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1472                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR |
1473                 INFINIPATH_HWE_PCIECPLDATAQUEUEERR |
1474                 INFINIPATH_HWE_PCIECPLHDRQUEUEERR |
1475                 INFINIPATH_HWE_SDMAMEMREADERR |
1476                 INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED |
1477                 INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT |
1478                 INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT |
1479                 INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT |
1480                 INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT |
1481                 INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR |
1482                 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR |
1483                 INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR |
1484                 INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR;
1485         dd->ipath_i_bitsextant =
1486                 INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED |
1487                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1488                 (INFINIPATH_I_RCVAVAIL_MASK <<
1489                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1490                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1491                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO |
1492                 INFINIPATH_I_JINT | INFINIPATH_I_SERDESTRIMDONE;
1493         dd->ipath_e_bitsextant =
1494                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1495                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1496                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1497                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1498                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1499                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1500                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1501                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1502                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1503                 INFINIPATH_E_SENDSPECIALTRIGGER |
1504                 INFINIPATH_E_SDMADISABLED | INFINIPATH_E_SMINPKTLEN |
1505                 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNDERRUN |
1506                 INFINIPATH_E_SPKTLEN | INFINIPATH_E_SDROPPEDSMPPKT |
1507                 INFINIPATH_E_SDROPPEDDATAPKT |
1508                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1509                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_SENDBUFMISUSE |
1510                 INFINIPATH_E_SDMAGENMISMATCH | INFINIPATH_E_SDMAOUTOFBOUND |
1511                 INFINIPATH_E_SDMATAILOUTOFBOUND | INFINIPATH_E_SDMABASE |
1512                 INFINIPATH_E_SDMA1STDESC | INFINIPATH_E_SDMARPYTAG |
1513                 INFINIPATH_E_SDMADWEN | INFINIPATH_E_SDMAMISSINGDW |
1514                 INFINIPATH_E_SDMAUNEXPDATA |
1515                 INFINIPATH_E_IBSTATUSCHANGED | INFINIPATH_E_INVALIDADDR |
1516                 INFINIPATH_E_RESET | INFINIPATH_E_HARDWARE |
1517                 INFINIPATH_E_SDMADESCADDRMISALIGN |
1518                 INFINIPATH_E_INVALIDEEPCMD;
1519
1520         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1521         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1522         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1523         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1524         dd->ipath_flags |= IPATH_INTREG_64 | IPATH_HAS_MULT_IB_SPEED
1525                 | IPATH_HAS_LINK_LATENCY;
1526
1527         /*
1528          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1529          * 2 is Some Misc, 3 is reserved for future.
1530          */
1531         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1532                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1533                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1534
1535         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1536                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1537                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1538
1539         dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1540
1541         ipath_linkrecovery = 0;
1542
1543         init_waitqueue_head(&dd->ipath_autoneg_wait);
1544         INIT_DELAYED_WORK(&dd->ipath_autoneg_work,  autoneg_work);
1545
1546         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1547         dd->ipath_link_speed_supported = IPATH_IB_SDR | IPATH_IB_DDR;
1548
1549         dd->ipath_link_width_enabled = dd->ipath_link_width_supported;
1550         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1551         /*
1552          * set the initial values to reasonable default, will be set
1553          * for real when link is up.
1554          */
1555         dd->ipath_link_width_active = IB_WIDTH_4X;
1556         dd->ipath_link_speed_active = IPATH_IB_SDR;
1557         dd->delay_mult = rate_to_delay[0][1];
1558 }
1559
1560
1561 /*
1562  * Setup the MSI stuff again after a reset.  I'd like to just call
1563  * pci_enable_msi() and request_irq() again, but when I do that,
1564  * the MSI enable bit doesn't get set in the command word, and
1565  * we switch to to a different interrupt vector, which is confusing,
1566  * so I instead just do it all inline.  Perhaps somehow can tie this
1567  * into the PCIe hotplug support at some point
1568  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1569  * or free_irq() at the start of ipath_setup_7220_reset().
1570  */
1571 static int ipath_reinit_msi(struct ipath_devdata *dd)
1572 {
1573         int ret = 0;
1574
1575         int pos;
1576         u16 control;
1577         if (!dd->ipath_msi_lo) /* Using intX, or init problem */
1578                 goto bail;
1579
1580         pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
1581         if (!pos) {
1582                 ipath_dev_err(dd, "Can't find MSI capability, "
1583                               "can't restore MSI settings\n");
1584                 goto bail;
1585         }
1586         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1587                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1588         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1589                                dd->ipath_msi_lo);
1590         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1591                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1592         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1593                                dd->ipath_msi_hi);
1594         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1595         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1596                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1597                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1598                            control, control | PCI_MSI_FLAGS_ENABLE);
1599                 control |= PCI_MSI_FLAGS_ENABLE;
1600                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1601                                       control);
1602         }
1603         /* now rewrite the data (vector) info */
1604         pci_write_config_word(dd->pcidev, pos +
1605                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1606                               dd->ipath_msi_data);
1607         ret = 1;
1608
1609 bail:
1610         if (!ret) {
1611                 ipath_dbg("Using INTx, MSI disabled or not configured\n");
1612                 ipath_enable_intx(dd->pcidev);
1613                 ret = 1;
1614         }
1615         /*
1616          * We restore the cachelinesize also, although it doesn't really
1617          * matter.
1618          */
1619         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1620                               dd->ipath_pci_cacheline);
1621         /* and now set the pci master bit again */
1622         pci_set_master(dd->pcidev);
1623
1624         return ret;
1625 }
1626
1627 /*
1628  * This routine sleeps, so it can only be called from user context, not
1629  * from interrupt context.  If we need interrupt context, we can split
1630  * it into two routines.
1631  */
1632 static int ipath_setup_7220_reset(struct ipath_devdata *dd)
1633 {
1634         u64 val;
1635         int i;
1636         int ret;
1637         u16 cmdval;
1638
1639         pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1640
1641         /* Use dev_err so it shows up in logs, etc. */
1642         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1643
1644         /* keep chip from being accessed in a few places */
1645         dd->ipath_flags &= ~(IPATH_INITTED | IPATH_PRESENT);
1646         val = dd->ipath_control | INFINIPATH_C_RESET;
1647         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1648         mb();
1649
1650         for (i = 1; i <= 5; i++) {
1651                 int r;
1652
1653                 /*
1654                  * Allow MBIST, etc. to complete; longer on each retry.
1655                  * We sometimes get machine checks from bus timeout if no
1656                  * response, so for now, make it *really* long.
1657                  */
1658                 msleep(1000 + (1 + i) * 2000);
1659                 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1660                                            dd->ipath_pcibar0);
1661                 if (r)
1662                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
1663                 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1664                                            dd->ipath_pcibar1);
1665                 if (r)
1666                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
1667                 /* now re-enable memory access */
1668                 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1669                 r = pci_enable_device(dd->pcidev);
1670                 if (r)
1671                         ipath_dev_err(dd, "pci_enable_device failed after "
1672                                       "reset: %d\n", r);
1673                 /*
1674                  * whether it fully enabled or not, mark as present,
1675                  * again (but not INITTED)
1676                  */
1677                 dd->ipath_flags |= IPATH_PRESENT;
1678                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1679                 if (val == dd->ipath_revision) {
1680                         ipath_cdbg(VERBOSE, "Got matching revision "
1681                                    "register %llx on try %d\n",
1682                                    (unsigned long long) val, i);
1683                         ret = ipath_reinit_msi(dd);
1684                         goto bail;
1685                 }
1686                 /* Probably getting -1 back */
1687                 ipath_dbg("Didn't get expected revision register, "
1688                           "got %llx, try %d\n", (unsigned long long) val,
1689                           i + 1);
1690         }
1691         ret = 0; /* failed */
1692
1693 bail:
1694         if (ret)
1695                 ipath_7220_pcie_params(dd, dd->ipath_boardrev);
1696
1697         return ret;
1698 }
1699
1700 /**
1701  * ipath_7220_put_tid - write a TID to the chip
1702  * @dd: the infinipath device
1703  * @tidptr: pointer to the expected TID (in chip) to udpate
1704  * @tidtype: 0 for eager, 1 for expected
1705  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1706  *
1707  * This exists as a separate routine to allow for selection of the
1708  * appropriate "flavor". The static calls in cleanup just use the
1709  * revision-agnostic form, as they are not performance critical.
1710  */
1711 static void ipath_7220_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1712                              u32 type, unsigned long pa)
1713 {
1714         if (pa != dd->ipath_tidinvalid) {
1715                 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
1716
1717                 /* paranoia checks */
1718                 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
1719                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1720                                  "not 2KB aligned!\n", pa);
1721                         return;
1722                 }
1723                 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
1724                         ipath_dev_err(dd,
1725                                       "BUG: Physical page address 0x%lx "
1726                                       "larger than supported\n", pa);
1727                         return;
1728                 }
1729
1730                 if (type == RCVHQ_RCV_TYPE_EAGER)
1731                         chippa |= dd->ipath_tidtemplate;
1732                 else /* for now, always full 4KB page */
1733                         chippa |= IBA7220_TID_SZ_4K;
1734                 writeq(chippa, tidptr);
1735         } else
1736                 writeq(pa, tidptr);
1737         mmiowb();
1738 }
1739
1740 /**
1741  * ipath_7220_clear_tid - clear all TID entries for a port, expected and eager
1742  * @dd: the infinipath device
1743  * @port: the port
1744  *
1745  * clear all TID entries for a port, expected and eager.
1746  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1747  * not 64, but they are still on 64 bit boundaries, so tidbase
1748  * is declared as u64 * for the pointer math, even though we write 32 bits
1749  */
1750 static void ipath_7220_clear_tids(struct ipath_devdata *dd, unsigned port)
1751 {
1752         u64 __iomem *tidbase;
1753         unsigned long tidinv;
1754         int i;
1755
1756         if (!dd->ipath_kregbase)
1757                 return;
1758
1759         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1760
1761         tidinv = dd->ipath_tidinvalid;
1762         tidbase = (u64 __iomem *)
1763                 ((char __iomem *)(dd->ipath_kregbase) +
1764                  dd->ipath_rcvtidbase +
1765                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1766
1767         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1768                 ipath_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1769                                    tidinv);
1770
1771         tidbase = (u64 __iomem *)
1772                 ((char __iomem *)(dd->ipath_kregbase) +
1773                  dd->ipath_rcvegrbase + port_egrtid_idx(dd, port)
1774                  * sizeof(*tidbase));
1775
1776         for (i = port ? dd->ipath_rcvegrcnt : dd->ipath_p0_rcvegrcnt; i; i--)
1777                 ipath_7220_put_tid(dd, &tidbase[i-1], RCVHQ_RCV_TYPE_EAGER,
1778                         tidinv);
1779 }
1780
1781 /**
1782  * ipath_7220_tidtemplate - setup constants for TID updates
1783  * @dd: the infinipath device
1784  *
1785  * We setup stuff that we use a lot, to avoid calculating each time
1786  */
1787 static void ipath_7220_tidtemplate(struct ipath_devdata *dd)
1788 {
1789         /* For now, we always allocate 4KB buffers (at init) so we can
1790          * receive max size packets.  We may want a module parameter to
1791          * specify 2KB or 4KB and/or make be per port instead of per device
1792          * for those who want to reduce memory footprint.  Note that the
1793          * ipath_rcvhdrentsize size must be large enough to hold the largest
1794          * IB header (currently 96 bytes) that we expect to handle (plus of
1795          * course the 2 dwords of RHF).
1796          */
1797         if (dd->ipath_rcvegrbufsize == 2048)
1798                 dd->ipath_tidtemplate = IBA7220_TID_SZ_2K;
1799         else if (dd->ipath_rcvegrbufsize == 4096)
1800                 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1801         else {
1802                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1803                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1804                          4096);
1805                 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1806         }
1807         dd->ipath_tidinvalid = 0;
1808 }
1809
1810 static int ipath_7220_early_init(struct ipath_devdata *dd)
1811 {
1812         u32 i, s;
1813
1814         if (strcmp(int_type, "auto") &&
1815             strcmp(int_type, "force_msi") &&
1816             strcmp(int_type, "force_intx")) {
1817                 ipath_dev_err(dd, "Invalid interrupt_type: '%s', expecting "
1818                               "auto, force_msi or force_intx\n", int_type);
1819                 return -EINVAL;
1820         }
1821
1822         /*
1823          * Control[4] has been added to change the arbitration within
1824          * the SDMA engine between favoring data fetches over descriptor
1825          * fetches.  ipath_sdma_fetch_arb==0 gives data fetches priority.
1826          */
1827         if (ipath_sdma_fetch_arb && (dd->ipath_minrev > 1))
1828                 dd->ipath_control |= 1<<4;
1829
1830         dd->ipath_flags |= IPATH_4BYTE_TID;
1831
1832         /*
1833          * For openfabrics, we need to be able to handle an IB header of
1834          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1835          * made them the same size as the PIO buffers.  This chip does not
1836          * handle arbitrary size buffers, so we need the header large enough
1837          * to handle largest IB header, but still have room for a 2KB MTU
1838          * standard IB packet.
1839          */
1840         dd->ipath_rcvhdrentsize = 24;
1841         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1842         dd->ipath_rhf_offset =
1843                 dd->ipath_rcvhdrentsize - sizeof(u64) / sizeof(u32);
1844
1845         dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1846         /*
1847          * the min() check here is currently a nop, but it may not always
1848          * be, depending on just how we do ipath_rcvegrbufsize
1849          */
1850         dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1851                                  dd->ipath_piosize2k,
1852                                  dd->ipath_rcvegrbufsize +
1853                                  (dd->ipath_rcvhdrentsize << 2));
1854         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1855
1856         ipath_7220_config_jint(dd, INFINIPATH_JINT_DEFAULT_IDLE_TICKS,
1857                                INFINIPATH_JINT_DEFAULT_MAX_PACKETS);
1858
1859         if (dd->ipath_boardrev) /* no eeprom on emulator */
1860                 ipath_get_eeprom_info(dd);
1861
1862         /* start of code to check and print procmon */
1863         s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1864         s &= ~(1U<<31); /* clear done bit */
1865         s |= 1U<<14; /* clear counter (write 1 to clear) */
1866         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1867         /* make sure clear_counter low long enough before start */
1868         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1869         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1870
1871         s &= ~(1U<<14); /* allow counter to count (before starting) */
1872         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1873         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1874         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1875         s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1876
1877         s |= 1U<<15; /* start the counter */
1878         s &= ~(1U<<31); /* clear done bit */
1879         s &= ~0x7ffU; /* clear frequency bits */
1880         s |= 0xe29; /* set frequency bits, in case cleared */
1881         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1882
1883         s = 0;
1884         for (i = 500; i > 0 && !(s&(1ULL<<31)); i--) {
1885                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1886                 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1887         }
1888         if (!(s&(1U<<31)))
1889                 ipath_dev_err(dd, "ProcMon register not valid: 0x%x\n", s);
1890         else
1891                 ipath_dbg("ProcMon=0x%x, count=0x%x\n", s, (s>>16)&0x1ff);
1892
1893         return 0;
1894 }
1895
1896 /**
1897  * ipath_init_7220_get_base_info - set chip-specific flags for user code
1898  * @pd: the infinipath port
1899  * @kbase: ipath_base_info pointer
1900  *
1901  * We set the PCIE flag because the lower bandwidth on PCIe vs
1902  * HyperTransport can affect some user packet algorithims.
1903  */
1904 static int ipath_7220_get_base_info(struct ipath_portdata *pd, void *kbase)
1905 {
1906         struct ipath_base_info *kinfo = kbase;
1907
1908         kinfo->spi_runtime_flags |=
1909                 IPATH_RUNTIME_PCIE | IPATH_RUNTIME_NODMA_RTAIL |
1910                 IPATH_RUNTIME_SDMA;
1911
1912         return 0;
1913 }
1914
1915 static void ipath_7220_free_irq(struct ipath_devdata *dd)
1916 {
1917         free_irq(dd->ipath_irq, dd);
1918         dd->ipath_irq = 0;
1919 }
1920
1921 static struct ipath_message_header *
1922 ipath_7220_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1923 {
1924         u32 offset = ipath_hdrget_offset(rhf_addr);
1925
1926         return (struct ipath_message_header *)
1927                 (rhf_addr - dd->ipath_rhf_offset + offset);
1928 }
1929
1930 static void ipath_7220_config_ports(struct ipath_devdata *dd, ushort cfgports)
1931 {
1932         u32 nchipports;
1933
1934         nchipports = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1935         if (!cfgports) {
1936                 int ncpus = num_online_cpus();
1937
1938                 if (ncpus <= 4)
1939                         dd->ipath_portcnt = 5;
1940                 else if (ncpus <= 8)
1941                         dd->ipath_portcnt = 9;
1942                 if (dd->ipath_portcnt)
1943                         ipath_dbg("Auto-configured for %u ports, %d cpus "
1944                                 "online\n", dd->ipath_portcnt, ncpus);
1945         } else if (cfgports <= nchipports)
1946                 dd->ipath_portcnt = cfgports;
1947         if (!dd->ipath_portcnt) /* none of the above, set to max */
1948                 dd->ipath_portcnt = nchipports;
1949         /*
1950          * chip can be configured for 5, 9, or 17 ports, and choice
1951          * affects number of eager TIDs per port (1K, 2K, 4K).
1952          */
1953         if (dd->ipath_portcnt > 9)
1954                 dd->ipath_rcvctrl |= 2ULL << IBA7220_R_PORTCFG_SHIFT;
1955         else if (dd->ipath_portcnt > 5)
1956                 dd->ipath_rcvctrl |= 1ULL << IBA7220_R_PORTCFG_SHIFT;
1957         /* else configure for default 5 receive ports */
1958         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1959                          dd->ipath_rcvctrl);
1960         dd->ipath_p0_rcvegrcnt = 2048; /* always */
1961         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1962                 dd->ipath_pioreserved = 3; /* kpiobufs used for PIO */
1963 }
1964
1965
1966 static int ipath_7220_get_ib_cfg(struct ipath_devdata *dd, int which)
1967 {
1968         int lsb, ret = 0;
1969         u64 maskr; /* right-justified mask */
1970
1971         switch (which) {
1972         case IPATH_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
1973                 lsb = IBA7220_IBC_HRTBT_SHIFT;
1974                 maskr = IBA7220_IBC_HRTBT_MASK;
1975                 break;
1976
1977         case IPATH_IB_CFG_LWID_ENB: /* Get allowed Link-width */
1978                 ret = dd->ipath_link_width_enabled;
1979                 goto done;
1980
1981         case IPATH_IB_CFG_LWID: /* Get currently active Link-width */
1982                 ret = dd->ipath_link_width_active;
1983                 goto done;
1984
1985         case IPATH_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
1986                 ret = dd->ipath_link_speed_enabled;
1987                 goto done;
1988
1989         case IPATH_IB_CFG_SPD: /* Get current Link spd */
1990                 ret = dd->ipath_link_speed_active;
1991                 goto done;
1992
1993         case IPATH_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
1994                 lsb = IBA7220_IBC_RXPOL_SHIFT;
1995                 maskr = IBA7220_IBC_RXPOL_MASK;
1996                 break;
1997
1998         case IPATH_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
1999                 lsb = IBA7220_IBC_LREV_SHIFT;
2000                 maskr = IBA7220_IBC_LREV_MASK;
2001                 break;
2002
2003         case IPATH_IB_CFG_LINKLATENCY:
2004                 ret = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrstatus)
2005                         & IBA7220_DDRSTAT_LINKLAT_MASK;
2006                 goto done;
2007
2008         default:
2009                 ret = -ENOTSUPP;
2010                 goto done;
2011         }
2012         ret = (int)((dd->ipath_ibcddrctrl >> lsb) & maskr);
2013 done:
2014         return ret;
2015 }
2016
2017 static int ipath_7220_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
2018 {
2019         int lsb, ret = 0, setforce = 0;
2020         u64 maskr; /* right-justified mask */
2021
2022         switch (which) {
2023         case IPATH_IB_CFG_LIDLMC:
2024                 /*
2025                  * Set LID and LMC. Combined to avoid possible hazard
2026                  * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2027                  */
2028                 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2029                 maskr = IBA7220_IBC_DLIDLMC_MASK;
2030                 break;
2031
2032         case IPATH_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2033                 if (val & IPATH_IB_HRTBT_ON &&
2034                         (dd->ipath_flags & IPATH_NO_HRTBT))
2035                         goto bail;
2036                 lsb = IBA7220_IBC_HRTBT_SHIFT;
2037                 maskr = IBA7220_IBC_HRTBT_MASK;
2038                 break;
2039
2040         case IPATH_IB_CFG_LWID_ENB: /* set allowed Link-width */
2041                 /*
2042                  * As with speed, only write the actual register if
2043                  * the link is currently down, otherwise takes effect
2044                  * on next link change.
2045                  */
2046                 dd->ipath_link_width_enabled = val;
2047                 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2048                         IPATH_LINKDOWN)
2049                         goto bail;
2050                 /*
2051                  * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2052                  * will get called because we want update
2053                  * link_width_active, and the change may not take
2054                  * effect for some time (if we are in POLL), so this
2055                  * flag will force the updown routine to be called
2056                  * on the next ibstatuschange down interrupt, even
2057                  * if it's not an down->up transition.
2058                  */
2059                 val--; /* convert from IB to chip */
2060                 maskr = IBA7220_IBC_WIDTH_MASK;
2061                 lsb = IBA7220_IBC_WIDTH_SHIFT;
2062                 setforce = 1;
2063                 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2064                 break;
2065
2066         case IPATH_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2067                 /*
2068                  * If we turn off IB1.2, need to preset SerDes defaults,
2069                  * but not right now. Set a flag for the next time
2070                  * we command the link down.  As with width, only write the
2071                  * actual register if the link is currently down, otherwise
2072                  * takes effect on next link change.  Since setting is being
2073                  * explictly requested (via MAD or sysfs), clear autoneg
2074                  * failure status if speed autoneg is enabled.
2075                  */
2076                 dd->ipath_link_speed_enabled = val;
2077                 if (dd->ipath_ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK &&
2078                     !(val & (val - 1)))
2079                         dd->ipath_presets_needed = 1;
2080                 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2081                         IPATH_LINKDOWN)
2082                         goto bail;
2083                 /*
2084                  * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2085                  * will get called because we want update
2086                  * link_speed_active, and the change may not take
2087                  * effect for some time (if we are in POLL), so this
2088                  * flag will force the updown routine to be called
2089                  * on the next ibstatuschange down interrupt, even
2090                  * if it's not an down->up transition.  When setting
2091                  * speed autoneg, clear AUTONEG_FAILED.
2092                  */
2093                 if (val == (IPATH_IB_SDR | IPATH_IB_DDR)) {
2094                         val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2095                                 IBA7220_IBC_IBTA_1_2_MASK;
2096                         dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2097                 } else
2098                         val = val == IPATH_IB_DDR ?  IBA7220_IBC_SPEED_DDR
2099                                 : IBA7220_IBC_SPEED_SDR;
2100                 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2101                         IBA7220_IBC_IBTA_1_2_MASK;
2102                 lsb = 0; /* speed bits are low bits */
2103                 setforce = 1;
2104                 break;
2105
2106         case IPATH_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2107                 lsb = IBA7220_IBC_RXPOL_SHIFT;
2108                 maskr = IBA7220_IBC_RXPOL_MASK;
2109                 break;
2110
2111         case IPATH_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2112                 lsb = IBA7220_IBC_LREV_SHIFT;
2113                 maskr = IBA7220_IBC_LREV_MASK;
2114                 break;
2115
2116         default:
2117                 ret = -ENOTSUPP;
2118                 goto bail;
2119         }
2120         dd->ipath_ibcddrctrl &= ~(maskr << lsb);
2121         dd->ipath_ibcddrctrl |= (((u64) val & maskr) << lsb);
2122         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2123                          dd->ipath_ibcddrctrl);
2124         if (setforce)
2125                 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2126 bail:
2127         return ret;
2128 }
2129
2130 static void ipath_7220_read_counters(struct ipath_devdata *dd,
2131                                      struct infinipath_counters *cntrs)
2132 {
2133         u64 *counters = (u64 *) cntrs;
2134         int i;
2135
2136         for (i = 0; i < sizeof(*cntrs) / sizeof(u64); i++)
2137                 counters[i] = ipath_snap_cntr(dd, i);
2138 }
2139
2140 /* if we are using MSI, try to fallback to INTx */
2141 static int ipath_7220_intr_fallback(struct ipath_devdata *dd)
2142 {
2143         if (dd->ipath_msi_lo) {
2144                 dev_info(&dd->pcidev->dev, "MSI interrupt not detected,"
2145                         " trying INTx interrupts\n");
2146                 ipath_7220_nomsi(dd);
2147                 ipath_enable_intx(dd->pcidev);
2148                 /*
2149                  * some newer kernels require free_irq before disable_msi,
2150                  * and irq can be changed during disable and intx enable
2151                  * and we need to therefore use the pcidev->irq value,
2152                  * not our saved MSI value.
2153                  */
2154                 dd->ipath_irq = dd->pcidev->irq;
2155                 if (request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
2156                         IPATH_DRV_NAME, dd))
2157                         ipath_dev_err(dd,
2158                                 "Could not re-request_irq for INTx\n");
2159                 return 1;
2160         }
2161         return 0;
2162 }
2163
2164 /*
2165  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
2166  * than resetting the IBC or external link state, and useful in some
2167  * cases to cause some retraining.  To do this right, we reset IBC
2168  * as well.
2169  */
2170 static void ipath_7220_xgxs_reset(struct ipath_devdata *dd)
2171 {
2172         u64 val, prev_val;
2173
2174         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2175         val = prev_val | INFINIPATH_XGXS_RESET;
2176         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
2177         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2178                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
2179         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2180         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
2181         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
2182         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2183                          dd->ipath_control);
2184 }
2185
2186
2187 /* Still needs cleanup, too much hardwired stuff */
2188 static void autoneg_send(struct ipath_devdata *dd,
2189         u32 *hdr, u32 dcnt, u32 *data)
2190 {
2191         int i;
2192         u64 cnt;
2193         u32 __iomem *piobuf;
2194         u32 pnum;
2195
2196         i = 0;
2197         cnt = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
2198         while (!(piobuf = ipath_getpiobuf(dd, cnt, &pnum))) {
2199                 if (i++ > 15) {
2200                         ipath_dbg("Couldn't get pio buffer for send\n");
2201                         return;
2202                 }
2203                 udelay(2);
2204         }
2205         if (dd->ipath_flags&IPATH_HAS_PBC_CNT)
2206                 cnt |= 0x80000000UL<<32; /* mark as VL15 */
2207         writeq(cnt, piobuf);
2208         ipath_flush_wc();
2209         __iowrite32_copy(piobuf + 2, hdr, 7);
2210         __iowrite32_copy(piobuf + 9, data, dcnt);
2211         ipath_flush_wc();
2212 }
2213
2214 /*
2215  * _start packet gets sent twice at start, _done gets sent twice at end
2216  */
2217 static void ipath_autoneg_send(struct ipath_devdata *dd, int which)
2218 {
2219         static u32 swapped;
2220         u32 dw, i, hcnt, dcnt, *data;
2221         static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
2222         static u32 madpayload_start[0x40] = {
2223                 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2224                 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2225                 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
2226                 };
2227         static u32 madpayload_done[0x40] = {
2228                 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2229                 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2230                 0x40000001, 0x1388, 0x15e, /* rest 0's */
2231                 };
2232         dcnt = ARRAY_SIZE(madpayload_start);
2233         hcnt = ARRAY_SIZE(hdr);
2234         if (!swapped) {
2235                 /* for maintainability, do it at runtime */
2236                 for (i = 0; i < hcnt; i++) {
2237                         dw = (__force u32) cpu_to_be32(hdr[i]);
2238                         hdr[i] = dw;
2239                 }
2240                 for (i = 0; i < dcnt; i++) {
2241                         dw = (__force u32) cpu_to_be32(madpayload_start[i]);
2242                         madpayload_start[i] = dw;
2243                         dw = (__force u32) cpu_to_be32(madpayload_done[i]);
2244                         madpayload_done[i] = dw;
2245                 }
2246                 swapped = 1;
2247         }
2248
2249         data = which ? madpayload_done : madpayload_start;
2250         ipath_cdbg(PKT, "Sending %s special MADs\n", which?"done":"start");
2251
2252         autoneg_send(dd, hdr, dcnt, data);
2253         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2254         udelay(2);
2255         autoneg_send(dd, hdr, dcnt, data);
2256         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2257         udelay(2);
2258 }
2259
2260
2261
2262 /*
2263  * Do the absolute minimum to cause an IB speed change, and make it
2264  * ready, but don't actually trigger the change.   The caller will
2265  * do that when ready (if link is in Polling training state, it will
2266  * happen immediately, otherwise when link next goes down)
2267  *
2268  * This routine should only be used as part of the DDR autonegotation
2269  * code for devices that are not compliant with IB 1.2 (or code that
2270  * fixes things up for same).
2271  *
2272  * When link has gone down, and autoneg enabled, or autoneg has
2273  * failed and we give up until next time we set both speeds, and
2274  * then we want IBTA enabled as well as "use max enabled speed.
2275  */
2276 static void set_speed_fast(struct ipath_devdata *dd, u32 speed)
2277 {
2278         dd->ipath_ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
2279                 IBA7220_IBC_IBTA_1_2_MASK |
2280                 (IBA7220_IBC_WIDTH_MASK << IBA7220_IBC_WIDTH_SHIFT));
2281
2282         if (speed == (IPATH_IB_SDR | IPATH_IB_DDR))
2283                 dd->ipath_ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
2284                         IBA7220_IBC_IBTA_1_2_MASK;
2285         else
2286                 dd->ipath_ibcddrctrl |= speed == IPATH_IB_DDR ?
2287                         IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2288
2289         /*
2290          * Convert from IB-style 1 = 1x, 2 = 4x, 3 = auto
2291          * to chip-centric       0 = 1x, 1 = 4x, 2 = auto
2292          */
2293         dd->ipath_ibcddrctrl |= (u64)(dd->ipath_link_width_enabled - 1) <<
2294                 IBA7220_IBC_WIDTH_SHIFT;
2295         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2296                         dd->ipath_ibcddrctrl);
2297         ipath_cdbg(VERBOSE, "setup for IB speed (%x) done\n", speed);
2298 }
2299
2300
2301 /*
2302  * this routine is only used when we are not talking to another
2303  * IB 1.2-compliant device that we think can do DDR.
2304  * (This includes all existing switch chips as of Oct 2007.)
2305  * 1.2-compliant devices go directly to DDR prior to reaching INIT
2306  */
2307 static void try_auto_neg(struct ipath_devdata *dd)
2308 {
2309         /*
2310          * required for older non-IB1.2 DDR switches.  Newer
2311          * non-IB-compliant switches don't need it, but so far,
2312          * aren't bothered by it either.  "Magic constant"
2313          */
2314         ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl),
2315                 0x3b9dc07);
2316         dd->ipath_flags |= IPATH_IB_AUTONEG_INPROG;
2317         ipath_autoneg_send(dd, 0);
2318         set_speed_fast(dd, IPATH_IB_DDR);
2319         ipath_toggle_rclkrls(dd);
2320         /* 2 msec is minimum length of a poll cycle */
2321         schedule_delayed_work(&dd->ipath_autoneg_work,
2322                 msecs_to_jiffies(2));
2323 }
2324
2325
2326 static int ipath_7220_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
2327 {
2328         int ret = 0;
2329         u32 ltstate = ipath_ib_linkstate(dd, ibcs);
2330
2331         dd->ipath_link_width_active =
2332                 ((ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1) ?
2333                     IB_WIDTH_4X : IB_WIDTH_1X;
2334         dd->ipath_link_speed_active =
2335                 ((ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1) ?
2336                     IPATH_IB_DDR : IPATH_IB_SDR;
2337
2338         if (!ibup) {
2339                 /*
2340                  * when link goes down we don't want aeq running, so it
2341                  * won't't interfere with IBC training, etc., and we need
2342                  * to go back to the static SerDes preset values
2343                  */
2344                 if (dd->ipath_x1_fix_tries &&
2345                          ltstate <= INFINIPATH_IBCS_LT_STATE_SLEEPQUIET &&
2346                         ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP)
2347                         dd->ipath_x1_fix_tries = 0;
2348                 if (!(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2349                         IPATH_IB_AUTONEG_INPROG)))
2350                         set_speed_fast(dd, dd->ipath_link_speed_enabled);
2351                 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2352                         ipath_cdbg(VERBOSE, "Setting RXEQ defaults\n");
2353                         ipath_sd7220_presets(dd);
2354                 }
2355                 /* this might better in ipath_sd7220_presets() */
2356                 ipath_set_relock_poll(dd, ibup);
2357         } else {
2358                 if (ipath_compat_ddr_negotiate &&
2359                     !(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2360                         IPATH_IB_AUTONEG_INPROG)) &&
2361                         dd->ipath_link_speed_active == IPATH_IB_SDR &&
2362                         (dd->ipath_link_speed_enabled &
2363                             (IPATH_IB_DDR | IPATH_IB_SDR)) ==
2364                             (IPATH_IB_DDR | IPATH_IB_SDR) &&
2365                         dd->ipath_autoneg_tries < IPATH_AUTONEG_TRIES) {
2366                         /* we are SDR, and DDR auto-negotiation enabled */
2367                         ++dd->ipath_autoneg_tries;
2368                         ipath_dbg("DDR negotiation try, %u/%u\n",
2369                                 dd->ipath_autoneg_tries,
2370                                 IPATH_AUTONEG_TRIES);
2371                         try_auto_neg(dd);
2372                         ret = 1; /* no other IB status change processing */
2373                 } else if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
2374                         && dd->ipath_link_speed_active == IPATH_IB_SDR) {
2375                         ipath_autoneg_send(dd, 1);
2376                         set_speed_fast(dd, IPATH_IB_DDR);
2377                         udelay(2);
2378                         ipath_toggle_rclkrls(dd);
2379                         ret = 1; /* no other IB status change processing */
2380                 } else {
2381                         if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
2382                                 (dd->ipath_link_speed_active & IPATH_IB_DDR)) {
2383                                 ipath_dbg("Got to INIT with DDR autoneg\n");
2384                                 dd->ipath_flags &= ~(IPATH_IB_AUTONEG_INPROG
2385                                         | IPATH_IB_AUTONEG_FAILED);
2386                                 dd->ipath_autoneg_tries = 0;
2387                                 /* re-enable SDR, for next link down */
2388                                 set_speed_fast(dd,
2389                                         dd->ipath_link_speed_enabled);
2390                                 wake_up(&dd->ipath_autoneg_wait);
2391                         } else if (dd->ipath_flags & IPATH_IB_AUTONEG_FAILED) {
2392                                 /*
2393                                  * clear autoneg failure flag, and do setup
2394                                  * so we'll try next time link goes down and
2395                                  * back to INIT (possibly connected to different
2396                                  * device).
2397                                  */
2398                                 ipath_dbg("INIT %sDR after autoneg failure\n",
2399                                         (dd->ipath_link_speed_active &
2400                                           IPATH_IB_DDR) ? "D" : "S");
2401                                 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2402                                 dd->ipath_ibcddrctrl |=
2403                                         IBA7220_IBC_IBTA_1_2_MASK;
2404                                 ipath_write_kreg(dd,
2405                                         IPATH_KREG_OFFSET(IBNCModeCtrl), 0);
2406                         }
2407                 }
2408                 /*
2409                  * if we are in 1X, and are in autoneg width, it
2410                  * could be due to an xgxs problem, so if we haven't
2411                  * already tried, try twice to get to 4X; if we
2412                  * tried, and couldn't, report it, since it will
2413                  * probably not be what is desired.
2414                  */
2415                 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
2416                         IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X)
2417                         && dd->ipath_link_width_active == IB_WIDTH_1X
2418                         && dd->ipath_x1_fix_tries < 3) {
2419                         if (++dd->ipath_x1_fix_tries == 3)
2420                                 dev_info(&dd->pcidev->dev,
2421                                         "IB link is in 1X mode\n");
2422                         else {
2423                                 ipath_cdbg(VERBOSE, "IB 1X in "
2424                                         "auto-width, try %u to be "
2425                                         "sure it's really 1X; "
2426                                         "ltstate %u\n",
2427                                          dd->ipath_x1_fix_tries,
2428                                          ltstate);
2429                                 dd->ipath_f_xgxs_reset(dd);
2430                                 ret = 1; /* skip other processing */
2431                         }
2432                 }
2433
2434                 if (!ret) {
2435                         dd->delay_mult = rate_to_delay
2436                             [(ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1]
2437                             [(ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1];
2438
2439                         ipath_set_relock_poll(dd, ibup);
2440                 }
2441         }
2442
2443         if (!ret)
2444                 ipath_setup_7220_setextled(dd, ipath_ib_linkstate(dd, ibcs),
2445                         ltstate);
2446         return ret;
2447 }
2448
2449
2450 /*
2451  * Handle the empirically determined mechanism for auto-negotiation
2452  * of DDR speed with switches.
2453  */
2454 static void autoneg_work(struct work_struct *work)
2455 {
2456         struct ipath_devdata *dd;
2457         u64 startms;
2458         u32 lastlts, i;
2459
2460         dd = container_of(work, struct ipath_devdata,
2461                 ipath_autoneg_work.work);
2462
2463         startms = jiffies_to_msecs(jiffies);
2464
2465         /*
2466          * busy wait for this first part, it should be at most a
2467          * few hundred usec, since we scheduled ourselves for 2msec.
2468          */
2469         for (i = 0; i < 25; i++) {
2470                 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
2471                 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
2472                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN_DISABLE);
2473                         break;
2474                 }
2475                 udelay(100);
2476         }
2477
2478         if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2479                 goto done; /* we got there early or told to stop */
2480
2481         /* we expect this to timeout */
2482         if (wait_event_timeout(dd->ipath_autoneg_wait,
2483                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2484                 msecs_to_jiffies(90)))
2485                 goto done;
2486
2487         ipath_toggle_rclkrls(dd);
2488
2489         /* we expect this to timeout */
2490         if (wait_event_timeout(dd->ipath_autoneg_wait,
2491                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2492                 msecs_to_jiffies(1700)))
2493                 goto done;
2494
2495         set_speed_fast(dd, IPATH_IB_SDR);
2496         ipath_toggle_rclkrls(dd);
2497
2498         /*
2499          * wait up to 250 msec for link to train and get to INIT at DDR;
2500          * this should terminate early
2501          */
2502         wait_event_timeout(dd->ipath_autoneg_wait,
2503                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2504                 msecs_to_jiffies(250));
2505 done:
2506         if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
2507                 ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
2508                         ipath_ib_state(dd, dd->ipath_lastibcstat),
2509                         (unsigned long long) jiffies_to_msecs(jiffies)-startms);
2510                 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
2511                 if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
2512                         dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
2513                         ipath_dbg("Giving up on DDR until next IB "
2514                                 "link Down\n");
2515                         dd->ipath_autoneg_tries = 0;
2516                 }
2517                 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2518         }
2519 }
2520
2521
2522 /**
2523  * ipath_init_iba7220_funcs - set up the chip-specific function pointers
2524  * @dd: the infinipath device
2525  *
2526  * This is global, and is called directly at init to set up the
2527  * chip-specific function pointers for later use.
2528  */
2529 void ipath_init_iba7220_funcs(struct ipath_devdata *dd)
2530 {
2531         dd->ipath_f_intrsetup = ipath_7220_intconfig;
2532         dd->ipath_f_bus = ipath_setup_7220_config;
2533         dd->ipath_f_reset = ipath_setup_7220_reset;
2534         dd->ipath_f_get_boardname = ipath_7220_boardname;
2535         dd->ipath_f_init_hwerrors = ipath_7220_init_hwerrors;
2536         dd->ipath_f_early_init = ipath_7220_early_init;
2537         dd->ipath_f_handle_hwerrors = ipath_7220_handle_hwerrors;
2538         dd->ipath_f_quiet_serdes = ipath_7220_quiet_serdes;
2539         dd->ipath_f_bringup_serdes = ipath_7220_bringup_serdes;
2540         dd->ipath_f_clear_tids = ipath_7220_clear_tids;
2541         dd->ipath_f_put_tid = ipath_7220_put_tid;
2542         dd->ipath_f_cleanup = ipath_setup_7220_cleanup;
2543         dd->ipath_f_setextled = ipath_setup_7220_setextled;
2544         dd->ipath_f_get_base_info = ipath_7220_get_base_info;
2545         dd->ipath_f_free_irq = ipath_7220_free_irq;
2546         dd->ipath_f_tidtemplate = ipath_7220_tidtemplate;
2547         dd->ipath_f_intr_fallback = ipath_7220_intr_fallback;
2548         dd->ipath_f_xgxs_reset = ipath_7220_xgxs_reset;
2549         dd->ipath_f_get_ib_cfg = ipath_7220_get_ib_cfg;
2550         dd->ipath_f_set_ib_cfg = ipath_7220_set_ib_cfg;
2551         dd->ipath_f_config_jint = ipath_7220_config_jint;
2552         dd->ipath_f_config_ports = ipath_7220_config_ports;
2553         dd->ipath_f_read_counters = ipath_7220_read_counters;
2554         dd->ipath_f_get_msgheader = ipath_7220_get_msgheader;
2555         dd->ipath_f_ib_updown = ipath_7220_ib_updown;
2556
2557         /* initialize chip-specific variables */
2558         ipath_init_7220_variables(dd);
2559 }