[PATCH] Fix oops in pata_pcmcia
[linux-2.6.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39
40 #include "cxio_resource.h"
41 #include "cxio_hal.h"
42 #include "cxgb3_offload.h"
43 #include "sge_defs.h"
44
45 static LIST_HEAD(rdev_list);
46 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
47
48 static inline struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
49 {
50         struct cxio_rdev *rdev;
51
52         list_for_each_entry(rdev, &rdev_list, entry)
53                 if (!strcmp(rdev->dev_name, dev_name))
54                         return rdev;
55         return NULL;
56 }
57
58 static inline struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev
59                                                              *tdev)
60 {
61         struct cxio_rdev *rdev;
62
63         list_for_each_entry(rdev, &rdev_list, entry)
64                 if (rdev->t3cdev_p == tdev)
65                         return rdev;
66         return NULL;
67 }
68
69 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
70                    enum t3_cq_opcode op, u32 credit)
71 {
72         int ret;
73         struct t3_cqe *cqe;
74         u32 rptr;
75
76         struct rdma_cq_op setup;
77         setup.id = cq->cqid;
78         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
79         setup.op = op;
80         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
81
82         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
83                 return ret;
84
85         /*
86          * If the rearm returned an index other than our current index,
87          * then there might be CQE's in flight (being DMA'd).  We must wait
88          * here for them to complete or the consumer can miss a notification.
89          */
90         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
91                 int i=0;
92
93                 rptr = cq->rptr;
94
95                 /*
96                  * Keep the generation correct by bumping rptr until it
97                  * matches the index returned by the rearm - 1.
98                  */
99                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
100                         rptr++;
101
102                 /*
103                  * Now rptr is the index for the (last) cqe that was
104                  * in-flight at the time the HW rearmed the CQ.  We
105                  * spin until that CQE is valid.
106                  */
107                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
108                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
109                         udelay(1);
110                         if (i++ > 1000000) {
111                                 BUG_ON(1);
112                                 printk(KERN_ERR "%s: stalled rnic\n",
113                                        rdev_p->dev_name);
114                                 return -EIO;
115                         }
116                 }
117         }
118         return 0;
119 }
120
121 static inline int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
122 {
123         struct rdma_cq_setup setup;
124         setup.id = cqid;
125         setup.base_addr = 0;    /* NULL address */
126         setup.size = 0;         /* disaable the CQ */
127         setup.credits = 0;
128         setup.credit_thres = 0;
129         setup.ovfl_mode = 0;
130         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
131 }
132
133 int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
134 {
135         u64 sge_cmd;
136         struct t3_modify_qp_wr *wqe;
137         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
138         if (!skb) {
139                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
140                 return -ENOMEM;
141         }
142         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
143         memset(wqe, 0, sizeof(*wqe));
144         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 1, qpid, 7);
145         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
146         sge_cmd = qpid << 8 | 3;
147         wqe->sge_cmd = cpu_to_be64(sge_cmd);
148         skb->priority = CPL_PRIORITY_CONTROL;
149         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
150 }
151
152 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
153 {
154         struct rdma_cq_setup setup;
155         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
156
157         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
158         if (!cq->cqid)
159                 return -ENOMEM;
160         cq->sw_queue = kzalloc(size, GFP_KERNEL);
161         if (!cq->sw_queue)
162                 return -ENOMEM;
163         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
164                                              (1UL << (cq->size_log2)) *
165                                              sizeof(struct t3_cqe),
166                                              &(cq->dma_addr), GFP_KERNEL);
167         if (!cq->queue) {
168                 kfree(cq->sw_queue);
169                 return -ENOMEM;
170         }
171         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
172         memset(cq->queue, 0, size);
173         setup.id = cq->cqid;
174         setup.base_addr = (u64) (cq->dma_addr);
175         setup.size = 1UL << cq->size_log2;
176         setup.credits = 65535;
177         setup.credit_thres = 1;
178         if (rdev_p->t3cdev_p->type == T3B)
179                 setup.ovfl_mode = 0;
180         else
181                 setup.ovfl_mode = 1;
182         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
183 }
184
185 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
186 {
187         struct rdma_cq_setup setup;
188         setup.id = cq->cqid;
189         setup.base_addr = (u64) (cq->dma_addr);
190         setup.size = 1UL << cq->size_log2;
191         setup.credits = setup.size;
192         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
193         setup.ovfl_mode = 1;
194         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
195 }
196
197 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
198 {
199         struct cxio_qpid_list *entry;
200         u32 qpid;
201         int i;
202
203         mutex_lock(&uctx->lock);
204         if (!list_empty(&uctx->qpids)) {
205                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
206                                    entry);
207                 list_del(&entry->entry);
208                 qpid = entry->qpid;
209                 kfree(entry);
210         } else {
211                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
212                 if (!qpid)
213                         goto out;
214                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
215                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
216                         if (!entry)
217                                 break;
218                         entry->qpid = i;
219                         list_add_tail(&entry->entry, &uctx->qpids);
220                 }
221         }
222 out:
223         mutex_unlock(&uctx->lock);
224         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
225         return qpid;
226 }
227
228 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
229                      struct cxio_ucontext *uctx)
230 {
231         struct cxio_qpid_list *entry;
232
233         entry = kmalloc(sizeof *entry, GFP_KERNEL);
234         if (!entry)
235                 return;
236         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
237         entry->qpid = qpid;
238         mutex_lock(&uctx->lock);
239         list_add_tail(&entry->entry, &uctx->qpids);
240         mutex_unlock(&uctx->lock);
241 }
242
243 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
244 {
245         struct list_head *pos, *nxt;
246         struct cxio_qpid_list *entry;
247
248         mutex_lock(&uctx->lock);
249         list_for_each_safe(pos, nxt, &uctx->qpids) {
250                 entry = list_entry(pos, struct cxio_qpid_list, entry);
251                 list_del_init(&entry->entry);
252                 if (!(entry->qpid & rdev_p->qpmask))
253                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
254                 kfree(entry);
255         }
256         mutex_unlock(&uctx->lock);
257 }
258
259 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
260 {
261         INIT_LIST_HEAD(&uctx->qpids);
262         mutex_init(&uctx->lock);
263 }
264
265 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
266                    struct t3_wq *wq, struct cxio_ucontext *uctx)
267 {
268         int depth = 1UL << wq->size_log2;
269         int rqsize = 1UL << wq->rq_size_log2;
270
271         wq->qpid = get_qpid(rdev_p, uctx);
272         if (!wq->qpid)
273                 return -ENOMEM;
274
275         wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
276         if (!wq->rq)
277                 goto err1;
278
279         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
280         if (!wq->rq_addr)
281                 goto err2;
282
283         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
284         if (!wq->sq)
285                 goto err3;
286
287         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
288                                              depth * sizeof(union t3_wr),
289                                              &(wq->dma_addr), GFP_KERNEL);
290         if (!wq->queue)
291                 goto err4;
292
293         memset(wq->queue, 0, depth * sizeof(union t3_wr));
294         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
295         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
296         if (!kernel_domain)
297                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
298                                         (wq->qpid << rdev_p->qpshift);
299         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __FUNCTION__,
300              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
301         return 0;
302 err4:
303         kfree(wq->sq);
304 err3:
305         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
306 err2:
307         kfree(wq->rq);
308 err1:
309         put_qpid(rdev_p, wq->qpid, uctx);
310         return -ENOMEM;
311 }
312
313 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
314 {
315         int err;
316         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
317         kfree(cq->sw_queue);
318         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
319                           (1UL << (cq->size_log2))
320                           * sizeof(struct t3_cqe), cq->queue,
321                           pci_unmap_addr(cq, mapping));
322         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
323         return err;
324 }
325
326 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
327                     struct cxio_ucontext *uctx)
328 {
329         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
330                           (1UL << (wq->size_log2))
331                           * sizeof(union t3_wr), wq->queue,
332                           pci_unmap_addr(wq, mapping));
333         kfree(wq->sq);
334         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
335         kfree(wq->rq);
336         put_qpid(rdev_p, wq->qpid, uctx);
337         return 0;
338 }
339
340 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
341 {
342         struct t3_cqe cqe;
343
344         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
345              wq, cq, cq->sw_rptr, cq->sw_wptr);
346         memset(&cqe, 0, sizeof(cqe));
347         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
348                                  V_CQE_OPCODE(T3_SEND) |
349                                  V_CQE_TYPE(0) |
350                                  V_CQE_SWCQE(1) |
351                                  V_CQE_QPID(wq->qpid) |
352                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
353                                                        cq->size_log2)));
354         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
355         cq->sw_wptr++;
356 }
357
358 void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
359 {
360         u32 ptr;
361
362         PDBG("%s wq %p cq %p\n", __FUNCTION__, wq, cq);
363
364         /* flush RQ */
365         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __FUNCTION__,
366             wq->rq_rptr, wq->rq_wptr, count);
367         ptr = wq->rq_rptr + count;
368         while (ptr++ != wq->rq_wptr)
369                 insert_recv_cqe(wq, cq);
370 }
371
372 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
373                           struct t3_swsq *sqp)
374 {
375         struct t3_cqe cqe;
376
377         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
378              wq, cq, cq->sw_rptr, cq->sw_wptr);
379         memset(&cqe, 0, sizeof(cqe));
380         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
381                                  V_CQE_OPCODE(sqp->opcode) |
382                                  V_CQE_TYPE(1) |
383                                  V_CQE_SWCQE(1) |
384                                  V_CQE_QPID(wq->qpid) |
385                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
386                                                        cq->size_log2)));
387         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
388
389         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
390         cq->sw_wptr++;
391 }
392
393 void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
394 {
395         __u32 ptr;
396         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
397
398         ptr = wq->sq_rptr + count;
399         sqp += count;
400         while (ptr != wq->sq_wptr) {
401                 insert_sq_cqe(wq, cq, sqp);
402                 sqp++;
403                 ptr++;
404         }
405 }
406
407 /*
408  * Move all CQEs from the HWCQ into the SWCQ.
409  */
410 void cxio_flush_hw_cq(struct t3_cq *cq)
411 {
412         struct t3_cqe *cqe, *swcqe;
413
414         PDBG("%s cq %p cqid 0x%x\n", __FUNCTION__, cq, cq->cqid);
415         cqe = cxio_next_hw_cqe(cq);
416         while (cqe) {
417                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
418                      __FUNCTION__, cq->rptr, cq->sw_wptr);
419                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
420                 *swcqe = *cqe;
421                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
422                 cq->sw_wptr++;
423                 cq->rptr++;
424                 cqe = cxio_next_hw_cqe(cq);
425         }
426 }
427
428 static inline int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
429 {
430         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
431                 return 0;
432
433         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
434                 return 0;
435
436         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
437                 return 0;
438
439         if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) &&
440             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
441                 return 0;
442
443         return 1;
444 }
445
446 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
447 {
448         struct t3_cqe *cqe;
449         u32 ptr;
450
451         *count = 0;
452         ptr = cq->sw_rptr;
453         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
454                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
455                 if ((SQ_TYPE(*cqe) || (CQE_OPCODE(*cqe) == T3_READ_RESP)) &&
456                     (CQE_QPID(*cqe) == wq->qpid))
457                         (*count)++;
458                 ptr++;
459         }
460         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
461 }
462
463 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
464 {
465         struct t3_cqe *cqe;
466         u32 ptr;
467
468         *count = 0;
469         PDBG("%s count zero %d\n", __FUNCTION__, *count);
470         ptr = cq->sw_rptr;
471         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
472                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
473                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
474                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
475                         (*count)++;
476                 ptr++;
477         }
478         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
479 }
480
481 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
482 {
483         struct rdma_cq_setup setup;
484         setup.id = 0;
485         setup.base_addr = 0;    /* NULL address */
486         setup.size = 1;         /* enable the CQ */
487         setup.credits = 0;
488
489         /* force SGE to redirect to RspQ and interrupt */
490         setup.credit_thres = 0;
491         setup.ovfl_mode = 1;
492         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
493 }
494
495 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
496 {
497         int err;
498         u64 sge_cmd, ctx0, ctx1;
499         u64 base_addr;
500         struct t3_modify_qp_wr *wqe;
501         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
502
503
504         if (!skb) {
505                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
506                 return -ENOMEM;
507         }
508         err = cxio_hal_init_ctrl_cq(rdev_p);
509         if (err) {
510                 PDBG("%s err %d initializing ctrl_cq\n", __FUNCTION__, err);
511                 return err;
512         }
513         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
514                                         &(rdev_p->rnic_info.pdev->dev),
515                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
516                                         sizeof(union t3_wr),
517                                         &(rdev_p->ctrl_qp.dma_addr),
518                                         GFP_KERNEL);
519         if (!rdev_p->ctrl_qp.workq) {
520                 PDBG("%s dma_alloc_coherent failed\n", __FUNCTION__);
521                 return -ENOMEM;
522         }
523         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
524                            rdev_p->ctrl_qp.dma_addr);
525         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
526         memset(rdev_p->ctrl_qp.workq, 0,
527                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
528
529         mutex_init(&rdev_p->ctrl_qp.lock);
530         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
531
532         /* update HW Ctrl QP context */
533         base_addr = rdev_p->ctrl_qp.dma_addr;
534         base_addr >>= 12;
535         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
536                 V_EC_BASE_LO((u32) base_addr & 0xffff));
537         ctx0 <<= 32;
538         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
539         base_addr >>= 16;
540         ctx1 = (u32) base_addr;
541         base_addr >>= 32;
542         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
543                         V_EC_TYPE(0) | V_EC_GEN(1) |
544                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
545         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
546         memset(wqe, 0, sizeof(*wqe));
547         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 1,
548                        T3_CTL_QP_TID, 7);
549         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
550         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
551         wqe->sge_cmd = cpu_to_be64(sge_cmd);
552         wqe->ctx1 = cpu_to_be64(ctx1);
553         wqe->ctx0 = cpu_to_be64(ctx0);
554         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
555              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
556              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
557         skb->priority = CPL_PRIORITY_CONTROL;
558         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
559 }
560
561 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
562 {
563         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
564                           (1UL << T3_CTRL_QP_SIZE_LOG2)
565                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
566                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
567         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
568 }
569
570 /* write len bytes of data into addr (32B aligned address)
571  * If data is NULL, clear len byte of memory to zero.
572  * caller aquires the ctrl_qp lock before the call
573  */
574 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
575                                       u32 len, void *data, int completion)
576 {
577         u32 i, nr_wqe, copy_len;
578         u8 *copy_data;
579         u8 wr_len, utx_len;     /* lenght in 8 byte flit */
580         enum t3_wr_flags flag;
581         __be64 *wqe;
582         u64 utx_cmd;
583         addr &= 0x7FFFFFF;
584         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
585         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
586              __FUNCTION__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
587              nr_wqe, data, addr);
588         utx_len = 3;            /* in 32B unit */
589         for (i = 0; i < nr_wqe; i++) {
590                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
591                            T3_CTRL_QP_SIZE_LOG2)) {
592                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
593                              "wait for more space i %d\n", __FUNCTION__,
594                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
595                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
596                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
597                                                      rdev_p->ctrl_qp.wptr,
598                                                      T3_CTRL_QP_SIZE_LOG2))) {
599                                 PDBG("%s ctrl_qp workq interrupted\n",
600                                      __FUNCTION__);
601                                 return -ERESTARTSYS;
602                         }
603                         PDBG("%s ctrl_qp wakeup, continue posting work request "
604                              "i %d\n", __FUNCTION__, i);
605                 }
606                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
607                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
608                 flag = 0;
609                 if (i == (nr_wqe - 1)) {
610                         /* last WQE */
611                         flag = completion ? T3_COMPLETION_FLAG : 0;
612                         if (len % 32)
613                                 utx_len = len / 32 + 1;
614                         else
615                                 utx_len = len / 32;
616                 }
617
618                 /*
619                  * Force a CQE to return the credit to the workq in case
620                  * we posted more than half the max QP size of WRs
621                  */
622                 if ((i != 0) &&
623                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
624                         flag = T3_COMPLETION_FLAG;
625                         PDBG("%s force completion at i %d\n", __FUNCTION__, i);
626                 }
627
628                 /* build the utx mem command */
629                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
630                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
631                 utx_cmd <<= 32;
632                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
633                 *wqe = cpu_to_be64(utx_cmd);
634                 wqe++;
635                 copy_data = (u8 *) data + i * 96;
636                 copy_len = len > 96 ? 96 : len;
637
638                 /* clear memory content if data is NULL */
639                 if (data)
640                         memcpy(wqe, copy_data, copy_len);
641                 else
642                         memset(wqe, 0, copy_len);
643                 if (copy_len % 32)
644                         memset(((u8 *) wqe) + copy_len, 0,
645                                32 - (copy_len % 32));
646                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
647                          (utx_len << 2);
648                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
649                               (1 << T3_CTRL_QP_SIZE_LOG2)));
650
651                 /* wptr in the WRID[31:0] */
652                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
653
654                 /*
655                  * This must be the last write with a memory barrier
656                  * for the genbit
657                  */
658                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
659                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
660                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
661                                wr_len);
662                 if (flag == T3_COMPLETION_FLAG)
663                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
664                 len -= 96;
665                 rdev_p->ctrl_qp.wptr++;
666         }
667         return 0;
668 }
669
670 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size
671  * OUT: stag index, actual pbl_size, pbl_addr allocated.
672  * TBD: shared memory region support
673  */
674 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
675                          u32 *stag, u8 stag_state, u32 pdid,
676                          enum tpt_mem_type type, enum tpt_mem_perm perm,
677                          u32 zbva, u64 to, u32 len, u8 page_size, __be64 *pbl,
678                          u32 *pbl_size, u32 *pbl_addr)
679 {
680         int err;
681         struct tpt_entry tpt;
682         u32 stag_idx;
683         u32 wptr;
684         int rereg = (*stag != T3_STAG_UNSET);
685
686         stag_state = stag_state > 0;
687         stag_idx = (*stag) >> 8;
688
689         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
690                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
691                 if (!stag_idx)
692                         return -ENOMEM;
693                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
694         }
695         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
696              __FUNCTION__, stag_state, type, pdid, stag_idx);
697
698         if (reset_tpt_entry)
699                 cxio_hal_pblpool_free(rdev_p, *pbl_addr, *pbl_size << 3);
700         else if (!rereg) {
701                 *pbl_addr = cxio_hal_pblpool_alloc(rdev_p, *pbl_size << 3);
702                 if (!*pbl_addr) {
703                         return -ENOMEM;
704                 }
705         }
706
707         mutex_lock(&rdev_p->ctrl_qp.lock);
708
709         /* write PBL first if any - update pbl only if pbl list exist */
710         if (pbl) {
711
712                 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
713                      __FUNCTION__, *pbl_addr, rdev_p->rnic_info.pbl_base,
714                      *pbl_size);
715                 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
716                                 (*pbl_addr >> 5),
717                                 (*pbl_size << 3), pbl, 0);
718                 if (err)
719                         goto ret;
720         }
721
722         /* write TPT entry */
723         if (reset_tpt_entry)
724                 memset(&tpt, 0, sizeof(tpt));
725         else {
726                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
727                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
728                                 V_TPT_STAG_STATE(stag_state) |
729                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
730                 BUG_ON(page_size >= 28);
731                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
732                                 F_TPT_MW_BIND_ENABLE |
733                                 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
734                                 V_TPT_PAGE_SIZE(page_size));
735                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
736                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, *pbl_addr)>>3));
737                 tpt.len = cpu_to_be32(len);
738                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
739                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
740                 tpt.rsvd_bind_cnt_or_pstag = 0;
741                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
742                                   cpu_to_be32(V_TPT_PBL_SIZE((*pbl_size) >> 2));
743         }
744         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
745                                        stag_idx +
746                                        (rdev_p->rnic_info.tpt_base >> 5),
747                                        sizeof(tpt), &tpt, 1);
748
749         /* release the stag index to free pool */
750         if (reset_tpt_entry)
751                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
752 ret:
753         wptr = rdev_p->ctrl_qp.wptr;
754         mutex_unlock(&rdev_p->ctrl_qp.lock);
755         if (!err)
756                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
757                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
758                                                       wptr)))
759                         return -ERESTARTSYS;
760         return err;
761 }
762
763 /* IN : stag key, pdid, pbl_size
764  * Out: stag index, actaul pbl_size, and pbl_addr allocated.
765  */
766 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid,
767                        enum tpt_mem_perm perm, u32 * pbl_size, u32 * pbl_addr)
768 {
769         *stag = T3_STAG_UNSET;
770         return (__cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
771                               perm, 0, 0ULL, 0, 0, NULL, pbl_size, pbl_addr));
772 }
773
774 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
775                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
776                            u8 page_size, __be64 *pbl, u32 *pbl_size,
777                            u32 *pbl_addr)
778 {
779         *stag = T3_STAG_UNSET;
780         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
781                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
782 }
783
784 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
785                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
786                            u8 page_size, __be64 *pbl, u32 *pbl_size,
787                            u32 *pbl_addr)
788 {
789         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
790                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
791 }
792
793 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
794                    u32 pbl_addr)
795 {
796         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
797                              &pbl_size, &pbl_addr);
798 }
799
800 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
801 {
802         u32 pbl_size = 0;
803         *stag = T3_STAG_UNSET;
804         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
805                              NULL, &pbl_size, NULL);
806 }
807
808 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
809 {
810         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
811                              NULL, NULL);
812 }
813
814 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
815 {
816         struct t3_rdma_init_wr *wqe;
817         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
818         if (!skb)
819                 return -ENOMEM;
820         PDBG("%s rdev_p %p\n", __FUNCTION__, rdev_p);
821         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
822         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
823         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
824                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
825         wqe->wrid.id1 = 0;
826         wqe->qpid = cpu_to_be32(attr->qpid);
827         wqe->pdid = cpu_to_be32(attr->pdid);
828         wqe->scqid = cpu_to_be32(attr->scqid);
829         wqe->rcqid = cpu_to_be32(attr->rcqid);
830         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
831         wqe->rq_size = cpu_to_be32(attr->rq_size);
832         wqe->mpaattrs = attr->mpaattrs;
833         wqe->qpcaps = attr->qpcaps;
834         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
835         wqe->flags = cpu_to_be32(attr->flags);
836         wqe->ord = cpu_to_be32(attr->ord);
837         wqe->ird = cpu_to_be32(attr->ird);
838         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
839         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
840         wqe->rsvd = 0;
841         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
842         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
843 }
844
845 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
846 {
847         cxio_ev_cb = ev_cb;
848 }
849
850 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
851 {
852         cxio_ev_cb = NULL;
853 }
854
855 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
856 {
857         static int cnt;
858         struct cxio_rdev *rdev_p = NULL;
859         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
860         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
861              " se %0x notify %0x cqbranch %0x creditth %0x\n",
862              cnt, __FUNCTION__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
863              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
864              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
865              RSPQ_CREDIT_THRESH(rsp_msg));
866         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
867              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
868              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
869              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
870              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
871              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
872         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
873         if (!rdev_p) {
874                 PDBG("%s called by t3cdev %p with null ulp\n", __FUNCTION__,
875                      t3cdev_p);
876                 return 0;
877         }
878         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
879                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
880                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
881                 dev_kfree_skb_irq(skb);
882         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
883                 dev_kfree_skb_irq(skb);
884         else if (cxio_ev_cb)
885                 (*cxio_ev_cb) (rdev_p, skb);
886         else
887                 dev_kfree_skb_irq(skb);
888         cnt++;
889         return 0;
890 }
891
892 /* Caller takes care of locking if needed */
893 int cxio_rdev_open(struct cxio_rdev *rdev_p)
894 {
895         struct net_device *netdev_p = NULL;
896         int err = 0;
897         if (strlen(rdev_p->dev_name)) {
898                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
899                         return -EBUSY;
900                 }
901                 netdev_p = dev_get_by_name(rdev_p->dev_name);
902                 if (!netdev_p) {
903                         return -EINVAL;
904                 }
905                 dev_put(netdev_p);
906         } else if (rdev_p->t3cdev_p) {
907                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
908                         return -EBUSY;
909                 }
910                 netdev_p = rdev_p->t3cdev_p->lldev;
911                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
912                         T3_MAX_DEV_NAME_LEN);
913         } else {
914                 PDBG("%s t3cdev_p or dev_name must be set\n", __FUNCTION__);
915                 return -EINVAL;
916         }
917
918         list_add_tail(&rdev_p->entry, &rdev_list);
919
920         PDBG("%s opening rnic dev %s\n", __FUNCTION__, rdev_p->dev_name);
921         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
922         if (!rdev_p->t3cdev_p)
923                 rdev_p->t3cdev_p = T3CDEV(netdev_p);
924         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
925         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
926                                          &(rdev_p->rnic_info));
927         if (err) {
928                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
929                      __FUNCTION__, rdev_p->t3cdev_p, err);
930                 goto err1;
931         }
932         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
933                                     &(rdev_p->port_info));
934         if (err) {
935                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
936                      __FUNCTION__, rdev_p->t3cdev_p, err);
937                 goto err1;
938         }
939
940         /*
941          * qpshift is the number of bits to shift the qpid left in order
942          * to get the correct address of the doorbell for that qp.
943          */
944         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
945         rdev_p->qpshift = PAGE_SHIFT -
946                           ilog2(65536 >>
947                                     ilog2(rdev_p->rnic_info.udbell_len >>
948                                               PAGE_SHIFT));
949         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
950         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
951         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
952              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
953              __FUNCTION__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
954              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
955              rdev_p->rnic_info.pbl_base,
956              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
957              rdev_p->rnic_info.rqt_top);
958         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
959              "qpnr %d qpmask 0x%x\n",
960              rdev_p->rnic_info.udbell_len,
961              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
962              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
963
964         err = cxio_hal_init_ctrl_qp(rdev_p);
965         if (err) {
966                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
967                        __FUNCTION__, err);
968                 goto err1;
969         }
970         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
971                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
972                                      T3_MAX_NUM_PD);
973         if (err) {
974                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
975                        __FUNCTION__, err);
976                 goto err2;
977         }
978         err = cxio_hal_pblpool_create(rdev_p);
979         if (err) {
980                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
981                        __FUNCTION__, err);
982                 goto err3;
983         }
984         err = cxio_hal_rqtpool_create(rdev_p);
985         if (err) {
986                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
987                        __FUNCTION__, err);
988                 goto err4;
989         }
990         return 0;
991 err4:
992         cxio_hal_pblpool_destroy(rdev_p);
993 err3:
994         cxio_hal_destroy_resource(rdev_p->rscp);
995 err2:
996         cxio_hal_destroy_ctrl_qp(rdev_p);
997 err1:
998         list_del(&rdev_p->entry);
999         return err;
1000 }
1001
1002 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1003 {
1004         if (rdev_p) {
1005                 cxio_hal_pblpool_destroy(rdev_p);
1006                 cxio_hal_rqtpool_destroy(rdev_p);
1007                 list_del(&rdev_p->entry);
1008                 rdev_p->t3cdev_p->ulp = NULL;
1009                 cxio_hal_destroy_ctrl_qp(rdev_p);
1010                 cxio_hal_destroy_resource(rdev_p->rscp);
1011         }
1012 }
1013
1014 int __init cxio_hal_init(void)
1015 {
1016         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1017                 return -ENOMEM;
1018         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1019         return 0;
1020 }
1021
1022 void __exit cxio_hal_exit(void)
1023 {
1024         struct cxio_rdev *rdev, *tmp;
1025
1026         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1027         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1028                 cxio_rdev_close(rdev);
1029         cxio_hal_destroy_rhdl_resource();
1030 }
1031
1032 static inline void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1033 {
1034         struct t3_swsq *sqp;
1035         __u32 ptr = wq->sq_rptr;
1036         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1037
1038         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1039         while (count--)
1040                 if (!sqp->signaled) {
1041                         ptr++;
1042                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1043                 } else if (sqp->complete) {
1044
1045                         /*
1046                          * Insert this completed cqe into the swcq.
1047                          */
1048                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1049                              __FUNCTION__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1050                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1051                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1052                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1053                                 = sqp->cqe;
1054                         cq->sw_wptr++;
1055                         sqp->signaled = 0;
1056                         break;
1057                 } else
1058                         break;
1059 }
1060
1061 static inline void create_read_req_cqe(struct t3_wq *wq,
1062                                        struct t3_cqe *hw_cqe,
1063                                        struct t3_cqe *read_cqe)
1064 {
1065         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1066         read_cqe->len = wq->oldest_read->read_len;
1067         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1068                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1069                                  V_CQE_OPCODE(T3_READ_REQ) |
1070                                  V_CQE_TYPE(1));
1071 }
1072
1073 /*
1074  * Return a ptr to the next read wr in the SWSQ or NULL.
1075  */
1076 static inline void advance_oldest_read(struct t3_wq *wq)
1077 {
1078
1079         u32 rptr = wq->oldest_read - wq->sq + 1;
1080         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1081
1082         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1083                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1084
1085                 if (wq->oldest_read->opcode == T3_READ_REQ)
1086                         return;
1087                 rptr++;
1088         }
1089         wq->oldest_read = NULL;
1090 }
1091
1092 /*
1093  * cxio_poll_cq
1094  *
1095  * Caller must:
1096  *     check the validity of the first CQE,
1097  *     supply the wq assicated with the qpid.
1098  *
1099  * credit: cq credit to return to sge.
1100  * cqe_flushed: 1 iff the CQE is flushed.
1101  * cqe: copy of the polled CQE.
1102  *
1103  * return value:
1104  *     0       CQE returned,
1105  *    -1       CQE skipped, try again.
1106  */
1107 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1108                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1109 {
1110         int ret = 0;
1111         struct t3_cqe *hw_cqe, read_cqe;
1112
1113         *cqe_flushed = 0;
1114         *credit = 0;
1115         hw_cqe = cxio_next_cqe(cq);
1116
1117         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1118              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1119              __FUNCTION__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1120              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1121              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1122              CQE_WRID_LOW(*hw_cqe));
1123
1124         /*
1125          * skip cqe's not affiliated with a QP.
1126          */
1127         if (wq == NULL) {
1128                 ret = -1;
1129                 goto skip_cqe;
1130         }
1131
1132         /*
1133          * Gotta tweak READ completions:
1134          *      1) the cqe doesn't contain the sq_wptr from the wr.
1135          *      2) opcode not reflected from the wr.
1136          *      3) read_len not reflected from the wr.
1137          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1138          */
1139         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1140
1141                 /*
1142                  * Don't write to the HWCQ, so create a new read req CQE
1143                  * in local memory.
1144                  */
1145                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1146                 hw_cqe = &read_cqe;
1147                 advance_oldest_read(wq);
1148         }
1149
1150         /*
1151          * T3A: Discard TERMINATE CQEs.
1152          */
1153         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1154                 ret = -1;
1155                 wq->error = 1;
1156                 goto skip_cqe;
1157         }
1158
1159         if (CQE_STATUS(*hw_cqe) || wq->error) {
1160                 *cqe_flushed = wq->error;
1161                 wq->error = 1;
1162
1163                 /*
1164                  * T3A inserts errors into the CQE.  We cannot return
1165                  * these as work completions.
1166                  */
1167                 /* incoming write failures */
1168                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1169                      && RQ_TYPE(*hw_cqe)) {
1170                         ret = -1;
1171                         goto skip_cqe;
1172                 }
1173                 /* incoming read request failures */
1174                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1175                         ret = -1;
1176                         goto skip_cqe;
1177                 }
1178
1179                 /* incoming SEND with no receive posted failures */
1180                 if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) &&
1181                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1182                         ret = -1;
1183                         goto skip_cqe;
1184                 }
1185                 goto proc_cqe;
1186         }
1187
1188         /*
1189          * RECV completion.
1190          */
1191         if (RQ_TYPE(*hw_cqe)) {
1192
1193                 /*
1194                  * HW only validates 4 bits of MSN.  So we must validate that
1195                  * the MSN in the SEND is the next expected MSN.  If its not,
1196                  * then we complete this with TPT_ERR_MSN and mark the wq in
1197                  * error.
1198                  */
1199                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1200                         wq->error = 1;
1201                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1202                         goto proc_cqe;
1203                 }
1204                 goto proc_cqe;
1205         }
1206
1207         /*
1208          * If we get here its a send completion.
1209          *
1210          * Handle out of order completion. These get stuffed
1211          * in the SW SQ. Then the SW SQ is walked to move any
1212          * now in-order completions into the SW CQ.  This handles
1213          * 2 cases:
1214          *      1) reaping unsignaled WRs when the first subsequent
1215          *         signaled WR is completed.
1216          *      2) out of order read completions.
1217          */
1218         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1219                 struct t3_swsq *sqp;
1220
1221                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1222                      __FUNCTION__,
1223                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1224                 sqp = wq->sq +
1225                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1226                 sqp->cqe = *hw_cqe;
1227                 sqp->complete = 1;
1228                 ret = -1;
1229                 goto flush_wq;
1230         }
1231
1232 proc_cqe:
1233         *cqe = *hw_cqe;
1234
1235         /*
1236          * Reap the associated WR(s) that are freed up with this
1237          * completion.
1238          */
1239         if (SQ_TYPE(*hw_cqe)) {
1240                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1241                 PDBG("%s completing sq idx %ld\n", __FUNCTION__,
1242                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1243                 *cookie = (wq->sq +
1244                            Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1245                 wq->sq_rptr++;
1246         } else {
1247                 PDBG("%s completing rq idx %ld\n", __FUNCTION__,
1248                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1249                 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1250                 wq->rq_rptr++;
1251         }
1252
1253 flush_wq:
1254         /*
1255          * Flush any completed cqes that are now in-order.
1256          */
1257         flush_completed_wrs(wq, cq);
1258
1259 skip_cqe:
1260         if (SW_CQE(*hw_cqe)) {
1261                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1262                      __FUNCTION__, cq, cq->cqid, cq->sw_rptr);
1263                 ++cq->sw_rptr;
1264         } else {
1265                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1266                      __FUNCTION__, cq, cq->cqid, cq->rptr);
1267                 ++cq->rptr;
1268
1269                 /*
1270                  * T3A: compute credits.
1271                  */
1272                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1273                     || ((cq->rptr - cq->wptr) >= 128)) {
1274                         *credit = cq->rptr - cq->wptr;
1275                         cq->wptr = cq->rptr;
1276                 }
1277         }
1278         return ret;
1279 }