3edd7060510fa6e668e46cc6deb1000fe4c4fc69
[linux-2.6.git] / drivers / ide / pci / aec62xx.c
1 /*
2  * linux/drivers/ide/pci/aec62xx.c              Version 0.11    March 27, 2002
3  *
4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
5  *
6  */
7
8 #include <linux/module.h>
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/hdreg.h>
14 #include <linux/ide.h>
15 #include <linux/init.h>
16
17 #include <asm/io.h>
18
19 struct chipset_bus_clock_list_entry {
20         u8 xfer_speed;
21         u8 chipset_settings;
22         u8 ultra_settings;
23 };
24
25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
26         {       XFER_UDMA_6,    0x31,   0x07    },
27         {       XFER_UDMA_5,    0x31,   0x06    },
28         {       XFER_UDMA_4,    0x31,   0x05    },
29         {       XFER_UDMA_3,    0x31,   0x04    },
30         {       XFER_UDMA_2,    0x31,   0x03    },
31         {       XFER_UDMA_1,    0x31,   0x02    },
32         {       XFER_UDMA_0,    0x31,   0x01    },
33
34         {       XFER_MW_DMA_2,  0x31,   0x00    },
35         {       XFER_MW_DMA_1,  0x31,   0x00    },
36         {       XFER_MW_DMA_0,  0x0a,   0x00    },
37         {       XFER_PIO_4,     0x31,   0x00    },
38         {       XFER_PIO_3,     0x33,   0x00    },
39         {       XFER_PIO_2,     0x08,   0x00    },
40         {       XFER_PIO_1,     0x0a,   0x00    },
41         {       XFER_PIO_0,     0x00,   0x00    },
42         {       0,              0x00,   0x00    }
43 };
44
45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
46         {       XFER_UDMA_6,    0x41,   0x06    },
47         {       XFER_UDMA_5,    0x41,   0x05    },
48         {       XFER_UDMA_4,    0x41,   0x04    },
49         {       XFER_UDMA_3,    0x41,   0x03    },
50         {       XFER_UDMA_2,    0x41,   0x02    },
51         {       XFER_UDMA_1,    0x41,   0x01    },
52         {       XFER_UDMA_0,    0x41,   0x01    },
53
54         {       XFER_MW_DMA_2,  0x41,   0x00    },
55         {       XFER_MW_DMA_1,  0x42,   0x00    },
56         {       XFER_MW_DMA_0,  0x7a,   0x00    },
57         {       XFER_PIO_4,     0x41,   0x00    },
58         {       XFER_PIO_3,     0x43,   0x00    },
59         {       XFER_PIO_2,     0x78,   0x00    },
60         {       XFER_PIO_1,     0x7a,   0x00    },
61         {       XFER_PIO_0,     0x70,   0x00    },
62         {       0,              0x00,   0x00    }
63 };
64
65 #define BUSCLOCK(D)     \
66         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
67
68
69 /*
70  * TO DO: active tuning and correction of cards without a bios.
71  */
72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
73 {
74         for ( ; chipset_table->xfer_speed ; chipset_table++)
75                 if (chipset_table->xfer_speed == speed) {
76                         return chipset_table->chipset_settings;
77                 }
78         return chipset_table->chipset_settings;
79 }
80
81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
82 {
83         for ( ; chipset_table->xfer_speed ; chipset_table++)
84                 if (chipset_table->xfer_speed == speed) {
85                         return chipset_table->ultra_settings;
86                 }
87         return chipset_table->ultra_settings;
88 }
89
90 static u8 aec62xx_ratemask (ide_drive_t *drive)
91 {
92         ide_hwif_t *hwif        = HWIF(drive);
93         u8 mode;
94
95         switch(hwif->pci_dev->device) {
96                 case PCI_DEVICE_ID_ARTOP_ATP865:
97                 case PCI_DEVICE_ID_ARTOP_ATP865R:
98                         mode = (hwif->INB(((hwif->channel) ?
99                                         hwif->mate->dma_status :
100                                         hwif->dma_status)) & 0x10) ? 4 : 3;
101                         break;
102                 case PCI_DEVICE_ID_ARTOP_ATP860:
103                 case PCI_DEVICE_ID_ARTOP_ATP860R:
104                         mode = 2;
105                         break;
106                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
107                 default:
108                         return 1;
109         }
110
111         if (!eighty_ninty_three(drive))
112                 mode = min(mode, (u8)1);
113         return mode;
114 }
115
116 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
117 {
118         ide_hwif_t *hwif        = HWIF(drive);
119         struct pci_dev *dev     = hwif->pci_dev;
120         u16 d_conf              = 0;
121         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
122         u8 ultra = 0, ultra_conf = 0;
123         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
124         unsigned long flags;
125
126         local_irq_save(flags);
127         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
128         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
129         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
130         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
131         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
132
133         tmp1 = 0x00;
134         tmp2 = 0x00;
135         pci_read_config_byte(dev, 0x54, &ultra);
136         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
137         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
138         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
139         pci_write_config_byte(dev, 0x54, tmp2);
140         local_irq_restore(flags);
141         return(ide_config_drive_speed(drive, speed));
142 }
143
144 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
145 {
146         ide_hwif_t *hwif        = HWIF(drive);
147         struct pci_dev *dev     = hwif->pci_dev;
148         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
149         u8 unit         = (drive->select.b.unit & 0x01);
150         u8 tmp1 = 0, tmp2 = 0;
151         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
152         unsigned long flags;
153
154         local_irq_save(flags);
155         /* high 4-bits: Active, low 4-bits: Recovery */
156         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
157         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
158         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
159
160         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
161         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
162         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
163         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
164         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
165         local_irq_restore(flags);
166         return(ide_config_drive_speed(drive, speed));
167 }
168
169 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
170 {
171         switch (HWIF(drive)->pci_dev->device) {
172                 case PCI_DEVICE_ID_ARTOP_ATP865:
173                 case PCI_DEVICE_ID_ARTOP_ATP865R:
174                 case PCI_DEVICE_ID_ARTOP_ATP860:
175                 case PCI_DEVICE_ID_ARTOP_ATP860R:
176                         return ((int) aec6260_tune_chipset(drive, speed));
177                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
178                         return ((int) aec6210_tune_chipset(drive, speed));
179                 default:
180                         return -1;
181         }
182 }
183
184 static int config_chipset_for_dma (ide_drive_t *drive)
185 {
186         u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));       
187
188         if (!(speed))
189                 return 0;
190
191         (void) aec62xx_tune_chipset(drive, speed);
192         return ide_dma_enable(drive);
193 }
194
195 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
196 {
197         u8 speed = 0;
198         u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
199
200         switch(pio) {
201                 case 5:         speed = new_pio; break;
202                 case 4:         speed = XFER_PIO_4; break;
203                 case 3:         speed = XFER_PIO_3; break;
204                 case 2:         speed = XFER_PIO_2; break;
205                 case 1:         speed = XFER_PIO_1; break;
206                 default:        speed = XFER_PIO_0; break;
207         }
208         (void) aec62xx_tune_chipset(drive, speed);
209 }
210
211 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
212 {
213         ide_hwif_t *hwif        = HWIF(drive);
214         struct hd_driveid *id   = drive->id;
215
216         if ((id->capability & 1) && drive->autodma) {
217
218                 if (ide_use_dma(drive)) {
219                         if (config_chipset_for_dma(drive))
220                                 return hwif->ide_dma_on(drive);
221                 }
222
223                 goto fast_ata_pio;
224
225         } else if ((id->capability & 8) || (id->field_valid & 2)) {
226 fast_ata_pio:
227                 aec62xx_tune_drive(drive, 5);
228                 return hwif->ide_dma_off_quietly(drive);
229         }
230         /* IORDY not supported */
231         return 0;
232 }
233
234 static int aec62xx_irq_timeout (ide_drive_t *drive)
235 {
236         ide_hwif_t *hwif        = HWIF(drive);
237         struct pci_dev *dev     = hwif->pci_dev;
238
239         switch(dev->device) {
240                 case PCI_DEVICE_ID_ARTOP_ATP860:
241                 case PCI_DEVICE_ID_ARTOP_ATP860R:
242                 case PCI_DEVICE_ID_ARTOP_ATP865:
243                 case PCI_DEVICE_ID_ARTOP_ATP865R:
244                         printk(" AEC62XX time out ");
245                 default:
246                         break;
247         }
248         return 0;
249 }
250
251 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
252 {
253         int bus_speed = system_bus_clock();
254
255         if (dev->resource[PCI_ROM_RESOURCE].start) {
256                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
257                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
258                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
259         }
260
261         if (bus_speed <= 33)
262                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
263         else
264                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
265
266         /* These are necessary to get AEC6280 Macintosh cards to work */
267         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
268             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
269                 u8 reg49h = 0, reg4ah = 0;
270                 /* Clear reset and test bits.  */
271                 pci_read_config_byte(dev, 0x49, &reg49h);
272                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
273                 /* Enable chip interrupt output.  */
274                 pci_read_config_byte(dev, 0x4a, &reg4ah);
275                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
276                 /* Enable burst mode. */
277                 pci_read_config_byte(dev, 0x4a, &reg4ah);
278                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
279         }
280
281         return dev->irq;
282 }
283
284 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
285 {
286         hwif->autodma = 0;
287         hwif->tuneproc = &aec62xx_tune_drive;
288         hwif->speedproc = &aec62xx_tune_chipset;
289
290         if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
291                 hwif->serialized = hwif->channel;
292                 hwif->no_dsc = 1;
293         }
294
295         if (hwif->mate)
296                 hwif->mate->serialized = hwif->serialized;
297
298         if (!hwif->dma_base) {
299                 hwif->drives[0].autotune = 1;
300                 hwif->drives[1].autotune = 1;
301                 return;
302         }
303
304         hwif->ultra_mask = 0x7f;
305         hwif->mwdma_mask = 0x07;
306         hwif->swdma_mask = 0x07;
307
308         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
309         hwif->ide_dma_lostirq   = &aec62xx_irq_timeout;
310         hwif->ide_dma_timeout   = &aec62xx_irq_timeout;
311         if (!noautodma)
312                 hwif->autodma = 1;
313         hwif->drives[0].autodma = hwif->autodma;
314         hwif->drives[1].autodma = hwif->autodma;
315 }
316
317 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
318 {
319         struct pci_dev *dev     = hwif->pci_dev;
320
321         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
322                 u8 reg54h = 0;
323                 unsigned long flags;
324
325                 spin_lock_irqsave(&ide_lock, flags);
326                 pci_read_config_byte(dev, 0x54, &reg54h);
327                 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
328                 spin_unlock_irqrestore(&ide_lock, flags);
329         } else {
330                 u8 ata66        = 0;
331                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
332                 if (!(hwif->udma_four))
333                         hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
334         }
335
336         ide_setup_dma(hwif, dmabase, 8);
337 }
338
339 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
340 {
341         return ide_setup_pci_device(dev, d);
342 }
343
344 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
345 {
346         unsigned long bar4reg = pci_resource_start(dev, 4);
347
348         if (inb(bar4reg+2) & 0x10) {
349                 strcpy(d->name, "AEC6880");
350                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
351                         strcpy(d->name, "AEC6880R");
352         } else {
353                 strcpy(d->name, "AEC6280");
354                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
355                         strcpy(d->name, "AEC6280R");
356         }
357
358         return ide_setup_pci_device(dev, d);
359 }
360
361 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
362         {       /* 0 */
363                 .name           = "AEC6210",
364                 .init_setup     = init_setup_aec62xx,
365                 .init_chipset   = init_chipset_aec62xx,
366                 .init_hwif      = init_hwif_aec62xx,
367                 .init_dma       = init_dma_aec62xx,
368                 .channels       = 2,
369                 .autodma        = AUTODMA,
370                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
371                 .bootable       = OFF_BOARD,
372         },{     /* 1 */
373                 .name           = "AEC6260",
374                 .init_setup     = init_setup_aec62xx,
375                 .init_chipset   = init_chipset_aec62xx,
376                 .init_hwif      = init_hwif_aec62xx,
377                 .init_dma       = init_dma_aec62xx,
378                 .channels       = 2,
379                 .autodma        = NOAUTODMA,
380                 .bootable       = OFF_BOARD,
381         },{     /* 2 */
382                 .name           = "AEC6260R",
383                 .init_setup     = init_setup_aec62xx,
384                 .init_chipset   = init_chipset_aec62xx,
385                 .init_hwif      = init_hwif_aec62xx,
386                 .init_dma       = init_dma_aec62xx,
387                 .channels       = 2,
388                 .autodma        = AUTODMA,
389                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
390                 .bootable       = NEVER_BOARD,
391         },{     /* 3 */
392                 .name           = "AEC6X80",
393                 .init_setup     = init_setup_aec6x80,
394                 .init_chipset   = init_chipset_aec62xx,
395                 .init_hwif      = init_hwif_aec62xx,
396                 .init_dma       = init_dma_aec62xx,
397                 .channels       = 2,
398                 .autodma        = AUTODMA,
399                 .bootable       = OFF_BOARD,
400         },{     /* 4 */
401                 .name           = "AEC6X80R",
402                 .init_setup     = init_setup_aec6x80,
403                 .init_chipset   = init_chipset_aec62xx,
404                 .init_hwif      = init_hwif_aec62xx,
405                 .init_dma       = init_dma_aec62xx,
406                 .channels       = 2,
407                 .autodma        = AUTODMA,
408                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
409                 .bootable       = OFF_BOARD,
410         }
411 };
412
413 /**
414  *      aec62xx_init_one        -       called when a AEC is found
415  *      @dev: the aec62xx device
416  *      @id: the matching pci id
417  *
418  *      Called when the PCI registration layer (or the IDE initialization)
419  *      finds a device matching our IDE device tables.
420  */
421  
422 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
423 {
424         ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
425
426         return d->init_setup(dev, d);
427 }
428
429 static const struct pci_device_id aec62xx_pci_tbl[] = {
430         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
431         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
432         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
433         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
434         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
435         { 0, },
436 };
437 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
438
439 static struct pci_driver driver = {
440         .name           = "AEC62xx_IDE",
441         .id_table       = aec62xx_pci_tbl,
442         .probe          = aec62xx_init_one,
443 };
444
445 static int aec62xx_ide_init(void)
446 {
447         return ide_pci_register_driver(&driver);
448 }
449
450 module_init(aec62xx_ide_init);
451
452 MODULE_AUTHOR("Andre Hedrick");
453 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
454 MODULE_LICENSE("GPL");