drm/ttm: split no_wait argument in 2 GPU or reserve wait
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_object.c
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <drm/drmP.h>
34 #include "radeon_drm.h"
35 #include "radeon.h"
36
37
38 int radeon_ttm_init(struct radeon_device *rdev);
39 void radeon_ttm_fini(struct radeon_device *rdev);
40 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
41
42 /*
43  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44  * function are calling it.
45  */
46
47 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
48 {
49         struct radeon_bo *bo;
50
51         bo = container_of(tbo, struct radeon_bo, tbo);
52         mutex_lock(&bo->rdev->gem.mutex);
53         list_del_init(&bo->list);
54         mutex_unlock(&bo->rdev->gem.mutex);
55         radeon_bo_clear_surface_reg(bo);
56         kfree(bo);
57 }
58
59 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
60 {
61         if (bo->destroy == &radeon_ttm_bo_destroy)
62                 return true;
63         return false;
64 }
65
66 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
67 {
68         u32 c = 0;
69
70         rbo->placement.fpfn = 0;
71         rbo->placement.lpfn = 0;
72         rbo->placement.placement = rbo->placements;
73         rbo->placement.busy_placement = rbo->placements;
74         if (domain & RADEON_GEM_DOMAIN_VRAM)
75                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
76                                         TTM_PL_FLAG_VRAM;
77         if (domain & RADEON_GEM_DOMAIN_GTT)
78                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
79         if (domain & RADEON_GEM_DOMAIN_CPU)
80                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
81         if (!c)
82                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
83         rbo->placement.num_placement = c;
84         rbo->placement.num_busy_placement = c;
85 }
86
87 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
88                         unsigned long size, bool kernel, u32 domain,
89                         struct radeon_bo **bo_ptr)
90 {
91         struct radeon_bo *bo;
92         enum ttm_bo_type type;
93         int r;
94
95         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
96                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
97         }
98         if (kernel) {
99                 type = ttm_bo_type_kernel;
100         } else {
101                 type = ttm_bo_type_device;
102         }
103         *bo_ptr = NULL;
104         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
105         if (bo == NULL)
106                 return -ENOMEM;
107         bo->rdev = rdev;
108         bo->gobj = gobj;
109         bo->surface_reg = -1;
110         INIT_LIST_HEAD(&bo->list);
111
112         radeon_ttm_placement_from_domain(bo, domain);
113         /* Kernel allocation are uninterruptible */
114         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
115                         &bo->placement, 0, 0, !kernel, NULL, size,
116                         &radeon_ttm_bo_destroy);
117         if (unlikely(r != 0)) {
118                 if (r != -ERESTARTSYS)
119                         dev_err(rdev->dev,
120                                 "object_init failed for (%lu, 0x%08X)\n",
121                                 size, domain);
122                 return r;
123         }
124         *bo_ptr = bo;
125         if (gobj) {
126                 mutex_lock(&bo->rdev->gem.mutex);
127                 list_add_tail(&bo->list, &rdev->gem.objects);
128                 mutex_unlock(&bo->rdev->gem.mutex);
129         }
130         return 0;
131 }
132
133 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
134 {
135         bool is_iomem;
136         int r;
137
138         if (bo->kptr) {
139                 if (ptr) {
140                         *ptr = bo->kptr;
141                 }
142                 return 0;
143         }
144         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
145         if (r) {
146                 return r;
147         }
148         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
149         if (ptr) {
150                 *ptr = bo->kptr;
151         }
152         radeon_bo_check_tiling(bo, 0, 0);
153         return 0;
154 }
155
156 void radeon_bo_kunmap(struct radeon_bo *bo)
157 {
158         if (bo->kptr == NULL)
159                 return;
160         bo->kptr = NULL;
161         radeon_bo_check_tiling(bo, 0, 0);
162         ttm_bo_kunmap(&bo->kmap);
163 }
164
165 void radeon_bo_unref(struct radeon_bo **bo)
166 {
167         struct ttm_buffer_object *tbo;
168
169         if ((*bo) == NULL)
170                 return;
171         tbo = &((*bo)->tbo);
172         ttm_bo_unref(&tbo);
173         if (tbo == NULL)
174                 *bo = NULL;
175 }
176
177 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
178 {
179         int r, i;
180
181         if (bo->pin_count) {
182                 bo->pin_count++;
183                 if (gpu_addr)
184                         *gpu_addr = radeon_bo_gpu_offset(bo);
185                 return 0;
186         }
187         radeon_ttm_placement_from_domain(bo, domain);
188         if (domain == RADEON_GEM_DOMAIN_VRAM) {
189                 /* force to pin into visible video ram */
190                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
191         }
192         for (i = 0; i < bo->placement.num_placement; i++)
193                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
194         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
195         if (likely(r == 0)) {
196                 bo->pin_count = 1;
197                 if (gpu_addr != NULL)
198                         *gpu_addr = radeon_bo_gpu_offset(bo);
199         }
200         if (unlikely(r != 0))
201                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
202         return r;
203 }
204
205 int radeon_bo_unpin(struct radeon_bo *bo)
206 {
207         int r, i;
208
209         if (!bo->pin_count) {
210                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
211                 return 0;
212         }
213         bo->pin_count--;
214         if (bo->pin_count)
215                 return 0;
216         for (i = 0; i < bo->placement.num_placement; i++)
217                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
218         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
219         if (unlikely(r != 0))
220                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
221         return r;
222 }
223
224 int radeon_bo_evict_vram(struct radeon_device *rdev)
225 {
226         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
227         if (0 && (rdev->flags & RADEON_IS_IGP)) {
228                 if (rdev->mc.igp_sideport_enabled == false)
229                         /* Useless to evict on IGP chips */
230                         return 0;
231         }
232         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
233 }
234
235 void radeon_bo_force_delete(struct radeon_device *rdev)
236 {
237         struct radeon_bo *bo, *n;
238         struct drm_gem_object *gobj;
239
240         if (list_empty(&rdev->gem.objects)) {
241                 return;
242         }
243         dev_err(rdev->dev, "Userspace still has active objects !\n");
244         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
245                 mutex_lock(&rdev->ddev->struct_mutex);
246                 gobj = bo->gobj;
247                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
248                         gobj, bo, (unsigned long)gobj->size,
249                         *((unsigned long *)&gobj->refcount));
250                 mutex_lock(&bo->rdev->gem.mutex);
251                 list_del_init(&bo->list);
252                 mutex_unlock(&bo->rdev->gem.mutex);
253                 radeon_bo_unref(&bo);
254                 gobj->driver_private = NULL;
255                 drm_gem_object_unreference(gobj);
256                 mutex_unlock(&rdev->ddev->struct_mutex);
257         }
258 }
259
260 int radeon_bo_init(struct radeon_device *rdev)
261 {
262         /* Add an MTRR for the VRAM */
263         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
264                         MTRR_TYPE_WRCOMB, 1);
265         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
266                 rdev->mc.mc_vram_size >> 20,
267                 (unsigned long long)rdev->mc.aper_size >> 20);
268         DRM_INFO("RAM width %dbits %cDR\n",
269                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
270         return radeon_ttm_init(rdev);
271 }
272
273 void radeon_bo_fini(struct radeon_device *rdev)
274 {
275         radeon_ttm_fini(rdev);
276 }
277
278 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
279                                 struct list_head *head)
280 {
281         if (lobj->wdomain) {
282                 list_add(&lobj->list, head);
283         } else {
284                 list_add_tail(&lobj->list, head);
285         }
286 }
287
288 int radeon_bo_list_reserve(struct list_head *head)
289 {
290         struct radeon_bo_list *lobj;
291         int r;
292
293         list_for_each_entry(lobj, head, list){
294                 r = radeon_bo_reserve(lobj->bo, false);
295                 if (unlikely(r != 0))
296                         return r;
297         }
298         return 0;
299 }
300
301 void radeon_bo_list_unreserve(struct list_head *head)
302 {
303         struct radeon_bo_list *lobj;
304
305         list_for_each_entry(lobj, head, list) {
306                 /* only unreserve object we successfully reserved */
307                 if (radeon_bo_is_reserved(lobj->bo))
308                         radeon_bo_unreserve(lobj->bo);
309         }
310 }
311
312 int radeon_bo_list_validate(struct list_head *head)
313 {
314         struct radeon_bo_list *lobj;
315         struct radeon_bo *bo;
316         int r;
317
318         r = radeon_bo_list_reserve(head);
319         if (unlikely(r != 0)) {
320                 return r;
321         }
322         list_for_each_entry(lobj, head, list) {
323                 bo = lobj->bo;
324                 if (!bo->pin_count) {
325                         if (lobj->wdomain) {
326                                 radeon_ttm_placement_from_domain(bo,
327                                                                 lobj->wdomain);
328                         } else {
329                                 radeon_ttm_placement_from_domain(bo,
330                                                                 lobj->rdomain);
331                         }
332                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
333                                                 true, false, false);
334                         if (unlikely(r))
335                                 return r;
336                 }
337                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
338                 lobj->tiling_flags = bo->tiling_flags;
339         }
340         return 0;
341 }
342
343 void radeon_bo_list_fence(struct list_head *head, void *fence)
344 {
345         struct radeon_bo_list *lobj;
346         struct radeon_bo *bo;
347         struct radeon_fence *old_fence = NULL;
348
349         list_for_each_entry(lobj, head, list) {
350                 bo = lobj->bo;
351                 spin_lock(&bo->tbo.lock);
352                 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
353                 bo->tbo.sync_obj = radeon_fence_ref(fence);
354                 bo->tbo.sync_obj_arg = NULL;
355                 spin_unlock(&bo->tbo.lock);
356                 if (old_fence) {
357                         radeon_fence_unref(&old_fence);
358                 }
359         }
360 }
361
362 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
363                              struct vm_area_struct *vma)
364 {
365         return ttm_fbdev_mmap(vma, &bo->tbo);
366 }
367
368 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
369 {
370         struct radeon_device *rdev = bo->rdev;
371         struct radeon_surface_reg *reg;
372         struct radeon_bo *old_object;
373         int steal;
374         int i;
375
376         BUG_ON(!atomic_read(&bo->tbo.reserved));
377
378         if (!bo->tiling_flags)
379                 return 0;
380
381         if (bo->surface_reg >= 0) {
382                 reg = &rdev->surface_regs[bo->surface_reg];
383                 i = bo->surface_reg;
384                 goto out;
385         }
386
387         steal = -1;
388         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
389
390                 reg = &rdev->surface_regs[i];
391                 if (!reg->bo)
392                         break;
393
394                 old_object = reg->bo;
395                 if (old_object->pin_count == 0)
396                         steal = i;
397         }
398
399         /* if we are all out */
400         if (i == RADEON_GEM_MAX_SURFACES) {
401                 if (steal == -1)
402                         return -ENOMEM;
403                 /* find someone with a surface reg and nuke their BO */
404                 reg = &rdev->surface_regs[steal];
405                 old_object = reg->bo;
406                 /* blow away the mapping */
407                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
408                 ttm_bo_unmap_virtual(&old_object->tbo);
409                 old_object->surface_reg = -1;
410                 i = steal;
411         }
412
413         bo->surface_reg = i;
414         reg->bo = bo;
415
416 out:
417         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
418                                bo->tbo.mem.mm_node->start << PAGE_SHIFT,
419                                bo->tbo.num_pages << PAGE_SHIFT);
420         return 0;
421 }
422
423 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
424 {
425         struct radeon_device *rdev = bo->rdev;
426         struct radeon_surface_reg *reg;
427
428         if (bo->surface_reg == -1)
429                 return;
430
431         reg = &rdev->surface_regs[bo->surface_reg];
432         radeon_clear_surface_reg(rdev, bo->surface_reg);
433
434         reg->bo = NULL;
435         bo->surface_reg = -1;
436 }
437
438 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
439                                 uint32_t tiling_flags, uint32_t pitch)
440 {
441         int r;
442
443         r = radeon_bo_reserve(bo, false);
444         if (unlikely(r != 0))
445                 return r;
446         bo->tiling_flags = tiling_flags;
447         bo->pitch = pitch;
448         radeon_bo_unreserve(bo);
449         return 0;
450 }
451
452 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
453                                 uint32_t *tiling_flags,
454                                 uint32_t *pitch)
455 {
456         BUG_ON(!atomic_read(&bo->tbo.reserved));
457         if (tiling_flags)
458                 *tiling_flags = bo->tiling_flags;
459         if (pitch)
460                 *pitch = bo->pitch;
461 }
462
463 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
464                                 bool force_drop)
465 {
466         BUG_ON(!atomic_read(&bo->tbo.reserved));
467
468         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
469                 return 0;
470
471         if (force_drop) {
472                 radeon_bo_clear_surface_reg(bo);
473                 return 0;
474         }
475
476         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
477                 if (!has_moved)
478                         return 0;
479
480                 if (bo->surface_reg >= 0)
481                         radeon_bo_clear_surface_reg(bo);
482                 return 0;
483         }
484
485         if ((bo->surface_reg >= 0) && !has_moved)
486                 return 0;
487
488         return radeon_bo_get_surface_reg(bo);
489 }
490
491 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
492                            struct ttm_mem_reg *mem)
493 {
494         struct radeon_bo *rbo;
495         if (!radeon_ttm_bo_is_radeon_bo(bo))
496                 return;
497         rbo = container_of(bo, struct radeon_bo, tbo);
498         radeon_bo_check_tiling(rbo, 0, 1);
499 }
500
501 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
502 {
503         struct radeon_bo *rbo;
504         if (!radeon_ttm_bo_is_radeon_bo(bo))
505                 return;
506         rbo = container_of(bo, struct radeon_bo, tbo);
507         radeon_bo_check_tiling(rbo, 0, 0);
508 }