Merge branch 'dbg-early-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/jwess...
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios.h
1 /*
2  * Copyright 2006-2007 Advanced Micro Devices, Inc.  
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22
23
24 /****************************************************************************/  
25 /*Portion I: Definitions  shared between VBIOS and Driver                   */
26 /****************************************************************************/
27
28
29 #ifndef _ATOMBIOS_H
30 #define _ATOMBIOS_H
31
32 #define ATOM_VERSION_MAJOR                   0x00020000
33 #define ATOM_VERSION_MINOR                   0x00000002
34
35 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
36
37 /* Endianness should be specified before inclusion,
38  * default to little endian
39  */
40 #ifndef ATOM_BIG_ENDIAN
41 #error Endian not specified
42 #endif
43
44 #ifdef _H2INC
45   #ifndef ULONG 
46     typedef unsigned long ULONG;
47   #endif
48
49   #ifndef UCHAR
50     typedef unsigned char UCHAR;
51   #endif
52
53   #ifndef USHORT 
54     typedef unsigned short USHORT;
55   #endif
56 #endif
57       
58 #define ATOM_DAC_A            0 
59 #define ATOM_DAC_B            1
60 #define ATOM_EXT_DAC          2
61
62 #define ATOM_CRTC1            0
63 #define ATOM_CRTC2            1
64 #define ATOM_CRTC3            2
65 #define ATOM_CRTC4            3
66 #define ATOM_CRTC5            4
67 #define ATOM_CRTC6            5
68 #define ATOM_CRTC_INVALID     0xFF
69
70 #define ATOM_DIGA             0
71 #define ATOM_DIGB             1
72
73 #define ATOM_PPLL1            0
74 #define ATOM_PPLL2            1
75 #define ATOM_DCPLL            2
76 #define ATOM_PPLL_INVALID     0xFF
77
78 #define ATOM_SCALER1          0
79 #define ATOM_SCALER2          1
80
81 #define ATOM_SCALER_DISABLE   0   
82 #define ATOM_SCALER_CENTER    1   
83 #define ATOM_SCALER_EXPANSION 2   
84 #define ATOM_SCALER_MULTI_EX  3   
85
86 #define ATOM_DISABLE          0
87 #define ATOM_ENABLE           1
88 #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
89 #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
90 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
91 #define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
92 #define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
93 #define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
94 #define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
95
96 #define ATOM_BLANKING         1
97 #define ATOM_BLANKING_OFF     0
98
99 #define ATOM_CURSOR1          0
100 #define ATOM_CURSOR2          1
101
102 #define ATOM_ICON1            0
103 #define ATOM_ICON2            1
104
105 #define ATOM_CRT1             0
106 #define ATOM_CRT2             1
107
108 #define ATOM_TV_NTSC          1
109 #define ATOM_TV_NTSCJ         2
110 #define ATOM_TV_PAL           3
111 #define ATOM_TV_PALM          4
112 #define ATOM_TV_PALCN         5
113 #define ATOM_TV_PALN          6
114 #define ATOM_TV_PAL60         7
115 #define ATOM_TV_SECAM         8
116 #define ATOM_TV_CV            16
117
118 #define ATOM_DAC1_PS2         1
119 #define ATOM_DAC1_CV          2
120 #define ATOM_DAC1_NTSC        3
121 #define ATOM_DAC1_PAL         4
122
123 #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
124 #define ATOM_DAC2_CV          ATOM_DAC1_CV
125 #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
126 #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
127  
128 #define ATOM_PM_ON            0
129 #define ATOM_PM_STANDBY       1
130 #define ATOM_PM_SUSPEND       2
131 #define ATOM_PM_OFF           3
132
133 /* Bit0:{=0:single, =1:dual},
134    Bit1 {=0:666RGB, =1:888RGB},
135    Bit2:3:{Grey level}
136    Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
137
138 #define ATOM_PANEL_MISC_DUAL               0x00000001
139 #define ATOM_PANEL_MISC_888RGB             0x00000002
140 #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
141 #define ATOM_PANEL_MISC_FPDI               0x00000010
142 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
143 #define ATOM_PANEL_MISC_SPATIAL            0x00000020
144 #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
145 #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
146
147
148 #define MEMTYPE_DDR1              "DDR1"
149 #define MEMTYPE_DDR2              "DDR2"
150 #define MEMTYPE_DDR3              "DDR3"
151 #define MEMTYPE_DDR4              "DDR4"
152
153 #define ASIC_BUS_TYPE_PCI         "PCI"
154 #define ASIC_BUS_TYPE_AGP         "AGP"
155 #define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
156
157 /* Maximum size of that FireGL flag string */
158
159 #define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
160 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
161
162 #define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
163 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 
164
165 #define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
166 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
167
168 #define HW_ASSISTED_I2C_STATUS_FAILURE          2
169 #define HW_ASSISTED_I2C_STATUS_SUCCESS          1
170
171 #pragma pack(1)                                       /* BIOS data must use byte aligment */
172
173 /*  Define offset to location of ROM header. */
174
175 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
176 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
177
178 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
179 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
180 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
181 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
182
183 /* Common header for all ROM Data tables.
184   Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header. 
185   And the pointer actually points to this header. */
186
187 typedef struct _ATOM_COMMON_TABLE_HEADER
188 {
189   USHORT usStructureSize;
190   UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
191   UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
192                                   /*Image can't be updated, while Driver needs to carry the new table! */
193 }ATOM_COMMON_TABLE_HEADER;
194
195 typedef struct _ATOM_ROM_HEADER
196 {
197   ATOM_COMMON_TABLE_HEADER              sHeader;
198   UCHAR  uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios, 
199                                       atombios should init it as "ATOM", don't change the position */
200   USHORT usBiosRuntimeSegmentAddress;
201   USHORT usProtectedModeInfoOffset;
202   USHORT usConfigFilenameOffset;
203   USHORT usCRC_BlockOffset;
204   USHORT usBIOS_BootupMessageOffset;
205   USHORT usInt10Offset;
206   USHORT usPciBusDevInitCode;
207   USHORT usIoBaseAddress;
208   USHORT usSubsystemVendorID;
209   USHORT usSubsystemID;
210   USHORT usPCI_InfoOffset; 
211   USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
212   USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
213   UCHAR  ucExtendedFunctionCode;
214   UCHAR  ucReserved;
215 }ATOM_ROM_HEADER;
216
217 /*==============================Command Table Portion==================================== */
218
219 #ifdef  UEFI_BUILD
220         #define UTEMP   USHORT
221         #define USHORT  void*
222 #endif
223
224 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
225   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
226   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
227   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
228   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
229   USHORT DIGxEncoderControl;                                                                             //Only used by Bios
230   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
231   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
232   USHORT MemoryParamAdjust;                                                                              //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
233   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
234   USHORT GPIOPinControl;                                                                                                 //Atomic Table,  only used by Bios
235   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
236   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
237   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
238   USHORT DynamicClockGating;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
239   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
240   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
241   USHORT MemoryPLLInit;
242   USHORT AdjustDisplayPll;                                                                                              //only used by Bios
243   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
244   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
245   USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios   
246   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
247   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
248   USHORT LCD1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
249   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
250   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1 
251   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1 
252   USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead 
253   USHORT GetConditionalGoldenSetting;            //only used by Bios
254   USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
255   USHORT TMDSAEncoderControl;                    //Atomic Table,  directly used by various SW components,latest version 1.3
256   USHORT LVDSEncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.3
257   USHORT TV1OutputControl;                       //Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
258   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
259   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1 
260   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1 
261   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1 
262   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
263   USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
264   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
265   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1 
266   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
267   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
268   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
269   USHORT UpdateCRTC_DoubleBufferRegisters;
270   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
271   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
272   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
273   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
274   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
275   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
276   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
277   USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
278   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
279   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
280   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
281   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
282   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
283   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
284   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
285   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
286   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
287   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
288   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
289   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
290   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
291   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
292   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
293   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
294   USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
295   USHORT SetupHWAssistedI2CStatus;               //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
296   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
297   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
298   USHORT EnableYUV;                              //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
299   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
300   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
301   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
302   USHORT DIG2TransmitterControl;                       //Atomic Table,directly used by various SW components,latest version 1.1 
303   USHORT ProcessAuxChannelTransaction;                                   //Function Table,only used by Bios
304   USHORT DPEncoderService;                                                                                       //Function Table,only used by Bios
305 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
306
307 // For backward compatible 
308 #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
309 #define UNIPHYTransmitterControl                                                     DIG1TransmitterControl
310 #define LVTMATransmitterControl                                                      DIG2TransmitterControl
311 #define SetCRTC_DPM_State                        GetConditionalGoldenSetting
312 #define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
313 #define HPDInterruptService                      ReadHWAssistedI2CStatus
314 #define EnableVGA_Access                         GetSCLKOverMCLKRatio
315
316 typedef struct _ATOM_MASTER_COMMAND_TABLE
317 {
318   ATOM_COMMON_TABLE_HEADER           sHeader;
319   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
320 }ATOM_MASTER_COMMAND_TABLE;
321
322 /****************************************************************************/  
323 // Structures used in every command table
324 /****************************************************************************/  
325 typedef struct _ATOM_TABLE_ATTRIBUTE
326 {
327 #if ATOM_BIG_ENDIAN
328   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
329   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
330   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
331 #else
332   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
333   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
334   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
335 #endif
336 }ATOM_TABLE_ATTRIBUTE;
337
338 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
339 {
340   ATOM_TABLE_ATTRIBUTE sbfAccess;
341   USHORT               susAccess;
342 }ATOM_TABLE_ATTRIBUTE_ACCESS;
343
344 /****************************************************************************/  
345 // Common header for all command tables.
346 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
347 // And the pointer actually points to this header.
348 /****************************************************************************/  
349 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
350 {
351   ATOM_COMMON_TABLE_HEADER CommonHeader;
352   ATOM_TABLE_ATTRIBUTE     TableAttribute;      
353 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
354
355 /****************************************************************************/  
356 // Structures used by ComputeMemoryEnginePLLTable
357 /****************************************************************************/  
358 #define COMPUTE_MEMORY_PLL_PARAM        1
359 #define COMPUTE_ENGINE_PLL_PARAM        2
360
361 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
362 {
363   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
364   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
365   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
366   UCHAR   ucFbDiv;        //return value
367   UCHAR   ucPostDiv;      //return value
368 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
369
370 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
371 {
372   ULONG   ulClock;        //When return, [23:0] return real clock 
373   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
374   USHORT  usFbDiv;                  //return Feedback value to be written to register
375   UCHAR   ucPostDiv;      //return post div to be written to register
376 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
377 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
378
379
380 #define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
381 #define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
382 #define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
383 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
384 #define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
385 #define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
386 #define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
387
388 #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
389 #define b3USE_MEMORY_SELF_REFRESH                 0x02       //Only applicable to memory clock change, when set, using memory self refresh during clock transition
390 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
391 #define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
392 #define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
393
394 typedef struct _ATOM_COMPUTE_CLOCK_FREQ
395 {
396 #if ATOM_BIG_ENDIAN
397   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
398   ULONG ulClockFreq:24;                       // in unit of 10kHz
399 #else
400   ULONG ulClockFreq:24;                       // in unit of 10kHz
401   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
402 #endif
403 }ATOM_COMPUTE_CLOCK_FREQ;
404
405 typedef struct _ATOM_S_MPLL_FB_DIVIDER
406 {
407   USHORT usFbDivFrac;  
408   USHORT usFbDiv;  
409 }ATOM_S_MPLL_FB_DIVIDER;
410
411 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
412 {
413   union
414   {
415     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
416     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
417   };
418   UCHAR   ucRefDiv;                           //Output Parameter      
419   UCHAR   ucPostDiv;                          //Output Parameter      
420   UCHAR   ucCntlFlag;                         //Output Parameter      
421   UCHAR   ucReserved;
422 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
423
424 // ucCntlFlag
425 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
426 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
427 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
428 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                                                8
429
430
431 // V4 are only used for APU which PLL outside GPU
432 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
433 {
434 #if ATOM_BIG_ENDIAN
435   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
436   ULONG  ulClock:24;         //Input= target clock, output = actual clock 
437 #else
438   ULONG  ulClock:24;         //Input= target clock, output = actual clock 
439   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
440 #endif
441 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
442
443 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
444 {
445   ATOM_COMPUTE_CLOCK_FREQ ulClock;
446   ULONG ulReserved[2];
447 }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
448
449 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
450 {
451   ATOM_COMPUTE_CLOCK_FREQ ulClock;
452   ULONG ulMemoryClock;
453   ULONG ulReserved;
454 }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
455
456 /****************************************************************************/  
457 // Structures used by SetEngineClockTable
458 /****************************************************************************/  
459 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
460 {
461   ULONG ulTargetEngineClock;          //In 10Khz unit
462 }SET_ENGINE_CLOCK_PARAMETERS;
463
464 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
465 {
466   ULONG ulTargetEngineClock;          //In 10Khz unit
467   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
468 }SET_ENGINE_CLOCK_PS_ALLOCATION;
469
470 /****************************************************************************/  
471 // Structures used by SetMemoryClockTable
472 /****************************************************************************/  
473 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
474 {
475   ULONG ulTargetMemoryClock;          //In 10Khz unit
476 }SET_MEMORY_CLOCK_PARAMETERS;
477
478 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
479 {
480   ULONG ulTargetMemoryClock;          //In 10Khz unit
481   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
482 }SET_MEMORY_CLOCK_PS_ALLOCATION;
483
484 /****************************************************************************/  
485 // Structures used by ASIC_Init.ctb
486 /****************************************************************************/  
487 typedef struct _ASIC_INIT_PARAMETERS
488 {
489   ULONG ulDefaultEngineClock;         //In 10Khz unit
490   ULONG ulDefaultMemoryClock;         //In 10Khz unit
491 }ASIC_INIT_PARAMETERS;
492
493 typedef struct _ASIC_INIT_PS_ALLOCATION
494 {
495   ASIC_INIT_PARAMETERS sASICInitClocks;
496   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
497 }ASIC_INIT_PS_ALLOCATION;
498
499 /****************************************************************************/  
500 // Structure used by DynamicClockGatingTable.ctb
501 /****************************************************************************/  
502 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 
503 {
504   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
505   UCHAR ucPadding[3];
506 }DYNAMIC_CLOCK_GATING_PARAMETERS;
507 #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
508
509 /****************************************************************************/  
510 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
511 /****************************************************************************/  
512 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
513 {
514   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
515   UCHAR ucPadding[3];
516 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
517 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
518
519 /****************************************************************************/  
520 // Structures used by DAC_LoadDetectionTable.ctb
521 /****************************************************************************/  
522 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
523 {
524   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
525   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
526   UCHAR  ucMisc;                                                                                        //Valid only when table revision =1.3 and above
527 }DAC_LOAD_DETECTION_PARAMETERS;
528
529 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
530 #define DAC_LOAD_MISC_YPrPb                                             0x01
531
532 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
533 {
534   DAC_LOAD_DETECTION_PARAMETERS            sDacload;
535   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
536 }DAC_LOAD_DETECTION_PS_ALLOCATION;
537
538 /****************************************************************************/  
539 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
540 /****************************************************************************/  
541 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 
542 {
543   USHORT usPixelClock;                // in 10KHz; for bios convenient
544   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
545   UCHAR  ucAction;                    // 0: turn off encoder
546                                       // 1: setup and turn on encoder
547                                       // 7: ATOM_ENCODER_INIT Initialize DAC
548 }DAC_ENCODER_CONTROL_PARAMETERS;
549
550 #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
551
552 /****************************************************************************/  
553 // Structures used by DIG1EncoderControlTable
554 //                    DIG2EncoderControlTable
555 //                    ExternalEncoderControlTable
556 /****************************************************************************/  
557 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
558 {
559   USHORT usPixelClock;          // in 10KHz; for bios convenient
560   UCHAR  ucConfig;                
561                             // [2] Link Select:
562                             // =0: PHY linkA if bfLane<3
563                             // =1: PHY linkB if bfLanes<3
564                             // =0: PHY linkA+B if bfLanes=3
565                             // [3] Transmitter Sel
566                             // =0: UNIPHY or PCIEPHY
567                             // =1: LVTMA                                        
568   UCHAR ucAction;           // =0: turn off encoder                                     
569                             // =1: turn on encoder                      
570   UCHAR ucEncoderMode;
571                             // =0: DP   encoder      
572                             // =1: LVDS encoder          
573                             // =2: DVI  encoder  
574                             // =3: HDMI encoder
575                             // =4: SDVO encoder
576   UCHAR ucLaneNum;          // how many lanes to enable
577   UCHAR ucReserved[2];
578 }DIG_ENCODER_CONTROL_PARAMETERS;
579 #define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
580 #define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
581
582 //ucConfig
583 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
584 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
585 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
586 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
587 #define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
588 #define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
589 #define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
590 #define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
591 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
592 #define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
593 #define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
594 #define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
595 #define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
596 #define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80                  // VBIOS Internal use, outside SW should set this bit=0
597 // ucAction
598 // ATOM_ENABLE:  Enable Encoder
599 // ATOM_DISABLE: Disable Encoder
600
601 //ucEncoderMode
602 #define ATOM_ENCODER_MODE_DP                                                                                    0
603 #define ATOM_ENCODER_MODE_LVDS                                                                          1
604 #define ATOM_ENCODER_MODE_DVI                                                                                   2
605 #define ATOM_ENCODER_MODE_HDMI                                                                          3
606 #define ATOM_ENCODER_MODE_SDVO                                                                          4
607 #define ATOM_ENCODER_MODE_DP_AUDIO                5
608 #define ATOM_ENCODER_MODE_TV                                                                                    13
609 #define ATOM_ENCODER_MODE_CV                                                                                    14
610 #define ATOM_ENCODER_MODE_CRT                                                                                   15
611
612 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
613 {
614 #if ATOM_BIG_ENDIAN
615     UCHAR ucReserved1:2;
616     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
617     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
618     UCHAR ucReserved:1;
619     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
620 #else
621     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
622     UCHAR ucReserved:1;
623     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
624     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
625     UCHAR ucReserved1:2;
626 #endif
627 }ATOM_DIG_ENCODER_CONFIG_V2;
628
629
630 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
631 {
632   USHORT usPixelClock;      // in 10KHz; for bios convenient
633   ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
634   UCHAR ucAction;                                       
635   UCHAR ucEncoderMode;
636                             // =0: DP   encoder      
637                             // =1: LVDS encoder          
638                             // =2: DVI  encoder  
639                             // =3: HDMI encoder
640                             // =4: SDVO encoder
641   UCHAR ucLaneNum;          // how many lanes to enable
642   UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
643   UCHAR ucReserved;
644 }DIG_ENCODER_CONTROL_PARAMETERS_V2;
645
646 //ucConfig
647 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                          0x01
648 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                 0x00
649 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                 0x01
650 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                              0x04
651 #define ATOM_ENCODER_CONFIG_V2_LINKA                                                              0x00
652 #define ATOM_ENCODER_CONFIG_V2_LINKB                                                              0x04
653 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK       0x18
654 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                 0x00
655 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                 0x08
656 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                 0x10
657
658 // ucAction:
659 // ATOM_DISABLE
660 // ATOM_ENABLE
661 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
662 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
663 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
664 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
665 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
666 #define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
667 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
668 #define ATOM_ENCODER_CMD_SETUP                        0x0f
669
670 // ucStatus
671 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
672 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
673
674 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
675 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
676 {
677 #if ATOM_BIG_ENDIAN
678     UCHAR ucReserved1:1;
679     UCHAR ucDigSel:3;             // =0: DIGA/B/C/D/E/F
680     UCHAR ucReserved:3;
681     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
682 #else
683     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
684     UCHAR ucReserved:3;
685     UCHAR ucDigSel:3;             // =0: DIGA/B/C/D/E/F
686     UCHAR ucReserved1:1;
687 #endif
688 }ATOM_DIG_ENCODER_CONFIG_V3;
689
690 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                                        0x70
691
692
693 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
694 {
695   USHORT usPixelClock;      // in 10KHz; for bios convenient
696   ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
697   UCHAR ucAction;                              
698   UCHAR ucEncoderMode;
699                             // =0: DP   encoder      
700                             // =1: LVDS encoder          
701                             // =2: DVI  encoder  
702                             // =3: HDMI encoder
703                             // =4: SDVO encoder
704                             // =5: DP audio
705   UCHAR ucLaneNum;          // how many lanes to enable
706   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
707   UCHAR ucReserved;
708 }DIG_ENCODER_CONTROL_PARAMETERS_V3;
709
710
711 // define ucBitPerColor: 
712 #define PANEL_BPC_UNDEFINE                               0x00
713 #define PANEL_6BIT_PER_COLOR                             0x01 
714 #define PANEL_8BIT_PER_COLOR                             0x02
715 #define PANEL_10BIT_PER_COLOR                            0x03
716 #define PANEL_12BIT_PER_COLOR                            0x04
717 #define PANEL_16BIT_PER_COLOR                            0x05
718
719 /****************************************************************************/  
720 // Structures used by UNIPHYTransmitterControlTable
721 //                    LVTMATransmitterControlTable
722 //                    DVOOutputControlTable
723 /****************************************************************************/  
724 typedef struct _ATOM_DP_VS_MODE
725 {
726   UCHAR ucLaneSel;
727   UCHAR ucLaneSet;
728 }ATOM_DP_VS_MODE;
729
730 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
731 {
732         union
733         {
734   USHORT usPixelClock;          // in 10KHz; for bios convenient
735         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
736   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
737         };
738   UCHAR ucConfig;
739                                                                                                         // [0]=0: 4 lane Link,      
740                                                                                                         //    =1: 8 lane Link ( Dual Links TMDS ) 
741                           // [1]=0: InCoherent mode   
742                                                                                                         //    =1: Coherent Mode                                                                         
743                                                                                                         // [2] Link Select:
744                                                                                                 // =0: PHY linkA   if bfLane<3
745                                                                                                         // =1: PHY linkB   if bfLanes<3
746                                                                                                 // =0: PHY linkA+B if bfLanes=3         
747                           // [5:4]PCIE lane Sel
748                           // =0: lane 0~3 or 0~7
749                           // =1: lane 4~7
750                           // =2: lane 8~11 or 8~15
751                           // =3: lane 12~15 
752         UCHAR ucAction;                           // =0: turn off encoder                                       
753                                 // =1: turn on encoder                  
754   UCHAR ucReserved[4];
755 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
756
757 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS                                      
758
759 //ucInitInfo
760 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff                  
761
762 //ucConfig 
763 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
764 #define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
765 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
766 #define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
767 #define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
768 #define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00                    
769 #define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
770
771 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
772 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
773 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
774
775 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
776 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
777 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
778 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
779 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
780 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
781 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
782 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
783 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
784 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
785 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
786
787 //ucAction
788 #define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
789 #define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
790 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
791 #define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
792 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
793 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
794 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
795 #define ATOM_TRANSMITTER_ACTION_INIT                                                   7
796 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
797 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
798 #define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
799 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
800 #define ATOM_TRANSMITTER_ACTION_POWER_ON               12
801 #define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
802
803 // Following are used for DigTransmitterControlTable ver1.2
804 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
805 {
806 #if ATOM_BIG_ENDIAN
807   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
808                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
809                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
810   UCHAR ucReserved:1;               
811   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
812   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
813   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
814                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
815
816   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
817   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
818 #else
819   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
820   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
821   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
822                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
823   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
824   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
825   UCHAR ucReserved:1;               
826   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
827                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
828                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
829 #endif
830 }ATOM_DIG_TRANSMITTER_CONFIG_V2;
831
832 //ucConfig 
833 //Bit0
834 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                  0x01
835
836 //Bit1
837 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                       0x02
838
839 //Bit2
840 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                        0x04
841 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                    0x00
842 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                            0x04
843
844 // Bit3
845 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK             0x08
846 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                   0x00                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
847 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                   0x08                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
848
849 // Bit4
850 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                          0x10
851
852 // Bit7:6
853 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
854 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                 0x00    //AB
855 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                 0x40    //CD
856 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                 0x80    //EF
857
858 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
859 {
860         union
861         {
862   USHORT usPixelClock;          // in 10KHz; for bios convenient
863         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
864   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
865         };
866   ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
867         UCHAR ucAction;                           // define as ATOM_TRANSMITER_ACTION_XXX
868   UCHAR ucReserved[4];
869 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
870
871 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
872 {
873 #if ATOM_BIG_ENDIAN
874   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
875                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
876                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
877   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
878   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
879   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
880                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
881   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
882   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
883 #else
884   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
885   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
886   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
887                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
888   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
889   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
890   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
891                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
892                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
893 #endif
894 }ATOM_DIG_TRANSMITTER_CONFIG_V3;
895
896 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
897 {
898         union
899         {
900     USHORT usPixelClock;                // in 10KHz; for bios convenient
901           USHORT usInitInfo;                    // when init uniphy,lower 8bit is used for connector type defined in objectid.h
902     ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
903         };
904   ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
905         UCHAR ucAction;                             // define as ATOM_TRANSMITER_ACTION_XXX
906   UCHAR ucLaneNum;
907   UCHAR ucReserved[3];
908 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
909
910 //ucConfig 
911 //Bit0
912 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR                  0x01
913
914 //Bit1
915 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                                       0x02
916
917 //Bit2
918 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK                        0x04
919 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA                                    0x00
920 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB                                            0x04
921
922 // Bit3
923 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK             0x08
924 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                   0x00
925 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                   0x08
926
927 // Bit5:4
928 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK               0x30
929 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL                                 0x00
930 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL                           0x10
931 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
932
933 // Bit7:6
934 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
935 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1                 0x00    //AB
936 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2                 0x40    //CD
937 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3                 0x80    //EF
938
939 /****************************************************************************/  
940 // Structures used by DAC1OuputControlTable
941 //                    DAC2OuputControlTable
942 //                    LVTMAOutputControlTable  (Before DEC30)
943 //                    TMDSAOutputControlTable  (Before DEC30)
944 /****************************************************************************/  
945 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
946 {
947   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
948                                       // When the display is LCD, in addition to above:
949                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
950                                       // ATOM_LCD_SELFTEST_STOP
951                                       
952   UCHAR  aucPadding[3];               // padding to DWORD aligned
953 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
954
955 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
956
957
958 #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
959 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
960
961 #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
962 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
963
964 #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
965 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
966
967 #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
968 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
969
970 #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
971 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
972
973 #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
974 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
975
976 #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
977 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
978
979 #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
980 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
981 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
982
983 /****************************************************************************/  
984 // Structures used by BlankCRTCTable
985 /****************************************************************************/  
986 typedef struct _BLANK_CRTC_PARAMETERS
987 {
988   UCHAR  ucCRTC;                        // ATOM_CRTC1 or ATOM_CRTC2
989   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
990   USHORT usBlackColorRCr;
991   USHORT usBlackColorGY;
992   USHORT usBlackColorBCb;
993 }BLANK_CRTC_PARAMETERS;
994 #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
995
996 /****************************************************************************/  
997 // Structures used by EnableCRTCTable
998 //                    EnableCRTCMemReqTable
999 //                    UpdateCRTC_DoubleBufferRegistersTable
1000 /****************************************************************************/  
1001 typedef struct _ENABLE_CRTC_PARAMETERS
1002 {
1003   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1004   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE 
1005   UCHAR ucPadding[2];
1006 }ENABLE_CRTC_PARAMETERS;
1007 #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
1008
1009 /****************************************************************************/  
1010 // Structures used by SetCRTC_OverScanTable
1011 /****************************************************************************/  
1012 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1013 {
1014   USHORT usOverscanRight;             // right
1015   USHORT usOverscanLeft;              // left
1016   USHORT usOverscanBottom;            // bottom
1017   USHORT usOverscanTop;               // top
1018   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
1019   UCHAR  ucPadding[3];
1020 }SET_CRTC_OVERSCAN_PARAMETERS;
1021 #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
1022
1023 /****************************************************************************/  
1024 // Structures used by SetCRTC_ReplicationTable
1025 /****************************************************************************/  
1026 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1027 {
1028   UCHAR ucH_Replication;              // horizontal replication
1029   UCHAR ucV_Replication;              // vertical replication
1030   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
1031   UCHAR ucPadding;
1032 }SET_CRTC_REPLICATION_PARAMETERS;
1033 #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
1034
1035 /****************************************************************************/  
1036 // Structures used by SelectCRTC_SourceTable
1037 /****************************************************************************/  
1038 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1039 {
1040   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1041   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1042   UCHAR ucPadding[2];
1043 }SELECT_CRTC_SOURCE_PARAMETERS;
1044 #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
1045
1046 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1047 {
1048   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1049   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1050   UCHAR ucEncodeMode;                                                                   // Encoding mode, only valid when using DIG1/DIG2/DVO
1051   UCHAR ucPadding;
1052 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
1053
1054 //ucEncoderID
1055 //#define ASIC_INT_DAC1_ENCODER_ID                                              0x00 
1056 //#define ASIC_INT_TV_ENCODER_ID                                                                        0x02
1057 //#define ASIC_INT_DIG1_ENCODER_ID                                                              0x03
1058 //#define ASIC_INT_DAC2_ENCODER_ID                                                              0x04
1059 //#define ASIC_EXT_TV_ENCODER_ID                                                                        0x06
1060 //#define ASIC_INT_DVO_ENCODER_ID                                                                       0x07
1061 //#define ASIC_INT_DIG2_ENCODER_ID                                                              0x09
1062 //#define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05
1063
1064 //ucEncodeMode
1065 //#define ATOM_ENCODER_MODE_DP                                                                          0
1066 //#define ATOM_ENCODER_MODE_LVDS                                                                        1
1067 //#define ATOM_ENCODER_MODE_DVI                                                                         2
1068 //#define ATOM_ENCODER_MODE_HDMI                                                                        3
1069 //#define ATOM_ENCODER_MODE_SDVO                                                                        4
1070 //#define ATOM_ENCODER_MODE_TV                                                                          13
1071 //#define ATOM_ENCODER_MODE_CV                                                                          14
1072 //#define ATOM_ENCODER_MODE_CRT                                                                         15
1073
1074 /****************************************************************************/  
1075 // Structures used by SetPixelClockTable
1076 //                    GetPixelClockTable 
1077 /****************************************************************************/  
1078 //Major revision=1., Minor revision=1
1079 typedef struct _PIXEL_CLOCK_PARAMETERS
1080 {
1081   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1082                                       // 0 means disable PPLL
1083   USHORT usRefDiv;                    // Reference divider
1084   USHORT usFbDiv;                     // feedback divider
1085   UCHAR  ucPostDiv;                   // post divider   
1086   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1087   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1088   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1089   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1090   UCHAR  ucPadding;
1091 }PIXEL_CLOCK_PARAMETERS;
1092
1093 //Major revision=1., Minor revision=2, add ucMiscIfno
1094 //ucMiscInfo:
1095 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1096 #define MISC_DEVICE_INDEX_MASK        0xF0
1097 #define MISC_DEVICE_INDEX_SHIFT       4
1098
1099 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1100 {
1101   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1102                                       // 0 means disable PPLL
1103   USHORT usRefDiv;                    // Reference divider
1104   USHORT usFbDiv;                     // feedback divider
1105   UCHAR  ucPostDiv;                   // post divider   
1106   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1107   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1108   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1109   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1110   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1111 }PIXEL_CLOCK_PARAMETERS_V2;
1112
1113 //Major revision=1., Minor revision=3, structure/definition change
1114 //ucEncoderMode:
1115 //ATOM_ENCODER_MODE_DP
1116 //ATOM_ENOCDER_MODE_LVDS
1117 //ATOM_ENOCDER_MODE_DVI
1118 //ATOM_ENOCDER_MODE_HDMI
1119 //ATOM_ENOCDER_MODE_SDVO
1120 //ATOM_ENCODER_MODE_TV                                                                          13
1121 //ATOM_ENCODER_MODE_CV                                                                          14
1122 //ATOM_ENCODER_MODE_CRT                                                                         15
1123
1124 //ucDVOConfig
1125 //#define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01
1126 //#define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00
1127 //#define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01
1128 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c
1129 //#define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00
1130 //#define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04
1131 //#define DVO_ENCODER_CONFIG_24BIT                                                              0x08
1132
1133 //ucMiscInfo: also changed, see below
1134 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
1135 #define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
1136 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
1137 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
1138 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
1139 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
1140 #define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
1141 // V1.4 for RoadRunner
1142 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
1143 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
1144
1145 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1146 {
1147   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1148                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1149   USHORT usRefDiv;                    // Reference divider
1150   USHORT usFbDiv;                     // feedback divider
1151   UCHAR  ucPostDiv;                   // post divider   
1152   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1153   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1154   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
1155         union
1156         {
1157   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1158         UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
1159         };
1160   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1161                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1162                                       // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1163 }PIXEL_CLOCK_PARAMETERS_V3;
1164
1165 #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
1166 #define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
1167
1168 typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1169 {
1170   UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to 
1171                              // drive the pixel clock. not used for DCPLL case.
1172   union{
1173   UCHAR  ucReserved;
1174   UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
1175   };
1176   USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
1177                              // 0 means disable PPLL/DCPLL. 
1178   USHORT usFbDiv;            // feedback divider integer part. 
1179   UCHAR  ucPostDiv;          // post divider. 
1180   UCHAR  ucRefDiv;           // Reference divider
1181   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1182   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h, 
1183                              // indicate which graphic encoder will be used. 
1184   UCHAR  ucEncoderMode;      // Encoder mode: 
1185   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL 
1186                              // bit[1]= when VGA timing is used. 
1187                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1188                              // bit[4]= RefClock source for PPLL. 
1189                              // =0: XTLAIN( default mode )
1190                                    // =1: other external clock source, which is pre-defined
1191                              //     by VBIOS depend on the feature required.
1192                              // bit[7:5]: reserved.
1193   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1194
1195 }PIXEL_CLOCK_PARAMETERS_V5;
1196
1197 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL                                     0x01
1198 #define PIXEL_CLOCK_V5_MISC_VGA_MODE                                                            0x02
1199 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
1200 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
1201 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
1202 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
1203 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
1204
1205 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1206 {
1207   PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1208 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1209
1210 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1211 {
1212   UCHAR  ucStatus;
1213   UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1214   UCHAR  ucReserved[2];
1215 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1216
1217 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1218 {
1219   PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1220 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1221
1222 /****************************************************************************/  
1223 // Structures used by AdjustDisplayPllTable
1224 /****************************************************************************/  
1225 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1226 {
1227         USHORT usPixelClock;
1228         UCHAR ucTransmitterID;
1229         UCHAR ucEncodeMode;
1230         union
1231         {
1232                 UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
1233                 UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
1234         };
1235         UCHAR ucReserved[3];
1236 }ADJUST_DISPLAY_PLL_PARAMETERS;
1237
1238 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
1239 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
1240
1241 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1242 {
1243         USHORT usPixelClock;                    // target pixel clock
1244         UCHAR ucTransmitterID;                  // transmitter id defined in objectid.h
1245         UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1246   UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1247         UCHAR ucReserved[3];
1248 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1249
1250 // usDispPllConfig v1.2 for RoadRunner
1251 #define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
1252 #define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
1253 #define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
1254 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
1255 #define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
1256 #define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
1257 #define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
1258 #define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
1259 #define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
1260 #define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
1261
1262
1263 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1264 {
1265   ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1266   UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1267   UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1268   UCHAR ucReserved[2];  
1269 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1270
1271 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1272 {
1273   union 
1274   {
1275     ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
1276     ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1277   };
1278 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1279
1280 /****************************************************************************/  
1281 // Structures used by EnableYUVTable
1282 /****************************************************************************/  
1283 typedef struct _ENABLE_YUV_PARAMETERS
1284 {
1285   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1286   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
1287   UCHAR ucPadding[2];
1288 }ENABLE_YUV_PARAMETERS;
1289 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1290
1291 /****************************************************************************/  
1292 // Structures used by GetMemoryClockTable
1293 /****************************************************************************/  
1294 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1295 {
1296   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
1297 } GET_MEMORY_CLOCK_PARAMETERS;
1298 #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
1299
1300 /****************************************************************************/  
1301 // Structures used by GetEngineClockTable
1302 /****************************************************************************/  
1303 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1304 {
1305   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
1306 } GET_ENGINE_CLOCK_PARAMETERS;
1307 #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
1308
1309 /****************************************************************************/  
1310 // Following Structures and constant may be obsolete
1311 /****************************************************************************/  
1312 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1313 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1314 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1315 {
1316   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1317   USHORT    usVRAMAddress;      //Adress in Frame Buffer where to pace raw EDID
1318   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
1319                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
1320   UCHAR     ucSlaveAddr;        //Read from which slave
1321   UCHAR     ucLineNumber;       //Read from which HW assisted line
1322 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1323 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1324
1325
1326 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
1327 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
1328 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
1329 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
1330 #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
1331
1332 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1333 {
1334   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1335   USHORT    usByteOffset;       //Write to which byte
1336                                 //Upper portion of usByteOffset is Format of data 
1337                                 //1bytePS+offsetPS
1338                                 //2bytesPS+offsetPS
1339                                 //blockID+offsetPS
1340                                 //blockID+offsetID
1341                                 //blockID+counterID+offsetID
1342   UCHAR     ucData;             //PS data1
1343   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
1344   UCHAR     ucSlaveAddr;        //Write to which slave
1345   UCHAR     ucLineNumber;       //Write from which HW assisted line
1346 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1347
1348 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1349
1350 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1351 {
1352   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1353   UCHAR     ucSlaveAddr;        //Write to which slave
1354   UCHAR     ucLineNumber;       //Write from which HW assisted line
1355 }SET_UP_HW_I2C_DATA_PARAMETERS;
1356
1357
1358 /**************************************************************************/
1359 #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1360
1361 /****************************************************************************/  
1362 // Structures used by PowerConnectorDetectionTable
1363 /****************************************************************************/  
1364 typedef struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
1365 {
1366   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1367         UCHAR   ucPwrBehaviorId;                                                        
1368         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
1369 }POWER_CONNECTOR_DETECTION_PARAMETERS;
1370
1371 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1372 {                               
1373   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1374         UCHAR   ucReserved;
1375         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
1376   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
1377 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1378
1379 /****************************LVDS SS Command Table Definitions**********************/
1380
1381 /****************************************************************************/  
1382 // Structures used by EnableSpreadSpectrumOnPPLLTable
1383 /****************************************************************************/  
1384 typedef struct  _ENABLE_LVDS_SS_PARAMETERS
1385 {
1386   USHORT  usSpreadSpectrumPercentage;       
1387   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1388   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1389   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1390   UCHAR   ucPadding[3];
1391 }ENABLE_LVDS_SS_PARAMETERS;
1392
1393 //ucTableFormatRevision=1,ucTableContentRevision=2
1394 typedef struct  _ENABLE_LVDS_SS_PARAMETERS_V2
1395 {
1396   USHORT  usSpreadSpectrumPercentage;       
1397   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1398   UCHAR   ucSpreadSpectrumStep;           //
1399   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1400   UCHAR   ucSpreadSpectrumDelay;
1401   UCHAR   ucSpreadSpectrumRange;
1402   UCHAR   ucPadding;
1403 }ENABLE_LVDS_SS_PARAMETERS_V2;
1404
1405 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1406 typedef struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1407 {
1408   USHORT  usSpreadSpectrumPercentage;
1409   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1410   UCHAR   ucSpreadSpectrumStep;           //
1411   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
1412   UCHAR   ucSpreadSpectrumDelay;
1413   UCHAR   ucSpreadSpectrumRange;
1414   UCHAR   ucPpll;                                                                                                 // ATOM_PPLL1/ATOM_PPLL2
1415 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1416
1417 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1418 {
1419   USHORT  usSpreadSpectrumPercentage;
1420   UCHAR   ucSpreadSpectrumType;         // Bit[0]: 0-Down Spread,1-Center Spread. 
1421                                         // Bit[1]: 1-Ext. 0-Int. 
1422                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1423                                         // Bits[7:4] reserved
1424   UCHAR   ucEnable;                         // ATOM_ENABLE or ATOM_DISABLE
1425   USHORT  usSpreadSpectrumAmount;       // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
1426   USHORT  usSpreadSpectrumStep;         // SS_STEP_SIZE_DSFRAC
1427 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1428
1429 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
1430 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
1431 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
1432 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
1433 #define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
1434 #define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
1435 #define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
1436 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
1437 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
1438 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
1439 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
1440
1441 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
1442
1443 /**************************************************************************/
1444
1445 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
1446 {
1447   PIXEL_CLOCK_PARAMETERS sPCLKInput;
1448   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 
1449 }SET_PIXEL_CLOCK_PS_ALLOCATION;
1450
1451 #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
1452
1453 /****************************************************************************/  
1454 // Structures used by ###
1455 /****************************************************************************/  
1456 typedef struct  _MEMORY_TRAINING_PARAMETERS
1457 {
1458   ULONG ulTargetMemoryClock;          //In 10Khz unit
1459 }MEMORY_TRAINING_PARAMETERS;
1460 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
1461
1462
1463 /****************************LVDS and other encoder command table definitions **********************/
1464
1465
1466 /****************************************************************************/  
1467 // Structures used by LVDSEncoderControlTable   (Before DCE30)
1468 //                    LVTMAEncoderControlTable  (Before DCE30)
1469 //                    TMDSAEncoderControlTable  (Before DCE30)
1470 /****************************************************************************/  
1471 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
1472 {
1473   USHORT usPixelClock;  // in 10KHz; for bios convenient
1474   UCHAR  ucMisc;        // bit0=0: Enable single link
1475                         //     =1: Enable dual link
1476                         // Bit1=0: 666RGB
1477                         //     =1: 888RGB
1478   UCHAR  ucAction;      // 0: turn off encoder
1479                         // 1: setup and turn on encoder
1480 }LVDS_ENCODER_CONTROL_PARAMETERS;
1481
1482 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
1483    
1484 #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
1485 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
1486
1487 #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
1488 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
1489
1490
1491 //ucTableFormatRevision=1,ucTableContentRevision=2
1492 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
1493 {
1494   USHORT usPixelClock;  // in 10KHz; for bios convenient
1495   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
1496   UCHAR  ucAction;      // 0: turn off encoder
1497                         // 1: setup and turn on encoder
1498   UCHAR  ucTruncate;    // bit0=0: Disable truncate
1499                         //     =1: Enable truncate
1500                         // bit4=0: 666RGB
1501                         //     =1: 888RGB
1502   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
1503                         //     =1: Enable spatial dithering
1504                         // bit4=0: 666RGB
1505                         //     =1: 888RGB
1506   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
1507                         //     =1: Enable temporal dithering
1508                         // bit4=0: 666RGB
1509                         //     =1: 888RGB
1510                         // bit5=0: Gray level 2
1511                         //     =1: Gray level 4
1512   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
1513                         //     =1: 25FRC_SEL pattern F
1514                         // bit6:5=0: 50FRC_SEL pattern A
1515                         //       =1: 50FRC_SEL pattern B
1516                         //       =2: 50FRC_SEL pattern C
1517                         //       =3: 50FRC_SEL pattern D
1518                         // bit7=0: 75FRC_SEL pattern E
1519                         //     =1: 75FRC_SEL pattern F
1520 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
1521
1522 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
1523    
1524 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
1525 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
1526   
1527 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
1528 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
1529
1530 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
1531 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
1532
1533 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1534 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
1535
1536 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1537 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
1538
1539 /****************************************************************************/  
1540 // Structures used by ###
1541 /****************************************************************************/  
1542 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
1543 {                               
1544   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
1545   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
1546   UCHAR    ucPadding[2];
1547 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
1548
1549 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
1550 {                               
1551   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
1552   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
1553 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
1554
1555 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
1556
1557 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
1558 {                               
1559   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
1560   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
1561 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
1562
1563 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
1564 {
1565   DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
1566   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1567 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
1568
1569 /****************************************************************************/  
1570 // Structures used by DVOEncoderControlTable
1571 /****************************************************************************/  
1572 //ucTableFormatRevision=1,ucTableContentRevision=3
1573
1574 //ucDVOConfig:
1575 #define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
1576 #define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
1577 #define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
1578 #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
1579 #define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
1580 #define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
1581 #define DVO_ENCODER_CONFIG_24BIT                                                                0x08
1582
1583 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
1584 {
1585   USHORT usPixelClock; 
1586   UCHAR  ucDVOConfig;
1587   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
1588   UCHAR  ucReseved[4];
1589 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
1590 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
1591
1592 //ucTableFormatRevision=1
1593 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 
1594 // bit1=0: non-coherent mode
1595 //     =1: coherent mode
1596
1597 //==========================================================================================
1598 //Only change is here next time when changing encoder parameter definitions again!
1599 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
1600 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
1601
1602 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1603 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
1604
1605 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1606 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
1607
1608 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
1609 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
1610
1611 //==========================================================================================
1612 #define PANEL_ENCODER_MISC_DUAL                0x01
1613 #define PANEL_ENCODER_MISC_COHERENT            0x02
1614 #define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
1615 #define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
1616
1617 #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
1618 #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
1619 #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
1620
1621 #define PANEL_ENCODER_TRUNCATE_EN              0x01
1622 #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
1623 #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
1624 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
1625 #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
1626 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
1627 #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
1628 #define PANEL_ENCODER_25FRC_MASK               0x10
1629 #define PANEL_ENCODER_25FRC_E                  0x00
1630 #define PANEL_ENCODER_25FRC_F                  0x10
1631 #define PANEL_ENCODER_50FRC_MASK               0x60
1632 #define PANEL_ENCODER_50FRC_A                  0x00
1633 #define PANEL_ENCODER_50FRC_B                  0x20
1634 #define PANEL_ENCODER_50FRC_C                  0x40
1635 #define PANEL_ENCODER_50FRC_D                  0x60
1636 #define PANEL_ENCODER_75FRC_MASK               0x80
1637 #define PANEL_ENCODER_75FRC_E                  0x00
1638 #define PANEL_ENCODER_75FRC_F                  0x80
1639
1640 /****************************************************************************/  
1641 // Structures used by SetVoltageTable
1642 /****************************************************************************/  
1643 #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
1644 #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
1645 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
1646 #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
1647 #define SET_VOLTAGE_INIT_MODE                  5
1648 #define SET_VOLTAGE_GET_MAX_VOLTAGE            6                                        //Gets the Max. voltage for the soldered Asic
1649
1650 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
1651 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
1652 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
1653
1654 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
1655 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1      
1656 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
1657
1658 typedef struct  _SET_VOLTAGE_PARAMETERS
1659 {
1660   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
1661   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
1662   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
1663   UCHAR    ucReserved;          
1664 }SET_VOLTAGE_PARAMETERS;
1665
1666 typedef struct  _SET_VOLTAGE_PARAMETERS_V2
1667 {
1668   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
1669   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
1670   USHORT   usVoltageLevel;              // real voltage level
1671 }SET_VOLTAGE_PARAMETERS_V2;
1672
1673 typedef struct _SET_VOLTAGE_PS_ALLOCATION
1674 {
1675   SET_VOLTAGE_PARAMETERS sASICSetVoltage;
1676   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1677 }SET_VOLTAGE_PS_ALLOCATION;
1678
1679 /****************************************************************************/  
1680 // Structures used by TVEncoderControlTable
1681 /****************************************************************************/  
1682 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
1683 {
1684   USHORT usPixelClock;                // in 10KHz; for bios convenient
1685   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
1686   UCHAR  ucAction;                    // 0: turn off encoder
1687                                       // 1: setup and turn on encoder
1688 }TV_ENCODER_CONTROL_PARAMETERS;
1689
1690 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
1691 {
1692   TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;          
1693   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
1694 }TV_ENCODER_CONTROL_PS_ALLOCATION;
1695
1696 //==============================Data Table Portion====================================
1697
1698 /****************************************************************************/  
1699 // Structure used in Data.mtb
1700 /****************************************************************************/  
1701 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
1702 {
1703   USHORT        UtilityPipeLine;                // Offest for the utility to get parser info,Don't change this position!
1704   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 
1705   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
1706   USHORT        StandardVESA_Timing;      // Only used by Bios
1707   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
1708   USHORT        DAC_Info;                 // Will be obsolete from R600
1709   USHORT        LVDS_Info;                // Shared by various SW components,latest version 1.1 
1710   USHORT        TMDS_Info;                // Will be obsolete from R600
1711   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1 
1712   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
1713   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600           
1714   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
1715   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
1716   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
1717   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
1718   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
1719   USHORT        CompassionateData;        // Will be obsolete from R600
1720   USHORT        SaveRestoreInfo;          // Only used by Bios
1721   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
1722   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
1723   USHORT        XTMDS_Info;               // Will be obsolete from R600
1724   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
1725   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
1726   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
1727   USHORT        MC_InitParameter;         // Only used by command table
1728   USHORT        ASIC_VDDC_Info;                                         // Will be obsolete from R600
1729   USHORT        ASIC_InternalSS_Info;                   // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
1730   USHORT        TV_VideoMode;                                                   // Only used by command table
1731   USHORT        VRAM_Info;                                                              // Only used by command table, latest version 1.3
1732   USHORT        MemoryTrainingInfo;                             // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
1733   USHORT        IntegratedSystemInfo;                   // Shared by various SW components
1734   USHORT        ASIC_ProfilingInfo;                             // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
1735   USHORT        VoltageObjectInfo;                              // Shared by various SW components, latest version 1.1
1736         USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
1737 }ATOM_MASTER_LIST_OF_DATA_TABLES;
1738
1739 typedef struct _ATOM_MASTER_DATA_TABLE
1740
1741   ATOM_COMMON_TABLE_HEADER sHeader;  
1742   ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
1743 }ATOM_MASTER_DATA_TABLE;
1744
1745 /****************************************************************************/  
1746 // Structure used in MultimediaCapabilityInfoTable
1747 /****************************************************************************/  
1748 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
1749 {
1750   ATOM_COMMON_TABLE_HEADER sHeader;  
1751   ULONG                    ulSignature;      // HW info table signature string "$ATI"
1752   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
1753   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
1754   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
1755   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
1756 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
1757
1758 /****************************************************************************/  
1759 // Structure used in MultimediaConfigInfoTable
1760 /****************************************************************************/  
1761 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
1762 {
1763   ATOM_COMMON_TABLE_HEADER sHeader;
1764   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
1765   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
1766   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
1767   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
1768   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
1769   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
1770   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
1771   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
1772   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1773   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1774   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1775   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1776   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1777 }ATOM_MULTIMEDIA_CONFIG_INFO;
1778
1779 /****************************************************************************/  
1780 // Structures used in FirmwareInfoTable
1781 /****************************************************************************/  
1782
1783 // usBIOSCapability Defintion:
1784 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 
1785 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 
1786 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 
1787 // Others: Reserved
1788 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
1789 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
1790 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
1791 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008              // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 
1792 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010              // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 
1793 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
1794 #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
1795 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
1796 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
1797 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
1798 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
1799 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
1800 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008              // (valid from v2.1 ): =1: memclk ss enable with external ss chip
1801 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010              // (valid from v2.1 ): =1: engclk ss enable with external ss chip
1802
1803 #ifndef _H2INC
1804
1805 //Please don't add or expand this bitfield structure below, this one will retire soon.!
1806 typedef struct _ATOM_FIRMWARE_CAPABILITY
1807 {
1808 #if ATOM_BIG_ENDIAN
1809   USHORT Reserved:3;
1810   USHORT HyperMemory_Size:4;
1811   USHORT HyperMemory_Support:1;
1812   USHORT PPMode_Assigned:1;
1813   USHORT WMI_SUPPORT:1;
1814   USHORT GPUControlsBL:1;
1815   USHORT EngineClockSS_Support:1;
1816   USHORT MemoryClockSS_Support:1;
1817   USHORT ExtendedDesktopSupport:1;
1818   USHORT DualCRTC_Support:1;
1819   USHORT FirmwarePosted:1;
1820 #else
1821   USHORT FirmwarePosted:1;
1822   USHORT DualCRTC_Support:1;
1823   USHORT ExtendedDesktopSupport:1;
1824   USHORT MemoryClockSS_Support:1;
1825   USHORT EngineClockSS_Support:1;
1826   USHORT GPUControlsBL:1;
1827   USHORT WMI_SUPPORT:1;
1828   USHORT PPMode_Assigned:1;
1829   USHORT HyperMemory_Support:1;
1830   USHORT HyperMemory_Size:4;
1831   USHORT Reserved:3;
1832 #endif
1833 }ATOM_FIRMWARE_CAPABILITY;
1834
1835 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
1836 {
1837   ATOM_FIRMWARE_CAPABILITY sbfAccess;
1838   USHORT                   susAccess;
1839 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
1840
1841 #else
1842
1843 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
1844 {
1845   USHORT                   susAccess;
1846 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
1847
1848 #endif
1849
1850 typedef struct _ATOM_FIRMWARE_INFO
1851 {
1852   ATOM_COMMON_TABLE_HEADER        sHeader; 
1853   ULONG                           ulFirmwareRevision;
1854   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1855   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1856   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1857   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1858   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1859   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1860   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1861   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1862   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1863   UCHAR                           ucASICMaxTemperature;
1864   UCHAR                           ucPadding[3];               //Don't use them
1865   ULONG                           aulReservedForBIOS[3];      //Don't use them
1866   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1867   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1868   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1869   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1870   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1871   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1872   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1873   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1874   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1875   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
1876   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1877   USHORT                          usReferenceClock;           //In 10Khz unit   
1878   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
1879   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1880   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1881   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1882 }ATOM_FIRMWARE_INFO;
1883
1884 typedef struct _ATOM_FIRMWARE_INFO_V1_2
1885 {
1886   ATOM_COMMON_TABLE_HEADER        sHeader; 
1887   ULONG                           ulFirmwareRevision;
1888   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1889   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1890   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1891   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1892   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1893   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1894   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1895   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1896   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1897   UCHAR                           ucASICMaxTemperature;
1898   UCHAR                           ucMinAllowedBL_Level;
1899   UCHAR                           ucPadding[2];               //Don't use them
1900   ULONG                           aulReservedForBIOS[2];      //Don't use them
1901   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1902   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1903   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1904   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1905   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1906   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1907   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1908   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1909   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1910   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1911   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1912   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1913   USHORT                          usReferenceClock;           //In 10Khz unit   
1914   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
1915   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1916   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1917   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1918 }ATOM_FIRMWARE_INFO_V1_2;
1919
1920 typedef struct _ATOM_FIRMWARE_INFO_V1_3
1921 {
1922   ATOM_COMMON_TABLE_HEADER        sHeader; 
1923   ULONG                           ulFirmwareRevision;
1924   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1925   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1926   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1927   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1928   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1929   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1930   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1931   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1932   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1933   UCHAR                           ucASICMaxTemperature;
1934   UCHAR                           ucMinAllowedBL_Level;
1935   UCHAR                           ucPadding[2];               //Don't use them
1936   ULONG                           aulReservedForBIOS;         //Don't use them
1937   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
1938   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1939   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1940   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1941   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1942   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1943   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1944   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1945   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1946   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1947   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1948   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1949   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1950   USHORT                          usReferenceClock;           //In 10Khz unit   
1951   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
1952   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1953   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1954   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1955 }ATOM_FIRMWARE_INFO_V1_3;
1956
1957 typedef struct _ATOM_FIRMWARE_INFO_V1_4
1958 {
1959   ATOM_COMMON_TABLE_HEADER        sHeader; 
1960   ULONG                           ulFirmwareRevision;
1961   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1962   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1963   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1964   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1965   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1966   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1967   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1968   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1969   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1970   UCHAR                           ucASICMaxTemperature;
1971   UCHAR                           ucMinAllowedBL_Level;
1972   USHORT                          usBootUpVDDCVoltage;        //In MV unit
1973   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
1974   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
1975   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
1976   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1977   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1978   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1979   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1980   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1981   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1982   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1983   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1984   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1985   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1986   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1987   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1988   USHORT                          usReferenceClock;           //In 10Khz unit   
1989   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
1990   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1991   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1992   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1993 }ATOM_FIRMWARE_INFO_V1_4;
1994
1995 //the structure below to be used from Cypress
1996 typedef struct _ATOM_FIRMWARE_INFO_V2_1
1997 {
1998   ATOM_COMMON_TABLE_HEADER        sHeader; 
1999   ULONG                           ulFirmwareRevision;
2000   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2001   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2002   ULONG                           ulReserved1;
2003   ULONG                           ulReserved2;
2004   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2005   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2006   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2007   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
2008   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
2009   UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
2010   UCHAR                           ucMinAllowedBL_Level;
2011   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2012   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2013   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2014   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
2015   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2016   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2017   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2018   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2019   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2020   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2021   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2022   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2023   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2024   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2025   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2026   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2027   USHORT                          usCoreReferenceClock;       //In 10Khz unit   
2028   USHORT                          usMemoryReferenceClock;     //In 10Khz unit   
2029   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2030   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2031   UCHAR                           ucReserved4[3];
2032 }ATOM_FIRMWARE_INFO_V2_1;
2033
2034
2035 #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_1
2036
2037 /****************************************************************************/  
2038 // Structures used in IntegratedSystemInfoTable
2039 /****************************************************************************/  
2040 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
2041 #define IGP_CAP_FLAG_AC_CARD               0x4
2042 #define IGP_CAP_FLAG_SDVO_CARD             0x8
2043 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
2044
2045 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2046 {
2047   ATOM_COMMON_TABLE_HEADER        sHeader; 
2048   ULONG                           ulBootUpEngineClock;              //in 10kHz unit
2049   ULONG                           ulBootUpMemoryClock;              //in 10kHz unit
2050   ULONG                           ulMaxSystemMemoryClock;           //in 10kHz unit
2051   ULONG                           ulMinSystemMemoryClock;           //in 10kHz unit
2052   UCHAR                           ucNumberOfCyclesInPeriodHi;
2053   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2054   USHORT                          usReserved1;
2055   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage 
2056   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage 
2057   ULONG                           ulReserved[2];
2058
2059   USHORT                                usFSBClock;                                 //In MHz unit
2060   USHORT                          usCapabilityFlag;                     //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2061                                                                                                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2062                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
2063   USHORT                                usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2064   USHORT                                usK8MemoryClock;            //in MHz unit
2065   USHORT                                usK8SyncStartDelay;         //in 0.01 us unit
2066   USHORT                                usK8DataReturnTime;         //in 0.01 us unit
2067   UCHAR                           ucMaxNBVoltage;
2068   UCHAR                           ucMinNBVoltage;
2069   UCHAR                           ucMemoryType;                                       //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2070   UCHAR                           ucNumberOfCyclesInPeriod;             //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 
2071   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2072   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
2073   UCHAR                           ucMaxNBVoltageHigh;    
2074   UCHAR                           ucMinNBVoltageHigh;
2075 }ATOM_INTEGRATED_SYSTEM_INFO;
2076
2077 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2078 ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock 
2079                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2080 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2081                         For AMD IGP,for now this can be 0
2082 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 
2083                         For AMD IGP,for now this can be 0
2084
2085 usFSBClock:             For Intel IGP,it's FSB Freq 
2086                         For AMD IGP,it's HT Link Speed
2087
2088 usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
2089 usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2090 usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2091
2092 VC:Voltage Control
2093 ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2094 ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2095
2096 ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 
2097 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 
2098
2099 ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2100 ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2101
2102
2103 usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2104 usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2105 */
2106
2107
2108 /*
2109 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2110 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 
2111 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2112
2113 SW components can access the IGP system infor structure in the same way as before
2114 */
2115
2116
2117 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2118 {
2119   ATOM_COMMON_TABLE_HEADER   sHeader;
2120   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
2121   ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
2122   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
2123   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
2124   ULONG                      ulMinSidePortClock;        //in 10kHz unit
2125   ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
2126   ULONG                      ulSystemConfig;            //see explanation below
2127   ULONG                      ulBootUpReqDisplayVector;
2128   ULONG                      ulOtherDisplayMisc;
2129   ULONG                      ulDDISlot1Config;
2130   ULONG                      ulDDISlot2Config;
2131   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2132   UCHAR                      ucUMAChannelNumber;
2133   UCHAR                      ucDockingPinBit;
2134   UCHAR                      ucDockingPinPolarity;
2135   ULONG                      ulDockingPinCFGInfo;
2136   ULONG                      ulCPUCapInfo;
2137   USHORT                     usNumberOfCyclesInPeriod;
2138   USHORT                     usMaxNBVoltage;
2139   USHORT                     usMinNBVoltage;
2140   USHORT                     usBootUpNBVoltage;
2141   ULONG                      ulHTLinkFreq;              //in 10Khz
2142   USHORT                     usMinHTLinkWidth;
2143   USHORT                     usMaxHTLinkWidth;
2144   USHORT                     usUMASyncStartDelay;
2145   USHORT                     usUMADataReturnTime;
2146   USHORT                     usLinkStatusZeroTime;
2147   USHORT                     usDACEfuse;                                //for storing badgap value (for RS880 only)
2148   ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
2149   ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
2150   USHORT                     usMaxUpStreamHTLinkWidth;
2151   USHORT                     usMaxDownStreamHTLinkWidth;
2152   USHORT                     usMinUpStreamHTLinkWidth;
2153   USHORT                     usMinDownStreamHTLinkWidth;
2154   USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2155   USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2156   ULONG                      ulReserved3[96];          //must be 0x0
2157 }ATOM_INTEGRATED_SYSTEM_INFO_V2;   
2158
2159 /*
2160 ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
2161 ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2162 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2163
2164 ulSystemConfig:  
2165 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 
2166 Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2167       =0: system boots up at driver control state. Power state depends on PowerPlay table.
2168 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2169 Bit[3]=1: Only one power state(Performance) will be supported.
2170       =0: Multiple power states supported from PowerPlay table.
2171 Bit[4]=1: CLMC is supported and enabled on current system. 
2172       =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.  
2173 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.  
2174       =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2175 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2176       =0: Voltage settings is determined by powerplay table.
2177 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2178       =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2179 Bit[8]=1: CDLF is supported and enabled on current system.
2180       =0: CDLF is not supported or enabled on current system.
2181 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2182       =0: DLL Shut Down feature is not enabled or supported on current system.
2183
2184 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2185
2186 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2187                                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2188
2189 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2190       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2191                         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2192       When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2193       in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2194       one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2195
2196                         [15:8] - Lane configuration attribute; 
2197       [23:16]- Connector type, possible value:
2198                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2199                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2200                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2201                CONNECTOR_OBJECT_ID_DISPLAYPORT
2202                CONNECTOR_OBJECT_ID_eDP
2203                         [31:24]- Reserved
2204
2205 ulDDISlot2Config: Same as Slot1.
2206 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2207 For IGP, Hypermemory is the only memory type showed in CCC.
2208
2209 ucUMAChannelNumber:  how many channels for the UMA;
2210
2211 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 
2212 ucDockingPinBit:     which bit in this register to read the pin status;
2213 ucDockingPinPolarity:Polarity of the pin when docked;
2214
2215 ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
2216
2217 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2218
2219 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 
2220 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2221                     GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2222                     PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2223                     GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2224
2225 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2226
2227 ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
2228 usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 
2229                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
2230 usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 
2231                     If CDLW enabled, both upstream and downstream width should be the same during bootup.  
2232
2233 usUMASyncStartDelay: Memory access latency, required for watermark calculation 
2234 usUMADataReturnTime: Memory access latency, required for watermark calculation
2235 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 
2236 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2237                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2238                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2239                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2240                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2241
2242 ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2243                              This must be less than or equal to ulHTLinkFreq(bootup frequency). 
2244 ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2245                              This must be less than or equal to ulHighVoltageHTLinkFreq.
2246
2247 usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2248 usMaxDownStreamHTLinkWidth:  same as above.
2249 usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2250 usMinDownStreamHTLinkWidth:  same as above.
2251 */
2252
2253
2254 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
2255 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
2256 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004 
2257 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
2258 #define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
2259 #define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
2260 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
2261 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
2262 #define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
2263 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
2264
2265 #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
2266
2267 #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
2268 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
2269 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
2270 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
2271 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
2272 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
2273
2274 #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
2275 #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
2276 #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
2277
2278 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
2279
2280 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2281 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
2282 {
2283   ATOM_COMMON_TABLE_HEADER   sHeader;
2284   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
2285   ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 
2286   ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2287   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
2288   ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
2289   ULONG                      ulBootUpReqDisplayVector;
2290   ULONG                      ulOtherDisplayMisc;
2291   ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
2292   ULONG                      ulSystemConfig;            //TBD
2293   ULONG                      ulCPUCapInfo;              //TBD
2294   USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2295   USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2296   USHORT                     usBootUpNBVoltage;         //boot up NB voltage
2297   UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2298   UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2299   ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
2300   ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
2301   ULONG                      ulDDISlot2Config;
2302   ULONG                      ulDDISlot3Config;
2303   ULONG                      ulDDISlot4Config;
2304   ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
2305   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2306   UCHAR                      ucUMAChannelNumber;
2307   USHORT                     usReserved;
2308   ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
2309   ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2310   ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2311   ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2312   ULONG                      ulReserved6[61];           //must be 0x0
2313 }ATOM_INTEGRATED_SYSTEM_INFO_V5;   
2314
2315 #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
2316 #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
2317 #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
2318 #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
2319 #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
2320 #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
2321 #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
2322 #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
2323 #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
2324 #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
2325 #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
2326 #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
2327 #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
2328 #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
2329
2330 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
2331 #define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00 
2332 #define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
2333 #define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
2334 #define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
2335 #define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
2336 #define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
2337 #define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
2338 #define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
2339 #define ASIC_EXT_DIG2_ENCODER_ID                                                                                                        0x08
2340 #define ASIC_INT_DIG3_ENCODER_ID                                                                                                        0x0a
2341 #define ASIC_INT_DIG4_ENCODER_ID                                                                                                        0x0b
2342 #define ASIC_INT_DIG5_ENCODER_ID                                                                                                        0x0c
2343 #define ASIC_INT_DIG6_ENCODER_ID                                                                                                        0x0d
2344
2345 //define Encoder attribute
2346 #define ATOM_ANALOG_ENCODER                                                                                                                             0
2347 #define ATOM_DIGITAL_ENCODER                                                                                                                    1               
2348 #define ATOM_DP_ENCODER                                                                                                                       2         
2349
2350 #define ATOM_ENCODER_ENUM_MASK                            0x70
2351 #define ATOM_ENCODER_ENUM_ID1                             0x00
2352 #define ATOM_ENCODER_ENUM_ID2                             0x10
2353 #define ATOM_ENCODER_ENUM_ID3                             0x20
2354 #define ATOM_ENCODER_ENUM_ID4                             0x30
2355 #define ATOM_ENCODER_ENUM_ID5                             0x40 
2356 #define ATOM_ENCODER_ENUM_ID6                             0x50
2357
2358 #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
2359 #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
2360 #define ATOM_DEVICE_TV1_INDEX                             0x00000002
2361 #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
2362 #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
2363 #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
2364 #define ATOM_DEVICE_DFP6_INDEX                            0x00000006
2365 #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
2366 #define ATOM_DEVICE_CV_INDEX                              0x00000008
2367 #define ATOM_DEVICE_DFP3_INDEX                            0x00000009
2368 #define ATOM_DEVICE_DFP4_INDEX                            0x0000000A
2369 #define ATOM_DEVICE_DFP5_INDEX                            0x0000000B
2370
2371 #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
2372 #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
2373 #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
2374 #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
2375 #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
2376 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
2377 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
2378
2379 #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
2380
2381 #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
2382 #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
2383 #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
2384 #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
2385 #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
2386 #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
2387 #define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
2388 #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
2389 #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
2390 #define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
2391 #define ATOM_DEVICE_DFP4_SUPPORT                          (0x1L << ATOM_DEVICE_DFP4_INDEX )
2392 #define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
2393
2394 #define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
2395 #define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
2396 #define ATOM_DEVICE_TV_SUPPORT                            (ATOM_DEVICE_TV1_SUPPORT)
2397 #define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
2398
2399 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
2400 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
2401 #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
2402 #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
2403 #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
2404 #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
2405 #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
2406 #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
2407 #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
2408 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
2409 #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
2410 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
2411 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
2412 #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
2413 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
2414
2415
2416 #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
2417 #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
2418 #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
2419 #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
2420 #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
2421 #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
2422
2423 #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
2424
2425 #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
2426 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
2427
2428 #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
2429 #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
2430 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
2431 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
2432 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
2433 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
2434
2435 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
2436 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
2437 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
2438 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
2439
2440 //  usDeviceSupport:
2441 //  Bits0       = 0 - no CRT1 support= 1- CRT1 is supported
2442 //  Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported
2443 //  Bit 2       = 0 - no TV1  support= 1- TV1  is supported
2444 //  Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported
2445 //  Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported
2446 //  Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported
2447 //  Bit 6       = 0 - no DFP6 support= 1- DFP6 is supported
2448 //  Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported
2449 //  Bit 8       = 0 - no CV   support= 1- CV   is supported
2450 //  Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported
2451 //  Bit 10      = 0 - no DFP4 support= 1- DFP4 is supported
2452 //  Bit 11      = 0 - no DFP5 support= 1- DFP5 is supported
2453 //   
2454 //  
2455
2456 /****************************************************************************/
2457 /* Structure used in MclkSS_InfoTable                                       */
2458 /****************************************************************************/
2459 //              ucI2C_ConfigID
2460 //    [7:0] - I2C LINE Associate ID
2461 //          = 0   - no I2C
2462 //    [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection)
2463 //                          =   0,  [6:0]=SW assisted I2C ID
2464 //    [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use
2465 //                          =   2,      HW engine for Multimedia use
2466 //                          =   3-7     Reserved for future I2C engines
2467 //              [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
2468
2469 typedef struct _ATOM_I2C_ID_CONFIG
2470 {
2471 #if ATOM_BIG_ENDIAN
2472   UCHAR   bfHW_Capable:1;
2473   UCHAR   bfHW_EngineID:3;
2474   UCHAR   bfI2C_LineMux:4;
2475 #else
2476   UCHAR   bfI2C_LineMux:4;
2477   UCHAR   bfHW_EngineID:3;
2478   UCHAR   bfHW_Capable:1;
2479 #endif
2480 }ATOM_I2C_ID_CONFIG;
2481
2482 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
2483 {
2484   ATOM_I2C_ID_CONFIG sbfAccess;
2485   UCHAR              ucAccess;
2486 }ATOM_I2C_ID_CONFIG_ACCESS;
2487    
2488
2489 /****************************************************************************/  
2490 // Structure used in GPIO_I2C_InfoTable
2491 /****************************************************************************/  
2492 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
2493 {
2494   USHORT                    usClkMaskRegisterIndex;
2495   USHORT                    usClkEnRegisterIndex;
2496   USHORT                    usClkY_RegisterIndex;
2497   USHORT                    usClkA_RegisterIndex;
2498   USHORT                    usDataMaskRegisterIndex;
2499   USHORT                    usDataEnRegisterIndex;
2500   USHORT                    usDataY_RegisterIndex;
2501   USHORT                    usDataA_RegisterIndex;
2502   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
2503   UCHAR                     ucClkMaskShift;
2504   UCHAR                     ucClkEnShift;
2505   UCHAR                     ucClkY_Shift;
2506   UCHAR                     ucClkA_Shift;
2507   UCHAR                     ucDataMaskShift;
2508   UCHAR                     ucDataEnShift;
2509   UCHAR                     ucDataY_Shift;
2510   UCHAR                     ucDataA_Shift;
2511   UCHAR                     ucReserved1;
2512   UCHAR                     ucReserved2;
2513 }ATOM_GPIO_I2C_ASSIGMENT;
2514
2515 typedef struct _ATOM_GPIO_I2C_INFO
2516
2517   ATOM_COMMON_TABLE_HEADER      sHeader;
2518   ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
2519 }ATOM_GPIO_I2C_INFO;
2520
2521 /****************************************************************************/  
2522 // Common Structure used in other structures
2523 /****************************************************************************/  
2524
2525 #ifndef _H2INC
2526   
2527 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2528 typedef struct _ATOM_MODE_MISC_INFO
2529
2530 #if ATOM_BIG_ENDIAN
2531   USHORT Reserved:6;
2532   USHORT RGB888:1;
2533   USHORT DoubleClock:1;
2534   USHORT Interlace:1;
2535   USHORT CompositeSync:1;
2536   USHORT V_ReplicationBy2:1;
2537   USHORT H_ReplicationBy2:1;
2538   USHORT VerticalCutOff:1;
2539   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
2540   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
2541   USHORT HorizontalCutOff:1;
2542 #else
2543   USHORT HorizontalCutOff:1;
2544   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
2545   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
2546   USHORT VerticalCutOff:1;
2547   USHORT H_ReplicationBy2:1;
2548   USHORT V_ReplicationBy2:1;
2549   USHORT CompositeSync:1;
2550   USHORT Interlace:1;
2551   USHORT DoubleClock:1;
2552   USHORT RGB888:1;
2553   USHORT Reserved:6;           
2554 #endif
2555 }ATOM_MODE_MISC_INFO;
2556   
2557 typedef union _ATOM_MODE_MISC_INFO_ACCESS
2558
2559   ATOM_MODE_MISC_INFO sbfAccess;
2560   USHORT              usAccess;
2561 }ATOM_MODE_MISC_INFO_ACCESS;
2562   
2563 #else
2564   
2565 typedef union _ATOM_MODE_MISC_INFO_ACCESS
2566
2567   USHORT              usAccess;
2568 }ATOM_MODE_MISC_INFO_ACCESS;
2569    
2570 #endif
2571
2572 // usModeMiscInfo-
2573 #define ATOM_H_CUTOFF           0x01
2574 #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
2575 #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
2576 #define ATOM_V_CUTOFF           0x08
2577 #define ATOM_H_REPLICATIONBY2   0x10
2578 #define ATOM_V_REPLICATIONBY2   0x20
2579 #define ATOM_COMPOSITESYNC      0x40
2580 #define ATOM_INTERLACE          0x80
2581 #define ATOM_DOUBLE_CLOCK_MODE  0x100
2582 #define ATOM_RGB888_MODE        0x200
2583
2584 //usRefreshRate-
2585 #define ATOM_REFRESH_43         43
2586 #define ATOM_REFRESH_47         47
2587 #define ATOM_REFRESH_56         56      
2588 #define ATOM_REFRESH_60         60
2589 #define ATOM_REFRESH_65         65
2590 #define ATOM_REFRESH_70         70
2591 #define ATOM_REFRESH_72         72
2592 #define ATOM_REFRESH_75         75
2593 #define ATOM_REFRESH_85         85
2594
2595 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
2596 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
2597 //
2598 //      VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
2599 //                                              =       EDID_HA + EDID_HBL
2600 //      VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA
2601 //      VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
2602 //                                              =       EDID_HA + EDID_HSO
2603 //      VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW
2604 //      VESA_BORDER                     =       EDID_BORDER
2605
2606 /****************************************************************************/  
2607 // Structure used in SetCRTC_UsingDTDTimingTable
2608 /****************************************************************************/  
2609 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
2610 {
2611   USHORT  usH_Size;
2612   USHORT  usH_Blanking_Time;
2613   USHORT  usV_Size;
2614   USHORT  usV_Blanking_Time;                    
2615   USHORT  usH_SyncOffset;
2616   USHORT  usH_SyncWidth;
2617   USHORT  usV_SyncOffset;
2618   USHORT  usV_SyncWidth;
2619   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;  
2620   UCHAR   ucH_Border;         // From DFP EDID
2621   UCHAR   ucV_Border;
2622   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2  
2623   UCHAR   ucPadding[3];
2624 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
2625
2626 /****************************************************************************/  
2627 // Structure used in SetCRTC_TimingTable
2628 /****************************************************************************/  
2629 typedef struct _SET_CRTC_TIMING_PARAMETERS
2630 {
2631   USHORT                      usH_Total;        // horizontal total
2632   USHORT                      usH_Disp;         // horizontal display
2633   USHORT                      usH_SyncStart;    // horozontal Sync start
2634   USHORT                      usH_SyncWidth;    // horizontal Sync width
2635   USHORT                      usV_Total;        // vertical total
2636   USHORT                      usV_Disp;         // vertical display
2637   USHORT                      usV_SyncStart;    // vertical Sync start
2638   USHORT                      usV_SyncWidth;    // vertical Sync width
2639   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
2640   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
2641   UCHAR                       ucOverscanRight;  // right
2642   UCHAR                       ucOverscanLeft;   // left
2643   UCHAR                       ucOverscanBottom; // bottom
2644   UCHAR                       ucOverscanTop;    // top
2645   UCHAR                       ucReserved;
2646 }SET_CRTC_TIMING_PARAMETERS;
2647 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
2648
2649 /****************************************************************************/  
2650 // Structure used in StandardVESA_TimingTable
2651 //                   AnalogTV_InfoTable 
2652 //                   ComponentVideoInfoTable
2653 /****************************************************************************/  
2654 typedef struct _ATOM_MODE_TIMING
2655 {
2656   USHORT  usCRTC_H_Total;
2657   USHORT  usCRTC_H_Disp;
2658   USHORT  usCRTC_H_SyncStart;
2659   USHORT  usCRTC_H_SyncWidth;
2660   USHORT  usCRTC_V_Total;
2661   USHORT  usCRTC_V_Disp;
2662   USHORT  usCRTC_V_SyncStart;
2663   USHORT  usCRTC_V_SyncWidth;
2664   USHORT  usPixelClock;                                                  //in 10Khz unit
2665   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
2666   USHORT  usCRTC_OverscanRight;
2667   USHORT  usCRTC_OverscanLeft;
2668   USHORT  usCRTC_OverscanBottom;
2669   USHORT  usCRTC_OverscanTop;
2670   USHORT  usReserve;
2671   UCHAR   ucInternalModeNumber;
2672   UCHAR   ucRefreshRate;
2673 }ATOM_MODE_TIMING;
2674
2675 typedef struct _ATOM_DTD_FORMAT
2676 {
2677   USHORT  usPixClk;
2678   USHORT  usHActive;
2679   USHORT  usHBlanking_Time;
2680   USHORT  usVActive;
2681   USHORT  usVBlanking_Time;                     
2682   USHORT  usHSyncOffset;
2683   USHORT  usHSyncWidth;
2684   USHORT  usVSyncOffset;
2685   USHORT  usVSyncWidth;
2686   USHORT  usImageHSize;
2687   USHORT  usImageVSize;
2688   UCHAR   ucHBorder;
2689   UCHAR   ucVBorder;
2690   ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
2691   UCHAR   ucInternalModeNumber;
2692   UCHAR   ucRefreshRate;
2693 }ATOM_DTD_FORMAT;
2694
2695 /****************************************************************************/  
2696 // Structure used in LVDS_InfoTable 
2697 //  * Need a document to describe this table
2698 /****************************************************************************/  
2699 #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
2700 #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
2701 #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
2702 #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
2703
2704 //ucTableFormatRevision=1
2705 //ucTableContentRevision=1
2706 typedef struct _ATOM_LVDS_INFO
2707 {
2708   ATOM_COMMON_TABLE_HEADER sHeader;  
2709   ATOM_DTD_FORMAT     sLCDTiming;
2710   USHORT              usModePatchTableOffset;
2711   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
2712   USHORT              usOffDelayInMs;
2713   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
2714   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
2715   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
2716                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
2717                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
2718                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
2719   UCHAR               ucPanelDefaultRefreshRate;
2720   UCHAR               ucPanelIdentification;
2721   UCHAR               ucSS_Id;
2722 }ATOM_LVDS_INFO;
2723
2724 //ucTableFormatRevision=1
2725 //ucTableContentRevision=2
2726 typedef struct _ATOM_LVDS_INFO_V12
2727 {
2728   ATOM_COMMON_TABLE_HEADER sHeader;  
2729   ATOM_DTD_FORMAT     sLCDTiming;
2730   USHORT              usExtInfoTableOffset;
2731   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
2732   USHORT              usOffDelayInMs;
2733   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
2734   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
2735   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
2736                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
2737                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
2738                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
2739   UCHAR               ucPanelDefaultRefreshRate;
2740   UCHAR               ucPanelIdentification;
2741   UCHAR               ucSS_Id;
2742   USHORT              usLCDVenderID;
2743   USHORT              usLCDProductID;
2744   UCHAR               ucLCDPanel_SpecialHandlingCap; 
2745         UCHAR                                                           ucPanelInfoSize;                                        //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
2746   UCHAR               ucReserved[2];
2747 }ATOM_LVDS_INFO_V12;
2748
2749 //Definitions for ucLCDPanel_SpecialHandlingCap:
2750
2751 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 
2752 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 
2753 #define LCDPANEL_CAP_READ_EDID                  0x1
2754
2755 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
2756 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
2757 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
2758 #define LCDPANEL_CAP_DRR_SUPPORTED              0x2
2759
2760 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
2761 #define LCDPANEL_CAP_eDP                        0x4
2762
2763
2764 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
2765 //Bit 6  5  4
2766                               //      0  0  0  -  Color bit depth is undefined
2767                               //      0  0  1  -  6 Bits per Primary Color
2768                               //      0  1  0  -  8 Bits per Primary Color
2769                               //      0  1  1  - 10 Bits per Primary Color
2770                               //      1  0  0  - 12 Bits per Primary Color
2771                               //      1  0  1  - 14 Bits per Primary Color
2772                               //      1  1  0  - 16 Bits per Primary Color
2773                               //      1  1  1  - Reserved
2774
2775 #define PANEL_COLOR_BIT_DEPTH_MASK    0x70
2776
2777 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}   
2778 #define PANEL_RANDOM_DITHER   0x80
2779 #define PANEL_RANDOM_DITHER_MASK   0x80
2780
2781
2782 #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12
2783
2784 typedef struct  _ATOM_PATCH_RECORD_MODE
2785 {
2786   UCHAR     ucRecordType;
2787   USHORT    usHDisp;
2788   USHORT    usVDisp;
2789 }ATOM_PATCH_RECORD_MODE;
2790
2791 typedef struct  _ATOM_LCD_RTS_RECORD
2792 {
2793   UCHAR     ucRecordType;
2794   UCHAR     ucRTSValue;
2795 }ATOM_LCD_RTS_RECORD;
2796
2797 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 
2798 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
2799 typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
2800 {
2801   UCHAR     ucRecordType;
2802   USHORT    usLCDCap;
2803 }ATOM_LCD_MODE_CONTROL_CAP;