Merge remote branch 'nouveau/for-airlied' into drm-next-stage
[linux-2.6.git] / drivers / gpu / drm / nouveau / nv50_display.c
1 /*
2  * Copyright (C) 2008 Maarten Maathuis.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26
27 #include "nv50_display.h"
28 #include "nouveau_crtc.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_connector.h"
31 #include "nouveau_fb.h"
32 #include "drm_crtc_helper.h"
33
34 static void
35 nv50_evo_channel_del(struct nouveau_channel **pchan)
36 {
37         struct nouveau_channel *chan = *pchan;
38
39         if (!chan)
40                 return;
41         *pchan = NULL;
42
43         nouveau_gpuobj_channel_takedown(chan);
44         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
45
46         if (chan->user)
47                 iounmap(chan->user);
48
49         kfree(chan);
50 }
51
52 static int
53 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
54                     uint32_t tile_flags, uint32_t magic_flags,
55                     uint32_t offset, uint32_t limit)
56 {
57         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
58         struct drm_device *dev = evo->dev;
59         struct nouveau_gpuobj *obj = NULL;
60         int ret;
61
62         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
63         if (ret)
64                 return ret;
65         obj->engine = NVOBJ_ENGINE_DISPLAY;
66
67         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
68         if (ret) {
69                 nouveau_gpuobj_del(dev, &obj);
70                 return ret;
71         }
72
73         dev_priv->engine.instmem.prepare_access(dev, true);
74         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
75         nv_wo32(dev, obj, 1, limit);
76         nv_wo32(dev, obj, 2, offset);
77         nv_wo32(dev, obj, 3, 0x00000000);
78         nv_wo32(dev, obj, 4, 0x00000000);
79         nv_wo32(dev, obj, 5, 0x00010000);
80         dev_priv->engine.instmem.finish_access(dev);
81
82         return 0;
83 }
84
85 static int
86 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
87 {
88         struct drm_nouveau_private *dev_priv = dev->dev_private;
89         struct nouveau_channel *chan;
90         int ret;
91
92         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
93         if (!chan)
94                 return -ENOMEM;
95         *pchan = chan;
96
97         chan->id = -1;
98         chan->dev = dev;
99         chan->user_get = 4;
100         chan->user_put = 0;
101
102         INIT_LIST_HEAD(&chan->ramht_refs);
103
104         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
105                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
106         if (ret) {
107                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
108                 nv50_evo_channel_del(pchan);
109                 return ret;
110         }
111
112         ret = nouveau_mem_init_heap(&chan->ramin_heap, chan->ramin->gpuobj->
113                                     im_pramin->start, 32768);
114         if (ret) {
115                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
116                 nv50_evo_channel_del(pchan);
117                 return ret;
118         }
119
120         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
121                                      0, &chan->ramht);
122         if (ret) {
123                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
124                 nv50_evo_channel_del(pchan);
125                 return ret;
126         }
127
128         if (dev_priv->chipset != 0x50) {
129                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
130                                           0, 0xffffffff);
131                 if (ret) {
132                         nv50_evo_channel_del(pchan);
133                         return ret;
134                 }
135
136
137                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
138                                           0, 0xffffffff);
139                 if (ret) {
140                         nv50_evo_channel_del(pchan);
141                         return ret;
142                 }
143         }
144
145         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
146                                   0, nouveau_mem_fb_amount(dev));
147         if (ret) {
148                 nv50_evo_channel_del(pchan);
149                 return ret;
150         }
151
152         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
153                              false, true, &chan->pushbuf_bo);
154         if (ret == 0)
155                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
156         if (ret) {
157                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
158                 nv50_evo_channel_del(pchan);
159                 return ret;
160         }
161
162         ret = nouveau_bo_map(chan->pushbuf_bo);
163         if (ret) {
164                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
165                 nv50_evo_channel_del(pchan);
166                 return ret;
167         }
168
169         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
170                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
171         if (!chan->user) {
172                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
173                 nv50_evo_channel_del(pchan);
174                 return -ENOMEM;
175         }
176
177         return 0;
178 }
179
180 int
181 nv50_display_init(struct drm_device *dev)
182 {
183         struct drm_nouveau_private *dev_priv = dev->dev_private;
184         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
185         struct nouveau_channel *evo = dev_priv->evo;
186         struct drm_connector *connector;
187         uint32_t val, ram_amount, hpd_en[2];
188         uint64_t start;
189         int ret, i;
190
191         NV_DEBUG_KMS(dev, "\n");
192
193         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
194         /*
195          * I think the 0x006101XX range is some kind of main control area
196          * that enables things.
197          */
198         /* CRTC? */
199         for (i = 0; i < 2; i++) {
200                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
201                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
202                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
203                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
204                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
205                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
206                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
207                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
208         }
209         /* DAC */
210         for (i = 0; i < 3; i++) {
211                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
212                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
213         }
214         /* SOR */
215         for (i = 0; i < 4; i++) {
216                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
217                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
218         }
219         /* Something not yet in use, tv-out maybe. */
220         for (i = 0; i < 3; i++) {
221                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
222                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
223         }
224
225         for (i = 0; i < 3; i++) {
226                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
227                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
228                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
229         }
230
231         /* This used to be in crtc unblank, but seems out of place there. */
232         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233         /* RAM is clamped to 256 MiB. */
234         ram_amount = nouveau_mem_fb_amount(dev);
235         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236         if (ram_amount > 256*1024*1024)
237                 ram_amount = 256*1024*1024;
238         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
239         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
240         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
241
242         /* The precise purpose is unknown, i suspect it has something to do
243          * with text mode.
244          */
245         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
246                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
247                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
248                 if (!nv_wait(0x006194e8, 2, 0)) {
249                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
250                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
251                                                 nv_rd32(dev, 0x6194e8));
252                         return -EBUSY;
253                 }
254         }
255
256         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
257          * stuck in some unspecified state
258          */
259         start = ptimer->read(dev);
260         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
261         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
262                 if ((val & 0x9f0000) == 0x20000)
263                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
264                                                         val | 0x800000);
265
266                 if ((val & 0x3f0000) == 0x30000)
267                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
268                                                         val | 0x200000);
269
270                 if (ptimer->read(dev) - start > 1000000000ULL) {
271                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
272                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
273                         return -EBUSY;
274                 }
275         }
276
277         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
278         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
279         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
280                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
281                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
282                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
283                 return -EBUSY;
284         }
285
286         for (i = 0; i < 2; i++) {
287                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
288                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
289                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
290                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
291                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
292                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
293                         return -EBUSY;
294                 }
295
296                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
297                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
298                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
299                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
300                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
301                         NV_ERROR(dev, "timeout: "
302                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
303                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
304                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
305                         return -EBUSY;
306                 }
307         }
308
309         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
310
311         /* initialise fifo */
312         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
313                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
314                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
315                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
316         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
317         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
318         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
319                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
320                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
321                 return -EBUSY;
322         }
323         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
324                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
325                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
326         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
327         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
328                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
329         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
330
331         evo->dma.max = (4096/4) - 2;
332         evo->dma.put = 0;
333         evo->dma.cur = evo->dma.put;
334         evo->dma.free = evo->dma.max - evo->dma.cur;
335
336         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
337         if (ret)
338                 return ret;
339
340         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
341                 OUT_RING(evo, 0);
342
343         ret = RING_SPACE(evo, 11);
344         if (ret)
345                 return ret;
346         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
347         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
348         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
349         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
350         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
351         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
352         OUT_RING(evo, 0);
353         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
354         OUT_RING(evo, 0);
355         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
356         OUT_RING(evo, 0);
357         FIRE_RING(evo);
358         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
359                 NV_ERROR(dev, "evo pushbuf stalled\n");
360
361         /* enable clock change interrupts. */
362         nv_wr32(dev, 0x610028, 0x00010001);
363         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
364                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
365                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
366
367         /* enable hotplug interrupts */
368         hpd_en[0] = hpd_en[1] = 0;
369         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370                 struct nouveau_connector *conn = nouveau_connector(connector);
371                 struct dcb_gpio_entry *gpio;
372
373                 if (conn->dcb->gpio_tag == 0xff)
374                         continue;
375
376                 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
377                 if (!gpio)
378                         continue;
379
380                 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
381         }
382
383         nv_wr32(dev, 0xe054, 0xffffffff);
384         nv_wr32(dev, 0xe050, hpd_en[0]);
385         if (dev_priv->chipset >= 0x90) {
386                 nv_wr32(dev, 0xe074, 0xffffffff);
387                 nv_wr32(dev, 0xe070, hpd_en[1]);
388         }
389
390         return 0;
391 }
392
393 static int nv50_display_disable(struct drm_device *dev)
394 {
395         struct drm_nouveau_private *dev_priv = dev->dev_private;
396         struct drm_crtc *drm_crtc;
397         int ret, i;
398
399         NV_DEBUG_KMS(dev, "\n");
400
401         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
402                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
403
404                 nv50_crtc_blank(crtc, true);
405         }
406
407         ret = RING_SPACE(dev_priv->evo, 2);
408         if (ret == 0) {
409                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
410                 OUT_RING(dev_priv->evo, 0);
411         }
412         FIRE_RING(dev_priv->evo);
413
414         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
415          * cleaning up?
416          */
417         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
418                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
419                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
420
421                 if (!crtc->base.enabled)
422                         continue;
423
424                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
425                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
426                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
427                                       "0x%08x\n", mask, mask);
428                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
429                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
430                 }
431         }
432
433         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
434         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
435         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
436                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
437                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
438                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
439         }
440
441         for (i = 0; i < 3; i++) {
442                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
443                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
444                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
445                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
446                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
447                 }
448         }
449
450         /* disable interrupts. */
451         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
452
453         /* disable hotplug interrupts */
454         nv_wr32(dev, 0xe054, 0xffffffff);
455         nv_wr32(dev, 0xe050, 0x00000000);
456         if (dev_priv->chipset >= 0x90) {
457                 nv_wr32(dev, 0xe074, 0xffffffff);
458                 nv_wr32(dev, 0xe070, 0x00000000);
459         }
460         return 0;
461 }
462
463 int nv50_display_create(struct drm_device *dev)
464 {
465         struct drm_nouveau_private *dev_priv = dev->dev_private;
466         struct dcb_table *dcb = &dev_priv->vbios.dcb;
467         int ret, i;
468
469         NV_DEBUG_KMS(dev, "\n");
470
471         /* init basic kernel modesetting */
472         drm_mode_config_init(dev);
473
474         /* Initialise some optional connector properties. */
475         drm_mode_create_scaling_mode_property(dev);
476         drm_mode_create_dithering_property(dev);
477
478         dev->mode_config.min_width = 0;
479         dev->mode_config.min_height = 0;
480
481         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
482
483         dev->mode_config.max_width = 8192;
484         dev->mode_config.max_height = 8192;
485
486         dev->mode_config.fb_base = dev_priv->fb_phys;
487
488         /* Create EVO channel */
489         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
490         if (ret) {
491                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
492                 return ret;
493         }
494
495         /* Create CRTC objects */
496         for (i = 0; i < 2; i++)
497                 nv50_crtc_create(dev, i);
498
499         /* We setup the encoders from the BIOS table */
500         for (i = 0 ; i < dcb->entries; i++) {
501                 struct dcb_entry *entry = &dcb->entry[i];
502
503                 if (entry->location != DCB_LOC_ON_CHIP) {
504                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
505                                 entry->type, ffs(entry->or) - 1);
506                         continue;
507                 }
508
509                 switch (entry->type) {
510                 case OUTPUT_TMDS:
511                 case OUTPUT_LVDS:
512                 case OUTPUT_DP:
513                         nv50_sor_create(dev, entry);
514                         break;
515                 case OUTPUT_ANALOG:
516                         nv50_dac_create(dev, entry);
517                         break;
518                 default:
519                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
520                         continue;
521                 }
522         }
523
524         for (i = 0 ; i < dcb->connector.entries; i++) {
525                 if (i != 0 && dcb->connector.entry[i].index ==
526                               dcb->connector.entry[i - 1].index)
527                         continue;
528                 nouveau_connector_create(dev, &dcb->connector.entry[i]);
529         }
530
531         ret = nv50_display_init(dev);
532         if (ret)
533                 return ret;
534
535         return 0;
536 }
537
538 int nv50_display_destroy(struct drm_device *dev)
539 {
540         struct drm_nouveau_private *dev_priv = dev->dev_private;
541
542         NV_DEBUG_KMS(dev, "\n");
543
544         drm_mode_config_cleanup(dev);
545
546         nv50_display_disable(dev);
547         nv50_evo_channel_del(&dev_priv->evo);
548
549         return 0;
550 }
551
552 static inline uint32_t
553 nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
554 {
555         struct drm_nouveau_private *dev_priv = dev->dev_private;
556         uint32_t mc;
557
558         if (sor) {
559                 if (dev_priv->chipset < 0x90 ||
560                     dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
561                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
562                 else
563                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
564         } else {
565                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
566         }
567
568         return mc;
569 }
570
571 static int
572 nv50_display_irq_head(struct drm_device *dev, int *phead,
573                       struct dcb_entry **pdcbent)
574 {
575         struct drm_nouveau_private *dev_priv = dev->dev_private;
576         uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
577         uint32_t dac = 0, sor = 0;
578         int head, i, or = 0, type = OUTPUT_ANY;
579
580         /* We're assuming that head 0 *or* head 1 will be active here,
581          * and not both.  I'm not sure if the hw will even signal both
582          * ever, but it definitely shouldn't for us as we commit each
583          * CRTC separately, and submission will be blocked by the GPU
584          * until we handle each in turn.
585          */
586         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
587         head = ffs((unk30 >> 9) & 3) - 1;
588         if (head < 0)
589                 return -EINVAL;
590
591         /* This assumes CRTCs are never bound to multiple encoders, which
592          * should be the case.
593          */
594         for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
595                 uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
596                 if (!(mc & (1 << head)))
597                         continue;
598
599                 switch ((mc >> 8) & 0xf) {
600                 case 0: type = OUTPUT_ANALOG; break;
601                 case 1: type = OUTPUT_TV; break;
602                 default:
603                         NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
604                         return -1;
605                 }
606
607                 or = i;
608         }
609
610         for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
611                 uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
612                 if (!(mc & (1 << head)))
613                         continue;
614
615                 switch ((mc >> 8) & 0xf) {
616                 case 0: type = OUTPUT_LVDS; break;
617                 case 1: type = OUTPUT_TMDS; break;
618                 case 2: type = OUTPUT_TMDS; break;
619                 case 5: type = OUTPUT_TMDS; break;
620                 case 8: type = OUTPUT_DP; break;
621                 case 9: type = OUTPUT_DP; break;
622                 default:
623                         NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
624                         return -1;
625                 }
626
627                 or = i;
628         }
629
630         NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
631         if (type == OUTPUT_ANY) {
632                 NV_ERROR(dev, "unknown encoder!!\n");
633                 return -1;
634         }
635
636         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
637                 struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i];
638
639                 if (dcbent->type != type)
640                         continue;
641
642                 if (!(dcbent->or & (1 << or)))
643                         continue;
644
645                 *phead = head;
646                 *pdcbent = dcbent;
647                 return 0;
648         }
649
650         NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
651         return 0;
652 }
653
654 static uint32_t
655 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
656                            int pxclk)
657 {
658         struct drm_nouveau_private *dev_priv = dev->dev_private;
659         struct nouveau_connector *nv_connector = NULL;
660         struct drm_encoder *encoder;
661         struct nvbios *bios = &dev_priv->vbios;
662         uint32_t mc, script = 0, or;
663
664         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
665                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
666
667                 if (nv_encoder->dcb != dcbent)
668                         continue;
669
670                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
671                 break;
672         }
673
674         or = ffs(dcbent->or) - 1;
675         mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
676         switch (dcbent->type) {
677         case OUTPUT_LVDS:
678                 script = (mc >> 8) & 0xf;
679                 if (bios->fp_no_ddc) {
680                         if (bios->fp.dual_link)
681                                 script |= 0x0100;
682                         if (bios->fp.if_is_24bit)
683                                 script |= 0x0200;
684                 } else {
685                         if (pxclk >= bios->fp.duallink_transition_clk) {
686                                 script |= 0x0100;
687                                 if (bios->fp.strapless_is_24bit & 2)
688                                         script |= 0x0200;
689                         } else
690                         if (bios->fp.strapless_is_24bit & 1)
691                                 script |= 0x0200;
692
693                         if (nv_connector && nv_connector->edid &&
694                             (nv_connector->edid->revision >= 4) &&
695                             (nv_connector->edid->input & 0x70) >= 0x20)
696                                 script |= 0x0200;
697                 }
698
699                 if (nouveau_uscript_lvds >= 0) {
700                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
701                                      "for output LVDS-%d\n", script,
702                                      nouveau_uscript_lvds, or);
703                         script = nouveau_uscript_lvds;
704                 }
705                 break;
706         case OUTPUT_TMDS:
707                 script = (mc >> 8) & 0xf;
708                 if (pxclk >= 165000)
709                         script |= 0x0100;
710
711                 if (nouveau_uscript_tmds >= 0) {
712                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
713                                      "for output TMDS-%d\n", script,
714                                      nouveau_uscript_tmds, or);
715                         script = nouveau_uscript_tmds;
716                 }
717                 break;
718         case OUTPUT_DP:
719                 script = (mc >> 8) & 0xf;
720                 break;
721         case OUTPUT_ANALOG:
722                 script = 0xff;
723                 break;
724         default:
725                 NV_ERROR(dev, "modeset on unsupported output type!\n");
726                 break;
727         }
728
729         return script;
730 }
731
732 static void
733 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
734 {
735         struct drm_nouveau_private *dev_priv = dev->dev_private;
736         struct nouveau_channel *chan;
737         struct list_head *entry, *tmp;
738
739         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
740                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
741
742                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
743                                                 chan->nvsw.vblsem_rval);
744                 list_del(&chan->nvsw.vbl_wait);
745         }
746 }
747
748 static void
749 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
750 {
751         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
752
753         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
754                 nv50_display_vblank_crtc_handler(dev, 0);
755
756         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
757                 nv50_display_vblank_crtc_handler(dev, 1);
758
759         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
760                      NV50_PDISPLAY_INTR_EN) & ~intr);
761         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
762 }
763
764 static void
765 nv50_display_unk10_handler(struct drm_device *dev)
766 {
767         struct dcb_entry *dcbent;
768         int head, ret;
769
770         ret = nv50_display_irq_head(dev, &head, &dcbent);
771         if (ret)
772                 goto ack;
773
774         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
775
776         nouveau_bios_run_display_table(dev, dcbent, 0, -1);
777
778 ack:
779         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
780         nv_wr32(dev, 0x610030, 0x80000000);
781 }
782
783 static void
784 nv50_display_unk20_handler(struct drm_device *dev)
785 {
786         struct dcb_entry *dcbent;
787         uint32_t tmp, pclk, script;
788         int head, or, ret;
789
790         ret = nv50_display_irq_head(dev, &head, &dcbent);
791         if (ret)
792                 goto ack;
793         or = ffs(dcbent->or) - 1;
794         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
795         script = nv50_display_script_select(dev, dcbent, pclk);
796
797         NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
798
799         if (dcbent->type != OUTPUT_DP)
800                 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
801
802         nv50_crtc_set_clock(dev, head, pclk);
803
804         nouveau_bios_run_display_table(dev, dcbent, script, pclk);
805
806         tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
807         tmp &= ~0x000000f;
808         nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
809
810         if (dcbent->type != OUTPUT_ANALOG) {
811                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
812                 tmp &= ~0x00000f0f;
813                 if (script & 0x0100)
814                         tmp |= 0x00000101;
815                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
816         } else {
817                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
818         }
819
820 ack:
821         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
822         nv_wr32(dev, 0x610030, 0x80000000);
823 }
824
825 static void
826 nv50_display_unk40_handler(struct drm_device *dev)
827 {
828         struct dcb_entry *dcbent;
829         int head, pclk, script, ret;
830
831         ret = nv50_display_irq_head(dev, &head, &dcbent);
832         if (ret)
833                 goto ack;
834         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
835         script = nv50_display_script_select(dev, dcbent, pclk);
836
837         nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
838
839 ack:
840         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
841         nv_wr32(dev, 0x610030, 0x80000000);
842         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
843 }
844
845 void
846 nv50_display_irq_handler_bh(struct work_struct *work)
847 {
848         struct drm_nouveau_private *dev_priv =
849                 container_of(work, struct drm_nouveau_private, irq_work);
850         struct drm_device *dev = dev_priv->dev;
851
852         for (;;) {
853                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
854                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
855
856                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
857
858                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
859                         nv50_display_unk10_handler(dev);
860                 else
861                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
862                         nv50_display_unk20_handler(dev);
863                 else
864                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
865                         nv50_display_unk40_handler(dev);
866                 else
867                         break;
868         }
869
870         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
871 }
872
873 static void
874 nv50_display_error_handler(struct drm_device *dev)
875 {
876         uint32_t addr, data;
877
878         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
879         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
880         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
881
882         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
883                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
884
885         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
886 }
887
888 static void
889 nv50_display_irq_hotplug(struct drm_device *dev)
890 {
891         struct drm_nouveau_private *dev_priv = dev->dev_private;
892         struct drm_connector *connector;
893         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
894         uint32_t unplug_mask, plug_mask, change_mask;
895         uint32_t hpd0, hpd1 = 0;
896
897         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
898         if (dev_priv->chipset >= 0x90)
899                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
900
901         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
902         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
903         change_mask = plug_mask | unplug_mask;
904
905         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
906                 struct drm_encoder_helper_funcs *helper;
907                 struct nouveau_connector *nv_connector =
908                         nouveau_connector(connector);
909                 struct nouveau_encoder *nv_encoder;
910                 struct dcb_gpio_entry *gpio;
911                 uint32_t reg;
912                 bool plugged;
913
914                 if (!nv_connector->dcb)
915                         continue;
916
917                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
918                 if (!gpio || !(change_mask & (1 << gpio->line)))
919                         continue;
920
921                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
922                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
923                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
924                         drm_get_connector_name(connector)) ;
925
926                 if (!connector->encoder || !connector->encoder->crtc ||
927                     !connector->encoder->crtc->enabled)
928                         continue;
929                 nv_encoder = nouveau_encoder(connector->encoder);
930                 helper = connector->encoder->helper_private;
931
932                 if (nv_encoder->dcb->type != OUTPUT_DP)
933                         continue;
934
935                 if (plugged)
936                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
937                 else
938                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
939         }
940
941         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
942         if (dev_priv->chipset >= 0x90)
943                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
944 }
945
946 void
947 nv50_display_irq_handler(struct drm_device *dev)
948 {
949         struct drm_nouveau_private *dev_priv = dev->dev_private;
950         uint32_t delayed = 0;
951
952         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG)
953                 nv50_display_irq_hotplug(dev);
954
955         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
956                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
957                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
958                 uint32_t clock;
959
960                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
961
962                 if (!intr0 && !(intr1 & ~delayed))
963                         break;
964
965                 if (intr0 & 0x00010000) {
966                         nv50_display_error_handler(dev);
967                         intr0 &= ~0x00010000;
968                 }
969
970                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
971                         nv50_display_vblank_handler(dev, intr1);
972                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
973                 }
974
975                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
976                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
977                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
978                 if (clock) {
979                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
980                         if (!work_pending(&dev_priv->irq_work))
981                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
982                         delayed |= clock;
983                         intr1 &= ~clock;
984                 }
985
986                 if (intr0) {
987                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
988                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
989                 }
990
991                 if (intr1) {
992                         NV_ERROR(dev,
993                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
994                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
995                 }
996         }
997 }
998