drm/radeon/kms/pm/r600: select the mid clock mode for single head low profile
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00488 */
866         int err_most = (target >> 8) + (target >> 10);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requriment prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirment prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984         struct drm_device *dev = crtc->dev;
985         struct drm_i915_private *dev_priv = dev->dev_private;
986         struct drm_framebuffer *fb = crtc->fb;
987         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990         int plane, i;
991         u32 fbc_ctl, fbc_ctl2;
992
993         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995         if (fb->pitch < dev_priv->cfb_pitch)
996                 dev_priv->cfb_pitch = fb->pitch;
997
998         /* FBC_CTL wants 64B units */
999         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000         dev_priv->cfb_fence = obj_priv->fence_reg;
1001         dev_priv->cfb_plane = intel_crtc->plane;
1002         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004         /* Clear old tags */
1005         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006                 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008         /* Set it up... */
1009         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010         if (obj_priv->tiling_mode != I915_TILING_NONE)
1011                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015         /* enable it... */
1016         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017         if (IS_I945GM(dev))
1018                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021         if (obj_priv->tiling_mode != I915_TILING_NONE)
1022                 fbc_ctl |= dev_priv->cfb_fence;
1023         I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         u32 fbc_ctl;
1033
1034         if (!I915_HAS_FBC(dev))
1035                 return;
1036
1037         /* Disable compression */
1038         fbc_ctl = I915_READ(FBC_CONTROL);
1039         fbc_ctl &= ~FBC_CTL_EN;
1040         I915_WRITE(FBC_CONTROL, fbc_ctl);
1041
1042         /* Wait for compressing bit to clear */
1043         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1044                 ; /* nothing */
1045
1046         intel_wait_for_vblank(dev);
1047
1048         DRM_DEBUG_KMS("disabled FBC\n");
1049 }
1050
1051 static bool i8xx_fbc_enabled(struct drm_device *dev)
1052 {
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054
1055         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1056 }
1057
1058 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1059 {
1060         struct drm_device *dev = crtc->dev;
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         struct drm_framebuffer *fb = crtc->fb;
1063         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1064         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1067                      DPFC_CTL_PLANEB);
1068         unsigned long stall_watermark = 200;
1069         u32 dpfc_ctl;
1070
1071         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1072         dev_priv->cfb_fence = obj_priv->fence_reg;
1073         dev_priv->cfb_plane = intel_crtc->plane;
1074
1075         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1076         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1077                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1078                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1079         } else {
1080                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1081         }
1082
1083         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1084         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1085                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1086                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1087         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1088
1089         /* enable it... */
1090         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1091
1092         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1093 }
1094
1095 void g4x_disable_fbc(struct drm_device *dev)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 dpfc_ctl;
1099
1100         /* Disable compression */
1101         dpfc_ctl = I915_READ(DPFC_CONTROL);
1102         dpfc_ctl &= ~DPFC_CTL_EN;
1103         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1104         intel_wait_for_vblank(dev);
1105
1106         DRM_DEBUG_KMS("disabled FBC\n");
1107 }
1108
1109 static bool g4x_fbc_enabled(struct drm_device *dev)
1110 {
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112
1113         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1114 }
1115
1116 bool intel_fbc_enabled(struct drm_device *dev)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120         if (!dev_priv->display.fbc_enabled)
1121                 return false;
1122
1123         return dev_priv->display.fbc_enabled(dev);
1124 }
1125
1126 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1129
1130         if (!dev_priv->display.enable_fbc)
1131                 return;
1132
1133         dev_priv->display.enable_fbc(crtc, interval);
1134 }
1135
1136 void intel_disable_fbc(struct drm_device *dev)
1137 {
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139
1140         if (!dev_priv->display.disable_fbc)
1141                 return;
1142
1143         dev_priv->display.disable_fbc(dev);
1144 }
1145
1146 /**
1147  * intel_update_fbc - enable/disable FBC as needed
1148  * @crtc: CRTC to point the compressor at
1149  * @mode: mode in use
1150  *
1151  * Set up the framebuffer compression hardware at mode set time.  We
1152  * enable it if possible:
1153  *   - plane A only (on pre-965)
1154  *   - no pixel mulitply/line duplication
1155  *   - no alpha buffer discard
1156  *   - no dual wide
1157  *   - framebuffer <= 2048 in width, 1536 in height
1158  *
1159  * We can't assume that any compression will take place (worst case),
1160  * so the compressed buffer has to be the same size as the uncompressed
1161  * one.  It also must reside (along with the line length buffer) in
1162  * stolen memory.
1163  *
1164  * We need to enable/disable FBC on a global basis.
1165  */
1166 static void intel_update_fbc(struct drm_crtc *crtc,
1167                              struct drm_display_mode *mode)
1168 {
1169         struct drm_device *dev = crtc->dev;
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct drm_framebuffer *fb = crtc->fb;
1172         struct intel_framebuffer *intel_fb;
1173         struct drm_i915_gem_object *obj_priv;
1174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1175         int plane = intel_crtc->plane;
1176
1177         if (!i915_powersave)
1178                 return;
1179
1180         if (!I915_HAS_FBC(dev))
1181                 return;
1182
1183         if (!crtc->fb)
1184                 return;
1185
1186         intel_fb = to_intel_framebuffer(fb);
1187         obj_priv = to_intel_bo(intel_fb->obj);
1188
1189         /*
1190          * If FBC is already on, we just have to verify that we can
1191          * keep it that way...
1192          * Need to disable if:
1193          *   - changing FBC params (stride, fence, mode)
1194          *   - new fb is too large to fit in compressed buffer
1195          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1196          */
1197         if (intel_fb->obj->size > dev_priv->cfb_size) {
1198                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1199                                 "compression\n");
1200                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1201                 goto out_disable;
1202         }
1203         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1204             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1205                 DRM_DEBUG_KMS("mode incompatible with compression, "
1206                                 "disabling\n");
1207                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1208                 goto out_disable;
1209         }
1210         if ((mode->hdisplay > 2048) ||
1211             (mode->vdisplay > 1536)) {
1212                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1213                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1214                 goto out_disable;
1215         }
1216         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1217                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1218                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1219                 goto out_disable;
1220         }
1221         if (obj_priv->tiling_mode != I915_TILING_X) {
1222                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1223                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1224                 goto out_disable;
1225         }
1226
1227         if (intel_fbc_enabled(dev)) {
1228                 /* We can re-enable it in this case, but need to update pitch */
1229                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1230                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1231                     (plane != dev_priv->cfb_plane))
1232                         intel_disable_fbc(dev);
1233         }
1234
1235         /* Now try to turn it back on if possible */
1236         if (!intel_fbc_enabled(dev))
1237                 intel_enable_fbc(crtc, 500);
1238
1239         return;
1240
1241 out_disable:
1242         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1243         /* Multiple disables should be harmless */
1244         if (intel_fbc_enabled(dev))
1245                 intel_disable_fbc(dev);
1246 }
1247
1248 static int
1249 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1250 {
1251         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1252         u32 alignment;
1253         int ret;
1254
1255         switch (obj_priv->tiling_mode) {
1256         case I915_TILING_NONE:
1257                 alignment = 64 * 1024;
1258                 break;
1259         case I915_TILING_X:
1260                 /* pin() will align the object as required by fence */
1261                 alignment = 0;
1262                 break;
1263         case I915_TILING_Y:
1264                 /* FIXME: Is this true? */
1265                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1266                 return -EINVAL;
1267         default:
1268                 BUG();
1269         }
1270
1271         ret = i915_gem_object_pin(obj, alignment);
1272         if (ret != 0)
1273                 return ret;
1274
1275         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1276          * fence, whereas 965+ only requires a fence if using
1277          * framebuffer compression.  For simplicity, we always install
1278          * a fence as the cost is not that onerous.
1279          */
1280         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1281             obj_priv->tiling_mode != I915_TILING_NONE) {
1282                 ret = i915_gem_object_get_fence_reg(obj);
1283                 if (ret != 0) {
1284                         i915_gem_object_unpin(obj);
1285                         return ret;
1286                 }
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int
1293 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1294                     struct drm_framebuffer *old_fb)
1295 {
1296         struct drm_device *dev = crtc->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct drm_i915_master_private *master_priv;
1299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1300         struct intel_framebuffer *intel_fb;
1301         struct drm_i915_gem_object *obj_priv;
1302         struct drm_gem_object *obj;
1303         int pipe = intel_crtc->pipe;
1304         int plane = intel_crtc->plane;
1305         unsigned long Start, Offset;
1306         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1307         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1308         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1309         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1310         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1311         u32 dspcntr;
1312         int ret;
1313
1314         /* no fb bound */
1315         if (!crtc->fb) {
1316                 DRM_DEBUG_KMS("No FB bound\n");
1317                 return 0;
1318         }
1319
1320         switch (plane) {
1321         case 0:
1322         case 1:
1323                 break;
1324         default:
1325                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1326                 return -EINVAL;
1327         }
1328
1329         intel_fb = to_intel_framebuffer(crtc->fb);
1330         obj = intel_fb->obj;
1331         obj_priv = to_intel_bo(obj);
1332
1333         mutex_lock(&dev->struct_mutex);
1334         ret = intel_pin_and_fence_fb_obj(dev, obj);
1335         if (ret != 0) {
1336                 mutex_unlock(&dev->struct_mutex);
1337                 return ret;
1338         }
1339
1340         ret = i915_gem_object_set_to_display_plane(obj);
1341         if (ret != 0) {
1342                 i915_gem_object_unpin(obj);
1343                 mutex_unlock(&dev->struct_mutex);
1344                 return ret;
1345         }
1346
1347         dspcntr = I915_READ(dspcntr_reg);
1348         /* Mask out pixel format bits in case we change it */
1349         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1350         switch (crtc->fb->bits_per_pixel) {
1351         case 8:
1352                 dspcntr |= DISPPLANE_8BPP;
1353                 break;
1354         case 16:
1355                 if (crtc->fb->depth == 15)
1356                         dspcntr |= DISPPLANE_15_16BPP;
1357                 else
1358                         dspcntr |= DISPPLANE_16BPP;
1359                 break;
1360         case 24:
1361         case 32:
1362                 if (crtc->fb->depth == 30)
1363                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1364                 else
1365                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1366                 break;
1367         default:
1368                 DRM_ERROR("Unknown color depth\n");
1369                 i915_gem_object_unpin(obj);
1370                 mutex_unlock(&dev->struct_mutex);
1371                 return -EINVAL;
1372         }
1373         if (IS_I965G(dev)) {
1374                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1375                         dspcntr |= DISPPLANE_TILED;
1376                 else
1377                         dspcntr &= ~DISPPLANE_TILED;
1378         }
1379
1380         if (HAS_PCH_SPLIT(dev))
1381                 /* must disable */
1382                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1383
1384         I915_WRITE(dspcntr_reg, dspcntr);
1385
1386         Start = obj_priv->gtt_offset;
1387         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1388
1389         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1390         I915_WRITE(dspstride, crtc->fb->pitch);
1391         if (IS_I965G(dev)) {
1392                 I915_WRITE(dspbase, Offset);
1393                 I915_READ(dspbase);
1394                 I915_WRITE(dspsurf, Start);
1395                 I915_READ(dspsurf);
1396                 I915_WRITE(dsptileoff, (y << 16) | x);
1397         } else {
1398                 I915_WRITE(dspbase, Start + Offset);
1399                 I915_READ(dspbase);
1400         }
1401
1402         if ((IS_I965G(dev) || plane == 0))
1403                 intel_update_fbc(crtc, &crtc->mode);
1404
1405         intel_wait_for_vblank(dev);
1406
1407         if (old_fb) {
1408                 intel_fb = to_intel_framebuffer(old_fb);
1409                 obj_priv = to_intel_bo(intel_fb->obj);
1410                 i915_gem_object_unpin(intel_fb->obj);
1411         }
1412         intel_increase_pllclock(crtc, true);
1413
1414         mutex_unlock(&dev->struct_mutex);
1415
1416         if (!dev->primary->master)
1417                 return 0;
1418
1419         master_priv = dev->primary->master->driver_priv;
1420         if (!master_priv->sarea_priv)
1421                 return 0;
1422
1423         if (pipe) {
1424                 master_priv->sarea_priv->pipeB_x = x;
1425                 master_priv->sarea_priv->pipeB_y = y;
1426         } else {
1427                 master_priv->sarea_priv->pipeA_x = x;
1428                 master_priv->sarea_priv->pipeA_y = y;
1429         }
1430
1431         return 0;
1432 }
1433
1434 /* Disable the VGA plane that we never use */
1435 static void i915_disable_vga (struct drm_device *dev)
1436 {
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         u8 sr1;
1439         u32 vga_reg;
1440
1441         if (HAS_PCH_SPLIT(dev))
1442                 vga_reg = CPU_VGACNTRL;
1443         else
1444                 vga_reg = VGACNTRL;
1445
1446         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1447                 return;
1448
1449         I915_WRITE8(VGA_SR_INDEX, 1);
1450         sr1 = I915_READ8(VGA_SR_DATA);
1451         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1452         udelay(100);
1453
1454         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1455 }
1456
1457 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1458 {
1459         struct drm_device *dev = crtc->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         u32 dpa_ctl;
1462
1463         DRM_DEBUG_KMS("\n");
1464         dpa_ctl = I915_READ(DP_A);
1465         dpa_ctl &= ~DP_PLL_ENABLE;
1466         I915_WRITE(DP_A, dpa_ctl);
1467 }
1468
1469 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1470 {
1471         struct drm_device *dev = crtc->dev;
1472         struct drm_i915_private *dev_priv = dev->dev_private;
1473         u32 dpa_ctl;
1474
1475         dpa_ctl = I915_READ(DP_A);
1476         dpa_ctl |= DP_PLL_ENABLE;
1477         I915_WRITE(DP_A, dpa_ctl);
1478         udelay(200);
1479 }
1480
1481
1482 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1483 {
1484         struct drm_device *dev = crtc->dev;
1485         struct drm_i915_private *dev_priv = dev->dev_private;
1486         u32 dpa_ctl;
1487
1488         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1489         dpa_ctl = I915_READ(DP_A);
1490         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1491
1492         if (clock < 200000) {
1493                 u32 temp;
1494                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1495                 /* workaround for 160Mhz:
1496                    1) program 0x4600c bits 15:0 = 0x8124
1497                    2) program 0x46010 bit 0 = 1
1498                    3) program 0x46034 bit 24 = 1
1499                    4) program 0x64000 bit 14 = 1
1500                    */
1501                 temp = I915_READ(0x4600c);
1502                 temp &= 0xffff0000;
1503                 I915_WRITE(0x4600c, temp | 0x8124);
1504
1505                 temp = I915_READ(0x46010);
1506                 I915_WRITE(0x46010, temp | 1);
1507
1508                 temp = I915_READ(0x46034);
1509                 I915_WRITE(0x46034, temp | (1 << 24));
1510         } else {
1511                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1512         }
1513         I915_WRITE(DP_A, dpa_ctl);
1514
1515         udelay(500);
1516 }
1517
1518 /* The FDI link training functions for ILK/Ibexpeak. */
1519 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1524         int pipe = intel_crtc->pipe;
1525         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1526         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1527         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1528         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1529         u32 temp, tries = 0;
1530
1531         /* enable CPU FDI TX and PCH FDI RX */
1532         temp = I915_READ(fdi_tx_reg);
1533         temp |= FDI_TX_ENABLE;
1534         temp &= ~(7 << 19);
1535         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1536         temp &= ~FDI_LINK_TRAIN_NONE;
1537         temp |= FDI_LINK_TRAIN_PATTERN_1;
1538         I915_WRITE(fdi_tx_reg, temp);
1539         I915_READ(fdi_tx_reg);
1540
1541         temp = I915_READ(fdi_rx_reg);
1542         temp &= ~FDI_LINK_TRAIN_NONE;
1543         temp |= FDI_LINK_TRAIN_PATTERN_1;
1544         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1545         I915_READ(fdi_rx_reg);
1546         udelay(150);
1547
1548         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1549            for train result */
1550         temp = I915_READ(fdi_rx_imr_reg);
1551         temp &= ~FDI_RX_SYMBOL_LOCK;
1552         temp &= ~FDI_RX_BIT_LOCK;
1553         I915_WRITE(fdi_rx_imr_reg, temp);
1554         I915_READ(fdi_rx_imr_reg);
1555         udelay(150);
1556
1557         for (;;) {
1558                 temp = I915_READ(fdi_rx_iir_reg);
1559                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1560
1561                 if ((temp & FDI_RX_BIT_LOCK)) {
1562                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1563                         I915_WRITE(fdi_rx_iir_reg,
1564                                    temp | FDI_RX_BIT_LOCK);
1565                         break;
1566                 }
1567
1568                 tries++;
1569
1570                 if (tries > 5) {
1571                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1572                         break;
1573                 }
1574         }
1575
1576         /* Train 2 */
1577         temp = I915_READ(fdi_tx_reg);
1578         temp &= ~FDI_LINK_TRAIN_NONE;
1579         temp |= FDI_LINK_TRAIN_PATTERN_2;
1580         I915_WRITE(fdi_tx_reg, temp);
1581
1582         temp = I915_READ(fdi_rx_reg);
1583         temp &= ~FDI_LINK_TRAIN_NONE;
1584         temp |= FDI_LINK_TRAIN_PATTERN_2;
1585         I915_WRITE(fdi_rx_reg, temp);
1586         udelay(150);
1587
1588         tries = 0;
1589
1590         for (;;) {
1591                 temp = I915_READ(fdi_rx_iir_reg);
1592                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1593
1594                 if (temp & FDI_RX_SYMBOL_LOCK) {
1595                         I915_WRITE(fdi_rx_iir_reg,
1596                                    temp | FDI_RX_SYMBOL_LOCK);
1597                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1598                         break;
1599                 }
1600
1601                 tries++;
1602
1603                 if (tries > 5) {
1604                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1605                         break;
1606                 }
1607         }
1608
1609         DRM_DEBUG_KMS("FDI train done\n");
1610 }
1611
1612 static int snb_b_fdi_train_param [] = {
1613         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1614         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1615         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1616         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1617 };
1618
1619 /* The FDI link training functions for SNB/Cougarpoint. */
1620 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1625         int pipe = intel_crtc->pipe;
1626         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1627         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1628         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1629         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1630         u32 temp, i;
1631
1632         /* enable CPU FDI TX and PCH FDI RX */
1633         temp = I915_READ(fdi_tx_reg);
1634         temp |= FDI_TX_ENABLE;
1635         temp &= ~(7 << 19);
1636         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1637         temp &= ~FDI_LINK_TRAIN_NONE;
1638         temp |= FDI_LINK_TRAIN_PATTERN_1;
1639         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1640         /* SNB-B */
1641         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1642         I915_WRITE(fdi_tx_reg, temp);
1643         I915_READ(fdi_tx_reg);
1644
1645         temp = I915_READ(fdi_rx_reg);
1646         if (HAS_PCH_CPT(dev)) {
1647                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1648                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1649         } else {
1650                 temp &= ~FDI_LINK_TRAIN_NONE;
1651                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1652         }
1653         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1654         I915_READ(fdi_rx_reg);
1655         udelay(150);
1656
1657         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1658            for train result */
1659         temp = I915_READ(fdi_rx_imr_reg);
1660         temp &= ~FDI_RX_SYMBOL_LOCK;
1661         temp &= ~FDI_RX_BIT_LOCK;
1662         I915_WRITE(fdi_rx_imr_reg, temp);
1663         I915_READ(fdi_rx_imr_reg);
1664         udelay(150);
1665
1666         for (i = 0; i < 4; i++ ) {
1667                 temp = I915_READ(fdi_tx_reg);
1668                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1669                 temp |= snb_b_fdi_train_param[i];
1670                 I915_WRITE(fdi_tx_reg, temp);
1671                 udelay(500);
1672
1673                 temp = I915_READ(fdi_rx_iir_reg);
1674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1675
1676                 if (temp & FDI_RX_BIT_LOCK) {
1677                         I915_WRITE(fdi_rx_iir_reg,
1678                                    temp | FDI_RX_BIT_LOCK);
1679                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1680                         break;
1681                 }
1682         }
1683         if (i == 4)
1684                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1685
1686         /* Train 2 */
1687         temp = I915_READ(fdi_tx_reg);
1688         temp &= ~FDI_LINK_TRAIN_NONE;
1689         temp |= FDI_LINK_TRAIN_PATTERN_2;
1690         if (IS_GEN6(dev)) {
1691                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1692                 /* SNB-B */
1693                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1694         }
1695         I915_WRITE(fdi_tx_reg, temp);
1696
1697         temp = I915_READ(fdi_rx_reg);
1698         if (HAS_PCH_CPT(dev)) {
1699                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1700                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1701         } else {
1702                 temp &= ~FDI_LINK_TRAIN_NONE;
1703                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1704         }
1705         I915_WRITE(fdi_rx_reg, temp);
1706         udelay(150);
1707
1708         for (i = 0; i < 4; i++ ) {
1709                 temp = I915_READ(fdi_tx_reg);
1710                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1711                 temp |= snb_b_fdi_train_param[i];
1712                 I915_WRITE(fdi_tx_reg, temp);
1713                 udelay(500);
1714
1715                 temp = I915_READ(fdi_rx_iir_reg);
1716                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1717
1718                 if (temp & FDI_RX_SYMBOL_LOCK) {
1719                         I915_WRITE(fdi_rx_iir_reg,
1720                                    temp | FDI_RX_SYMBOL_LOCK);
1721                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1722                         break;
1723                 }
1724         }
1725         if (i == 4)
1726                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1727
1728         DRM_DEBUG_KMS("FDI train done.\n");
1729 }
1730
1731 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1732 {
1733         struct drm_device *dev = crtc->dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1736         int pipe = intel_crtc->pipe;
1737         int plane = intel_crtc->plane;
1738         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1739         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1740         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1741         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1742         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1743         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1744         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1745         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1746         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1747         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1748         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1749         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1750         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1751         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1752         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1753         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1754         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1755         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1756         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1757         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1758         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1759         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1760         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1761         u32 temp;
1762         int n;
1763         u32 pipe_bpc;
1764
1765         temp = I915_READ(pipeconf_reg);
1766         pipe_bpc = temp & PIPE_BPC_MASK;
1767
1768         /* XXX: When our outputs are all unaware of DPMS modes other than off
1769          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1770          */
1771         switch (mode) {
1772         case DRM_MODE_DPMS_ON:
1773         case DRM_MODE_DPMS_STANDBY:
1774         case DRM_MODE_DPMS_SUSPEND:
1775                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1776
1777                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1778                         temp = I915_READ(PCH_LVDS);
1779                         if ((temp & LVDS_PORT_EN) == 0) {
1780                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1781                                 POSTING_READ(PCH_LVDS);
1782                         }
1783                 }
1784
1785                 if (HAS_eDP) {
1786                         /* enable eDP PLL */
1787                         ironlake_enable_pll_edp(crtc);
1788                 } else {
1789
1790                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1791                         temp = I915_READ(fdi_rx_reg);
1792                         /*
1793                          * make the BPC in FDI Rx be consistent with that in
1794                          * pipeconf reg.
1795                          */
1796                         temp &= ~(0x7 << 16);
1797                         temp |= (pipe_bpc << 11);
1798                         temp &= ~(7 << 19);
1799                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1800                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1801                         I915_READ(fdi_rx_reg);
1802                         udelay(200);
1803
1804                         /* Switch from Rawclk to PCDclk */
1805                         temp = I915_READ(fdi_rx_reg);
1806                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1807                         I915_READ(fdi_rx_reg);
1808                         udelay(200);
1809
1810                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1811                         temp = I915_READ(fdi_tx_reg);
1812                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1813                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1814                                 I915_READ(fdi_tx_reg);
1815                                 udelay(100);
1816                         }
1817                 }
1818
1819                 /* Enable panel fitting for LVDS */
1820                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1821                         temp = I915_READ(pf_ctl_reg);
1822                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1823
1824                         /* currently full aspect */
1825                         I915_WRITE(pf_win_pos, 0);
1826
1827                         I915_WRITE(pf_win_size,
1828                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1829                                    (dev_priv->panel_fixed_mode->vdisplay));
1830                 }
1831
1832                 /* Enable CPU pipe */
1833                 temp = I915_READ(pipeconf_reg);
1834                 if ((temp & PIPEACONF_ENABLE) == 0) {
1835                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1836                         I915_READ(pipeconf_reg);
1837                         udelay(100);
1838                 }
1839
1840                 /* configure and enable CPU plane */
1841                 temp = I915_READ(dspcntr_reg);
1842                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1843                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1844                         /* Flush the plane changes */
1845                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1846                 }
1847
1848                 if (!HAS_eDP) {
1849                         /* For PCH output, training FDI link */
1850                         if (IS_GEN6(dev))
1851                                 gen6_fdi_link_train(crtc);
1852                         else
1853                                 ironlake_fdi_link_train(crtc);
1854
1855                         /* enable PCH DPLL */
1856                         temp = I915_READ(pch_dpll_reg);
1857                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1858                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1859                                 I915_READ(pch_dpll_reg);
1860                         }
1861                         udelay(200);
1862
1863                         if (HAS_PCH_CPT(dev)) {
1864                                 /* Be sure PCH DPLL SEL is set */
1865                                 temp = I915_READ(PCH_DPLL_SEL);
1866                                 if (trans_dpll_sel == 0 &&
1867                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1868                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1869                                 else if (trans_dpll_sel == 1 &&
1870                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1871                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1872                                 I915_WRITE(PCH_DPLL_SEL, temp);
1873                                 I915_READ(PCH_DPLL_SEL);
1874                         }
1875
1876                         /* set transcoder timing */
1877                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1878                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1879                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1880
1881                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1882                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1883                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1884
1885                         /* enable normal train */
1886                         temp = I915_READ(fdi_tx_reg);
1887                         temp &= ~FDI_LINK_TRAIN_NONE;
1888                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1889                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1890                         I915_READ(fdi_tx_reg);
1891
1892                         temp = I915_READ(fdi_rx_reg);
1893                         if (HAS_PCH_CPT(dev)) {
1894                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1895                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1896                         } else {
1897                                 temp &= ~FDI_LINK_TRAIN_NONE;
1898                                 temp |= FDI_LINK_TRAIN_NONE;
1899                         }
1900                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1901                         I915_READ(fdi_rx_reg);
1902
1903                         /* wait one idle pattern time */
1904                         udelay(100);
1905
1906                         /* For PCH DP, enable TRANS_DP_CTL */
1907                         if (HAS_PCH_CPT(dev) &&
1908                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1909                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1910                                 int reg;
1911
1912                                 reg = I915_READ(trans_dp_ctl);
1913                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1914                                 reg = TRANS_DP_OUTPUT_ENABLE |
1915                                       TRANS_DP_ENH_FRAMING |
1916                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1917                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1918
1919                                 switch (intel_trans_dp_port_sel(crtc)) {
1920                                 case PCH_DP_B:
1921                                         reg |= TRANS_DP_PORT_SEL_B;
1922                                         break;
1923                                 case PCH_DP_C:
1924                                         reg |= TRANS_DP_PORT_SEL_C;
1925                                         break;
1926                                 case PCH_DP_D:
1927                                         reg |= TRANS_DP_PORT_SEL_D;
1928                                         break;
1929                                 default:
1930                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1931                                         reg |= TRANS_DP_PORT_SEL_B;
1932                                         break;
1933                                 }
1934
1935                                 I915_WRITE(trans_dp_ctl, reg);
1936                                 POSTING_READ(trans_dp_ctl);
1937                         }
1938
1939                         /* enable PCH transcoder */
1940                         temp = I915_READ(transconf_reg);
1941                         /*
1942                          * make the BPC in transcoder be consistent with
1943                          * that in pipeconf reg.
1944                          */
1945                         temp &= ~PIPE_BPC_MASK;
1946                         temp |= pipe_bpc;
1947                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1948                         I915_READ(transconf_reg);
1949
1950                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1951                                 ;
1952
1953                 }
1954
1955                 intel_crtc_load_lut(crtc);
1956
1957         break;
1958         case DRM_MODE_DPMS_OFF:
1959                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1960
1961                 drm_vblank_off(dev, pipe);
1962                 /* Disable display plane */
1963                 temp = I915_READ(dspcntr_reg);
1964                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1965                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1966                         /* Flush the plane changes */
1967                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1968                         I915_READ(dspbase_reg);
1969                 }
1970
1971                 i915_disable_vga(dev);
1972
1973                 /* disable cpu pipe, disable after all planes disabled */
1974                 temp = I915_READ(pipeconf_reg);
1975                 if ((temp & PIPEACONF_ENABLE) != 0) {
1976                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1977                         I915_READ(pipeconf_reg);
1978                         n = 0;
1979                         /* wait for cpu pipe off, pipe state */
1980                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1981                                 n++;
1982                                 if (n < 60) {
1983                                         udelay(500);
1984                                         continue;
1985                                 } else {
1986                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1987                                                                 pipe);
1988                                         break;
1989                                 }
1990                         }
1991                 } else
1992                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1993
1994                 udelay(100);
1995
1996                 /* Disable PF */
1997                 temp = I915_READ(pf_ctl_reg);
1998                 if ((temp & PF_ENABLE) != 0) {
1999                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2000                         I915_READ(pf_ctl_reg);
2001                 }
2002                 I915_WRITE(pf_win_size, 0);
2003                 POSTING_READ(pf_win_size);
2004
2005
2006                 /* disable CPU FDI tx and PCH FDI rx */
2007                 temp = I915_READ(fdi_tx_reg);
2008                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2009                 I915_READ(fdi_tx_reg);
2010
2011                 temp = I915_READ(fdi_rx_reg);
2012                 /* BPC in FDI rx is consistent with that in pipeconf */
2013                 temp &= ~(0x07 << 16);
2014                 temp |= (pipe_bpc << 11);
2015                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2016                 I915_READ(fdi_rx_reg);
2017
2018                 udelay(100);
2019
2020                 /* still set train pattern 1 */
2021                 temp = I915_READ(fdi_tx_reg);
2022                 temp &= ~FDI_LINK_TRAIN_NONE;
2023                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2024                 I915_WRITE(fdi_tx_reg, temp);
2025                 POSTING_READ(fdi_tx_reg);
2026
2027                 temp = I915_READ(fdi_rx_reg);
2028                 if (HAS_PCH_CPT(dev)) {
2029                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2030                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2031                 } else {
2032                         temp &= ~FDI_LINK_TRAIN_NONE;
2033                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2034                 }
2035                 I915_WRITE(fdi_rx_reg, temp);
2036                 POSTING_READ(fdi_rx_reg);
2037
2038                 udelay(100);
2039
2040                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2041                         temp = I915_READ(PCH_LVDS);
2042                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2043                         I915_READ(PCH_LVDS);
2044                         udelay(100);
2045                 }
2046
2047                 /* disable PCH transcoder */
2048                 temp = I915_READ(transconf_reg);
2049                 if ((temp & TRANS_ENABLE) != 0) {
2050                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2051                         I915_READ(transconf_reg);
2052                         n = 0;
2053                         /* wait for PCH transcoder off, transcoder state */
2054                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2055                                 n++;
2056                                 if (n < 60) {
2057                                         udelay(500);
2058                                         continue;
2059                                 } else {
2060                                         DRM_DEBUG_KMS("transcoder %d off "
2061                                                         "delay\n", pipe);
2062                                         break;
2063                                 }
2064                         }
2065                 }
2066
2067                 temp = I915_READ(transconf_reg);
2068                 /* BPC in transcoder is consistent with that in pipeconf */
2069                 temp &= ~PIPE_BPC_MASK;
2070                 temp |= pipe_bpc;
2071                 I915_WRITE(transconf_reg, temp);
2072                 I915_READ(transconf_reg);
2073                 udelay(100);
2074
2075                 if (HAS_PCH_CPT(dev)) {
2076                         /* disable TRANS_DP_CTL */
2077                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2078                         int reg;
2079
2080                         reg = I915_READ(trans_dp_ctl);
2081                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2082                         I915_WRITE(trans_dp_ctl, reg);
2083                         POSTING_READ(trans_dp_ctl);
2084
2085                         /* disable DPLL_SEL */
2086                         temp = I915_READ(PCH_DPLL_SEL);
2087                         if (trans_dpll_sel == 0)
2088                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2089                         else
2090                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2091                         I915_WRITE(PCH_DPLL_SEL, temp);
2092                         I915_READ(PCH_DPLL_SEL);
2093
2094                 }
2095
2096                 /* disable PCH DPLL */
2097                 temp = I915_READ(pch_dpll_reg);
2098                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2099                 I915_READ(pch_dpll_reg);
2100
2101                 if (HAS_eDP) {
2102                         ironlake_disable_pll_edp(crtc);
2103                 }
2104
2105                 /* Switch from PCDclk to Rawclk */
2106                 temp = I915_READ(fdi_rx_reg);
2107                 temp &= ~FDI_SEL_PCDCLK;
2108                 I915_WRITE(fdi_rx_reg, temp);
2109                 I915_READ(fdi_rx_reg);
2110
2111                 /* Disable CPU FDI TX PLL */
2112                 temp = I915_READ(fdi_tx_reg);
2113                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2114                 I915_READ(fdi_tx_reg);
2115                 udelay(100);
2116
2117                 temp = I915_READ(fdi_rx_reg);
2118                 temp &= ~FDI_RX_PLL_ENABLE;
2119                 I915_WRITE(fdi_rx_reg, temp);
2120                 I915_READ(fdi_rx_reg);
2121
2122                 /* Wait for the clocks to turn off. */
2123                 udelay(100);
2124                 break;
2125         }
2126 }
2127
2128 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2129 {
2130         struct intel_overlay *overlay;
2131         int ret;
2132
2133         if (!enable && intel_crtc->overlay) {
2134                 overlay = intel_crtc->overlay;
2135                 mutex_lock(&overlay->dev->struct_mutex);
2136                 for (;;) {
2137                         ret = intel_overlay_switch_off(overlay);
2138                         if (ret == 0)
2139                                 break;
2140
2141                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2142                         if (ret != 0) {
2143                                 /* overlay doesn't react anymore. Usually
2144                                  * results in a black screen and an unkillable
2145                                  * X server. */
2146                                 BUG();
2147                                 overlay->hw_wedged = HW_WEDGED;
2148                                 break;
2149                         }
2150                 }
2151                 mutex_unlock(&overlay->dev->struct_mutex);
2152         }
2153         /* Let userspace switch the overlay on again. In most cases userspace
2154          * has to recompute where to put it anyway. */
2155
2156         return;
2157 }
2158
2159 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2160 {
2161         struct drm_device *dev = crtc->dev;
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164         int pipe = intel_crtc->pipe;
2165         int plane = intel_crtc->plane;
2166         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2167         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2168         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2169         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2170         u32 temp;
2171
2172         /* XXX: When our outputs are all unaware of DPMS modes other than off
2173          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2174          */
2175         switch (mode) {
2176         case DRM_MODE_DPMS_ON:
2177         case DRM_MODE_DPMS_STANDBY:
2178         case DRM_MODE_DPMS_SUSPEND:
2179                 intel_update_watermarks(dev);
2180
2181                 /* Enable the DPLL */
2182                 temp = I915_READ(dpll_reg);
2183                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2184                         I915_WRITE(dpll_reg, temp);
2185                         I915_READ(dpll_reg);
2186                         /* Wait for the clocks to stabilize. */
2187                         udelay(150);
2188                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2189                         I915_READ(dpll_reg);
2190                         /* Wait for the clocks to stabilize. */
2191                         udelay(150);
2192                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2193                         I915_READ(dpll_reg);
2194                         /* Wait for the clocks to stabilize. */
2195                         udelay(150);
2196                 }
2197
2198                 /* Enable the pipe */
2199                 temp = I915_READ(pipeconf_reg);
2200                 if ((temp & PIPEACONF_ENABLE) == 0)
2201                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2202
2203                 /* Enable the plane */
2204                 temp = I915_READ(dspcntr_reg);
2205                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2206                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2207                         /* Flush the plane changes */
2208                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2209                 }
2210
2211                 intel_crtc_load_lut(crtc);
2212
2213                 if ((IS_I965G(dev) || plane == 0))
2214                         intel_update_fbc(crtc, &crtc->mode);
2215
2216                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2217                 intel_crtc_dpms_overlay(intel_crtc, true);
2218         break;
2219         case DRM_MODE_DPMS_OFF:
2220                 intel_update_watermarks(dev);
2221
2222                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2223                 intel_crtc_dpms_overlay(intel_crtc, false);
2224                 drm_vblank_off(dev, pipe);
2225
2226                 if (dev_priv->cfb_plane == plane &&
2227                     dev_priv->display.disable_fbc)
2228                         dev_priv->display.disable_fbc(dev);
2229
2230                 /* Disable the VGA plane that we never use */
2231                 i915_disable_vga(dev);
2232
2233                 /* Disable display plane */
2234                 temp = I915_READ(dspcntr_reg);
2235                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2236                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2237                         /* Flush the plane changes */
2238                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2239                         I915_READ(dspbase_reg);
2240                 }
2241
2242                 if (!IS_I9XX(dev)) {
2243                         /* Wait for vblank for the disable to take effect */
2244                         intel_wait_for_vblank(dev);
2245                 }
2246
2247                 /* Next, disable display pipes */
2248                 temp = I915_READ(pipeconf_reg);
2249                 if ((temp & PIPEACONF_ENABLE) != 0) {
2250                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2251                         I915_READ(pipeconf_reg);
2252                 }
2253
2254                 /* Wait for vblank for the disable to take effect. */
2255                 intel_wait_for_vblank(dev);
2256
2257                 temp = I915_READ(dpll_reg);
2258                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2259                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2260                         I915_READ(dpll_reg);
2261                 }
2262
2263                 /* Wait for the clocks to turn off. */
2264                 udelay(150);
2265                 break;
2266         }
2267 }
2268
2269 /**
2270  * Sets the power management mode of the pipe and plane.
2271  *
2272  * This code should probably grow support for turning the cursor off and back
2273  * on appropriately at the same time as we're turning the pipe off/on.
2274  */
2275 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2276 {
2277         struct drm_device *dev = crtc->dev;
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279         struct drm_i915_master_private *master_priv;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int pipe = intel_crtc->pipe;
2282         bool enabled;
2283
2284         dev_priv->display.dpms(crtc, mode);
2285
2286         intel_crtc->dpms_mode = mode;
2287
2288         if (!dev->primary->master)
2289                 return;
2290
2291         master_priv = dev->primary->master->driver_priv;
2292         if (!master_priv->sarea_priv)
2293                 return;
2294
2295         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2296
2297         switch (pipe) {
2298         case 0:
2299                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2300                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2301                 break;
2302         case 1:
2303                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2304                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2305                 break;
2306         default:
2307                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2308                 break;
2309         }
2310 }
2311
2312 static void intel_crtc_prepare (struct drm_crtc *crtc)
2313 {
2314         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2315         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2316 }
2317
2318 static void intel_crtc_commit (struct drm_crtc *crtc)
2319 {
2320         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2321         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2322 }
2323
2324 void intel_encoder_prepare (struct drm_encoder *encoder)
2325 {
2326         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2327         /* lvds has its own version of prepare see intel_lvds_prepare */
2328         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2329 }
2330
2331 void intel_encoder_commit (struct drm_encoder *encoder)
2332 {
2333         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2334         /* lvds has its own version of commit see intel_lvds_commit */
2335         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2336 }
2337
2338 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2339                                   struct drm_display_mode *mode,
2340                                   struct drm_display_mode *adjusted_mode)
2341 {
2342         struct drm_device *dev = crtc->dev;
2343         if (HAS_PCH_SPLIT(dev)) {
2344                 /* FDI link clock is fixed at 2.7G */
2345                 if (mode->clock * 3 > 27000 * 4)
2346                         return MODE_CLOCK_HIGH;
2347         }
2348         return true;
2349 }
2350
2351 static int i945_get_display_clock_speed(struct drm_device *dev)
2352 {
2353         return 400000;
2354 }
2355
2356 static int i915_get_display_clock_speed(struct drm_device *dev)
2357 {
2358         return 333000;
2359 }
2360
2361 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2362 {
2363         return 200000;
2364 }
2365
2366 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2367 {
2368         u16 gcfgc = 0;
2369
2370         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2371
2372         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2373                 return 133000;
2374         else {
2375                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2376                 case GC_DISPLAY_CLOCK_333_MHZ:
2377                         return 333000;
2378                 default:
2379                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2380                         return 190000;
2381                 }
2382         }
2383 }
2384
2385 static int i865_get_display_clock_speed(struct drm_device *dev)
2386 {
2387         return 266000;
2388 }
2389
2390 static int i855_get_display_clock_speed(struct drm_device *dev)
2391 {
2392         u16 hpllcc = 0;
2393         /* Assume that the hardware is in the high speed state.  This
2394          * should be the default.
2395          */
2396         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2397         case GC_CLOCK_133_200:
2398         case GC_CLOCK_100_200:
2399                 return 200000;
2400         case GC_CLOCK_166_250:
2401                 return 250000;
2402         case GC_CLOCK_100_133:
2403                 return 133000;
2404         }
2405
2406         /* Shouldn't happen */
2407         return 0;
2408 }
2409
2410 static int i830_get_display_clock_speed(struct drm_device *dev)
2411 {
2412         return 133000;
2413 }
2414
2415 /**
2416  * Return the pipe currently connected to the panel fitter,
2417  * or -1 if the panel fitter is not present or not in use
2418  */
2419 int intel_panel_fitter_pipe (struct drm_device *dev)
2420 {
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         u32  pfit_control;
2423
2424         /* i830 doesn't have a panel fitter */
2425         if (IS_I830(dev))
2426                 return -1;
2427
2428         pfit_control = I915_READ(PFIT_CONTROL);
2429
2430         /* See if the panel fitter is in use */
2431         if ((pfit_control & PFIT_ENABLE) == 0)
2432                 return -1;
2433
2434         /* 965 can place panel fitter on either pipe */
2435         if (IS_I965G(dev))
2436                 return (pfit_control >> 29) & 0x3;
2437
2438         /* older chips can only use pipe 1 */
2439         return 1;
2440 }
2441
2442 struct fdi_m_n {
2443         u32        tu;
2444         u32        gmch_m;
2445         u32        gmch_n;
2446         u32        link_m;
2447         u32        link_n;
2448 };
2449
2450 static void
2451 fdi_reduce_ratio(u32 *num, u32 *den)
2452 {
2453         while (*num > 0xffffff || *den > 0xffffff) {
2454                 *num >>= 1;
2455                 *den >>= 1;
2456         }
2457 }
2458
2459 #define DATA_N 0x800000
2460 #define LINK_N 0x80000
2461
2462 static void
2463 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2464                      int link_clock, struct fdi_m_n *m_n)
2465 {
2466         u64 temp;
2467
2468         m_n->tu = 64; /* default size */
2469
2470         temp = (u64) DATA_N * pixel_clock;
2471         temp = div_u64(temp, link_clock);
2472         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2473         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2474         m_n->gmch_n = DATA_N;
2475         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2476
2477         temp = (u64) LINK_N * pixel_clock;
2478         m_n->link_m = div_u64(temp, link_clock);
2479         m_n->link_n = LINK_N;
2480         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2481 }
2482
2483
2484 struct intel_watermark_params {
2485         unsigned long fifo_size;
2486         unsigned long max_wm;
2487         unsigned long default_wm;
2488         unsigned long guard_size;
2489         unsigned long cacheline_size;
2490 };
2491
2492 /* Pineview has different values for various configs */
2493 static struct intel_watermark_params pineview_display_wm = {
2494         PINEVIEW_DISPLAY_FIFO,
2495         PINEVIEW_MAX_WM,
2496         PINEVIEW_DFT_WM,
2497         PINEVIEW_GUARD_WM,
2498         PINEVIEW_FIFO_LINE_SIZE
2499 };
2500 static struct intel_watermark_params pineview_display_hplloff_wm = {
2501         PINEVIEW_DISPLAY_FIFO,
2502         PINEVIEW_MAX_WM,
2503         PINEVIEW_DFT_HPLLOFF_WM,
2504         PINEVIEW_GUARD_WM,
2505         PINEVIEW_FIFO_LINE_SIZE
2506 };
2507 static struct intel_watermark_params pineview_cursor_wm = {
2508         PINEVIEW_CURSOR_FIFO,
2509         PINEVIEW_CURSOR_MAX_WM,
2510         PINEVIEW_CURSOR_DFT_WM,
2511         PINEVIEW_CURSOR_GUARD_WM,
2512         PINEVIEW_FIFO_LINE_SIZE,
2513 };
2514 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2515         PINEVIEW_CURSOR_FIFO,
2516         PINEVIEW_CURSOR_MAX_WM,
2517         PINEVIEW_CURSOR_DFT_WM,
2518         PINEVIEW_CURSOR_GUARD_WM,
2519         PINEVIEW_FIFO_LINE_SIZE
2520 };
2521 static struct intel_watermark_params g4x_wm_info = {
2522         G4X_FIFO_SIZE,
2523         G4X_MAX_WM,
2524         G4X_MAX_WM,
2525         2,
2526         G4X_FIFO_LINE_SIZE,
2527 };
2528 static struct intel_watermark_params i945_wm_info = {
2529         I945_FIFO_SIZE,
2530         I915_MAX_WM,
2531         1,
2532         2,
2533         I915_FIFO_LINE_SIZE
2534 };
2535 static struct intel_watermark_params i915_wm_info = {
2536         I915_FIFO_SIZE,
2537         I915_MAX_WM,
2538         1,
2539         2,
2540         I915_FIFO_LINE_SIZE
2541 };
2542 static struct intel_watermark_params i855_wm_info = {
2543         I855GM_FIFO_SIZE,
2544         I915_MAX_WM,
2545         1,
2546         2,
2547         I830_FIFO_LINE_SIZE
2548 };
2549 static struct intel_watermark_params i830_wm_info = {
2550         I830_FIFO_SIZE,
2551         I915_MAX_WM,
2552         1,
2553         2,
2554         I830_FIFO_LINE_SIZE
2555 };
2556
2557 static struct intel_watermark_params ironlake_display_wm_info = {
2558         ILK_DISPLAY_FIFO,
2559         ILK_DISPLAY_MAXWM,
2560         ILK_DISPLAY_DFTWM,
2561         2,
2562         ILK_FIFO_LINE_SIZE
2563 };
2564
2565 static struct intel_watermark_params ironlake_display_srwm_info = {
2566         ILK_DISPLAY_SR_FIFO,
2567         ILK_DISPLAY_MAX_SRWM,
2568         ILK_DISPLAY_DFT_SRWM,
2569         2,
2570         ILK_FIFO_LINE_SIZE
2571 };
2572
2573 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2574         ILK_CURSOR_SR_FIFO,
2575         ILK_CURSOR_MAX_SRWM,
2576         ILK_CURSOR_DFT_SRWM,
2577         2,
2578         ILK_FIFO_LINE_SIZE
2579 };
2580
2581 /**
2582  * intel_calculate_wm - calculate watermark level
2583  * @clock_in_khz: pixel clock
2584  * @wm: chip FIFO params
2585  * @pixel_size: display pixel size
2586  * @latency_ns: memory latency for the platform
2587  *
2588  * Calculate the watermark level (the level at which the display plane will
2589  * start fetching from memory again).  Each chip has a different display
2590  * FIFO size and allocation, so the caller needs to figure that out and pass
2591  * in the correct intel_watermark_params structure.
2592  *
2593  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2594  * on the pixel size.  When it reaches the watermark level, it'll start
2595  * fetching FIFO line sized based chunks from memory until the FIFO fills
2596  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2597  * will occur, and a display engine hang could result.
2598  */
2599 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2600                                         struct intel_watermark_params *wm,
2601                                         int pixel_size,
2602                                         unsigned long latency_ns)
2603 {
2604         long entries_required, wm_size;
2605
2606         /*
2607          * Note: we need to make sure we don't overflow for various clock &
2608          * latency values.
2609          * clocks go from a few thousand to several hundred thousand.
2610          * latency is usually a few thousand
2611          */
2612         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2613                 1000;
2614         entries_required /= wm->cacheline_size;
2615
2616         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2617
2618         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2619
2620         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2621
2622         /* Don't promote wm_size to unsigned... */
2623         if (wm_size > (long)wm->max_wm)
2624                 wm_size = wm->max_wm;
2625         if (wm_size <= 0)
2626                 wm_size = wm->default_wm;
2627         return wm_size;
2628 }
2629
2630 struct cxsr_latency {
2631         int is_desktop;
2632         unsigned long fsb_freq;
2633         unsigned long mem_freq;
2634         unsigned long display_sr;
2635         unsigned long display_hpll_disable;
2636         unsigned long cursor_sr;
2637         unsigned long cursor_hpll_disable;
2638 };
2639
2640 static struct cxsr_latency cxsr_latency_table[] = {
2641         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2642         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2643         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2644
2645         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2646         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2647         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2648
2649         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2650         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2651         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2652
2653         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2654         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2655         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2656
2657         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2658         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2659         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2660
2661         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2662         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2663         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2664 };
2665
2666 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2667                                                    int mem)
2668 {
2669         int i;
2670         struct cxsr_latency *latency;
2671
2672         if (fsb == 0 || mem == 0)
2673                 return NULL;
2674
2675         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2676                 latency = &cxsr_latency_table[i];
2677                 if (is_desktop == latency->is_desktop &&
2678                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2679                         return latency;
2680         }
2681
2682         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2683
2684         return NULL;
2685 }
2686
2687 static void pineview_disable_cxsr(struct drm_device *dev)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         u32 reg;
2691
2692         /* deactivate cxsr */
2693         reg = I915_READ(DSPFW3);
2694         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2695         I915_WRITE(DSPFW3, reg);
2696         DRM_INFO("Big FIFO is disabled\n");
2697 }
2698
2699 /*
2700  * Latency for FIFO fetches is dependent on several factors:
2701  *   - memory configuration (speed, channels)
2702  *   - chipset
2703  *   - current MCH state
2704  * It can be fairly high in some situations, so here we assume a fairly
2705  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2706  * set this value too high, the FIFO will fetch frequently to stay full)
2707  * and power consumption (set it too low to save power and we might see
2708  * FIFO underruns and display "flicker").
2709  *
2710  * A value of 5us seems to be a good balance; safe for very low end
2711  * platforms but not overly aggressive on lower latency configs.
2712  */
2713 static const int latency_ns = 5000;
2714
2715 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2716 {
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         uint32_t dsparb = I915_READ(DSPARB);
2719         int size;
2720
2721         if (plane == 0)
2722                 size = dsparb & 0x7f;
2723         else
2724                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2725                         (dsparb & 0x7f);
2726
2727         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2728                         plane ? "B" : "A", size);
2729
2730         return size;
2731 }
2732
2733 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2734 {
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         uint32_t dsparb = I915_READ(DSPARB);
2737         int size;
2738
2739         if (plane == 0)
2740                 size = dsparb & 0x1ff;
2741         else
2742                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2743                         (dsparb & 0x1ff);
2744         size >>= 1; /* Convert to cachelines */
2745
2746         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2747                         plane ? "B" : "A", size);
2748
2749         return size;
2750 }
2751
2752 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         uint32_t dsparb = I915_READ(DSPARB);
2756         int size;
2757
2758         size = dsparb & 0x7f;
2759         size >>= 2; /* Convert to cachelines */
2760
2761         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2762                         plane ? "B" : "A",
2763                   size);
2764
2765         return size;
2766 }
2767
2768 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         uint32_t dsparb = I915_READ(DSPARB);
2772         int size;
2773
2774         size = dsparb & 0x7f;
2775         size >>= 1; /* Convert to cachelines */
2776
2777         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2778                         plane ? "B" : "A", size);
2779
2780         return size;
2781 }
2782
2783 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2784                           int planeb_clock, int sr_hdisplay, int pixel_size)
2785 {
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         u32 reg;
2788         unsigned long wm;
2789         struct cxsr_latency *latency;
2790         int sr_clock;
2791
2792         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2793                                          dev_priv->mem_freq);
2794         if (!latency) {
2795                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2796                 pineview_disable_cxsr(dev);
2797                 return;
2798         }
2799
2800         if (!planea_clock || !planeb_clock) {
2801                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2802
2803                 /* Display SR */
2804                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2805                                         pixel_size, latency->display_sr);
2806                 reg = I915_READ(DSPFW1);
2807                 reg &= ~DSPFW_SR_MASK;
2808                 reg |= wm << DSPFW_SR_SHIFT;
2809                 I915_WRITE(DSPFW1, reg);
2810                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2811
2812                 /* cursor SR */
2813                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2814                                         pixel_size, latency->cursor_sr);
2815                 reg = I915_READ(DSPFW3);
2816                 reg &= ~DSPFW_CURSOR_SR_MASK;
2817                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2818                 I915_WRITE(DSPFW3, reg);
2819
2820                 /* Display HPLL off SR */
2821                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2822                                         pixel_size, latency->display_hpll_disable);
2823                 reg = I915_READ(DSPFW3);
2824                 reg &= ~DSPFW_HPLL_SR_MASK;
2825                 reg |= wm & DSPFW_HPLL_SR_MASK;
2826                 I915_WRITE(DSPFW3, reg);
2827
2828                 /* cursor HPLL off SR */
2829                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2830                                         pixel_size, latency->cursor_hpll_disable);
2831                 reg = I915_READ(DSPFW3);
2832                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2833                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2834                 I915_WRITE(DSPFW3, reg);
2835                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2836
2837                 /* activate cxsr */
2838                 reg = I915_READ(DSPFW3);
2839                 reg |= PINEVIEW_SELF_REFRESH_EN;
2840                 I915_WRITE(DSPFW3, reg);
2841                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2842         } else {
2843                 pineview_disable_cxsr(dev);
2844                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2845         }
2846 }
2847
2848 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2849                           int planeb_clock, int sr_hdisplay, int pixel_size)
2850 {
2851         struct drm_i915_private *dev_priv = dev->dev_private;
2852         int total_size, cacheline_size;
2853         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2854         struct intel_watermark_params planea_params, planeb_params;
2855         unsigned long line_time_us;
2856         int sr_clock, sr_entries = 0, entries_required;
2857
2858         /* Create copies of the base settings for each pipe */
2859         planea_params = planeb_params = g4x_wm_info;
2860
2861         /* Grab a couple of global values before we overwrite them */
2862         total_size = planea_params.fifo_size;
2863         cacheline_size = planea_params.cacheline_size;
2864
2865         /*
2866          * Note: we need to make sure we don't overflow for various clock &
2867          * latency values.
2868          * clocks go from a few thousand to several hundred thousand.
2869          * latency is usually a few thousand
2870          */
2871         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2872                 1000;
2873         entries_required /= G4X_FIFO_LINE_SIZE;
2874         planea_wm = entries_required + planea_params.guard_size;
2875
2876         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2877                 1000;
2878         entries_required /= G4X_FIFO_LINE_SIZE;
2879         planeb_wm = entries_required + planeb_params.guard_size;
2880
2881         cursora_wm = cursorb_wm = 16;
2882         cursor_sr = 32;
2883
2884         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2885
2886         /* Calc sr entries for one plane configs */
2887         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2888                 /* self-refresh has much higher latency */
2889                 static const int sr_latency_ns = 12000;
2890
2891                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2892                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2893
2894                 /* Use ns/us then divide to preserve precision */
2895                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2896                               pixel_size * sr_hdisplay) / 1000;
2897                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2898                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2899                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2900         } else {
2901                 /* Turn off self refresh if both pipes are enabled */
2902                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2903                                         & ~FW_BLC_SELF_EN);
2904         }
2905
2906         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2907                   planea_wm, planeb_wm, sr_entries);
2908
2909         planea_wm &= 0x3f;
2910         planeb_wm &= 0x3f;
2911
2912         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2913                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2914                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2915         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2916                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2917         /* HPLL off in SR has some issues on G4x... disable it */
2918         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2919                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2920 }
2921
2922 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2923                            int planeb_clock, int sr_hdisplay, int pixel_size)
2924 {
2925         struct drm_i915_private *dev_priv = dev->dev_private;
2926         unsigned long line_time_us;
2927         int sr_clock, sr_entries, srwm = 1;
2928
2929         /* Calc sr entries for one plane configs */
2930         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2931                 /* self-refresh has much higher latency */
2932                 static const int sr_latency_ns = 12000;
2933
2934                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2935                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2936
2937                 /* Use ns/us then divide to preserve precision */
2938                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2939                               pixel_size * sr_hdisplay) / 1000;
2940                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2941                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2942                 srwm = I945_FIFO_SIZE - sr_entries;
2943                 if (srwm < 0)
2944                         srwm = 1;
2945                 srwm &= 0x3f;
2946                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2947         } else {
2948                 /* Turn off self refresh if both pipes are enabled */
2949                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2950                                         & ~FW_BLC_SELF_EN);
2951         }
2952
2953         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2954                       srwm);
2955
2956         /* 965 has limitations... */
2957         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2958                    (8 << 0));
2959         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2960 }
2961
2962 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2963                            int planeb_clock, int sr_hdisplay, int pixel_size)
2964 {
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         uint32_t fwater_lo;
2967         uint32_t fwater_hi;
2968         int total_size, cacheline_size, cwm, srwm = 1;
2969         int planea_wm, planeb_wm;
2970         struct intel_watermark_params planea_params, planeb_params;
2971         unsigned long line_time_us;
2972         int sr_clock, sr_entries = 0;
2973
2974         /* Create copies of the base settings for each pipe */
2975         if (IS_I965GM(dev) || IS_I945GM(dev))
2976                 planea_params = planeb_params = i945_wm_info;
2977         else if (IS_I9XX(dev))
2978                 planea_params = planeb_params = i915_wm_info;
2979         else
2980                 planea_params = planeb_params = i855_wm_info;
2981
2982         /* Grab a couple of global values before we overwrite them */
2983         total_size = planea_params.fifo_size;
2984         cacheline_size = planea_params.cacheline_size;
2985
2986         /* Update per-plane FIFO sizes */
2987         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2988         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2989
2990         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2991                                        pixel_size, latency_ns);
2992         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2993                                        pixel_size, latency_ns);
2994         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2995
2996         /*
2997          * Overlay gets an aggressive default since video jitter is bad.
2998          */
2999         cwm = 2;
3000
3001         /* Calc sr entries for one plane configs */
3002         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3003             (!planea_clock || !planeb_clock)) {
3004                 /* self-refresh has much higher latency */
3005                 static const int sr_latency_ns = 6000;
3006
3007                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3008                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3009
3010                 /* Use ns/us then divide to preserve precision */
3011                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3012                               pixel_size * sr_hdisplay) / 1000;
3013                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3014                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3015                 srwm = total_size - sr_entries;
3016                 if (srwm < 0)
3017                         srwm = 1;
3018
3019                 if (IS_I945G(dev) || IS_I945GM(dev))
3020                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3021                 else if (IS_I915GM(dev)) {
3022                         /* 915M has a smaller SRWM field */
3023                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3024                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3025                 }
3026         } else {
3027                 /* Turn off self refresh if both pipes are enabled */
3028                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3029                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3030                                    & ~FW_BLC_SELF_EN);
3031                 } else if (IS_I915GM(dev)) {
3032                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3033                 }
3034         }
3035
3036         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3037                   planea_wm, planeb_wm, cwm, srwm);
3038
3039         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3040         fwater_hi = (cwm & 0x1f);
3041
3042         /* Set request length to 8 cachelines per fetch */
3043         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3044         fwater_hi = fwater_hi | (1 << 8);
3045
3046         I915_WRITE(FW_BLC, fwater_lo);
3047         I915_WRITE(FW_BLC2, fwater_hi);
3048 }
3049
3050 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3051                            int unused2, int pixel_size)
3052 {
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3055         int planea_wm;
3056
3057         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3058
3059         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3060                                        pixel_size, latency_ns);
3061         fwater_lo |= (3<<8) | planea_wm;
3062
3063         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3064
3065         I915_WRITE(FW_BLC, fwater_lo);
3066 }
3067
3068 #define ILK_LP0_PLANE_LATENCY           700
3069
3070 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3071                        int planeb_clock, int sr_hdisplay, int pixel_size)
3072 {
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3075         int sr_wm, cursor_wm;
3076         unsigned long line_time_us;
3077         int sr_clock, entries_required;
3078         u32 reg_value;
3079
3080         /* Calculate and update the watermark for plane A */
3081         if (planea_clock) {
3082                 entries_required = ((planea_clock