26792af7e1a15591559c40837b1778a5d9051689
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41  * Interrupts that are always left unmasked.
42  *
43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44  * we leave them always unmasked in IMR and then control enabling them through
45  * PIPESTAT alone.
46  */
47 #define I915_INTERRUPT_ENABLE_FIX                       \
48         (I915_ASLE_INTERRUPT |                          \
49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59                                  PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
65                                          DRM_I915_VBLANK_PIPE_B)
66
67 void
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69 {
70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71                 dev_priv->gt_irq_mask_reg &= ~mask;
72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73                 (void) I915_READ(GTIMR);
74         }
75 }
76
77 static inline void
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79 {
80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81                 dev_priv->gt_irq_mask_reg |= mask;
82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83                 (void) I915_READ(GTIMR);
84         }
85 }
86
87 /* For display hotplug interrupt */
88 void
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90 {
91         if ((dev_priv->irq_mask_reg & mask) != 0) {
92                 dev_priv->irq_mask_reg &= ~mask;
93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94                 (void) I915_READ(DEIMR);
95         }
96 }
97
98 static inline void
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100 {
101         if ((dev_priv->irq_mask_reg & mask) != mask) {
102                 dev_priv->irq_mask_reg |= mask;
103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104                 (void) I915_READ(DEIMR);
105         }
106 }
107
108 void
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110 {
111         if ((dev_priv->irq_mask_reg & mask) != 0) {
112                 dev_priv->irq_mask_reg &= ~mask;
113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114                 (void) I915_READ(IMR);
115         }
116 }
117
118 static inline void
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120 {
121         if ((dev_priv->irq_mask_reg & mask) != mask) {
122                 dev_priv->irq_mask_reg |= mask;
123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124                 (void) I915_READ(IMR);
125         }
126 }
127
128 static inline u32
129 i915_pipestat(int pipe)
130 {
131         if (pipe == 0)
132                 return PIPEASTAT;
133         if (pipe == 1)
134                 return PIPEBSTAT;
135         BUG();
136 }
137
138 void
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140 {
141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
142                 u32 reg = i915_pipestat(pipe);
143
144                 dev_priv->pipestat[pipe] |= mask;
145                 /* Enable the interrupt, clear any pending status */
146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147                 (void) I915_READ(reg);
148         }
149 }
150
151 void
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153 {
154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
155                 u32 reg = i915_pipestat(pipe);
156
157                 dev_priv->pipestat[pipe] &= ~mask;
158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159                 (void) I915_READ(reg);
160         }
161 }
162
163 /**
164  * intel_enable_asle - enable ASLE interrupt for OpRegion
165  */
166 void intel_enable_asle (struct drm_device *dev)
167 {
168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
170         if (HAS_PCH_SPLIT(dev))
171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
172         else {
173                 i915_enable_pipestat(dev_priv, 1,
174                                      I915_LEGACY_BLC_EVENT_ENABLE);
175                 if (IS_I965G(dev))
176                         i915_enable_pipestat(dev_priv, 0,
177                                              I915_LEGACY_BLC_EVENT_ENABLE);
178         }
179 }
180
181 /**
182  * i915_pipe_enabled - check if a pipe is enabled
183  * @dev: DRM device
184  * @pipe: pipe to check
185  *
186  * Reading certain registers when the pipe is disabled can hang the chip.
187  * Use this routine to make sure the PLL is running and the pipe is active
188  * before reading such registers if unsure.
189  */
190 static int
191 i915_pipe_enabled(struct drm_device *dev, int pipe)
192 {
193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
195
196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
197                 return 1;
198
199         return 0;
200 }
201
202 /* Called from drm generic code, passed a 'crtc', which
203  * we use as a pipe index
204  */
205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
206 {
207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208         unsigned long high_frame;
209         unsigned long low_frame;
210         u32 high1, high2, low, count;
211
212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
214
215         if (!i915_pipe_enabled(dev, pipe)) {
216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
217                                 "pipe %d\n", pipe);
218                 return 0;
219         }
220
221         /*
222          * High & low register fields aren't synchronized, so make sure
223          * we get a low value that's stable across two reads of the high
224          * register.
225          */
226         do {
227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228                          PIPE_FRAME_HIGH_SHIFT);
229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
230                         PIPE_FRAME_LOW_SHIFT);
231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
232                          PIPE_FRAME_HIGH_SHIFT);
233         } while (high1 != high2);
234
235         count = (high1 << 8) | low;
236
237         return count;
238 }
239
240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
241 {
242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
244
245         if (!i915_pipe_enabled(dev, pipe)) {
246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
247                                         "pipe %d\n", pipe);
248                 return 0;
249         }
250
251         return I915_READ(reg);
252 }
253
254 /*
255  * Handle hotplug events outside the interrupt handler proper.
256  */
257 static void i915_hotplug_work_func(struct work_struct *work)
258 {
259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
260                                                     hotplug_work);
261         struct drm_device *dev = dev_priv->dev;
262         struct drm_mode_config *mode_config = &dev->mode_config;
263         struct drm_encoder *encoder;
264
265         if (mode_config->num_encoder) {
266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
268         
269                         if (intel_encoder->hot_plug)
270                                 (*intel_encoder->hot_plug) (intel_encoder);
271                 }
272         }
273         /* Just fire off a uevent and let userspace tell us what to do */
274         drm_helper_hpd_irq_event(dev);
275 }
276
277 static void i915_handle_rps_change(struct drm_device *dev)
278 {
279         drm_i915_private_t *dev_priv = dev->dev_private;
280         u32 busy_up, busy_down, max_avg, min_avg;
281         u16 rgvswctl;
282         u8 new_delay = dev_priv->cur_delay;
283
284         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
285         busy_up = I915_READ(RCPREVBSYTUPAVG);
286         busy_down = I915_READ(RCPREVBSYTDNAVG);
287         max_avg = I915_READ(RCBMAXAVG);
288         min_avg = I915_READ(RCBMINAVG);
289
290         /* Handle RCS change request from hw */
291         if (busy_up > max_avg) {
292                 if (dev_priv->cur_delay != dev_priv->max_delay)
293                         new_delay = dev_priv->cur_delay - 1;
294                 if (new_delay < dev_priv->max_delay)
295                         new_delay = dev_priv->max_delay;
296         } else if (busy_down < min_avg) {
297                 if (dev_priv->cur_delay != dev_priv->min_delay)
298                         new_delay = dev_priv->cur_delay + 1;
299                 if (new_delay > dev_priv->min_delay)
300                         new_delay = dev_priv->min_delay;
301         }
302
303         DRM_DEBUG("rps change requested: %d -> %d\n",
304                   dev_priv->cur_delay, new_delay);
305
306         rgvswctl = I915_READ(MEMSWCTL);
307         if (rgvswctl & MEMCTL_CMD_STS) {
308                 DRM_ERROR("gpu busy, RCS change rejected\n");
309                 return; /* still busy with another command */
310         }
311
312         /* Program the new state */
313         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
314                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
315         I915_WRITE(MEMSWCTL, rgvswctl);
316         POSTING_READ(MEMSWCTL);
317
318         rgvswctl |= MEMCTL_CMD_STS;
319         I915_WRITE(MEMSWCTL, rgvswctl);
320
321         dev_priv->cur_delay = new_delay;
322
323         DRM_DEBUG("rps changed\n");
324
325         return;
326 }
327
328 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
329 {
330         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
331         int ret = IRQ_NONE;
332         u32 de_iir, gt_iir, de_ier, pch_iir;
333         struct drm_i915_master_private *master_priv;
334
335         /* disable master interrupt before clearing iir  */
336         de_ier = I915_READ(DEIER);
337         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
338         (void)I915_READ(DEIER);
339
340         de_iir = I915_READ(DEIIR);
341         gt_iir = I915_READ(GTIIR);
342         pch_iir = I915_READ(SDEIIR);
343
344         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
345                 goto done;
346
347         ret = IRQ_HANDLED;
348
349         if (dev->primary->master) {
350                 master_priv = dev->primary->master->driver_priv;
351                 if (master_priv->sarea_priv)
352                         master_priv->sarea_priv->last_dispatch =
353                                 READ_BREADCRUMB(dev_priv);
354         }
355
356         if (gt_iir & GT_PIPE_NOTIFY) {
357                 u32 seqno = i915_get_gem_seqno(dev);
358                 dev_priv->mm.irq_gem_seqno = seqno;
359                 trace_i915_gem_request_complete(dev, seqno);
360                 DRM_WAKEUP(&dev_priv->irq_queue);
361                 dev_priv->hangcheck_count = 0;
362                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
363         }
364
365         if (de_iir & DE_GSE)
366                 ironlake_opregion_gse_intr(dev);
367
368         if (de_iir & DE_PLANEA_FLIP_DONE) {
369                 intel_prepare_page_flip(dev, 0);
370                 intel_finish_page_flip(dev, 0);
371         }
372
373         if (de_iir & DE_PLANEB_FLIP_DONE) {
374                 intel_prepare_page_flip(dev, 1);
375                 intel_finish_page_flip(dev, 1);
376         }
377
378         if (de_iir & DE_PIPEA_VBLANK)
379                 drm_handle_vblank(dev, 0);
380
381         if (de_iir & DE_PIPEB_VBLANK)
382                 drm_handle_vblank(dev, 1);
383
384         /* check event from PCH */
385         if ((de_iir & DE_PCH_EVENT) &&
386             (pch_iir & SDE_HOTPLUG_MASK)) {
387                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
388         }
389
390         if (de_iir & DE_PCU_EVENT) {
391                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
392                 i915_handle_rps_change(dev);
393         }
394
395         /* should clear PCH hotplug event before clear CPU irq */
396         I915_WRITE(SDEIIR, pch_iir);
397         I915_WRITE(GTIIR, gt_iir);
398         I915_WRITE(DEIIR, de_iir);
399
400 done:
401         I915_WRITE(DEIER, de_ier);
402         (void)I915_READ(DEIER);
403
404         return ret;
405 }
406
407 /**
408  * i915_error_work_func - do process context error handling work
409  * @work: work struct
410  *
411  * Fire an error uevent so userspace can see that a hang or error
412  * was detected.
413  */
414 static void i915_error_work_func(struct work_struct *work)
415 {
416         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
417                                                     error_work);
418         struct drm_device *dev = dev_priv->dev;
419         char *error_event[] = { "ERROR=1", NULL };
420         char *reset_event[] = { "RESET=1", NULL };
421         char *reset_done_event[] = { "ERROR=0", NULL };
422
423         DRM_DEBUG_DRIVER("generating error event\n");
424         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
425
426         if (atomic_read(&dev_priv->mm.wedged)) {
427                 if (IS_I965G(dev)) {
428                         DRM_DEBUG_DRIVER("resetting chip\n");
429                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
430                         if (!i965_reset(dev, GDRST_RENDER)) {
431                                 atomic_set(&dev_priv->mm.wedged, 0);
432                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
433                         }
434                 } else {
435                         DRM_DEBUG_DRIVER("reboot required\n");
436                 }
437         }
438 }
439
440 static struct drm_i915_error_object *
441 i915_error_object_create(struct drm_device *dev,
442                          struct drm_gem_object *src)
443 {
444         struct drm_i915_error_object *dst;
445         struct drm_i915_gem_object *src_priv;
446         int page, page_count;
447
448         if (src == NULL)
449                 return NULL;
450
451         src_priv = to_intel_bo(src);
452         if (src_priv->pages == NULL)
453                 return NULL;
454
455         page_count = src->size / PAGE_SIZE;
456
457         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
458         if (dst == NULL)
459                 return NULL;
460
461         for (page = 0; page < page_count; page++) {
462                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
463                 if (d == NULL)
464                         goto unwind;
465                 s = kmap_atomic(src_priv->pages[page], KM_USER0);
466                 memcpy(d, s, PAGE_SIZE);
467                 kunmap_atomic(s, KM_USER0);
468                 dst->pages[page] = d;
469         }
470         dst->page_count = page_count;
471         dst->gtt_offset = src_priv->gtt_offset;
472
473         return dst;
474
475 unwind:
476         while (page--)
477                 kfree(dst->pages[page]);
478         kfree(dst);
479         return NULL;
480 }
481
482 static void
483 i915_error_object_free(struct drm_i915_error_object *obj)
484 {
485         int page;
486
487         if (obj == NULL)
488                 return;
489
490         for (page = 0; page < obj->page_count; page++)
491                 kfree(obj->pages[page]);
492
493         kfree(obj);
494 }
495
496 static void
497 i915_error_state_free(struct drm_device *dev,
498                       struct drm_i915_error_state *error)
499 {
500         i915_error_object_free(error->batchbuffer[0]);
501         i915_error_object_free(error->batchbuffer[1]);
502         i915_error_object_free(error->ringbuffer);
503         kfree(error->active_bo);
504         kfree(error);
505 }
506
507 static u32
508 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
509 {
510         u32 cmd;
511
512         if (IS_I830(dev) || IS_845G(dev))
513                 cmd = MI_BATCH_BUFFER;
514         else if (IS_I965G(dev))
515                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
516                        MI_BATCH_NON_SECURE_I965);
517         else
518                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
519
520         return ring[0] == cmd ? ring[1] : 0;
521 }
522
523 static u32
524 i915_ringbuffer_last_batch(struct drm_device *dev)
525 {
526         struct drm_i915_private *dev_priv = dev->dev_private;
527         u32 head, bbaddr;
528         u32 *ring;
529
530         /* Locate the current position in the ringbuffer and walk back
531          * to find the most recently dispatched batch buffer.
532          */
533         bbaddr = 0;
534         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
535         ring = (u32 *)(dev_priv->ring.virtual_start + head);
536
537         while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
538                 bbaddr = i915_get_bbaddr(dev, ring);
539                 if (bbaddr)
540                         break;
541         }
542
543         if (bbaddr == 0) {
544                 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
545                 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
546                         bbaddr = i915_get_bbaddr(dev, ring);
547                         if (bbaddr)
548                                 break;
549                 }
550         }
551
552         return bbaddr;
553 }
554
555 /**
556  * i915_capture_error_state - capture an error record for later analysis
557  * @dev: drm device
558  *
559  * Should be called when an error is detected (either a hang or an error
560  * interrupt) to capture error state from the time of the error.  Fills
561  * out a structure which becomes available in debugfs for user level tools
562  * to pick up.
563  */
564 static void i915_capture_error_state(struct drm_device *dev)
565 {
566         struct drm_i915_private *dev_priv = dev->dev_private;
567         struct drm_i915_gem_object *obj_priv;
568         struct drm_i915_error_state *error;
569         struct drm_gem_object *batchbuffer[2];
570         unsigned long flags;
571         u32 bbaddr;
572         int count;
573
574         spin_lock_irqsave(&dev_priv->error_lock, flags);
575         error = dev_priv->first_error;
576         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
577         if (error)
578                 return;
579
580         error = kmalloc(sizeof(*error), GFP_ATOMIC);
581         if (!error) {
582                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
583                 return;
584         }
585
586         error->seqno = i915_get_gem_seqno(dev);
587         error->eir = I915_READ(EIR);
588         error->pgtbl_er = I915_READ(PGTBL_ER);
589         error->pipeastat = I915_READ(PIPEASTAT);
590         error->pipebstat = I915_READ(PIPEBSTAT);
591         error->instpm = I915_READ(INSTPM);
592         if (!IS_I965G(dev)) {
593                 error->ipeir = I915_READ(IPEIR);
594                 error->ipehr = I915_READ(IPEHR);
595                 error->instdone = I915_READ(INSTDONE);
596                 error->acthd = I915_READ(ACTHD);
597                 error->bbaddr = 0;
598         } else {
599                 error->ipeir = I915_READ(IPEIR_I965);
600                 error->ipehr = I915_READ(IPEHR_I965);
601                 error->instdone = I915_READ(INSTDONE_I965);
602                 error->instps = I915_READ(INSTPS);
603                 error->instdone1 = I915_READ(INSTDONE1);
604                 error->acthd = I915_READ(ACTHD_I965);
605                 error->bbaddr = I915_READ64(BB_ADDR);
606         }
607
608         bbaddr = i915_ringbuffer_last_batch(dev);
609
610         /* Grab the current batchbuffer, most likely to have crashed. */
611         batchbuffer[0] = NULL;
612         batchbuffer[1] = NULL;
613         count = 0;
614         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
615                 struct drm_gem_object *obj = &obj_priv->base;
616
617                 if (batchbuffer[0] == NULL &&
618                     bbaddr >= obj_priv->gtt_offset &&
619                     bbaddr < obj_priv->gtt_offset + obj->size)
620                         batchbuffer[0] = obj;
621
622                 if (batchbuffer[1] == NULL &&
623                     error->acthd >= obj_priv->gtt_offset &&
624                     error->acthd < obj_priv->gtt_offset + obj->size &&
625                     batchbuffer[0] != obj)
626                         batchbuffer[1] = obj;
627
628                 count++;
629         }
630
631         /* We need to copy these to an anonymous buffer as the simplest
632          * method to avoid being overwritten by userpace.
633          */
634         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
635         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
636
637         /* Record the ringbuffer */
638         error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
639
640         /* Record buffers on the active list. */
641         error->active_bo = NULL;
642         error->active_bo_count = 0;
643
644         if (count)
645                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
646                                            GFP_ATOMIC);
647
648         if (error->active_bo) {
649                 int i = 0;
650                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
651                         struct drm_gem_object *obj = &obj_priv->base;
652
653                         error->active_bo[i].size = obj->size;
654                         error->active_bo[i].name = obj->name;
655                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
656                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
657                         error->active_bo[i].read_domains = obj->read_domains;
658                         error->active_bo[i].write_domain = obj->write_domain;
659                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
660                         error->active_bo[i].pinned = 0;
661                         if (obj_priv->pin_count > 0)
662                                 error->active_bo[i].pinned = 1;
663                         if (obj_priv->user_pin_count > 0)
664                                 error->active_bo[i].pinned = -1;
665                         error->active_bo[i].tiling = obj_priv->tiling_mode;
666                         error->active_bo[i].dirty = obj_priv->dirty;
667                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
668
669                         if (++i == count)
670                                 break;
671                 }
672                 error->active_bo_count = i;
673         }
674
675         do_gettimeofday(&error->time);
676
677         spin_lock_irqsave(&dev_priv->error_lock, flags);
678         if (dev_priv->first_error == NULL) {
679                 dev_priv->first_error = error;
680                 error = NULL;
681         }
682         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
683
684         if (error)
685                 i915_error_state_free(dev, error);
686 }
687
688 void i915_destroy_error_state(struct drm_device *dev)
689 {
690         struct drm_i915_private *dev_priv = dev->dev_private;
691         struct drm_i915_error_state *error;
692
693         spin_lock(&dev_priv->error_lock);
694         error = dev_priv->first_error;
695         dev_priv->first_error = NULL;
696         spin_unlock(&dev_priv->error_lock);
697
698         if (error)
699                 i915_error_state_free(dev, error);
700 }
701
702 /**
703  * i915_handle_error - handle an error interrupt
704  * @dev: drm device
705  *
706  * Do some basic checking of regsiter state at error interrupt time and
707  * dump it to the syslog.  Also call i915_capture_error_state() to make
708  * sure we get a record and make it available in debugfs.  Fire a uevent
709  * so userspace knows something bad happened (should trigger collection
710  * of a ring dump etc.).
711  */
712 static void i915_handle_error(struct drm_device *dev, bool wedged)
713 {
714         struct drm_i915_private *dev_priv = dev->dev_private;
715         u32 eir = I915_READ(EIR);
716         u32 pipea_stats = I915_READ(PIPEASTAT);
717         u32 pipeb_stats = I915_READ(PIPEBSTAT);
718
719         i915_capture_error_state(dev);
720
721         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
722                eir);
723
724         if (IS_G4X(dev)) {
725                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
726                         u32 ipeir = I915_READ(IPEIR_I965);
727
728                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
729                                I915_READ(IPEIR_I965));
730                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
731                                I915_READ(IPEHR_I965));
732                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
733                                I915_READ(INSTDONE_I965));
734                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
735                                I915_READ(INSTPS));
736                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
737                                I915_READ(INSTDONE1));
738                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
739                                I915_READ(ACTHD_I965));
740                         I915_WRITE(IPEIR_I965, ipeir);
741                         (void)I915_READ(IPEIR_I965);
742                 }
743                 if (eir & GM45_ERROR_PAGE_TABLE) {
744                         u32 pgtbl_err = I915_READ(PGTBL_ER);
745                         printk(KERN_ERR "page table error\n");
746                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
747                                pgtbl_err);
748                         I915_WRITE(PGTBL_ER, pgtbl_err);
749                         (void)I915_READ(PGTBL_ER);
750                 }
751         }
752
753         if (IS_I9XX(dev)) {
754                 if (eir & I915_ERROR_PAGE_TABLE) {
755                         u32 pgtbl_err = I915_READ(PGTBL_ER);
756                         printk(KERN_ERR "page table error\n");
757                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
758                                pgtbl_err);
759                         I915_WRITE(PGTBL_ER, pgtbl_err);
760                         (void)I915_READ(PGTBL_ER);
761                 }
762         }
763
764         if (eir & I915_ERROR_MEMORY_REFRESH) {
765                 printk(KERN_ERR "memory refresh error\n");
766                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
767                        pipea_stats);
768                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
769                        pipeb_stats);
770                 /* pipestat has already been acked */
771         }
772         if (eir & I915_ERROR_INSTRUCTION) {
773                 printk(KERN_ERR "instruction error\n");
774                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
775                        I915_READ(INSTPM));
776                 if (!IS_I965G(dev)) {
777                         u32 ipeir = I915_READ(IPEIR);
778
779                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
780                                I915_READ(IPEIR));
781                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
782                                I915_READ(IPEHR));
783                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
784                                I915_READ(INSTDONE));
785                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
786                                I915_READ(ACTHD));
787                         I915_WRITE(IPEIR, ipeir);
788                         (void)I915_READ(IPEIR);
789                 } else {
790                         u32 ipeir = I915_READ(IPEIR_I965);
791
792                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
793                                I915_READ(IPEIR_I965));
794                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
795                                I915_READ(IPEHR_I965));
796                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
797                                I915_READ(INSTDONE_I965));
798                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
799                                I915_READ(INSTPS));
800                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
801                                I915_READ(INSTDONE1));
802                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
803                                I915_READ(ACTHD_I965));
804                         I915_WRITE(IPEIR_I965, ipeir);
805                         (void)I915_READ(IPEIR_I965);
806                 }
807         }
808
809         I915_WRITE(EIR, eir);
810         (void)I915_READ(EIR);
811         eir = I915_READ(EIR);
812         if (eir) {
813                 /*
814                  * some errors might have become stuck,
815                  * mask them.
816                  */
817                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
818                 I915_WRITE(EMR, I915_READ(EMR) | eir);
819                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
820         }
821
822         if (wedged) {
823                 atomic_set(&dev_priv->mm.wedged, 1);
824
825                 /*
826                  * Wakeup waiting processes so they don't hang
827                  */
828                 DRM_WAKEUP(&dev_priv->irq_queue);
829         }
830
831         queue_work(dev_priv->wq, &dev_priv->error_work);
832 }
833
834 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
835 {
836         struct drm_device *dev = (struct drm_device *) arg;
837         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
838         struct drm_i915_master_private *master_priv;
839         u32 iir, new_iir;
840         u32 pipea_stats, pipeb_stats;
841         u32 vblank_status;
842         u32 vblank_enable;
843         int vblank = 0;
844         unsigned long irqflags;
845         int irq_received;
846         int ret = IRQ_NONE;
847
848         atomic_inc(&dev_priv->irq_received);
849
850         if (HAS_PCH_SPLIT(dev))
851                 return ironlake_irq_handler(dev);
852
853         iir = I915_READ(IIR);
854
855         if (IS_I965G(dev)) {
856                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
857                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
858         } else {
859                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
860                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
861         }
862
863         for (;;) {
864                 irq_received = iir != 0;
865
866                 /* Can't rely on pipestat interrupt bit in iir as it might
867                  * have been cleared after the pipestat interrupt was received.
868                  * It doesn't set the bit in iir again, but it still produces
869                  * interrupts (for non-MSI).
870                  */
871                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
872                 pipea_stats = I915_READ(PIPEASTAT);
873                 pipeb_stats = I915_READ(PIPEBSTAT);
874
875                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
876                         i915_handle_error(dev, false);
877
878                 /*
879                  * Clear the PIPE(A|B)STAT regs before the IIR
880                  */
881                 if (pipea_stats & 0x8000ffff) {
882                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
883                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
884                         I915_WRITE(PIPEASTAT, pipea_stats);
885                         irq_received = 1;
886                 }
887
888                 if (pipeb_stats & 0x8000ffff) {
889                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
890                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
891                         I915_WRITE(PIPEBSTAT, pipeb_stats);
892                         irq_received = 1;
893                 }
894                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
895
896                 if (!irq_received)
897                         break;
898
899                 ret = IRQ_HANDLED;
900
901                 /* Consume port.  Then clear IIR or we'll miss events */
902                 if ((I915_HAS_HOTPLUG(dev)) &&
903                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
904                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
905
906                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
907                                   hotplug_status);
908                         if (hotplug_status & dev_priv->hotplug_supported_mask)
909                                 queue_work(dev_priv->wq,
910                                            &dev_priv->hotplug_work);
911
912                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
913                         I915_READ(PORT_HOTPLUG_STAT);
914                 }
915
916                 I915_WRITE(IIR, iir);
917                 new_iir = I915_READ(IIR); /* Flush posted writes */
918
919                 if (dev->primary->master) {
920                         master_priv = dev->primary->master->driver_priv;
921                         if (master_priv->sarea_priv)
922                                 master_priv->sarea_priv->last_dispatch =
923                                         READ_BREADCRUMB(dev_priv);
924                 }
925
926                 if (iir & I915_USER_INTERRUPT) {
927                         u32 seqno = i915_get_gem_seqno(dev);
928                         dev_priv->mm.irq_gem_seqno = seqno;
929                         trace_i915_gem_request_complete(dev, seqno);
930                         DRM_WAKEUP(&dev_priv->irq_queue);
931                         dev_priv->hangcheck_count = 0;
932                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
933                 }
934
935                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
936                         intel_prepare_page_flip(dev, 0);
937
938                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
939                         intel_prepare_page_flip(dev, 1);
940
941                 if (pipea_stats & vblank_status) {
942                         vblank++;
943                         drm_handle_vblank(dev, 0);
944                         intel_finish_page_flip(dev, 0);
945                 }
946
947                 if (pipeb_stats & vblank_status) {
948                         vblank++;
949                         drm_handle_vblank(dev, 1);
950                         intel_finish_page_flip(dev, 1);
951                 }
952
953                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
954                     (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
955                     (iir & I915_ASLE_INTERRUPT))
956                         opregion_asle_intr(dev);
957
958                 /* With MSI, interrupts are only generated when iir
959                  * transitions from zero to nonzero.  If another bit got
960                  * set while we were handling the existing iir bits, then
961                  * we would never get another interrupt.
962                  *
963                  * This is fine on non-MSI as well, as if we hit this path
964                  * we avoid exiting the interrupt handler only to generate
965                  * another one.
966                  *
967                  * Note that for MSI this could cause a stray interrupt report
968                  * if an interrupt landed in the time between writing IIR and
969                  * the posting read.  This should be rare enough to never
970                  * trigger the 99% of 100,000 interrupts test for disabling
971                  * stray interrupts.
972                  */
973                 iir = new_iir;
974         }
975
976         return ret;
977 }
978
979 static int i915_emit_irq(struct drm_device * dev)
980 {
981         drm_i915_private_t *dev_priv = dev->dev_private;
982         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
983         RING_LOCALS;
984
985         i915_kernel_lost_context(dev);
986
987         DRM_DEBUG_DRIVER("\n");
988
989         dev_priv->counter++;
990         if (dev_priv->counter > 0x7FFFFFFFUL)
991                 dev_priv->counter = 1;
992         if (master_priv->sarea_priv)
993                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
994
995         BEGIN_LP_RING(4);
996         OUT_RING(MI_STORE_DWORD_INDEX);
997         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
998         OUT_RING(dev_priv->counter);
999         OUT_RING(MI_USER_INTERRUPT);
1000         ADVANCE_LP_RING();
1001
1002         return dev_priv->counter;
1003 }
1004
1005 void i915_user_irq_get(struct drm_device *dev)
1006 {
1007         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1008         unsigned long irqflags;
1009
1010         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1011         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
1012                 if (HAS_PCH_SPLIT(dev))
1013                         ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1014                 else
1015                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1016         }
1017         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1018 }
1019
1020 void i915_user_irq_put(struct drm_device *dev)
1021 {
1022         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1023         unsigned long irqflags;
1024
1025         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1026         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
1027         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
1028                 if (HAS_PCH_SPLIT(dev))
1029                         ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1030                 else
1031                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1032         }
1033         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1034 }
1035
1036 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1037 {
1038         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1039
1040         if (dev_priv->trace_irq_seqno == 0)
1041                 i915_user_irq_get(dev);
1042
1043         dev_priv->trace_irq_seqno = seqno;
1044 }
1045
1046 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1047 {
1048         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1049         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1050         int ret = 0;
1051
1052         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1053                   READ_BREADCRUMB(dev_priv));
1054
1055         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1056                 if (master_priv->sarea_priv)
1057                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1058                 return 0;
1059         }
1060
1061         if (master_priv->sarea_priv)
1062                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1063
1064         i915_user_irq_get(dev);
1065         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1066                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1067         i915_user_irq_put(dev);
1068
1069         if (ret == -EBUSY) {
1070                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1071                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1072         }
1073
1074         return ret;
1075 }
1076
1077 /* Needs the lock as it touches the ring.
1078  */
1079 int i915_irq_emit(struct drm_device *dev, void *data,
1080                          struct drm_file *file_priv)
1081 {
1082         drm_i915_private_t *dev_priv = dev->dev_private;
1083         drm_i915_irq_emit_t *emit = data;
1084         int result;
1085
1086         if (!dev_priv || !dev_priv->ring.virtual_start) {
1087                 DRM_ERROR("called with no initialization\n");
1088                 return -EINVAL;
1089         }
1090
1091         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1092
1093         mutex_lock(&dev->struct_mutex);
1094         result = i915_emit_irq(dev);
1095         mutex_unlock(&dev->struct_mutex);
1096
1097         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1098                 DRM_ERROR("copy_to_user\n");
1099                 return -EFAULT;
1100         }
1101
1102         return 0;
1103 }
1104
1105 /* Doesn't need the hardware lock.
1106  */
1107 int i915_irq_wait(struct drm_device *dev, void *data,
1108                          struct drm_file *file_priv)
1109 {
1110         drm_i915_private_t *dev_priv = dev->dev_private;
1111         drm_i915_irq_wait_t *irqwait = data;
1112
1113         if (!dev_priv) {
1114                 DRM_ERROR("called with no initialization\n");
1115                 return -EINVAL;
1116         }
1117
1118         return i915_wait_irq(dev, irqwait->irq_seq);
1119 }
1120
1121 /* Called from drm generic code, passed 'crtc' which
1122  * we use as a pipe index
1123  */
1124 int i915_enable_vblank(struct drm_device *dev, int pipe)
1125 {
1126         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1127         unsigned long irqflags;
1128         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1129         u32 pipeconf;
1130
1131         pipeconf = I915_READ(pipeconf_reg);
1132         if (!(pipeconf & PIPEACONF_ENABLE))
1133                 return -EINVAL;
1134
1135         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1136         if (HAS_PCH_SPLIT(dev))
1137                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 
1138                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1139         else if (IS_I965G(dev))
1140                 i915_enable_pipestat(dev_priv, pipe,
1141                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1142         else
1143                 i915_enable_pipestat(dev_priv, pipe,
1144                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1145         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1146         return 0;
1147 }
1148
1149 /* Called from drm generic code, passed 'crtc' which
1150  * we use as a pipe index
1151  */
1152 void i915_disable_vblank(struct drm_device *dev, int pipe)
1153 {
1154         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1155         unsigned long irqflags;
1156
1157         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1158         if (HAS_PCH_SPLIT(dev))
1159                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 
1160                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1161         else
1162                 i915_disable_pipestat(dev_priv, pipe,
1163                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1164                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1165         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1166 }
1167
1168 void i915_enable_interrupt (struct drm_device *dev)
1169 {
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171
1172         if (!HAS_PCH_SPLIT(dev))
1173                 opregion_enable_asle(dev);
1174         dev_priv->irq_enabled = 1;
1175 }
1176
1177
1178 /* Set the vblank monitor pipe
1179  */
1180 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1181                          struct drm_file *file_priv)
1182 {
1183         drm_i915_private_t *dev_priv = dev->dev_private;
1184
1185         if (!dev_priv) {
1186                 DRM_ERROR("called with no initialization\n");
1187                 return -EINVAL;
1188         }
1189
1190         return 0;
1191 }
1192
1193 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1194                          struct drm_file *file_priv)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         drm_i915_vblank_pipe_t *pipe = data;
1198
1199         if (!dev_priv) {
1200                 DRM_ERROR("called with no initialization\n");
1201                 return -EINVAL;
1202         }
1203
1204         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1205
1206         return 0;
1207 }
1208
1209 /**
1210  * Schedule buffer swap at given vertical blank.
1211  */
1212 int i915_vblank_swap(struct drm_device *dev, void *data,
1213                      struct drm_file *file_priv)
1214 {
1215         /* The delayed swap mechanism was fundamentally racy, and has been
1216          * removed.  The model was that the client requested a delayed flip/swap
1217          * from the kernel, then waited for vblank before continuing to perform
1218          * rendering.  The problem was that the kernel might wake the client
1219          * up before it dispatched the vblank swap (since the lock has to be
1220          * held while touching the ringbuffer), in which case the client would
1221          * clear and start the next frame before the swap occurred, and
1222          * flicker would occur in addition to likely missing the vblank.
1223          *
1224          * In the absence of this ioctl, userland falls back to a correct path
1225          * of waiting for a vblank, then dispatching the swap on its own.
1226          * Context switching to userland and back is plenty fast enough for
1227          * meeting the requirements of vblank swapping.
1228          */
1229         return -EINVAL;
1230 }
1231
1232 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1233         drm_i915_private_t *dev_priv = dev->dev_private;
1234         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1235 }
1236
1237 /**
1238  * This is called when the chip hasn't reported back with completed
1239  * batchbuffers in a long time. The first time this is called we simply record
1240  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1241  * again, we assume the chip is wedged and try to fix it.
1242  */
1243 void i915_hangcheck_elapsed(unsigned long data)
1244 {
1245         struct drm_device *dev = (struct drm_device *)data;
1246         drm_i915_private_t *dev_priv = dev->dev_private;
1247         uint32_t acthd;
1248
1249         /* No reset support on this chip yet. */
1250         if (IS_GEN6(dev))
1251                 return;
1252
1253         if (!IS_I965G(dev))
1254                 acthd = I915_READ(ACTHD);
1255         else
1256                 acthd = I915_READ(ACTHD_I965);
1257
1258         /* If all work is done then ACTHD clearly hasn't advanced. */
1259         if (list_empty(&dev_priv->mm.request_list) ||
1260                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1261                 dev_priv->hangcheck_count = 0;
1262                 return;
1263         }
1264
1265         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1266                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1267                 i915_handle_error(dev, true);
1268                 return;
1269         } 
1270
1271         /* Reset timer case chip hangs without another request being added */
1272         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1273
1274         if (acthd != dev_priv->last_acthd)
1275                 dev_priv->hangcheck_count = 0;
1276         else
1277                 dev_priv->hangcheck_count++;
1278
1279         dev_priv->last_acthd = acthd;
1280 }
1281
1282 /* drm_dma.h hooks
1283 */
1284 static void ironlake_irq_preinstall(struct drm_device *dev)
1285 {
1286         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1287
1288         I915_WRITE(HWSTAM, 0xeffe);
1289
1290         /* XXX hotplug from PCH */
1291
1292         I915_WRITE(DEIMR, 0xffffffff);
1293         I915_WRITE(DEIER, 0x0);
1294         (void) I915_READ(DEIER);
1295
1296         /* and GT */
1297         I915_WRITE(GTIMR, 0xffffffff);
1298         I915_WRITE(GTIER, 0x0);
1299         (void) I915_READ(GTIER);
1300
1301         /* south display irq */
1302         I915_WRITE(SDEIMR, 0xffffffff);
1303         I915_WRITE(SDEIER, 0x0);
1304         (void) I915_READ(SDEIER);
1305 }
1306
1307 static int ironlake_irq_postinstall(struct drm_device *dev)
1308 {
1309         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1310         /* enable kind of interrupts always enabled */
1311         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1312                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1313         u32 render_mask = GT_PIPE_NOTIFY;
1314         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1315                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1316
1317         dev_priv->irq_mask_reg = ~display_mask;
1318         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1319
1320         /* should always can generate irq */
1321         I915_WRITE(DEIIR, I915_READ(DEIIR));
1322         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1323         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1324         (void) I915_READ(DEIER);
1325
1326         /* user interrupt should be enabled, but masked initial */
1327         dev_priv->gt_irq_mask_reg = 0xffffffff;
1328         dev_priv->gt_irq_enable_reg = render_mask;
1329
1330         I915_WRITE(GTIIR, I915_READ(GTIIR));
1331         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1332         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1333         (void) I915_READ(GTIER);
1334
1335         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1336         dev_priv->pch_irq_enable_reg = hotplug_mask;
1337
1338         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1339         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1340         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1341         (void) I915_READ(SDEIER);
1342
1343         if (IS_IRONLAKE_M(dev)) {
1344                 /* Clear & enable PCU event interrupts */
1345                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1346                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1347                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1348         }
1349
1350         return 0;
1351 }
1352
1353 void i915_driver_irq_preinstall(struct drm_device * dev)
1354 {
1355         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1356
1357         atomic_set(&dev_priv->irq_received, 0);
1358
1359         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1360         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1361
1362         if (HAS_PCH_SPLIT(dev)) {
1363                 ironlake_irq_preinstall(dev);
1364                 return;
1365         }
1366
1367         if (I915_HAS_HOTPLUG(dev)) {
1368                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1369                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1370         }
1371
1372         I915_WRITE(HWSTAM, 0xeffe);
1373         I915_WRITE(PIPEASTAT, 0);
1374         I915_WRITE(PIPEBSTAT, 0);
1375         I915_WRITE(IMR, 0xffffffff);
1376         I915_WRITE(IER, 0x0);
1377         (void) I915_READ(IER);
1378 }
1379
1380 /*
1381  * Must be called after intel_modeset_init or hotplug interrupts won't be
1382  * enabled correctly.
1383  */
1384 int i915_driver_irq_postinstall(struct drm_device *dev)
1385 {
1386         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1387         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1388         u32 error_mask;
1389
1390         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1391
1392         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1393
1394         if (HAS_PCH_SPLIT(dev))
1395                 return ironlake_irq_postinstall(dev);
1396
1397         /* Unmask the interrupts that we always want on. */
1398         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1399
1400         dev_priv->pipestat[0] = 0;
1401         dev_priv->pipestat[1] = 0;
1402
1403         if (I915_HAS_HOTPLUG(dev)) {
1404                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1405
1406                 /* Note HDMI and DP share bits */
1407                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1408                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1409                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1410                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1411                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1412                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1413                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1414                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1415                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1416                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1417                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1418                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1419                 /* Ignore TV since it's buggy */
1420
1421                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1422
1423                 /* Enable in IER... */
1424                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1425                 /* and unmask in IMR */
1426                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1427         }
1428
1429         /*
1430          * Enable some error detection, note the instruction error mask
1431          * bit is reserved, so we leave it masked.
1432          */
1433         if (IS_G4X(dev)) {
1434                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1435                                GM45_ERROR_MEM_PRIV |
1436                                GM45_ERROR_CP_PRIV |
1437                                I915_ERROR_MEMORY_REFRESH);
1438         } else {
1439                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1440                                I915_ERROR_MEMORY_REFRESH);
1441         }
1442         I915_WRITE(EMR, error_mask);
1443
1444         /* Disable pipe interrupt enables, clear pending pipe status */
1445         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1446         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1447         /* Clear pending interrupt status */
1448         I915_WRITE(IIR, I915_READ(IIR));
1449
1450         I915_WRITE(IER, enable_mask);
1451         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1452         (void) I915_READ(IER);
1453
1454         opregion_enable_asle(dev);
1455
1456         return 0;
1457 }
1458
1459 static void ironlake_irq_uninstall(struct drm_device *dev)
1460 {
1461         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1462         I915_WRITE(HWSTAM, 0xffffffff);
1463
1464         I915_WRITE(DEIMR, 0xffffffff);
1465         I915_WRITE(DEIER, 0x0);
1466         I915_WRITE(DEIIR, I915_READ(DEIIR));
1467
1468         I915_WRITE(GTIMR, 0xffffffff);
1469         I915_WRITE(GTIER, 0x0);
1470         I915_WRITE(GTIIR, I915_READ(GTIIR));
1471 }
1472
1473 void i915_driver_irq_uninstall(struct drm_device * dev)
1474 {
1475         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1476
1477         if (!dev_priv)
1478                 return;
1479
1480         dev_priv->vblank_pipe = 0;
1481
1482         if (HAS_PCH_SPLIT(dev)) {
1483                 ironlake_irq_uninstall(dev);
1484                 return;
1485         }
1486
1487         if (I915_HAS_HOTPLUG(dev)) {
1488                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1489                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1490         }
1491
1492         I915_WRITE(HWSTAM, 0xffffffff);
1493         I915_WRITE(PIPEASTAT, 0);
1494         I915_WRITE(PIPEBSTAT, 0);
1495         I915_WRITE(IMR, 0xffffffff);
1496         I915_WRITE(IER, 0x0);
1497
1498         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1499         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1500         I915_WRITE(IIR, I915_READ(IIR));
1501 }