drm: add 32/64 support for MGA/R128/i915
[linux-2.6.git] / drivers / char / drm / r128_drv.h
1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2  * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
3  *
4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6  * All rights reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Rickard E. (Rik) Faith <faith@valinux.com>
29  *    Kevin E. Martin <martin@valinux.com>
30  *    Gareth Hughes <gareth@valinux.com>
31  *    Michel D�zer <daenzerm@student.ethz.ch>
32  */
33
34 #ifndef __R128_DRV_H__
35 #define __R128_DRV_H__
36
37 /* General customization:
38  */
39 #define DRIVER_AUTHOR           "Gareth Hughes, VA Linux Systems Inc."
40
41 #define DRIVER_NAME             "r128"
42 #define DRIVER_DESC             "ATI Rage 128"
43 #define DRIVER_DATE             "20030725"
44
45 /* Interface history:
46  *
47  * ??  - ??
48  * 2.4 - Add support for ycbcr textures (no new ioctls)
49  * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
50  */
51 #define DRIVER_MAJOR            2
52 #define DRIVER_MINOR            5
53 #define DRIVER_PATCHLEVEL       0
54
55
56 #define GET_RING_HEAD(dev_priv)         R128_READ( R128_PM4_BUFFER_DL_RPTR )
57
58 typedef struct drm_r128_freelist {
59         unsigned int age;
60         drm_buf_t *buf;
61         struct drm_r128_freelist *next;
62         struct drm_r128_freelist *prev;
63 } drm_r128_freelist_t;
64
65 typedef struct drm_r128_ring_buffer {
66         u32 *start;
67         u32 *end;
68         int size;
69         int size_l2qw;
70
71         u32 tail;
72         u32 tail_mask;
73         int space;
74
75         int high_mark;
76 } drm_r128_ring_buffer_t;
77
78 typedef struct drm_r128_private {
79         drm_r128_ring_buffer_t ring;
80         drm_r128_sarea_t *sarea_priv;
81
82         int cce_mode;
83         int cce_fifo_size;
84         int cce_running;
85
86         drm_r128_freelist_t *head;
87         drm_r128_freelist_t *tail;
88
89         int usec_timeout;
90         int is_pci;
91         unsigned long phys_pci_gart;
92         dma_addr_t bus_pci_gart;
93         unsigned long cce_buffers_offset;
94
95         atomic_t idle_count;
96
97         int page_flipping;
98         int current_page;
99         u32 crtc_offset;
100         u32 crtc_offset_cntl;
101
102         u32 color_fmt;
103         unsigned int front_offset;
104         unsigned int front_pitch;
105         unsigned int back_offset;
106         unsigned int back_pitch;
107
108         u32 depth_fmt;
109         unsigned int depth_offset;
110         unsigned int depth_pitch;
111         unsigned int span_offset;
112
113         u32 front_pitch_offset_c;
114         u32 back_pitch_offset_c;
115         u32 depth_pitch_offset_c;
116         u32 span_pitch_offset_c;
117
118         drm_local_map_t *sarea;
119         drm_local_map_t *mmio;
120         drm_local_map_t *cce_ring;
121         drm_local_map_t *ring_rptr;
122         drm_local_map_t *agp_textures;
123 } drm_r128_private_t;
124
125 typedef struct drm_r128_buf_priv {
126         u32 age;
127         int prim;
128         int discard;
129         int dispatched;
130         drm_r128_freelist_t *list_entry;
131 } drm_r128_buf_priv_t;
132
133                                 /* r128_cce.c */
134 extern int r128_cce_init( DRM_IOCTL_ARGS );
135 extern int r128_cce_start( DRM_IOCTL_ARGS );
136 extern int r128_cce_stop( DRM_IOCTL_ARGS );
137 extern int r128_cce_reset( DRM_IOCTL_ARGS );
138 extern int r128_cce_idle( DRM_IOCTL_ARGS );
139 extern int r128_engine_reset( DRM_IOCTL_ARGS );
140 extern int r128_fullscreen( DRM_IOCTL_ARGS );
141 extern int r128_cce_buffers( DRM_IOCTL_ARGS );
142
143 extern void r128_freelist_reset( drm_device_t *dev );
144
145 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
146
147 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
148 extern int r128_do_cleanup_cce( drm_device_t *dev );
149
150 extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
151
152 extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS );
153 extern void r128_driver_irq_preinstall( drm_device_t *dev );
154 extern void r128_driver_irq_postinstall( drm_device_t *dev );
155 extern void r128_driver_irq_uninstall( drm_device_t *dev );
156 extern void r128_driver_pretakedown(drm_device_t *dev);
157 extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
158
159 extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
160                               unsigned long arg);
161
162 /* Register definitions, register access macros and drmAddMap constants
163  * for Rage 128 kernel driver.
164  */
165
166 #define R128_AUX_SC_CNTL                0x1660
167 #       define R128_AUX1_SC_EN                  (1 << 0)
168 #       define R128_AUX1_SC_MODE_OR             (0 << 1)
169 #       define R128_AUX1_SC_MODE_NAND           (1 << 1)
170 #       define R128_AUX2_SC_EN                  (1 << 2)
171 #       define R128_AUX2_SC_MODE_OR             (0 << 3)
172 #       define R128_AUX2_SC_MODE_NAND           (1 << 3)
173 #       define R128_AUX3_SC_EN                  (1 << 4)
174 #       define R128_AUX3_SC_MODE_OR             (0 << 5)
175 #       define R128_AUX3_SC_MODE_NAND           (1 << 5)
176 #define R128_AUX1_SC_LEFT               0x1664
177 #define R128_AUX1_SC_RIGHT              0x1668
178 #define R128_AUX1_SC_TOP                0x166c
179 #define R128_AUX1_SC_BOTTOM             0x1670
180 #define R128_AUX2_SC_LEFT               0x1674
181 #define R128_AUX2_SC_RIGHT              0x1678
182 #define R128_AUX2_SC_TOP                0x167c
183 #define R128_AUX2_SC_BOTTOM             0x1680
184 #define R128_AUX3_SC_LEFT               0x1684
185 #define R128_AUX3_SC_RIGHT              0x1688
186 #define R128_AUX3_SC_TOP                0x168c
187 #define R128_AUX3_SC_BOTTOM             0x1690
188
189 #define R128_BRUSH_DATA0                0x1480
190 #define R128_BUS_CNTL                   0x0030
191 #       define R128_BUS_MASTER_DIS              (1 << 6)
192
193 #define R128_CLOCK_CNTL_INDEX           0x0008
194 #define R128_CLOCK_CNTL_DATA            0x000c
195 #       define R128_PLL_WR_EN                   (1 << 7)
196 #define R128_CONSTANT_COLOR_C           0x1d34
197 #define R128_CRTC_OFFSET                0x0224
198 #define R128_CRTC_OFFSET_CNTL           0x0228
199 #       define R128_CRTC_OFFSET_FLIP_CNTL       (1 << 16)
200
201 #define R128_DP_GUI_MASTER_CNTL         0x146c
202 #       define R128_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
203 #       define R128_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)
204 #       define R128_GMC_BRUSH_SOLID_COLOR       (13   <<  4)
205 #       define R128_GMC_BRUSH_NONE              (15   <<  4)
206 #       define R128_GMC_DST_16BPP               (4    <<  8)
207 #       define R128_GMC_DST_24BPP               (5    <<  8)
208 #       define R128_GMC_DST_32BPP               (6    <<  8)
209 #       define R128_GMC_DST_DATATYPE_SHIFT      8
210 #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
211 #       define R128_DP_SRC_SOURCE_MEMORY        (2    << 24)
212 #       define R128_DP_SRC_SOURCE_HOST_DATA     (3    << 24)
213 #       define R128_GMC_CLR_CMP_CNTL_DIS        (1    << 28)
214 #       define R128_GMC_AUX_CLIP_DIS            (1    << 29)
215 #       define R128_GMC_WR_MSK_DIS              (1    << 30)
216 #       define R128_ROP3_S                      0x00cc0000
217 #       define R128_ROP3_P                      0x00f00000
218 #define R128_DP_WRITE_MASK              0x16cc
219 #define R128_DST_PITCH_OFFSET_C         0x1c80
220 #       define R128_DST_TILE                    (1 << 31)
221
222 #define R128_GEN_INT_CNTL               0x0040
223 #       define R128_CRTC_VBLANK_INT_EN          (1 <<  0)
224 #define R128_GEN_INT_STATUS             0x0044
225 #       define R128_CRTC_VBLANK_INT             (1 <<  0)
226 #       define R128_CRTC_VBLANK_INT_AK          (1 <<  0)
227 #define R128_GEN_RESET_CNTL             0x00f0
228 #       define R128_SOFT_RESET_GUI              (1 <<  0)
229
230 #define R128_GUI_SCRATCH_REG0           0x15e0
231 #define R128_GUI_SCRATCH_REG1           0x15e4
232 #define R128_GUI_SCRATCH_REG2           0x15e8
233 #define R128_GUI_SCRATCH_REG3           0x15ec
234 #define R128_GUI_SCRATCH_REG4           0x15f0
235 #define R128_GUI_SCRATCH_REG5           0x15f4
236
237 #define R128_GUI_STAT                   0x1740
238 #       define R128_GUI_FIFOCNT_MASK            0x0fff
239 #       define R128_GUI_ACTIVE                  (1 << 31)
240
241 #define R128_MCLK_CNTL                  0x000f
242 #       define R128_FORCE_GCP                   (1 << 16)
243 #       define R128_FORCE_PIPE3D_CP             (1 << 17)
244 #       define R128_FORCE_RCP                   (1 << 18)
245
246 #define R128_PC_GUI_CTLSTAT             0x1748
247 #define R128_PC_NGUI_CTLSTAT            0x0184
248 #       define R128_PC_FLUSH_GUI                (3 << 0)
249 #       define R128_PC_RI_GUI                   (1 << 2)
250 #       define R128_PC_FLUSH_ALL                0x00ff
251 #       define R128_PC_BUSY                     (1 << 31)
252
253 #define R128_PCI_GART_PAGE              0x017c
254 #define R128_PRIM_TEX_CNTL_C            0x1cb0
255
256 #define R128_SCALE_3D_CNTL              0x1a00
257 #define R128_SEC_TEX_CNTL_C             0x1d00
258 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
259 #define R128_SETUP_CNTL                 0x1bc4
260 #define R128_STEN_REF_MASK_C            0x1d40
261
262 #define R128_TEX_CNTL_C                 0x1c9c
263 #       define R128_TEX_CACHE_FLUSH             (1 << 23)
264
265 #define R128_WAIT_UNTIL                 0x1720
266 #       define R128_EVENT_CRTC_OFFSET           (1 << 0)
267 #define R128_WINDOW_XY_OFFSET           0x1bcc
268
269
270 /* CCE registers
271  */
272 #define R128_PM4_BUFFER_OFFSET          0x0700
273 #define R128_PM4_BUFFER_CNTL            0x0704
274 #       define R128_PM4_MASK                    (15 << 28)
275 #       define R128_PM4_NONPM4                  (0  << 28)
276 #       define R128_PM4_192PIO                  (1  << 28)
277 #       define R128_PM4_192BM                   (2  << 28)
278 #       define R128_PM4_128PIO_64INDBM          (3  << 28)
279 #       define R128_PM4_128BM_64INDBM           (4  << 28)
280 #       define R128_PM4_64PIO_128INDBM          (5  << 28)
281 #       define R128_PM4_64BM_128INDBM           (6  << 28)
282 #       define R128_PM4_64PIO_64VCBM_64INDBM    (7  << 28)
283 #       define R128_PM4_64BM_64VCBM_64INDBM     (8  << 28)
284 #       define R128_PM4_64PIO_64VCPIO_64INDPIO  (15 << 28)
285 #       define R128_PM4_BUFFER_CNTL_NOUPDATE    (1  << 27)
286
287 #define R128_PM4_BUFFER_WM_CNTL         0x0708
288 #       define R128_WMA_SHIFT                   0
289 #       define R128_WMB_SHIFT                   8
290 #       define R128_WMC_SHIFT                   16
291 #       define R128_WB_WM_SHIFT                 24
292
293 #define R128_PM4_BUFFER_DL_RPTR_ADDR    0x070c
294 #define R128_PM4_BUFFER_DL_RPTR         0x0710
295 #define R128_PM4_BUFFER_DL_WPTR         0x0714
296 #       define R128_PM4_BUFFER_DL_DONE          (1 << 31)
297
298 #define R128_PM4_VC_FPU_SETUP           0x071c
299
300 #define R128_PM4_IW_INDOFF              0x0738
301 #define R128_PM4_IW_INDSIZE             0x073c
302
303 #define R128_PM4_STAT                   0x07b8
304 #       define R128_PM4_FIFOCNT_MASK            0x0fff
305 #       define R128_PM4_BUSY                    (1 << 16)
306 #       define R128_PM4_GUI_ACTIVE              (1 << 31)
307
308 #define R128_PM4_MICROCODE_ADDR         0x07d4
309 #define R128_PM4_MICROCODE_RADDR        0x07d8
310 #define R128_PM4_MICROCODE_DATAH        0x07dc
311 #define R128_PM4_MICROCODE_DATAL        0x07e0
312
313 #define R128_PM4_BUFFER_ADDR            0x07f0
314 #define R128_PM4_MICRO_CNTL             0x07fc
315 #       define R128_PM4_MICRO_FREERUN           (1 << 30)
316
317 #define R128_PM4_FIFO_DATA_EVEN         0x1000
318 #define R128_PM4_FIFO_DATA_ODD          0x1004
319
320
321 /* CCE command packets
322  */
323 #define R128_CCE_PACKET0                0x00000000
324 #define R128_CCE_PACKET1                0x40000000
325 #define R128_CCE_PACKET2                0x80000000
326 #define R128_CCE_PACKET3                0xC0000000
327 #       define R128_CNTL_HOSTDATA_BLT           0x00009400
328 #       define R128_CNTL_PAINT_MULTI            0x00009A00
329 #       define R128_CNTL_BITBLT_MULTI           0x00009B00
330 #       define R128_3D_RNDR_GEN_INDX_PRIM       0x00002300
331
332 #define R128_CCE_PACKET_MASK            0xC0000000
333 #define R128_CCE_PACKET_COUNT_MASK      0x3fff0000
334 #define R128_CCE_PACKET0_REG_MASK       0x000007ff
335 #define R128_CCE_PACKET1_REG0_MASK      0x000007ff
336 #define R128_CCE_PACKET1_REG1_MASK      0x003ff800
337
338 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE         0x00000000
339 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT        0x00000001
340 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE         0x00000002
341 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE    0x00000003
342 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST     0x00000004
343 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN      0x00000005
344 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP    0x00000006
345 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2    0x00000007
346 #define R128_CCE_VC_CNTL_PRIM_WALK_IND          0x00000010
347 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST         0x00000020
348 #define R128_CCE_VC_CNTL_PRIM_WALK_RING         0x00000030
349 #define R128_CCE_VC_CNTL_NUM_SHIFT              16
350
351 #define R128_DATATYPE_VQ                0
352 #define R128_DATATYPE_CI4               1
353 #define R128_DATATYPE_CI8               2
354 #define R128_DATATYPE_ARGB1555          3
355 #define R128_DATATYPE_RGB565            4
356 #define R128_DATATYPE_RGB888            5
357 #define R128_DATATYPE_ARGB8888          6
358 #define R128_DATATYPE_RGB332            7
359 #define R128_DATATYPE_Y8                8
360 #define R128_DATATYPE_RGB8              9
361 #define R128_DATATYPE_CI16              10
362 #define R128_DATATYPE_YVYU422           11
363 #define R128_DATATYPE_VYUY422           12
364 #define R128_DATATYPE_AYUV444           14
365 #define R128_DATATYPE_ARGB4444          15
366
367 /* Constants */
368 #define R128_AGP_OFFSET                 0x02000000
369
370 #define R128_WATERMARK_L                16
371 #define R128_WATERMARK_M                8
372 #define R128_WATERMARK_N                8
373 #define R128_WATERMARK_K                128
374
375 #define R128_MAX_USEC_TIMEOUT           100000  /* 100 ms */
376
377 #define R128_LAST_FRAME_REG             R128_GUI_SCRATCH_REG0
378 #define R128_LAST_DISPATCH_REG          R128_GUI_SCRATCH_REG1
379 #define R128_MAX_VB_AGE                 0x7fffffff
380 #define R128_MAX_VB_VERTS               (0xffff)
381
382 #define R128_RING_HIGH_MARK             128
383
384 #define R128_PERFORMANCE_BOXES          0
385
386 #define R128_READ(reg)          DRM_READ32(  dev_priv->mmio, (reg) )
387 #define R128_WRITE(reg,val)     DRM_WRITE32( dev_priv->mmio, (reg), (val) )
388 #define R128_READ8(reg)         DRM_READ8(   dev_priv->mmio, (reg) )
389 #define R128_WRITE8(reg,val)    DRM_WRITE8(  dev_priv->mmio, (reg), (val) )
390
391 #define R128_WRITE_PLL(addr,val)                                        \
392 do {                                                                    \
393         R128_WRITE8(R128_CLOCK_CNTL_INDEX,                              \
394                     ((addr) & 0x1f) | R128_PLL_WR_EN);                  \
395         R128_WRITE(R128_CLOCK_CNTL_DATA, (val));                        \
396 } while (0)
397
398
399 #define CCE_PACKET0( reg, n )           (R128_CCE_PACKET0 |             \
400                                          ((n) << 16) | ((reg) >> 2))
401 #define CCE_PACKET1( reg0, reg1 )       (R128_CCE_PACKET1 |             \
402                                          (((reg1) >> 2) << 11) | ((reg0) >> 2))
403 #define CCE_PACKET2()                   (R128_CCE_PACKET2)
404 #define CCE_PACKET3( pkt, n )           (R128_CCE_PACKET3 |             \
405                                          (pkt) | ((n) << 16))
406
407
408 static __inline__ void
409 r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
410 {
411         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
412         ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32);
413         if ( ring->space <= 0 )
414                 ring->space += ring->size;
415 }
416
417 /* ================================================================
418  * Misc helper macros
419  */
420
421 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )                         \
422 do {                                                                    \
423         drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;          \
424         if ( ring->space < ring->high_mark ) {                          \
425                 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {      \
426                         r128_update_ring_snapshot( dev_priv );          \
427                         if ( ring->space >= ring->high_mark )           \
428                                 goto __ring_space_done;                 \
429                         DRM_UDELAY(1);                          \
430                 }                                                       \
431                 DRM_ERROR( "ring space check failed!\n" );              \
432                 return DRM_ERR(EBUSY);                          \
433         }                                                               \
434  __ring_space_done:                                                     \
435         ;                                                               \
436 } while (0)
437
438 #define VB_AGE_TEST_WITH_RETURN( dev_priv )                             \
439 do {                                                                    \
440         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;            \
441         if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) {           \
442                 int __ret = r128_do_cce_idle( dev_priv );               \
443                 if ( __ret ) return __ret;                              \
444                 sarea_priv->last_dispatch = 0;                          \
445                 r128_freelist_reset( dev );                             \
446         }                                                               \
447 } while (0)
448
449 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do {                             \
450         OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) );                  \
451         OUT_RING( R128_EVENT_CRTC_OFFSET );                             \
452 } while (0)
453
454
455 /* ================================================================
456  * Ring control
457  */
458
459 #define R128_VERBOSE    0
460
461 #define RING_LOCALS                                                     \
462         int write, _nr; unsigned int tail_mask; volatile u32 *ring;
463
464 #define BEGIN_RING( n ) do {                                            \
465         if ( R128_VERBOSE ) {                                           \
466                 DRM_INFO( "BEGIN_RING( %d ) in %s\n",                   \
467                            (n), __FUNCTION__ );                         \
468         }                                                               \
469         if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {              \
470                 COMMIT_RING();                                          \
471                 r128_wait_ring( dev_priv, (n) * sizeof(u32) );          \
472         }                                                               \
473         _nr = n; dev_priv->ring.space -= (n) * sizeof(u32);             \
474         ring = dev_priv->ring.start;                                    \
475         write = dev_priv->ring.tail;                                    \
476         tail_mask = dev_priv->ring.tail_mask;                           \
477 } while (0)
478
479 /* You can set this to zero if you want.  If the card locks up, you'll
480  * need to keep this set.  It works around a bug in early revs of the
481  * Rage 128 chipset, where the CCE would read 32 dwords past the end of
482  * the ring buffer before wrapping around.
483  */
484 #define R128_BROKEN_CCE 1
485
486 #define ADVANCE_RING() do {                                             \
487         if ( R128_VERBOSE ) {                                           \
488                 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",     \
489                           write, dev_priv->ring.tail );                 \
490         }                                                               \
491         if ( R128_BROKEN_CCE && write < 32 ) {                          \
492                 memcpy( dev_priv->ring.end,                             \
493                         dev_priv->ring.start,                           \
494                         write * sizeof(u32) );                          \
495         }                                                               \
496         if (((dev_priv->ring.tail + _nr) & tail_mask) != write) {       \
497                 DRM_ERROR(                                              \
498                         "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",        \
499                         ((dev_priv->ring.tail + _nr) & tail_mask),      \
500                         write, __LINE__);                               \
501         } else                                                          \
502                 dev_priv->ring.tail = write;                            \
503 } while (0)
504
505 #define COMMIT_RING() do {                                              \
506         if ( R128_VERBOSE ) {                                           \
507                 DRM_INFO( "COMMIT_RING() tail=0x%06x\n",                \
508                         dev_priv->ring.tail );                          \
509         }                                                               \
510         DRM_MEMORYBARRIER();                                            \
511         R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail );     \
512         R128_READ( R128_PM4_BUFFER_DL_WPTR );                           \
513 } while (0)
514
515 #define OUT_RING( x ) do {                                              \
516         if ( R128_VERBOSE ) {                                           \
517                 DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",            \
518                            (unsigned int)(x), write );                  \
519         }                                                               \
520         ring[write++] = cpu_to_le32( x );                               \
521         write &= tail_mask;                                             \
522 } while (0)
523
524 #endif /* __R128_DRV_H__ */