drm: add 32/64 support for MGA/R128/i915
[linux-2.6.git] / drivers / char / drm / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /**************************************************************************
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  **************************************************************************/
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 /* General customization:
34  */
35
36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
37
38 #define DRIVER_NAME             "i915"
39 #define DRIVER_DESC             "Intel Graphics"
40 #define DRIVER_DATE             "20040405"
41
42 /* Interface history:
43  *
44  * 1.1: Original.
45  */
46 #define DRIVER_MAJOR            1
47 #define DRIVER_MINOR            1
48 #define DRIVER_PATCHLEVEL       0
49
50 /* We use our own dma mechanisms, not the drm template code.  However,
51  * the shared IRQ code is useful to us:
52  */
53 #define __HAVE_PM               1
54
55 typedef struct _drm_i915_ring_buffer {
56         int tail_mask;
57         unsigned long Start;
58         unsigned long End;
59         unsigned long Size;
60         u8 *virtual_start;
61         int head;
62         int tail;
63         int space;
64         drm_local_map_t map;
65 } drm_i915_ring_buffer_t;
66
67 struct mem_block {
68         struct mem_block *next;
69         struct mem_block *prev;
70         int start;
71         int size;
72         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
73 };
74
75 typedef struct drm_i915_private {
76         drm_local_map_t *sarea;
77         drm_local_map_t *mmio_map;
78
79         drm_i915_sarea_t *sarea_priv;
80         drm_i915_ring_buffer_t ring;
81
82         void *hw_status_page;
83         unsigned long counter;
84         dma_addr_t dma_status_page;
85
86         int back_offset;
87         int front_offset;
88         int current_page;
89         int page_flipping;
90         int use_mi_batchbuffer_start;
91
92         wait_queue_head_t irq_queue;
93         atomic_t irq_received;
94         atomic_t irq_emitted;
95
96         int tex_lru_log_granularity;
97         int allow_batchbuffer;
98         struct mem_block *agp_heap;
99 } drm_i915_private_t;
100
101                                 /* i915_dma.c */
102 extern int i915_dma_init(DRM_IOCTL_ARGS);
103 extern int i915_dma_cleanup(drm_device_t * dev);
104 extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
105 extern int i915_batchbuffer(DRM_IOCTL_ARGS);
106 extern int i915_flip_bufs(DRM_IOCTL_ARGS);
107 extern int i915_getparam(DRM_IOCTL_ARGS);
108 extern int i915_setparam(DRM_IOCTL_ARGS);
109 extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
110 extern void i915_kernel_lost_context(drm_device_t * dev);
111 extern void i915_driver_pretakedown(drm_device_t *dev);
112 extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
113
114 /* i915_irq.c */
115 extern int i915_irq_emit(DRM_IOCTL_ARGS);
116 extern int i915_irq_wait(DRM_IOCTL_ARGS);
117 extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
118 extern int i915_emit_irq(drm_device_t * dev);
119
120 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
121 extern void i915_driver_irq_preinstall(drm_device_t *dev);
122 extern void i915_driver_irq_postinstall(drm_device_t *dev);
123 extern void i915_driver_irq_uninstall(drm_device_t *dev);
124
125 /* i915_mem.c */
126 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
127 extern int i915_mem_free(DRM_IOCTL_ARGS);
128 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
129 extern void i915_mem_takedown(struct mem_block **heap);
130 extern void i915_mem_release(drm_device_t * dev,
131                              DRMFILE filp, struct mem_block *heap);
132
133 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
134                               unsigned long arg)
135
136
137 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
138 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
139 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, reg)
140 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, reg, val)
141
142 #define I915_VERBOSE 0
143
144 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
145                         volatile char *virt;
146
147 #define BEGIN_LP_RING(n) do {                           \
148         if (I915_VERBOSE)                               \
149                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
150                           n, __FUNCTION__);             \
151         if (dev_priv->ring.space < n*4)                 \
152                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
153         outcount = 0;                                   \
154         outring = dev_priv->ring.tail;                  \
155         ringmask = dev_priv->ring.tail_mask;            \
156         virt = dev_priv->ring.virtual_start;            \
157 } while (0)
158
159 #define OUT_RING(n) do {                                        \
160         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
161         *(volatile unsigned int *)(virt + outring) = n;         \
162         outcount++;                                             \
163         outring += 4;                                           \
164         outring &= ringmask;                                    \
165 } while (0)
166
167 #define ADVANCE_LP_RING() do {                                          \
168         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
169         dev_priv->ring.tail = outring;                                  \
170         dev_priv->ring.space -= outcount * 4;                           \
171         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
172 } while(0)
173
174 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
175
176 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
177 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
178 #define CMD_REPORT_HEAD                 (7<<23)
179 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
180 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
181
182 #define INST_PARSER_CLIENT   0x00000000
183 #define INST_OP_FLUSH        0x02000000
184 #define INST_FLUSH_MAP_CACHE 0x00000001
185
186 #define BB1_START_ADDR_MASK   (~0x7)
187 #define BB1_PROTECTED         (1<<0)
188 #define BB1_UNPROTECTED       (0<<0)
189 #define BB2_END_ADDR_MASK     (~0x7)
190
191 #define I915REG_HWSTAM          0x02098
192 #define I915REG_INT_IDENTITY_R  0x020a4
193 #define I915REG_INT_MASK_R      0x020a8
194 #define I915REG_INT_ENABLE_R    0x020a0
195
196 #define SRX_INDEX               0x3c4
197 #define SRX_DATA                0x3c5
198 #define SR01                    1
199 #define SR01_SCREEN_OFF         (1<<5)
200
201 #define PPCR                    0x61204
202 #define PPCR_ON                 (1<<0)
203
204 #define ADPA                    0x61100
205 #define ADPA_DPMS_MASK          (~(3<<10))
206 #define ADPA_DPMS_ON            (0<<10)
207 #define ADPA_DPMS_SUSPEND       (1<<10)
208 #define ADPA_DPMS_STANDBY       (2<<10)
209 #define ADPA_DPMS_OFF           (3<<10)
210
211 #define NOPID                   0x2094
212 #define LP_RING                 0x2030
213 #define HP_RING                 0x2040
214 #define RING_TAIL               0x00
215 #define TAIL_ADDR               0x001FFFF8
216 #define RING_HEAD               0x04
217 #define HEAD_WRAP_COUNT         0xFFE00000
218 #define HEAD_WRAP_ONE           0x00200000
219 #define HEAD_ADDR               0x001FFFFC
220 #define RING_START              0x08
221 #define START_ADDR              0x0xFFFFF000
222 #define RING_LEN                0x0C
223 #define RING_NR_PAGES           0x001FF000
224 #define RING_REPORT_MASK        0x00000006
225 #define RING_REPORT_64K         0x00000002
226 #define RING_REPORT_128K        0x00000004
227 #define RING_NO_REPORT          0x00000000
228 #define RING_VALID_MASK         0x00000001
229 #define RING_VALID              0x00000001
230 #define RING_INVALID            0x00000000
231
232 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
233 #define SC_UPDATE_SCISSOR       (0x1<<1)
234 #define SC_ENABLE_MASK          (0x1<<0)
235 #define SC_ENABLE               (0x1<<0)
236
237 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
238 #define SCI_YMIN_MASK      (0xffff<<16)
239 #define SCI_XMIN_MASK      (0xffff<<0)
240 #define SCI_YMAX_MASK      (0xffff<<16)
241 #define SCI_XMAX_MASK      (0xffff<<0)
242
243 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
244 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
245 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
246 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
247 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
248 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
249 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
250
251 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
252 #define MI_BATCH_BUFFER_START   (0x31<<23)
253 #define MI_BATCH_BUFFER_END     (0xA<<23)
254 #define MI_BATCH_NON_SECURE     (1)
255
256 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
257 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
258 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
259
260 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
261
262 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
263 #define ASYNC_FLIP                (1<<22)
264
265 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
266
267 #endif