[AGPGART] intel_agp: Add support for G33, Q33 and Q35 chipsets
[linux-2.6.git] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
24 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
25 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
26 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
27 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
28 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
29 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
30 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
31
32 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
33                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
34                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
35                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
36                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB)
37
38 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
39                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
40                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
41
42 extern int agp_memory_reserved;
43
44
45 /* Intel 815 register */
46 #define INTEL_815_APCONT        0x51
47 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
48
49 /* Intel i820 registers */
50 #define INTEL_I820_RDCR         0x51
51 #define INTEL_I820_ERRSTS       0xc8
52
53 /* Intel i840 registers */
54 #define INTEL_I840_MCHCFG       0x50
55 #define INTEL_I840_ERRSTS       0xc8
56
57 /* Intel i850 registers */
58 #define INTEL_I850_MCHCFG       0x50
59 #define INTEL_I850_ERRSTS       0xc8
60
61 /* intel 915G registers */
62 #define I915_GMADDR     0x18
63 #define I915_MMADDR     0x10
64 #define I915_PTEADDR    0x1C
65 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
66 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
67 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
68 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
69
70 /* Intel 965G registers */
71 #define I965_MSAC 0x62
72
73 /* Intel 7505 registers */
74 #define INTEL_I7505_APSIZE      0x74
75 #define INTEL_I7505_NCAPID      0x60
76 #define INTEL_I7505_NISTAT      0x6c
77 #define INTEL_I7505_ATTBASE     0x78
78 #define INTEL_I7505_ERRSTS      0x42
79 #define INTEL_I7505_AGPCTRL     0x70
80 #define INTEL_I7505_MCHCFG      0x50
81
82 static const struct aper_size_info_fixed intel_i810_sizes[] =
83 {
84         {64, 16384, 4},
85         /* The 32M mode still requires a 64k gatt */
86         {32, 8192, 4}
87 };
88
89 #define AGP_DCACHE_MEMORY       1
90 #define AGP_PHYS_MEMORY         2
91 #define INTEL_AGP_CACHED_MEMORY 3
92
93 static struct gatt_mask intel_i810_masks[] =
94 {
95         {.mask = I810_PTE_VALID, .type = 0},
96         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
97         {.mask = I810_PTE_VALID, .type = 0},
98         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
99          .type = INTEL_AGP_CACHED_MEMORY}
100 };
101
102 static struct _intel_private {
103         struct pci_dev *pcidev; /* device one */
104         u8 __iomem *registers;
105         u32 __iomem *gtt;               /* I915G */
106         int num_dcache_entries;
107         /* gtt_entries is the number of gtt entries that are already mapped
108          * to stolen memory.  Stolen memory is larger than the memory mapped
109          * through gtt_entries, as it includes some reserved space for the BIOS
110          * popup and for the GTT.
111          */
112         int gtt_entries;                        /* i830+ */
113 } intel_private;
114
115 static int intel_i810_fetch_size(void)
116 {
117         u32 smram_miscc;
118         struct aper_size_info_fixed *values;
119
120         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
121         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
122
123         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
124                 printk(KERN_WARNING PFX "i810 is disabled\n");
125                 return 0;
126         }
127         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
128                 agp_bridge->previous_size =
129                         agp_bridge->current_size = (void *) (values + 1);
130                 agp_bridge->aperture_size_idx = 1;
131                 return values[1].size;
132         } else {
133                 agp_bridge->previous_size =
134                         agp_bridge->current_size = (void *) (values);
135                 agp_bridge->aperture_size_idx = 0;
136                 return values[0].size;
137         }
138
139         return 0;
140 }
141
142 static int intel_i810_configure(void)
143 {
144         struct aper_size_info_fixed *current_size;
145         u32 temp;
146         int i;
147
148         current_size = A_SIZE_FIX(agp_bridge->current_size);
149
150         if (!intel_private.registers) {
151                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
152                 temp &= 0xfff80000;
153
154                 intel_private.registers = ioremap(temp, 128 * 4096);
155                 if (!intel_private.registers) {
156                         printk(KERN_ERR PFX "Unable to remap memory.\n");
157                         return -ENOMEM;
158                 }
159         }
160
161         if ((readl(intel_private.registers+I810_DRAM_CTL)
162                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
163                 /* This will need to be dynamically assigned */
164                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
165                 intel_private.num_dcache_entries = 1024;
166         }
167         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
168         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
169         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
170         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
171
172         if (agp_bridge->driver->needs_scratch_page) {
173                 for (i = 0; i < current_size->num_entries; i++) {
174                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
175                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
176                 }
177         }
178         global_cache_flush();
179         return 0;
180 }
181
182 static void intel_i810_cleanup(void)
183 {
184         writel(0, intel_private.registers+I810_PGETBL_CTL);
185         readl(intel_private.registers); /* PCI Posting. */
186         iounmap(intel_private.registers);
187 }
188
189 static void intel_i810_tlbflush(struct agp_memory *mem)
190 {
191         return;
192 }
193
194 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
195 {
196         return;
197 }
198
199 /* Exists to support ARGB cursors */
200 static void *i8xx_alloc_pages(void)
201 {
202         struct page * page;
203
204         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
205         if (page == NULL)
206                 return NULL;
207
208         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
209                 change_page_attr(page, 4, PAGE_KERNEL);
210                 global_flush_tlb();
211                 __free_pages(page, 2);
212                 return NULL;
213         }
214         global_flush_tlb();
215         get_page(page);
216         SetPageLocked(page);
217         atomic_inc(&agp_bridge->current_memory_agp);
218         return page_address(page);
219 }
220
221 static void i8xx_destroy_pages(void *addr)
222 {
223         struct page *page;
224
225         if (addr == NULL)
226                 return;
227
228         page = virt_to_page(addr);
229         change_page_attr(page, 4, PAGE_KERNEL);
230         global_flush_tlb();
231         put_page(page);
232         unlock_page(page);
233         __free_pages(page, 2);
234         atomic_dec(&agp_bridge->current_memory_agp);
235 }
236
237 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
238                                         int type)
239 {
240         if (type < AGP_USER_TYPES)
241                 return type;
242         else if (type == AGP_USER_CACHED_MEMORY)
243                 return INTEL_AGP_CACHED_MEMORY;
244         else
245                 return 0;
246 }
247
248 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
249                                 int type)
250 {
251         int i, j, num_entries;
252         void *temp;
253         int ret = -EINVAL;
254         int mask_type;
255
256         if (mem->page_count == 0)
257                 goto out;
258
259         temp = agp_bridge->current_size;
260         num_entries = A_SIZE_FIX(temp)->num_entries;
261
262         if ((pg_start + mem->page_count) > num_entries)
263                 goto out_err;
264
265
266         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
267                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
268                         ret = -EBUSY;
269                         goto out_err;
270                 }
271         }
272
273         if (type != mem->type)
274                 goto out_err;
275
276         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
277
278         switch (mask_type) {
279         case AGP_DCACHE_MEMORY:
280                 if (!mem->is_flushed)
281                         global_cache_flush();
282                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
283                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
284                                intel_private.registers+I810_PTE_BASE+(i*4));
285                 }
286                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
287                 break;
288         case AGP_PHYS_MEMORY:
289         case AGP_NORMAL_MEMORY:
290                 if (!mem->is_flushed)
291                         global_cache_flush();
292                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
293                         writel(agp_bridge->driver->mask_memory(agp_bridge,
294                                                                mem->memory[i],
295                                                                mask_type),
296                                intel_private.registers+I810_PTE_BASE+(j*4));
297                 }
298                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
299                 break;
300         default:
301                 goto out_err;
302         }
303
304         agp_bridge->driver->tlb_flush(mem);
305 out:
306         ret = 0;
307 out_err:
308         mem->is_flushed = 1;
309         return ret;
310 }
311
312 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
313                                 int type)
314 {
315         int i;
316
317         if (mem->page_count == 0)
318                 return 0;
319
320         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
321                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
322         }
323         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
324
325         agp_bridge->driver->tlb_flush(mem);
326         return 0;
327 }
328
329 /*
330  * The i810/i830 requires a physical address to program its mouse
331  * pointer into hardware.
332  * However the Xserver still writes to it through the agp aperture.
333  */
334 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
335 {
336         struct agp_memory *new;
337         void *addr;
338
339         switch (pg_count) {
340         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
341                 global_flush_tlb();
342                 break;
343         case 4:
344                 /* kludge to get 4 physical pages for ARGB cursor */
345                 addr = i8xx_alloc_pages();
346                 break;
347         default:
348                 return NULL;
349         }
350
351         if (addr == NULL)
352                 return NULL;
353
354         new = agp_create_memory(pg_count);
355         if (new == NULL)
356                 return NULL;
357
358         new->memory[0] = virt_to_gart(addr);
359         if (pg_count == 4) {
360                 /* kludge to get 4 physical pages for ARGB cursor */
361                 new->memory[1] = new->memory[0] + PAGE_SIZE;
362                 new->memory[2] = new->memory[1] + PAGE_SIZE;
363                 new->memory[3] = new->memory[2] + PAGE_SIZE;
364         }
365         new->page_count = pg_count;
366         new->num_scratch_pages = pg_count;
367         new->type = AGP_PHYS_MEMORY;
368         new->physical = new->memory[0];
369         return new;
370 }
371
372 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
373 {
374         struct agp_memory *new;
375
376         if (type == AGP_DCACHE_MEMORY) {
377                 if (pg_count != intel_private.num_dcache_entries)
378                         return NULL;
379
380                 new = agp_create_memory(1);
381                 if (new == NULL)
382                         return NULL;
383
384                 new->type = AGP_DCACHE_MEMORY;
385                 new->page_count = pg_count;
386                 new->num_scratch_pages = 0;
387                 agp_free_page_array(new);
388                 return new;
389         }
390         if (type == AGP_PHYS_MEMORY)
391                 return alloc_agpphysmem_i8xx(pg_count, type);
392         return NULL;
393 }
394
395 static void intel_i810_free_by_type(struct agp_memory *curr)
396 {
397         agp_free_key(curr->key);
398         if (curr->type == AGP_PHYS_MEMORY) {
399                 if (curr->page_count == 4)
400                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
401                 else {
402                         agp_bridge->driver->agp_destroy_page(
403                                  gart_to_virt(curr->memory[0]));
404                         global_flush_tlb();
405                 }
406                 agp_free_page_array(curr);
407         }
408         kfree(curr);
409 }
410
411 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
412         unsigned long addr, int type)
413 {
414         /* Type checking must be done elsewhere */
415         return addr | bridge->driver->masks[type].mask;
416 }
417
418 static struct aper_size_info_fixed intel_i830_sizes[] =
419 {
420         {128, 32768, 5},
421         /* The 64M mode still requires a 128k gatt */
422         {64, 16384, 5},
423         {256, 65536, 6},
424         {512, 131072, 7},
425 };
426
427 static void intel_i830_init_gtt_entries(void)
428 {
429         u16 gmch_ctrl;
430         int gtt_entries;
431         u8 rdct;
432         int local = 0;
433         static const int ddt[4] = { 0, 16, 32, 64 };
434         int size; /* reserved space (in kb) at the top of stolen memory */
435
436         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
437
438         if (IS_I965) {
439                 u32 pgetbl_ctl;
440                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
441
442                 /* The 965 has a field telling us the size of the GTT,
443                  * which may be larger than what is necessary to map the
444                  * aperture.
445                  */
446                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
447                 case I965_PGETBL_SIZE_128KB:
448                         size = 128;
449                         break;
450                 case I965_PGETBL_SIZE_256KB:
451                         size = 256;
452                         break;
453                 case I965_PGETBL_SIZE_512KB:
454                         size = 512;
455                         break;
456                 default:
457                         printk(KERN_INFO PFX "Unknown page table size, "
458                                "assuming 512KB\n");
459                         size = 512;
460                 }
461                 size += 4; /* add in BIOS popup space */
462         } else if (IS_G33) {
463         /* G33's GTT size defined in gmch_ctrl */
464                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
465                 case G33_PGETBL_SIZE_1M:
466                         size = 1024;
467                         break;
468                 case G33_PGETBL_SIZE_2M:
469                         size = 2048;
470                         break;
471                 default:
472                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
473                                 "assuming 512KB\n",
474                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
475                         size = 512;
476                 }
477                 size += 4;
478         } else {
479                 /* On previous hardware, the GTT size was just what was
480                  * required to map the aperture.
481                  */
482                 size = agp_bridge->driver->fetch_size() + 4;
483         }
484
485         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
486             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
487                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
488                 case I830_GMCH_GMS_STOLEN_512:
489                         gtt_entries = KB(512) - KB(size);
490                         break;
491                 case I830_GMCH_GMS_STOLEN_1024:
492                         gtt_entries = MB(1) - KB(size);
493                         break;
494                 case I830_GMCH_GMS_STOLEN_8192:
495                         gtt_entries = MB(8) - KB(size);
496                         break;
497                 case I830_GMCH_GMS_LOCAL:
498                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
499                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
500                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
501                         local = 1;
502                         break;
503                 default:
504                         gtt_entries = 0;
505                         break;
506                 }
507         } else {
508                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
509                 case I855_GMCH_GMS_STOLEN_1M:
510                         gtt_entries = MB(1) - KB(size);
511                         break;
512                 case I855_GMCH_GMS_STOLEN_4M:
513                         gtt_entries = MB(4) - KB(size);
514                         break;
515                 case I855_GMCH_GMS_STOLEN_8M:
516                         gtt_entries = MB(8) - KB(size);
517                         break;
518                 case I855_GMCH_GMS_STOLEN_16M:
519                         gtt_entries = MB(16) - KB(size);
520                         break;
521                 case I855_GMCH_GMS_STOLEN_32M:
522                         gtt_entries = MB(32) - KB(size);
523                         break;
524                 case I915_GMCH_GMS_STOLEN_48M:
525                         /* Check it's really I915G */
526                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
527                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
528                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
529                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
530                             IS_I965 || IS_G33)
531                                 gtt_entries = MB(48) - KB(size);
532                         else
533                                 gtt_entries = 0;
534                         break;
535                 case I915_GMCH_GMS_STOLEN_64M:
536                         /* Check it's really I915G */
537                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
538                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
539                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
540                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
541                             IS_I965 || IS_G33)
542                                 gtt_entries = MB(64) - KB(size);
543                         else
544                                 gtt_entries = 0;
545                         break;
546                 case G33_GMCH_GMS_STOLEN_128M:
547                         if (IS_G33)
548                                 gtt_entries = MB(128) - KB(size);
549                         else
550                                 gtt_entries = 0;
551                         break;
552                 case G33_GMCH_GMS_STOLEN_256M:
553                         if (IS_G33)
554                                 gtt_entries = MB(256) - KB(size);
555                         else
556                                 gtt_entries = 0;
557                         break;
558                 default:
559                         gtt_entries = 0;
560                         break;
561                 }
562         }
563         if (gtt_entries > 0)
564                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
565                        gtt_entries / KB(1), local ? "local" : "stolen");
566         else
567                 printk(KERN_INFO PFX
568                        "No pre-allocated video memory detected.\n");
569         gtt_entries /= KB(4);
570
571         intel_private.gtt_entries = gtt_entries;
572 }
573
574 /* The intel i830 automatically initializes the agp aperture during POST.
575  * Use the memory already set aside for in the GTT.
576  */
577 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
578 {
579         int page_order;
580         struct aper_size_info_fixed *size;
581         int num_entries;
582         u32 temp;
583
584         size = agp_bridge->current_size;
585         page_order = size->page_order;
586         num_entries = size->num_entries;
587         agp_bridge->gatt_table_real = NULL;
588
589         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
590         temp &= 0xfff80000;
591
592         intel_private.registers = ioremap(temp,128 * 4096);
593         if (!intel_private.registers)
594                 return -ENOMEM;
595
596         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
597         global_cache_flush();   /* FIXME: ?? */
598
599         /* we have to call this as early as possible after the MMIO base address is known */
600         intel_i830_init_gtt_entries();
601
602         agp_bridge->gatt_table = NULL;
603
604         agp_bridge->gatt_bus_addr = temp;
605
606         return 0;
607 }
608
609 /* Return the gatt table to a sane state. Use the top of stolen
610  * memory for the GTT.
611  */
612 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
613 {
614         return 0;
615 }
616
617 static int intel_i830_fetch_size(void)
618 {
619         u16 gmch_ctrl;
620         struct aper_size_info_fixed *values;
621
622         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
623
624         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
625             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
626                 /* 855GM/852GM/865G has 128MB aperture size */
627                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
628                 agp_bridge->aperture_size_idx = 0;
629                 return values[0].size;
630         }
631
632         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
633
634         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
635                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
636                 agp_bridge->aperture_size_idx = 0;
637                 return values[0].size;
638         } else {
639                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
640                 agp_bridge->aperture_size_idx = 1;
641                 return values[1].size;
642         }
643
644         return 0;
645 }
646
647 static int intel_i830_configure(void)
648 {
649         struct aper_size_info_fixed *current_size;
650         u32 temp;
651         u16 gmch_ctrl;
652         int i;
653
654         current_size = A_SIZE_FIX(agp_bridge->current_size);
655
656         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
657         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
658
659         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
660         gmch_ctrl |= I830_GMCH_ENABLED;
661         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
662
663         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
664         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
665
666         if (agp_bridge->driver->needs_scratch_page) {
667                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
668                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
669                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
670                 }
671         }
672
673         global_cache_flush();
674         return 0;
675 }
676
677 static void intel_i830_cleanup(void)
678 {
679         iounmap(intel_private.registers);
680 }
681
682 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
683 {
684         int i,j,num_entries;
685         void *temp;
686         int ret = -EINVAL;
687         int mask_type;
688
689         if (mem->page_count == 0)
690                 goto out;
691
692         temp = agp_bridge->current_size;
693         num_entries = A_SIZE_FIX(temp)->num_entries;
694
695         if (pg_start < intel_private.gtt_entries) {
696                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
697                                 pg_start,intel_private.gtt_entries);
698
699                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
700                 goto out_err;
701         }
702
703         if ((pg_start + mem->page_count) > num_entries)
704                 goto out_err;
705
706         /* The i830 can't check the GTT for entries since its read only,
707          * depend on the caller to make the correct offset decisions.
708          */
709
710         if (type != mem->type)
711                 goto out_err;
712
713         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
714
715         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
716             mask_type != INTEL_AGP_CACHED_MEMORY)
717                 goto out_err;
718
719         if (!mem->is_flushed)
720                 global_cache_flush();
721
722         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
723                 writel(agp_bridge->driver->mask_memory(agp_bridge,
724                                                        mem->memory[i], mask_type),
725                        intel_private.registers+I810_PTE_BASE+(j*4));
726         }
727         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
728         agp_bridge->driver->tlb_flush(mem);
729
730 out:
731         ret = 0;
732 out_err:
733         mem->is_flushed = 1;
734         return ret;
735 }
736
737 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
738                                 int type)
739 {
740         int i;
741
742         if (mem->page_count == 0)
743                 return 0;
744
745         if (pg_start < intel_private.gtt_entries) {
746                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
747                 return -EINVAL;
748         }
749
750         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
751                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
752         }
753         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
754
755         agp_bridge->driver->tlb_flush(mem);
756         return 0;
757 }
758
759 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
760 {
761         if (type == AGP_PHYS_MEMORY)
762                 return alloc_agpphysmem_i8xx(pg_count, type);
763         /* always return NULL for other allocation types for now */
764         return NULL;
765 }
766
767 static int intel_i915_configure(void)
768 {
769         struct aper_size_info_fixed *current_size;
770         u32 temp;
771         u16 gmch_ctrl;
772         int i;
773
774         current_size = A_SIZE_FIX(agp_bridge->current_size);
775
776         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
777
778         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
779
780         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
781         gmch_ctrl |= I830_GMCH_ENABLED;
782         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
783
784         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
785         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
786
787         if (agp_bridge->driver->needs_scratch_page) {
788                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
789                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
790                         readl(intel_private.gtt+i);     /* PCI Posting. */
791                 }
792         }
793
794         global_cache_flush();
795         return 0;
796 }
797
798 static void intel_i915_cleanup(void)
799 {
800         iounmap(intel_private.gtt);
801         iounmap(intel_private.registers);
802 }
803
804 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
805                                 int type)
806 {
807         int i,j,num_entries;
808         void *temp;
809         int ret = -EINVAL;
810         int mask_type;
811
812         if (mem->page_count == 0)
813                 goto out;
814
815         temp = agp_bridge->current_size;
816         num_entries = A_SIZE_FIX(temp)->num_entries;
817
818         if (pg_start < intel_private.gtt_entries) {
819                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
820                                 pg_start,intel_private.gtt_entries);
821
822                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
823                 goto out_err;
824         }
825
826         if ((pg_start + mem->page_count) > num_entries)
827                 goto out_err;
828
829         /* The i915 can't check the GTT for entries since its read only,
830          * depend on the caller to make the correct offset decisions.
831          */
832
833         if (type != mem->type)
834                 goto out_err;
835
836         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
837
838         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
839             mask_type != INTEL_AGP_CACHED_MEMORY)
840                 goto out_err;
841
842         if (!mem->is_flushed)
843                 global_cache_flush();
844
845         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
846                 writel(agp_bridge->driver->mask_memory(agp_bridge,
847                         mem->memory[i], mask_type), intel_private.gtt+j);
848         }
849
850         readl(intel_private.gtt+j-1);
851         agp_bridge->driver->tlb_flush(mem);
852
853  out:
854         ret = 0;
855  out_err:
856         mem->is_flushed = 1;
857         return ret;
858 }
859
860 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
861                                 int type)
862 {
863         int i;
864
865         if (mem->page_count == 0)
866                 return 0;
867
868         if (pg_start < intel_private.gtt_entries) {
869                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
870                 return -EINVAL;
871         }
872
873         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
874                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
875         }
876         readl(intel_private.gtt+i-1);
877
878         agp_bridge->driver->tlb_flush(mem);
879         return 0;
880 }
881
882 /* Return the aperture size by just checking the resource length.  The effect
883  * described in the spec of the MSAC registers is just changing of the
884  * resource size.
885  */
886 static int intel_i9xx_fetch_size(void)
887 {
888         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
889         int aper_size; /* size in megabytes */
890         int i;
891
892         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
893
894         for (i = 0; i < num_sizes; i++) {
895                 if (aper_size == intel_i830_sizes[i].size) {
896                         agp_bridge->current_size = intel_i830_sizes + i;
897                         agp_bridge->previous_size = agp_bridge->current_size;
898                         return aper_size;
899                 }
900         }
901
902         return 0;
903 }
904
905 /* The intel i915 automatically initializes the agp aperture during POST.
906  * Use the memory already set aside for in the GTT.
907  */
908 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
909 {
910         int page_order;
911         struct aper_size_info_fixed *size;
912         int num_entries;
913         u32 temp, temp2;
914
915         size = agp_bridge->current_size;
916         page_order = size->page_order;
917         num_entries = size->num_entries;
918         agp_bridge->gatt_table_real = NULL;
919
920         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
921         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
922
923         intel_private.gtt = ioremap(temp2, 256 * 1024);
924         if (!intel_private.gtt)
925                 return -ENOMEM;
926
927         temp &= 0xfff80000;
928
929         intel_private.registers = ioremap(temp,128 * 4096);
930         if (!intel_private.registers)
931                 return -ENOMEM;
932
933         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
934         global_cache_flush();   /* FIXME: ? */
935
936         /* we have to call this as early as possible after the MMIO base address is known */
937         intel_i830_init_gtt_entries();
938
939         agp_bridge->gatt_table = NULL;
940
941         agp_bridge->gatt_bus_addr = temp;
942
943         return 0;
944 }
945
946 /*
947  * The i965 supports 36-bit physical addresses, but to keep
948  * the format of the GTT the same, the bits that don't fit
949  * in a 32-bit word are shifted down to bits 4..7.
950  *
951  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
952  * is always zero on 32-bit architectures, so no need to make
953  * this conditional.
954  */
955 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
956         unsigned long addr, int type)
957 {
958         /* Shift high bits down */
959         addr |= (addr >> 28) & 0xf0;
960
961         /* Type checking must be done elsewhere */
962         return addr | bridge->driver->masks[type].mask;
963 }
964
965 /* The intel i965 automatically initializes the agp aperture during POST.
966  * Use the memory already set aside for in the GTT.
967  */
968 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
969 {
970        int page_order;
971        struct aper_size_info_fixed *size;
972        int num_entries;
973        u32 temp;
974
975        size = agp_bridge->current_size;
976        page_order = size->page_order;
977        num_entries = size->num_entries;
978        agp_bridge->gatt_table_real = NULL;
979
980        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
981
982        temp &= 0xfff00000;
983        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
984
985        if (!intel_private.gtt)
986                return -ENOMEM;
987
988
989        intel_private.registers = ioremap(temp,128 * 4096);
990        if (!intel_private.registers)
991                return -ENOMEM;
992
993        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
994        global_cache_flush();   /* FIXME: ? */
995
996        /* we have to call this as early as possible after the MMIO base address is known */
997        intel_i830_init_gtt_entries();
998
999        agp_bridge->gatt_table = NULL;
1000
1001        agp_bridge->gatt_bus_addr = temp;
1002
1003        return 0;
1004 }
1005
1006
1007 static int intel_fetch_size(void)
1008 {
1009         int i;
1010         u16 temp;
1011         struct aper_size_info_16 *values;
1012
1013         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1014         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1015
1016         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1017                 if (temp == values[i].size_value) {
1018                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1019                         agp_bridge->aperture_size_idx = i;
1020                         return values[i].size;
1021                 }
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int __intel_8xx_fetch_size(u8 temp)
1028 {
1029         int i;
1030         struct aper_size_info_8 *values;
1031
1032         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1033
1034         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1035                 if (temp == values[i].size_value) {
1036                         agp_bridge->previous_size =
1037                                 agp_bridge->current_size = (void *) (values + i);
1038                         agp_bridge->aperture_size_idx = i;
1039                         return values[i].size;
1040                 }
1041         }
1042         return 0;
1043 }
1044
1045 static int intel_8xx_fetch_size(void)
1046 {
1047         u8 temp;
1048
1049         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1050         return __intel_8xx_fetch_size(temp);
1051 }
1052
1053 static int intel_815_fetch_size(void)
1054 {
1055         u8 temp;
1056
1057         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1058          * one non-reserved bit, so mask the others out ... */
1059         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1060         temp &= (1 << 3);
1061
1062         return __intel_8xx_fetch_size(temp);
1063 }
1064
1065 static void intel_tlbflush(struct agp_memory *mem)
1066 {
1067         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1068         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1069 }
1070
1071
1072 static void intel_8xx_tlbflush(struct agp_memory *mem)
1073 {
1074         u32 temp;
1075         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1076         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1077         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1078         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1079 }
1080
1081
1082 static void intel_cleanup(void)
1083 {
1084         u16 temp;
1085         struct aper_size_info_16 *previous_size;
1086
1087         previous_size = A_SIZE_16(agp_bridge->previous_size);
1088         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1089         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1090         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1091 }
1092
1093
1094 static void intel_8xx_cleanup(void)
1095 {
1096         u16 temp;
1097         struct aper_size_info_8 *previous_size;
1098
1099         previous_size = A_SIZE_8(agp_bridge->previous_size);
1100         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1101         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1102         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1103 }
1104
1105
1106 static int intel_configure(void)
1107 {
1108         u32 temp;
1109         u16 temp2;
1110         struct aper_size_info_16 *current_size;
1111
1112         current_size = A_SIZE_16(agp_bridge->current_size);
1113
1114         /* aperture size */
1115         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1116
1117         /* address to map to */
1118         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1119         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1120
1121         /* attbase - aperture base */
1122         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1123
1124         /* agpctrl */
1125         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1126
1127         /* paccfg/nbxcfg */
1128         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1129         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1130                         (temp2 & ~(1 << 10)) | (1 << 9));
1131         /* clear any possible error conditions */
1132         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1133         return 0;
1134 }
1135
1136 static int intel_815_configure(void)
1137 {
1138         u32 temp, addr;
1139         u8 temp2;
1140         struct aper_size_info_8 *current_size;
1141
1142         /* attbase - aperture base */
1143         /* the Intel 815 chipset spec. says that bits 29-31 in the
1144         * ATTBASE register are reserved -> try not to write them */
1145         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1146                 printk (KERN_EMERG PFX "gatt bus addr too high");
1147                 return -EINVAL;
1148         }
1149
1150         current_size = A_SIZE_8(agp_bridge->current_size);
1151
1152         /* aperture size */
1153         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1154                         current_size->size_value);
1155
1156         /* address to map to */
1157         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1158         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1159
1160         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1161         addr &= INTEL_815_ATTBASE_MASK;
1162         addr |= agp_bridge->gatt_bus_addr;
1163         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1164
1165         /* agpctrl */
1166         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1167
1168         /* apcont */
1169         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1170         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1171
1172         /* clear any possible error conditions */
1173         /* Oddness : this chipset seems to have no ERRSTS register ! */
1174         return 0;
1175 }
1176
1177 static void intel_820_tlbflush(struct agp_memory *mem)
1178 {
1179         return;
1180 }
1181
1182 static void intel_820_cleanup(void)
1183 {
1184         u8 temp;
1185         struct aper_size_info_8 *previous_size;
1186
1187         previous_size = A_SIZE_8(agp_bridge->previous_size);
1188         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1189         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1190                         temp & ~(1 << 1));
1191         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1192                         previous_size->size_value);
1193 }
1194
1195
1196 static int intel_820_configure(void)
1197 {
1198         u32 temp;
1199         u8 temp2;
1200         struct aper_size_info_8 *current_size;
1201
1202         current_size = A_SIZE_8(agp_bridge->current_size);
1203
1204         /* aperture size */
1205         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1206
1207         /* address to map to */
1208         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1209         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1210
1211         /* attbase - aperture base */
1212         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1213
1214         /* agpctrl */
1215         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1216
1217         /* global enable aperture access */
1218         /* This flag is not accessed through MCHCFG register as in */
1219         /* i850 chipset. */
1220         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1221         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1222         /* clear any possible AGP-related error conditions */
1223         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1224         return 0;
1225 }
1226
1227 static int intel_840_configure(void)
1228 {
1229         u32 temp;
1230         u16 temp2;
1231         struct aper_size_info_8 *current_size;
1232
1233         current_size = A_SIZE_8(agp_bridge->current_size);
1234
1235         /* aperture size */
1236         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1237
1238         /* address to map to */
1239         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1240         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1241
1242         /* attbase - aperture base */
1243         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1244
1245         /* agpctrl */
1246         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1247
1248         /* mcgcfg */
1249         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1250         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1251         /* clear any possible error conditions */
1252         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1253         return 0;
1254 }
1255
1256 static int intel_845_configure(void)
1257 {
1258         u32 temp;
1259         u8 temp2;
1260         struct aper_size_info_8 *current_size;
1261
1262         current_size = A_SIZE_8(agp_bridge->current_size);
1263
1264         /* aperture size */
1265         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1266
1267         if (agp_bridge->apbase_config != 0) {
1268                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1269                                        agp_bridge->apbase_config);
1270         } else {
1271                 /* address to map to */
1272                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1273                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1274                 agp_bridge->apbase_config = temp;
1275         }
1276
1277         /* attbase - aperture base */
1278         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1279
1280         /* agpctrl */
1281         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1282
1283         /* agpm */
1284         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1285         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1286         /* clear any possible error conditions */
1287         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1288         return 0;
1289 }
1290
1291 static int intel_850_configure(void)
1292 {
1293         u32 temp;
1294         u16 temp2;
1295         struct aper_size_info_8 *current_size;
1296
1297         current_size = A_SIZE_8(agp_bridge->current_size);
1298
1299         /* aperture size */
1300         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1301
1302         /* address to map to */
1303         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1304         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1305
1306         /* attbase - aperture base */
1307         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1308
1309         /* agpctrl */
1310         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1311
1312         /* mcgcfg */
1313         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1314         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1315         /* clear any possible AGP-related error conditions */
1316         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1317         return 0;
1318 }
1319
1320 static int intel_860_configure(void)
1321 {
1322         u32 temp;
1323         u16 temp2;
1324         struct aper_size_info_8 *current_size;
1325
1326         current_size = A_SIZE_8(agp_bridge->current_size);
1327
1328         /* aperture size */
1329         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1330
1331         /* address to map to */
1332         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1333         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1334
1335         /* attbase - aperture base */
1336         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1337
1338         /* agpctrl */
1339         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1340
1341         /* mcgcfg */
1342         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1343         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1344         /* clear any possible AGP-related error conditions */
1345         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1346         return 0;
1347 }
1348
1349 static int intel_830mp_configure(void)
1350 {
1351         u32 temp;
1352         u16 temp2;
1353         struct aper_size_info_8 *current_size;
1354
1355         current_size = A_SIZE_8(agp_bridge->current_size);
1356
1357         /* aperture size */
1358         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1359
1360         /* address to map to */
1361         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1362         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1363
1364         /* attbase - aperture base */
1365         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1366
1367         /* agpctrl */
1368         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1369
1370         /* gmch */
1371         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1372         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1373         /* clear any possible AGP-related error conditions */
1374         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1375         return 0;
1376 }
1377
1378 static int intel_7505_configure(void)
1379 {
1380         u32 temp;
1381         u16 temp2;
1382         struct aper_size_info_8 *current_size;
1383
1384         current_size = A_SIZE_8(agp_bridge->current_size);
1385
1386         /* aperture size */
1387         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1388
1389         /* address to map to */
1390         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1391         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1392
1393         /* attbase - aperture base */
1394         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1395
1396         /* agpctrl */
1397         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1398
1399         /* mchcfg */
1400         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1401         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1402
1403         return 0;
1404 }
1405
1406 /* Setup function */
1407 static const struct gatt_mask intel_generic_masks[] =
1408 {
1409         {.mask = 0x00000017, .type = 0}
1410 };
1411
1412 static const struct aper_size_info_8 intel_815_sizes[2] =
1413 {
1414         {64, 16384, 4, 0},
1415         {32, 8192, 3, 8},
1416 };
1417
1418 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1419 {
1420         {256, 65536, 6, 0},
1421         {128, 32768, 5, 32},
1422         {64, 16384, 4, 48},
1423         {32, 8192, 3, 56},
1424         {16, 4096, 2, 60},
1425         {8, 2048, 1, 62},
1426         {4, 1024, 0, 63}
1427 };
1428
1429 static const struct aper_size_info_16 intel_generic_sizes[7] =
1430 {
1431         {256, 65536, 6, 0},
1432         {128, 32768, 5, 32},
1433         {64, 16384, 4, 48},
1434         {32, 8192, 3, 56},
1435         {16, 4096, 2, 60},
1436         {8, 2048, 1, 62},
1437         {4, 1024, 0, 63}
1438 };
1439
1440 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1441 {
1442         {256, 65536, 6, 0},
1443         {128, 32768, 5, 32},
1444         {64, 16384, 4, 48},
1445         {32, 8192, 3, 56}
1446 };
1447
1448 static const struct agp_bridge_driver intel_generic_driver = {
1449         .owner                  = THIS_MODULE,
1450         .aperture_sizes         = intel_generic_sizes,
1451         .size_type              = U16_APER_SIZE,
1452         .num_aperture_sizes     = 7,
1453         .configure              = intel_configure,
1454         .fetch_size             = intel_fetch_size,
1455         .cleanup                = intel_cleanup,
1456         .tlb_flush              = intel_tlbflush,
1457         .mask_memory            = agp_generic_mask_memory,
1458         .masks                  = intel_generic_masks,
1459         .agp_enable             = agp_generic_enable,
1460         .cache_flush            = global_cache_flush,
1461         .create_gatt_table      = agp_generic_create_gatt_table,
1462         .free_gatt_table        = agp_generic_free_gatt_table,
1463         .insert_memory          = agp_generic_insert_memory,
1464         .remove_memory          = agp_generic_remove_memory,
1465         .alloc_by_type          = agp_generic_alloc_by_type,
1466         .free_by_type           = agp_generic_free_by_type,
1467         .agp_alloc_page         = agp_generic_alloc_page,
1468         .agp_destroy_page       = agp_generic_destroy_page,
1469         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1470 };
1471
1472 static const struct agp_bridge_driver intel_810_driver = {
1473         .owner                  = THIS_MODULE,
1474         .aperture_sizes         = intel_i810_sizes,
1475         .size_type              = FIXED_APER_SIZE,
1476         .num_aperture_sizes     = 2,
1477         .needs_scratch_page     = TRUE,
1478         .configure              = intel_i810_configure,
1479         .fetch_size             = intel_i810_fetch_size,
1480         .cleanup                = intel_i810_cleanup,
1481         .tlb_flush              = intel_i810_tlbflush,
1482         .mask_memory            = intel_i810_mask_memory,
1483         .masks                  = intel_i810_masks,
1484         .agp_enable             = intel_i810_agp_enable,
1485         .cache_flush            = global_cache_flush,
1486         .create_gatt_table      = agp_generic_create_gatt_table,
1487         .free_gatt_table        = agp_generic_free_gatt_table,
1488         .insert_memory          = intel_i810_insert_entries,
1489         .remove_memory          = intel_i810_remove_entries,
1490         .alloc_by_type          = intel_i810_alloc_by_type,
1491         .free_by_type           = intel_i810_free_by_type,
1492         .agp_alloc_page         = agp_generic_alloc_page,
1493         .agp_destroy_page       = agp_generic_destroy_page,
1494         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1495 };
1496
1497 static const struct agp_bridge_driver intel_815_driver = {
1498         .owner                  = THIS_MODULE,
1499         .aperture_sizes         = intel_815_sizes,
1500         .size_type              = U8_APER_SIZE,
1501         .num_aperture_sizes     = 2,
1502         .configure              = intel_815_configure,
1503         .fetch_size             = intel_815_fetch_size,
1504         .cleanup                = intel_8xx_cleanup,
1505         .tlb_flush              = intel_8xx_tlbflush,
1506         .mask_memory            = agp_generic_mask_memory,
1507         .masks                  = intel_generic_masks,
1508         .agp_enable             = agp_generic_enable,
1509         .cache_flush            = global_cache_flush,
1510         .create_gatt_table      = agp_generic_create_gatt_table,
1511         .free_gatt_table        = agp_generic_free_gatt_table,
1512         .insert_memory          = agp_generic_insert_memory,
1513         .remove_memory          = agp_generic_remove_memory,
1514         .alloc_by_type          = agp_generic_alloc_by_type,
1515         .free_by_type           = agp_generic_free_by_type,
1516         .agp_alloc_page         = agp_generic_alloc_page,
1517         .agp_destroy_page       = agp_generic_destroy_page,
1518         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1519 };
1520
1521 static const struct agp_bridge_driver intel_830_driver = {
1522         .owner                  = THIS_MODULE,
1523         .aperture_sizes         = intel_i830_sizes,
1524         .size_type              = FIXED_APER_SIZE,
1525         .num_aperture_sizes     = 4,
1526         .needs_scratch_page     = TRUE,
1527         .configure              = intel_i830_configure,
1528         .fetch_size             = intel_i830_fetch_size,
1529         .cleanup                = intel_i830_cleanup,
1530         .tlb_flush              = intel_i810_tlbflush,
1531         .mask_memory            = intel_i810_mask_memory,
1532         .masks                  = intel_i810_masks,
1533         .agp_enable             = intel_i810_agp_enable,
1534         .cache_flush            = global_cache_flush,
1535         .create_gatt_table      = intel_i830_create_gatt_table,
1536         .free_gatt_table        = intel_i830_free_gatt_table,
1537         .insert_memory          = intel_i830_insert_entries,
1538         .remove_memory          = intel_i830_remove_entries,
1539         .alloc_by_type          = intel_i830_alloc_by_type,
1540         .free_by_type           = intel_i810_free_by_type,
1541         .agp_alloc_page         = agp_generic_alloc_page,
1542         .agp_destroy_page       = agp_generic_destroy_page,
1543         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1544 };
1545
1546 static const struct agp_bridge_driver intel_820_driver = {
1547         .owner                  = THIS_MODULE,
1548         .aperture_sizes         = intel_8xx_sizes,
1549         .size_type              = U8_APER_SIZE,
1550         .num_aperture_sizes     = 7,
1551         .configure              = intel_820_configure,
1552         .fetch_size             = intel_8xx_fetch_size,
1553         .cleanup                = intel_820_cleanup,
1554         .tlb_flush              = intel_820_tlbflush,
1555         .mask_memory            = agp_generic_mask_memory,
1556         .masks                  = intel_generic_masks,
1557         .agp_enable             = agp_generic_enable,
1558         .cache_flush            = global_cache_flush,
1559         .create_gatt_table      = agp_generic_create_gatt_table,
1560         .free_gatt_table        = agp_generic_free_gatt_table,
1561         .insert_memory          = agp_generic_insert_memory,
1562         .remove_memory          = agp_generic_remove_memory,
1563         .alloc_by_type          = agp_generic_alloc_by_type,
1564         .free_by_type           = agp_generic_free_by_type,
1565         .agp_alloc_page         = agp_generic_alloc_page,
1566         .agp_destroy_page       = agp_generic_destroy_page,
1567         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1568 };
1569
1570 static const struct agp_bridge_driver intel_830mp_driver = {
1571         .owner                  = THIS_MODULE,
1572         .aperture_sizes         = intel_830mp_sizes,
1573         .size_type              = U8_APER_SIZE,
1574         .num_aperture_sizes     = 4,
1575         .configure              = intel_830mp_configure,
1576         .fetch_size             = intel_8xx_fetch_size,
1577         .cleanup                = intel_8xx_cleanup,
1578         .tlb_flush              = intel_8xx_tlbflush,
1579         .mask_memory            = agp_generic_mask_memory,
1580         .masks                  = intel_generic_masks,
1581         .agp_enable             = agp_generic_enable,
1582         .cache_flush            = global_cache_flush,
1583         .create_gatt_table      = agp_generic_create_gatt_table,
1584         .free_gatt_table        = agp_generic_free_gatt_table,
1585         .insert_memory          = agp_generic_insert_memory,
1586         .remove_memory          = agp_generic_remove_memory,
1587         .alloc_by_type          = agp_generic_alloc_by_type,
1588         .free_by_type           = agp_generic_free_by_type,
1589         .agp_alloc_page         = agp_generic_alloc_page,
1590         .agp_destroy_page       = agp_generic_destroy_page,
1591         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1592 };
1593
1594 static const struct agp_bridge_driver intel_840_driver = {
1595         .owner                  = THIS_MODULE,
1596         .aperture_sizes         = intel_8xx_sizes,
1597         .size_type              = U8_APER_SIZE,
1598         .num_aperture_sizes     = 7,
1599         .configure              = intel_840_configure,
1600         .fetch_size             = intel_8xx_fetch_size,
1601         .cleanup                = intel_8xx_cleanup,
1602         .tlb_flush              = intel_8xx_tlbflush,
1603         .mask_memory            = agp_generic_mask_memory,
1604         .masks                  = intel_generic_masks,
1605         .agp_enable             = agp_generic_enable,
1606         .cache_flush            = global_cache_flush,
1607         .create_gatt_table      = agp_generic_create_gatt_table,
1608         .free_gatt_table        = agp_generic_free_gatt_table,
1609         .insert_memory          = agp_generic_insert_memory,
1610         .remove_memory          = agp_generic_remove_memory,
1611         .alloc_by_type          = agp_generic_alloc_by_type,
1612         .free_by_type           = agp_generic_free_by_type,
1613         .agp_alloc_page         = agp_generic_alloc_page,
1614         .agp_destroy_page       = agp_generic_destroy_page,
1615         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1616 };
1617
1618 static const struct agp_bridge_driver intel_845_driver = {
1619         .owner                  = THIS_MODULE,
1620         .aperture_sizes         = intel_8xx_sizes,
1621         .size_type              = U8_APER_SIZE,
1622         .num_aperture_sizes     = 7,
1623         .configure              = intel_845_configure,
1624         .fetch_size             = intel_8xx_fetch_size,
1625         .cleanup                = intel_8xx_cleanup,
1626         .tlb_flush              = intel_8xx_tlbflush,
1627         .mask_memory            = agp_generic_mask_memory,
1628         .masks                  = intel_generic_masks,
1629         .agp_enable             = agp_generic_enable,
1630         .cache_flush            = global_cache_flush,
1631         .create_gatt_table      = agp_generic_create_gatt_table,
1632         .free_gatt_table        = agp_generic_free_gatt_table,
1633         .insert_memory          = agp_generic_insert_memory,
1634         .remove_memory          = agp_generic_remove_memory,
1635         .alloc_by_type          = agp_generic_alloc_by_type,
1636         .free_by_type           = agp_generic_free_by_type,
1637         .agp_alloc_page         = agp_generic_alloc_page,
1638         .agp_destroy_page       = agp_generic_destroy_page,
1639         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1640 };
1641
1642 static const struct agp_bridge_driver intel_850_driver = {
1643         .owner                  = THIS_MODULE,
1644         .aperture_sizes         = intel_8xx_sizes,
1645         .size_type              = U8_APER_SIZE,
1646         .num_aperture_sizes     = 7,
1647         .configure              = intel_850_configure,
1648         .fetch_size             = intel_8xx_fetch_size,
1649         .cleanup                = intel_8xx_cleanup,
1650         .tlb_flush              = intel_8xx_tlbflush,
1651         .mask_memory            = agp_generic_mask_memory,
1652         .masks                  = intel_generic_masks,
1653         .agp_enable             = agp_generic_enable,
1654         .cache_flush            = global_cache_flush,
1655         .create_gatt_table      = agp_generic_create_gatt_table,
1656         .free_gatt_table        = agp_generic_free_gatt_table,
1657         .insert_memory          = agp_generic_insert_memory,
1658         .remove_memory          = agp_generic_remove_memory,
1659         .alloc_by_type          = agp_generic_alloc_by_type,
1660         .free_by_type           = agp_generic_free_by_type,
1661         .agp_alloc_page         = agp_generic_alloc_page,
1662         .agp_destroy_page       = agp_generic_destroy_page,
1663         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1664 };
1665
1666 static const struct agp_bridge_driver intel_860_driver = {
1667         .owner                  = THIS_MODULE,
1668         .aperture_sizes         = intel_8xx_sizes,
1669         .size_type              = U8_APER_SIZE,
1670         .num_aperture_sizes     = 7,
1671         .configure              = intel_860_configure,
1672         .fetch_size             = intel_8xx_fetch_size,
1673         .cleanup                = intel_8xx_cleanup,
1674         .tlb_flush              = intel_8xx_tlbflush,
1675         .mask_memory            = agp_generic_mask_memory,
1676         .masks                  = intel_generic_masks,
1677         .agp_enable             = agp_generic_enable,
1678         .cache_flush            = global_cache_flush,
1679         .create_gatt_table      = agp_generic_create_gatt_table,
1680         .free_gatt_table        = agp_generic_free_gatt_table,
1681         .insert_memory          = agp_generic_insert_memory,
1682         .remove_memory          = agp_generic_remove_memory,
1683         .alloc_by_type          = agp_generic_alloc_by_type,
1684         .free_by_type           = agp_generic_free_by_type,
1685         .agp_alloc_page         = agp_generic_alloc_page,
1686         .agp_destroy_page       = agp_generic_destroy_page,
1687         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1688 };
1689
1690 static const struct agp_bridge_driver intel_915_driver = {
1691         .owner                  = THIS_MODULE,
1692         .aperture_sizes         = intel_i830_sizes,
1693         .size_type              = FIXED_APER_SIZE,
1694         .num_aperture_sizes     = 4,
1695         .needs_scratch_page     = TRUE,
1696         .configure              = intel_i915_configure,
1697         .fetch_size             = intel_i9xx_fetch_size,
1698         .cleanup                = intel_i915_cleanup,
1699         .tlb_flush              = intel_i810_tlbflush,
1700         .mask_memory            = intel_i810_mask_memory,
1701         .masks                  = intel_i810_masks,
1702         .agp_enable             = intel_i810_agp_enable,
1703         .cache_flush            = global_cache_flush,
1704         .create_gatt_table      = intel_i915_create_gatt_table,
1705         .free_gatt_table        = intel_i830_free_gatt_table,
1706         .insert_memory          = intel_i915_insert_entries,
1707         .remove_memory          = intel_i915_remove_entries,
1708         .alloc_by_type          = intel_i830_alloc_by_type,
1709         .free_by_type           = intel_i810_free_by_type,
1710         .agp_alloc_page         = agp_generic_alloc_page,
1711         .agp_destroy_page       = agp_generic_destroy_page,
1712         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1713 };
1714
1715 static const struct agp_bridge_driver intel_i965_driver = {
1716        .owner                  = THIS_MODULE,
1717        .aperture_sizes         = intel_i830_sizes,
1718        .size_type              = FIXED_APER_SIZE,
1719        .num_aperture_sizes     = 4,
1720        .needs_scratch_page     = TRUE,
1721        .configure              = intel_i915_configure,
1722        .fetch_size             = intel_i9xx_fetch_size,
1723        .cleanup                = intel_i915_cleanup,
1724        .tlb_flush              = intel_i810_tlbflush,
1725        .mask_memory            = intel_i965_mask_memory,
1726        .masks                  = intel_i810_masks,
1727        .agp_enable             = intel_i810_agp_enable,
1728        .cache_flush            = global_cache_flush,
1729        .create_gatt_table      = intel_i965_create_gatt_table,
1730        .free_gatt_table        = intel_i830_free_gatt_table,
1731        .insert_memory          = intel_i915_insert_entries,
1732        .remove_memory          = intel_i915_remove_entries,
1733        .alloc_by_type          = intel_i830_alloc_by_type,
1734        .free_by_type           = intel_i810_free_by_type,
1735        .agp_alloc_page         = agp_generic_alloc_page,
1736        .agp_destroy_page       = agp_generic_destroy_page,
1737        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1738 };
1739
1740 static const struct agp_bridge_driver intel_7505_driver = {
1741         .owner                  = THIS_MODULE,
1742         .aperture_sizes         = intel_8xx_sizes,
1743         .size_type              = U8_APER_SIZE,
1744         .num_aperture_sizes     = 7,
1745         .configure              = intel_7505_configure,
1746         .fetch_size             = intel_8xx_fetch_size,
1747         .cleanup                = intel_8xx_cleanup,
1748         .tlb_flush              = intel_8xx_tlbflush,
1749         .mask_memory            = agp_generic_mask_memory,
1750         .masks                  = intel_generic_masks,
1751         .agp_enable             = agp_generic_enable,
1752         .cache_flush            = global_cache_flush,
1753         .create_gatt_table      = agp_generic_create_gatt_table,
1754         .free_gatt_table        = agp_generic_free_gatt_table,
1755         .insert_memory          = agp_generic_insert_memory,
1756         .remove_memory          = agp_generic_remove_memory,
1757         .alloc_by_type          = agp_generic_alloc_by_type,
1758         .free_by_type           = agp_generic_free_by_type,
1759         .agp_alloc_page         = agp_generic_alloc_page,
1760         .agp_destroy_page       = agp_generic_destroy_page,
1761         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1762 };
1763
1764 static const struct agp_bridge_driver intel_g33_driver = {
1765         .owner                  = THIS_MODULE,
1766         .aperture_sizes         = intel_i830_sizes,
1767         .size_type              = FIXED_APER_SIZE,
1768         .num_aperture_sizes     = 4,
1769         .needs_scratch_page     = TRUE,
1770         .configure              = intel_i915_configure,
1771         .fetch_size             = intel_i9xx_fetch_size,
1772         .cleanup                = intel_i915_cleanup,
1773         .tlb_flush              = intel_i810_tlbflush,
1774         .mask_memory            = intel_i965_mask_memory,
1775         .masks                  = intel_i810_masks,
1776         .agp_enable             = intel_i810_agp_enable,
1777         .cache_flush            = global_cache_flush,
1778         .create_gatt_table      = intel_i915_create_gatt_table,
1779         .free_gatt_table        = intel_i830_free_gatt_table,
1780         .insert_memory          = intel_i915_insert_entries,
1781         .remove_memory          = intel_i915_remove_entries,
1782         .alloc_by_type          = intel_i830_alloc_by_type,
1783         .free_by_type           = intel_i810_free_by_type,
1784         .agp_alloc_page         = agp_generic_alloc_page,
1785         .agp_destroy_page       = agp_generic_destroy_page,
1786         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1787 };
1788
1789 static int find_gmch(u16 device)
1790 {
1791         struct pci_dev *gmch_device;
1792
1793         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1794         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1795                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1796                                 device, gmch_device);
1797         }
1798
1799         if (!gmch_device)
1800                 return 0;
1801
1802         intel_private.pcidev = gmch_device;
1803         return 1;
1804 }
1805
1806 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1807  * driver and gmch_driver must be non-null, and find_gmch will determine
1808  * which one should be used if a gmch_chip_id is present.
1809  */
1810 static const struct intel_driver_description {
1811         unsigned int chip_id;
1812         unsigned int gmch_chip_id;
1813         char *name;
1814         const struct agp_bridge_driver *driver;
1815         const struct agp_bridge_driver *gmch_driver;
1816 } intel_agp_chipsets[] = {
1817         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL },
1818         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL },
1819         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL },
1820         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1821                 NULL, &intel_810_driver },
1822         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1823                 NULL, &intel_810_driver },
1824         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1825                 NULL, &intel_810_driver },
1826         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1827                 &intel_810_driver, &intel_815_driver },
1828         { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL },
1829         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL },
1830         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1831                 &intel_830mp_driver, &intel_830_driver },
1832         { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL },
1833         { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL },
1834         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1835                 &intel_845_driver, &intel_830_driver },
1836         { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL },
1837         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
1838         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1839                 &intel_845_driver, &intel_830_driver },
1840         { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
1841         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
1842                 &intel_845_driver, &intel_830_driver },
1843         { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
1844         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1845                 &intel_845_driver, &intel_915_driver },
1846         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1847                 &intel_845_driver, &intel_915_driver },
1848         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1849                 &intel_845_driver, &intel_915_driver },
1850         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1851                 &intel_845_driver, &intel_915_driver },
1852         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1853                 &intel_845_driver, &intel_915_driver },
1854         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1855                 &intel_845_driver, &intel_i965_driver },
1856         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, "965G",
1857                 &intel_845_driver, &intel_i965_driver },
1858         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1859                 &intel_845_driver, &intel_i965_driver },
1860         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1861                 &intel_845_driver, &intel_i965_driver },
1862         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1863                 &intel_845_driver, &intel_i965_driver },
1864         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1865                 &intel_845_driver, &intel_i965_driver },
1866         { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
1867         { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
1868         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1869                 &intel_845_driver, &intel_g33_driver },
1870         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1871                 &intel_845_driver, &intel_g33_driver },
1872         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1873                 &intel_845_driver, &intel_g33_driver },
1874         { 0, 0, NULL, NULL, NULL }
1875 };
1876
1877 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1878                                      const struct pci_device_id *ent)
1879 {
1880         struct agp_bridge_data *bridge;
1881         u8 cap_ptr = 0;
1882         struct resource *r;
1883         int i;
1884
1885         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1886
1887         bridge = agp_alloc_bridge();
1888         if (!bridge)
1889                 return -ENOMEM;
1890
1891         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1892                 /* In case that multiple models of gfx chip may
1893                    stand on same host bridge type, this can be
1894                    sure we detect the right IGD. */
1895                 if ((pdev->device == intel_agp_chipsets[i].chip_id) &&
1896                         ((intel_agp_chipsets[i].gmch_chip_id == 0) ||
1897                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)))
1898                         break;
1899         }
1900
1901         if (intel_agp_chipsets[i].name == NULL) {
1902                 if (cap_ptr)
1903                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1904                                "(device id: %04x)\n", pdev->device);
1905                 agp_put_bridge(bridge);
1906                 return -ENODEV;
1907         }
1908
1909         if (intel_agp_chipsets[i].gmch_chip_id != 0)
1910             bridge->driver = intel_agp_chipsets[i].gmch_driver;
1911         else
1912             bridge->driver = intel_agp_chipsets[i].driver;
1913
1914         if (bridge->driver == NULL) {
1915                 printk(KERN_WARNING PFX "Failed to find bridge device "
1916                         "(chip_id: %04x)\n", intel_agp_chipsets[i].gmch_chip_id);
1917                 agp_put_bridge(bridge);
1918                 return -ENODEV;
1919         }
1920
1921         bridge->dev = pdev;
1922         bridge->capndx = cap_ptr;
1923         bridge->dev_private_data = &intel_private;
1924
1925         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1926                 intel_agp_chipsets[i].name);
1927
1928         /*
1929         * The following fixes the case where the BIOS has "forgotten" to
1930         * provide an address range for the GART.
1931         * 20030610 - hamish@zot.org
1932         */
1933         r = &pdev->resource[0];
1934         if (!r->start && r->end) {
1935                 if (pci_assign_resource(pdev, 0)) {
1936                         printk(KERN_ERR PFX "could not assign resource 0\n");
1937                         agp_put_bridge(bridge);
1938                         return -ENODEV;
1939                 }
1940         }
1941
1942         /*
1943         * If the device has not been properly setup, the following will catch
1944         * the problem and should stop the system from crashing.
1945         * 20030610 - hamish@zot.org
1946         */
1947         if (pci_enable_device(pdev)) {
1948                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1949                 agp_put_bridge(bridge);
1950                 return -ENODEV;
1951         }
1952
1953         /* Fill in the mode register */
1954         if (cap_ptr) {
1955                 pci_read_config_dword(pdev,
1956                                 bridge->capndx+PCI_AGP_STATUS,
1957                                 &bridge->mode);
1958         }
1959
1960         pci_set_drvdata(pdev, bridge);
1961         return agp_add_bridge(bridge);
1962 }
1963
1964 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1965 {
1966         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1967
1968         agp_remove_bridge(bridge);
1969
1970         if (intel_private.pcidev)
1971                 pci_dev_put(intel_private.pcidev);
1972
1973         agp_put_bridge(bridge);
1974 }
1975
1976 #ifdef CONFIG_PM
1977 static int agp_intel_resume(struct pci_dev *pdev)
1978 {
1979         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1980
1981         pci_restore_state(pdev);
1982
1983         /* We should restore our graphics device's config space,
1984          * as host bridge (00:00) resumes before graphics device (02:00),
1985          * then our access to its pci space can work right.
1986          */
1987         if (intel_private.pcidev)
1988                 pci_restore_state(intel_private.pcidev);
1989
1990         if (bridge->driver == &intel_generic_driver)
1991                 intel_configure();
1992         else if (bridge->driver == &intel_850_driver)
1993                 intel_850_configure();
1994         else if (bridge->driver == &intel_845_driver)
1995                 intel_845_configure();
1996         else if (bridge->driver == &intel_830mp_driver)
1997                 intel_830mp_configure();
1998         else if (bridge->driver == &intel_915_driver)
1999                 intel_i915_configure();
2000         else if (bridge->driver == &intel_830_driver)
2001                 intel_i830_configure();
2002         else if (bridge->driver == &intel_810_driver)
2003                 intel_i810_configure();
2004         else if (bridge->driver == &intel_i965_driver)
2005                 intel_i915_configure();
2006
2007         return 0;
2008 }
2009 #endif
2010
2011 static struct pci_device_id agp_intel_pci_table[] = {
2012 #define ID(x)                                           \
2013         {                                               \
2014         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2015         .class_mask     = ~0,                           \
2016         .vendor         = PCI_VENDOR_ID_INTEL,          \
2017         .device         = x,                            \
2018         .subvendor      = PCI_ANY_ID,                   \
2019         .subdevice      = PCI_ANY_ID,                   \
2020         }
2021         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2022         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2023         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2024         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2025         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2026         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2027         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2028         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2029         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2030         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2031         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2032         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2033         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2034         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2035         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2036         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2037         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2038         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2039         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2040         ID(PCI_DEVICE_ID_INTEL_7505_0),
2041         ID(PCI_DEVICE_ID_INTEL_7205_0),
2042         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2043         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2044         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2045         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2046         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2047         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2048         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2049         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2050         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2051         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2052         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2053         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2054         { }
2055 };
2056
2057 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2058
2059 static struct pci_driver agp_intel_pci_driver = {
2060         .name           = "agpgart-intel",
2061         .id_table       = agp_intel_pci_table,
2062         .probe          = agp_intel_probe,
2063         .remove         = __devexit_p(agp_intel_remove),
2064 #ifdef CONFIG_PM
2065         .resume         = agp_intel_resume,
2066 #endif
2067 };
2068
2069 static int __init agp_intel_init(void)
2070 {
2071         if (agp_off)
2072                 return -EINVAL;
2073         return pci_register_driver(&agp_intel_pci_driver);
2074 }
2075
2076 static void __exit agp_intel_cleanup(void)
2077 {
2078         pci_unregister_driver(&agp_intel_pci_driver);
2079 }
2080
2081 module_init(agp_intel_init);
2082 module_exit(agp_intel_cleanup);
2083
2084 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2085 MODULE_LICENSE("GPL and additional rights");