]> nv-tegra.nvidia Code Review - linux-2.6.git/blob - drivers/char/agp/intel-agp.c
[AGPGART] intel_agp: add support for 945GME
[linux-2.6.git] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
24 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
25
26 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
27                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
28                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
29                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
30                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB)
31
32
33 extern int agp_memory_reserved;
34
35
36 /* Intel 815 register */
37 #define INTEL_815_APCONT        0x51
38 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
39
40 /* Intel i820 registers */
41 #define INTEL_I820_RDCR         0x51
42 #define INTEL_I820_ERRSTS       0xc8
43
44 /* Intel i840 registers */
45 #define INTEL_I840_MCHCFG       0x50
46 #define INTEL_I840_ERRSTS       0xc8
47
48 /* Intel i850 registers */
49 #define INTEL_I850_MCHCFG       0x50
50 #define INTEL_I850_ERRSTS       0xc8
51
52 /* intel 915G registers */
53 #define I915_GMADDR     0x18
54 #define I915_MMADDR     0x10
55 #define I915_PTEADDR    0x1C
56 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
57 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
58
59 /* Intel 965G registers */
60 #define I965_MSAC 0x62
61
62 /* Intel 7505 registers */
63 #define INTEL_I7505_APSIZE      0x74
64 #define INTEL_I7505_NCAPID      0x60
65 #define INTEL_I7505_NISTAT      0x6c
66 #define INTEL_I7505_ATTBASE     0x78
67 #define INTEL_I7505_ERRSTS      0x42
68 #define INTEL_I7505_AGPCTRL     0x70
69 #define INTEL_I7505_MCHCFG      0x50
70
71 static const struct aper_size_info_fixed intel_i810_sizes[] =
72 {
73         {64, 16384, 4},
74         /* The 32M mode still requires a 64k gatt */
75         {32, 8192, 4}
76 };
77
78 #define AGP_DCACHE_MEMORY       1
79 #define AGP_PHYS_MEMORY         2
80 #define INTEL_AGP_CACHED_MEMORY 3
81
82 static struct gatt_mask intel_i810_masks[] =
83 {
84         {.mask = I810_PTE_VALID, .type = 0},
85         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
86         {.mask = I810_PTE_VALID, .type = 0},
87         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
88          .type = INTEL_AGP_CACHED_MEMORY}
89 };
90
91 static struct _intel_private {
92         struct pci_dev *pcidev; /* device one */
93         u8 __iomem *registers;
94         u32 __iomem *gtt;               /* I915G */
95         int num_dcache_entries;
96         /* gtt_entries is the number of gtt entries that are already mapped
97          * to stolen memory.  Stolen memory is larger than the memory mapped
98          * through gtt_entries, as it includes some reserved space for the BIOS
99          * popup and for the GTT.
100          */
101         int gtt_entries;                        /* i830+ */
102 } intel_private;
103
104 static int intel_i810_fetch_size(void)
105 {
106         u32 smram_miscc;
107         struct aper_size_info_fixed *values;
108
109         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
110         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
111
112         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
113                 printk(KERN_WARNING PFX "i810 is disabled\n");
114                 return 0;
115         }
116         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
117                 agp_bridge->previous_size =
118                         agp_bridge->current_size = (void *) (values + 1);
119                 agp_bridge->aperture_size_idx = 1;
120                 return values[1].size;
121         } else {
122                 agp_bridge->previous_size =
123                         agp_bridge->current_size = (void *) (values);
124                 agp_bridge->aperture_size_idx = 0;
125                 return values[0].size;
126         }
127
128         return 0;
129 }
130
131 static int intel_i810_configure(void)
132 {
133         struct aper_size_info_fixed *current_size;
134         u32 temp;
135         int i;
136
137         current_size = A_SIZE_FIX(agp_bridge->current_size);
138
139         if (!intel_private.registers) {
140                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
141                 temp &= 0xfff80000;
142
143                 intel_private.registers = ioremap(temp, 128 * 4096);
144                 if (!intel_private.registers) {
145                         printk(KERN_ERR PFX "Unable to remap memory.\n");
146                         return -ENOMEM;
147                 }
148         }
149
150         if ((readl(intel_private.registers+I810_DRAM_CTL)
151                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
152                 /* This will need to be dynamically assigned */
153                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
154                 intel_private.num_dcache_entries = 1024;
155         }
156         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
157         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
158         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
159         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
160
161         if (agp_bridge->driver->needs_scratch_page) {
162                 for (i = 0; i < current_size->num_entries; i++) {
163                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
164                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
165                 }
166         }
167         global_cache_flush();
168         return 0;
169 }
170
171 static void intel_i810_cleanup(void)
172 {
173         writel(0, intel_private.registers+I810_PGETBL_CTL);
174         readl(intel_private.registers); /* PCI Posting. */
175         iounmap(intel_private.registers);
176 }
177
178 static void intel_i810_tlbflush(struct agp_memory *mem)
179 {
180         return;
181 }
182
183 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
184 {
185         return;
186 }
187
188 /* Exists to support ARGB cursors */
189 static void *i8xx_alloc_pages(void)
190 {
191         struct page * page;
192
193         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
194         if (page == NULL)
195                 return NULL;
196
197         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
198                 change_page_attr(page, 4, PAGE_KERNEL);
199                 global_flush_tlb();
200                 __free_pages(page, 2);
201                 return NULL;
202         }
203         global_flush_tlb();
204         get_page(page);
205         SetPageLocked(page);
206         atomic_inc(&agp_bridge->current_memory_agp);
207         return page_address(page);
208 }
209
210 static void i8xx_destroy_pages(void *addr)
211 {
212         struct page *page;
213
214         if (addr == NULL)
215                 return;
216
217         page = virt_to_page(addr);
218         change_page_attr(page, 4, PAGE_KERNEL);
219         global_flush_tlb();
220         put_page(page);
221         unlock_page(page);
222         __free_pages(page, 2);
223         atomic_dec(&agp_bridge->current_memory_agp);
224 }
225
226 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
227                                         int type)
228 {
229         if (type < AGP_USER_TYPES)
230                 return type;
231         else if (type == AGP_USER_CACHED_MEMORY)
232                 return INTEL_AGP_CACHED_MEMORY;
233         else
234                 return 0;
235 }
236
237 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
238                                 int type)
239 {
240         int i, j, num_entries;
241         void *temp;
242         int ret = -EINVAL;
243         int mask_type;
244
245         if (mem->page_count == 0)
246                 goto out;
247
248         temp = agp_bridge->current_size;
249         num_entries = A_SIZE_FIX(temp)->num_entries;
250
251         if ((pg_start + mem->page_count) > num_entries)
252                 goto out_err;
253
254
255         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
256                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
257                         ret = -EBUSY;
258                         goto out_err;
259                 }
260         }
261
262         if (type != mem->type)
263                 goto out_err;
264
265         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
266
267         switch (mask_type) {
268         case AGP_DCACHE_MEMORY:
269                 if (!mem->is_flushed)
270                         global_cache_flush();
271                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
272                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
273                                intel_private.registers+I810_PTE_BASE+(i*4));
274                 }
275                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
276                 break;
277         case AGP_PHYS_MEMORY:
278         case AGP_NORMAL_MEMORY:
279                 if (!mem->is_flushed)
280                         global_cache_flush();
281                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
282                         writel(agp_bridge->driver->mask_memory(agp_bridge,
283                                                                mem->memory[i],
284                                                                mask_type),
285                                intel_private.registers+I810_PTE_BASE+(j*4));
286                 }
287                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
288                 break;
289         default:
290                 goto out_err;
291         }
292
293         agp_bridge->driver->tlb_flush(mem);
294 out:
295         ret = 0;
296 out_err:
297         mem->is_flushed = 1;
298         return ret;
299 }
300
301 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
302                                 int type)
303 {
304         int i;
305
306         if (mem->page_count == 0)
307                 return 0;
308
309         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
310                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
311         }
312         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
313
314         agp_bridge->driver->tlb_flush(mem);
315         return 0;
316 }
317
318 /*
319  * The i810/i830 requires a physical address to program its mouse
320  * pointer into hardware.
321  * However the Xserver still writes to it through the agp aperture.
322  */
323 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
324 {
325         struct agp_memory *new;
326         void *addr;
327
328         switch (pg_count) {
329         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
330                 global_flush_tlb();
331                 break;
332         case 4:
333                 /* kludge to get 4 physical pages for ARGB cursor */
334                 addr = i8xx_alloc_pages();
335                 break;
336         default:
337                 return NULL;
338         }
339
340         if (addr == NULL)
341                 return NULL;
342
343         new = agp_create_memory(pg_count);
344         if (new == NULL)
345                 return NULL;
346
347         new->memory[0] = virt_to_gart(addr);
348         if (pg_count == 4) {
349                 /* kludge to get 4 physical pages for ARGB cursor */
350                 new->memory[1] = new->memory[0] + PAGE_SIZE;
351                 new->memory[2] = new->memory[1] + PAGE_SIZE;
352                 new->memory[3] = new->memory[2] + PAGE_SIZE;
353         }
354         new->page_count = pg_count;
355         new->num_scratch_pages = pg_count;
356         new->type = AGP_PHYS_MEMORY;
357         new->physical = new->memory[0];
358         return new;
359 }
360
361 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
362 {
363         struct agp_memory *new;
364
365         if (type == AGP_DCACHE_MEMORY) {
366                 if (pg_count != intel_private.num_dcache_entries)
367                         return NULL;
368
369                 new = agp_create_memory(1);
370                 if (new == NULL)
371                         return NULL;
372
373                 new->type = AGP_DCACHE_MEMORY;
374                 new->page_count = pg_count;
375                 new->num_scratch_pages = 0;
376                 agp_free_page_array(new);
377                 return new;
378         }
379         if (type == AGP_PHYS_MEMORY)
380                 return alloc_agpphysmem_i8xx(pg_count, type);
381         return NULL;
382 }
383
384 static void intel_i810_free_by_type(struct agp_memory *curr)
385 {
386         agp_free_key(curr->key);
387         if (curr->type == AGP_PHYS_MEMORY) {
388                 if (curr->page_count == 4)
389                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
390                 else {
391                         agp_bridge->driver->agp_destroy_page(
392                                  gart_to_virt(curr->memory[0]));
393                         global_flush_tlb();
394                 }
395                 agp_free_page_array(curr);
396         }
397         kfree(curr);
398 }
399
400 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
401         unsigned long addr, int type)
402 {
403         /* Type checking must be done elsewhere */
404         return addr | bridge->driver->masks[type].mask;
405 }
406
407 static struct aper_size_info_fixed intel_i830_sizes[] =
408 {
409         {128, 32768, 5},
410         /* The 64M mode still requires a 128k gatt */
411         {64, 16384, 5},
412         {256, 65536, 6},
413         {512, 131072, 7},
414 };
415
416 static void intel_i830_init_gtt_entries(void)
417 {
418         u16 gmch_ctrl;
419         int gtt_entries;
420         u8 rdct;
421         int local = 0;
422         static const int ddt[4] = { 0, 16, 32, 64 };
423         int size; /* reserved space (in kb) at the top of stolen memory */
424
425         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
426
427         if (IS_I965) {
428                 u32 pgetbl_ctl;
429                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
430
431                 /* The 965 has a field telling us the size of the GTT,
432                  * which may be larger than what is necessary to map the
433                  * aperture.
434                  */
435                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
436                 case I965_PGETBL_SIZE_128KB:
437                         size = 128;
438                         break;
439                 case I965_PGETBL_SIZE_256KB:
440                         size = 256;
441                         break;
442                 case I965_PGETBL_SIZE_512KB:
443                         size = 512;
444                         break;
445                 default:
446                         printk(KERN_INFO PFX "Unknown page table size, "
447                                "assuming 512KB\n");
448                         size = 512;
449                 }
450                 size += 4; /* add in BIOS popup space */
451         } else {
452                 /* On previous hardware, the GTT size was just what was
453                  * required to map the aperture.
454                  */
455                 size = agp_bridge->driver->fetch_size() + 4;
456         }
457
458         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
459             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
460                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
461                 case I830_GMCH_GMS_STOLEN_512:
462                         gtt_entries = KB(512) - KB(size);
463                         break;
464                 case I830_GMCH_GMS_STOLEN_1024:
465                         gtt_entries = MB(1) - KB(size);
466                         break;
467                 case I830_GMCH_GMS_STOLEN_8192:
468                         gtt_entries = MB(8) - KB(size);
469                         break;
470                 case I830_GMCH_GMS_LOCAL:
471                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
472                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
473                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
474                         local = 1;
475                         break;
476                 default:
477                         gtt_entries = 0;
478                         break;
479                 }
480         } else {
481                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
482                 case I855_GMCH_GMS_STOLEN_1M:
483                         gtt_entries = MB(1) - KB(size);
484                         break;
485                 case I855_GMCH_GMS_STOLEN_4M:
486                         gtt_entries = MB(4) - KB(size);
487                         break;
488                 case I855_GMCH_GMS_STOLEN_8M:
489                         gtt_entries = MB(8) - KB(size);
490                         break;
491                 case I855_GMCH_GMS_STOLEN_16M:
492                         gtt_entries = MB(16) - KB(size);
493                         break;
494                 case I855_GMCH_GMS_STOLEN_32M:
495                         gtt_entries = MB(32) - KB(size);
496                         break;
497                 case I915_GMCH_GMS_STOLEN_48M:
498                         /* Check it's really I915G */
499                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
500                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
501                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
502                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
503                                 gtt_entries = MB(48) - KB(size);
504                         else
505                                 gtt_entries = 0;
506                         break;
507                 case I915_GMCH_GMS_STOLEN_64M:
508                         /* Check it's really I915G */
509                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
510                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
511                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
512                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
513                                 gtt_entries = MB(64) - KB(size);
514                         else
515                                 gtt_entries = 0;
516                 default:
517                         gtt_entries = 0;
518                         break;
519                 }
520         }
521         if (gtt_entries > 0)
522                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
523                        gtt_entries / KB(1), local ? "local" : "stolen");
524         else
525                 printk(KERN_INFO PFX
526                        "No pre-allocated video memory detected.\n");
527         gtt_entries /= KB(4);
528
529         intel_private.gtt_entries = gtt_entries;
530 }
531
532 /* The intel i830 automatically initializes the agp aperture during POST.
533  * Use the memory already set aside for in the GTT.
534  */
535 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
536 {
537         int page_order;
538         struct aper_size_info_fixed *size;
539         int num_entries;
540         u32 temp;
541
542         size = agp_bridge->current_size;
543         page_order = size->page_order;
544         num_entries = size->num_entries;
545         agp_bridge->gatt_table_real = NULL;
546
547         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
548         temp &= 0xfff80000;
549
550         intel_private.registers = ioremap(temp,128 * 4096);
551         if (!intel_private.registers)
552                 return -ENOMEM;
553
554         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
555         global_cache_flush();   /* FIXME: ?? */
556
557         /* we have to call this as early as possible after the MMIO base address is known */
558         intel_i830_init_gtt_entries();
559
560         agp_bridge->gatt_table = NULL;
561
562         agp_bridge->gatt_bus_addr = temp;
563
564         return 0;
565 }
566
567 /* Return the gatt table to a sane state. Use the top of stolen
568  * memory for the GTT.
569  */
570 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
571 {
572         return 0;
573 }
574
575 static int intel_i830_fetch_size(void)
576 {
577         u16 gmch_ctrl;
578         struct aper_size_info_fixed *values;
579
580         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
581
582         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
583             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
584                 /* 855GM/852GM/865G has 128MB aperture size */
585                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
586                 agp_bridge->aperture_size_idx = 0;
587                 return values[0].size;
588         }
589
590         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
591
592         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
593                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
594                 agp_bridge->aperture_size_idx = 0;
595                 return values[0].size;
596         } else {
597                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
598                 agp_bridge->aperture_size_idx = 1;
599                 return values[1].size;
600         }
601
602         return 0;
603 }
604
605 static int intel_i830_configure(void)
606 {
607         struct aper_size_info_fixed *current_size;
608         u32 temp;
609         u16 gmch_ctrl;
610         int i;
611
612         current_size = A_SIZE_FIX(agp_bridge->current_size);
613
614         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
615         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
616
617         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
618         gmch_ctrl |= I830_GMCH_ENABLED;
619         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
620
621         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
622         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
623
624         if (agp_bridge->driver->needs_scratch_page) {
625                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
626                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
627                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
628                 }
629         }
630
631         global_cache_flush();
632         return 0;
633 }
634
635 static void intel_i830_cleanup(void)
636 {
637         iounmap(intel_private.registers);
638 }
639
640 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
641 {
642         int i,j,num_entries;
643         void *temp;
644         int ret = -EINVAL;
645         int mask_type;
646
647         if (mem->page_count == 0)
648                 goto out;
649
650         temp = agp_bridge->current_size;
651         num_entries = A_SIZE_FIX(temp)->num_entries;
652
653         if (pg_start < intel_private.gtt_entries) {
654                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
655                                 pg_start,intel_private.gtt_entries);
656
657                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
658                 goto out_err;
659         }
660
661         if ((pg_start + mem->page_count) > num_entries)
662                 goto out_err;
663
664         /* The i830 can't check the GTT for entries since its read only,
665          * depend on the caller to make the correct offset decisions.
666          */
667
668         if (type != mem->type)
669                 goto out_err;
670
671         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
672
673         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
674             mask_type != INTEL_AGP_CACHED_MEMORY)
675                 goto out_err;
676
677         if (!mem->is_flushed)
678                 global_cache_flush();
679
680         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
681                 writel(agp_bridge->driver->mask_memory(agp_bridge,
682                                                        mem->memory[i], mask_type),
683                        intel_private.registers+I810_PTE_BASE+(j*4));
684         }
685         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
686         agp_bridge->driver->tlb_flush(mem);
687
688 out:
689         ret = 0;
690 out_err:
691         mem->is_flushed = 1;
692         return ret;
693 }
694
695 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
696                                 int type)
697 {
698         int i;
699
700         if (mem->page_count == 0)
701                 return 0;
702
703         if (pg_start < intel_private.gtt_entries) {
704                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
705                 return -EINVAL;
706         }
707
708         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
709                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
710         }
711         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
712
713         agp_bridge->driver->tlb_flush(mem);
714         return 0;
715 }
716
717 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
718 {
719         if (type == AGP_PHYS_MEMORY)
720                 return alloc_agpphysmem_i8xx(pg_count, type);
721         /* always return NULL for other allocation types for now */
722         return NULL;
723 }
724
725 static int intel_i915_configure(void)
726 {
727         struct aper_size_info_fixed *current_size;
728         u32 temp;
729         u16 gmch_ctrl;
730         int i;
731
732         current_size = A_SIZE_FIX(agp_bridge->current_size);
733
734         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
735
736         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
737
738         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
739         gmch_ctrl |= I830_GMCH_ENABLED;
740         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
741
742         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
743         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
744
745         if (agp_bridge->driver->needs_scratch_page) {
746                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
747                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
748                         readl(intel_private.gtt+i);     /* PCI Posting. */
749                 }
750         }
751
752         global_cache_flush();
753         return 0;
754 }
755
756 static void intel_i915_cleanup(void)
757 {
758         iounmap(intel_private.gtt);
759         iounmap(intel_private.registers);
760 }
761
762 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
763                                 int type)
764 {
765         int i,j,num_entries;
766         void *temp;
767         int ret = -EINVAL;
768         int mask_type;
769
770         if (mem->page_count == 0)
771                 goto out;
772
773         temp = agp_bridge->current_size;
774         num_entries = A_SIZE_FIX(temp)->num_entries;
775
776         if (pg_start < intel_private.gtt_entries) {
777                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
778                                 pg_start,intel_private.gtt_entries);
779
780                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
781                 goto out_err;
782         }
783
784         if ((pg_start + mem->page_count) > num_entries)
785                 goto out_err;
786
787         /* The i915 can't check the GTT for entries since its read only,
788          * depend on the caller to make the correct offset decisions.
789          */
790
791         if (type != mem->type)
792                 goto out_err;
793
794         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
795
796         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
797             mask_type != INTEL_AGP_CACHED_MEMORY)
798                 goto out_err;
799
800         if (!mem->is_flushed)
801                 global_cache_flush();
802
803         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
804                 writel(agp_bridge->driver->mask_memory(agp_bridge,
805                         mem->memory[i], mask_type), intel_private.gtt+j);
806         }
807
808         readl(intel_private.gtt+j-1);
809         agp_bridge->driver->tlb_flush(mem);
810
811  out:
812         ret = 0;
813  out_err:
814         mem->is_flushed = 1;
815         return ret;
816 }
817
818 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
819                                 int type)
820 {
821         int i;
822
823         if (mem->page_count == 0)
824                 return 0;
825
826         if (pg_start < intel_private.gtt_entries) {
827                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
828                 return -EINVAL;
829         }
830
831         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
832                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
833         }
834         readl(intel_private.gtt+i-1);
835
836         agp_bridge->driver->tlb_flush(mem);
837         return 0;
838 }
839
840 /* Return the aperture size by just checking the resource length.  The effect
841  * described in the spec of the MSAC registers is just changing of the
842  * resource size.
843  */
844 static int intel_i9xx_fetch_size(void)
845 {
846         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
847         int aper_size; /* size in megabytes */
848         int i;
849
850         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
851
852         for (i = 0; i < num_sizes; i++) {
853                 if (aper_size == intel_i830_sizes[i].size) {
854                         agp_bridge->current_size = intel_i830_sizes + i;
855                         agp_bridge->previous_size = agp_bridge->current_size;
856                         return aper_size;
857                 }
858         }
859
860         return 0;
861 }
862
863 /* The intel i915 automatically initializes the agp aperture during POST.
864  * Use the memory already set aside for in the GTT.
865  */
866 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
867 {
868         int page_order;
869         struct aper_size_info_fixed *size;
870         int num_entries;
871         u32 temp, temp2;
872
873         size = agp_bridge->current_size;
874         page_order = size->page_order;
875         num_entries = size->num_entries;
876         agp_bridge->gatt_table_real = NULL;
877
878         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
879         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
880
881         intel_private.gtt = ioremap(temp2, 256 * 1024);
882         if (!intel_private.gtt)
883                 return -ENOMEM;
884
885         temp &= 0xfff80000;
886
887         intel_private.registers = ioremap(temp,128 * 4096);
888         if (!intel_private.registers)
889                 return -ENOMEM;
890
891         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
892         global_cache_flush();   /* FIXME: ? */
893
894         /* we have to call this as early as possible after the MMIO base address is known */
895         intel_i830_init_gtt_entries();
896
897         agp_bridge->gatt_table = NULL;
898
899         agp_bridge->gatt_bus_addr = temp;
900
901         return 0;
902 }
903
904 /*
905  * The i965 supports 36-bit physical addresses, but to keep
906  * the format of the GTT the same, the bits that don't fit
907  * in a 32-bit word are shifted down to bits 4..7.
908  *
909  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
910  * is always zero on 32-bit architectures, so no need to make
911  * this conditional.
912  */
913 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
914         unsigned long addr, int type)
915 {
916         /* Shift high bits down */
917         addr |= (addr >> 28) & 0xf0;
918
919         /* Type checking must be done elsewhere */
920         return addr | bridge->driver->masks[type].mask;
921 }
922
923 /* The intel i965 automatically initializes the agp aperture during POST.
924  * Use the memory already set aside for in the GTT.
925  */
926 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
927 {
928        int page_order;
929        struct aper_size_info_fixed *size;
930        int num_entries;
931        u32 temp;
932
933        size = agp_bridge->current_size;
934        page_order = size->page_order;
935        num_entries = size->num_entries;
936        agp_bridge->gatt_table_real = NULL;
937
938        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
939
940        temp &= 0xfff00000;
941        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
942
943        if (!intel_private.gtt)
944                return -ENOMEM;
945
946
947        intel_private.registers = ioremap(temp,128 * 4096);
948        if (!intel_private.registers)
949                return -ENOMEM;
950
951        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
952        global_cache_flush();   /* FIXME: ? */
953
954        /* we have to call this as early as possible after the MMIO base address is known */
955        intel_i830_init_gtt_entries();
956
957        agp_bridge->gatt_table = NULL;
958
959        agp_bridge->gatt_bus_addr = temp;
960
961        return 0;
962 }
963
964
965 static int intel_fetch_size(void)
966 {
967         int i;
968         u16 temp;
969         struct aper_size_info_16 *values;
970
971         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
972         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
973
974         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
975                 if (temp == values[i].size_value) {
976                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
977                         agp_bridge->aperture_size_idx = i;
978                         return values[i].size;
979                 }
980         }
981
982         return 0;
983 }
984
985 static int __intel_8xx_fetch_size(u8 temp)
986 {
987         int i;
988         struct aper_size_info_8 *values;
989
990         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
991
992         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
993                 if (temp == values[i].size_value) {
994                         agp_bridge->previous_size =
995                                 agp_bridge->current_size = (void *) (values + i);
996                         agp_bridge->aperture_size_idx = i;
997                         return values[i].size;
998                 }
999         }
1000         return 0;
1001 }
1002
1003 static int intel_8xx_fetch_size(void)
1004 {
1005         u8 temp;
1006
1007         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1008         return __intel_8xx_fetch_size(temp);
1009 }
1010
1011 static int intel_815_fetch_size(void)
1012 {
1013         u8 temp;
1014
1015         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1016          * one non-reserved bit, so mask the others out ... */
1017         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1018         temp &= (1 << 3);
1019
1020         return __intel_8xx_fetch_size(temp);
1021 }
1022
1023 static void intel_tlbflush(struct agp_memory *mem)
1024 {
1025         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1026         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1027 }
1028
1029
1030 static void intel_8xx_tlbflush(struct agp_memory *mem)
1031 {
1032         u32 temp;
1033         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1034         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1035         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1036         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1037 }
1038
1039
1040 static void intel_cleanup(void)
1041 {
1042         u16 temp;
1043         struct aper_size_info_16 *previous_size;
1044
1045         previous_size = A_SIZE_16(agp_bridge->previous_size);
1046         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1047         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1048         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1049 }
1050
1051
1052 static void intel_8xx_cleanup(void)
1053 {
1054         u16 temp;
1055         struct aper_size_info_8 *previous_size;
1056
1057         previous_size = A_SIZE_8(agp_bridge->previous_size);
1058         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1059         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1060         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1061 }
1062
1063
1064 static int intel_configure(void)
1065 {
1066         u32 temp;
1067         u16 temp2;
1068         struct aper_size_info_16 *current_size;
1069
1070         current_size = A_SIZE_16(agp_bridge->current_size);
1071
1072         /* aperture size */
1073         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1074
1075         /* address to map to */
1076         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1077         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1078
1079         /* attbase - aperture base */
1080         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1081
1082         /* agpctrl */
1083         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1084
1085         /* paccfg/nbxcfg */
1086         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1087         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1088                         (temp2 & ~(1 << 10)) | (1 << 9));
1089         /* clear any possible error conditions */
1090         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1091         return 0;
1092 }
1093
1094 static int intel_815_configure(void)
1095 {
1096         u32 temp, addr;
1097         u8 temp2;
1098         struct aper_size_info_8 *current_size;
1099
1100         /* attbase - aperture base */
1101         /* the Intel 815 chipset spec. says that bits 29-31 in the
1102         * ATTBASE register are reserved -> try not to write them */
1103         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1104                 printk (KERN_EMERG PFX "gatt bus addr too high");
1105                 return -EINVAL;
1106         }
1107
1108         current_size = A_SIZE_8(agp_bridge->current_size);
1109
1110         /* aperture size */
1111         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1112                         current_size->size_value);
1113
1114         /* address to map to */
1115         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1116         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1117
1118         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1119         addr &= INTEL_815_ATTBASE_MASK;
1120         addr |= agp_bridge->gatt_bus_addr;
1121         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1122
1123         /* agpctrl */
1124         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1125
1126         /* apcont */
1127         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1128         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1129
1130         /* clear any possible error conditions */
1131         /* Oddness : this chipset seems to have no ERRSTS register ! */
1132         return 0;
1133 }
1134
1135 static void intel_820_tlbflush(struct agp_memory *mem)
1136 {
1137         return;
1138 }
1139
1140 static void intel_820_cleanup(void)
1141 {
1142         u8 temp;
1143         struct aper_size_info_8 *previous_size;
1144
1145         previous_size = A_SIZE_8(agp_bridge->previous_size);
1146         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1147         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1148                         temp & ~(1 << 1));
1149         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1150                         previous_size->size_value);
1151 }
1152
1153
1154 static int intel_820_configure(void)
1155 {
1156         u32 temp;
1157         u8 temp2;
1158         struct aper_size_info_8 *current_size;
1159
1160         current_size = A_SIZE_8(agp_bridge->current_size);
1161
1162         /* aperture size */
1163         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1164
1165         /* address to map to */
1166         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1167         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1168
1169         /* attbase - aperture base */
1170         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1171
1172         /* agpctrl */
1173         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1174
1175         /* global enable aperture access */
1176         /* This flag is not accessed through MCHCFG register as in */
1177         /* i850 chipset. */
1178         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1179         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1180         /* clear any possible AGP-related error conditions */
1181         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1182         return 0;
1183 }
1184
1185 static int intel_840_configure(void)
1186 {
1187         u32 temp;
1188         u16 temp2;
1189         struct aper_size_info_8 *current_size;
1190
1191         current_size = A_SIZE_8(agp_bridge->current_size);
1192
1193         /* aperture size */
1194         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1195
1196         /* address to map to */
1197         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1198         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1199
1200         /* attbase - aperture base */
1201         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1202
1203         /* agpctrl */
1204         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1205
1206         /* mcgcfg */
1207         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1208         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1209         /* clear any possible error conditions */
1210         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1211         return 0;
1212 }
1213
1214 static int intel_845_configure(void)
1215 {
1216         u32 temp;
1217         u8 temp2;
1218         struct aper_size_info_8 *current_size;
1219
1220         current_size = A_SIZE_8(agp_bridge->current_size);
1221
1222         /* aperture size */
1223         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1224
1225         if (agp_bridge->apbase_config != 0) {
1226                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1227                                        agp_bridge->apbase_config);
1228         } else {
1229                 /* address to map to */
1230                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1231                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1232                 agp_bridge->apbase_config = temp;
1233         }
1234
1235         /* attbase - aperture base */
1236         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1237
1238         /* agpctrl */
1239         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1240
1241         /* agpm */
1242         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1243         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1244         /* clear any possible error conditions */
1245         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1246         return 0;
1247 }
1248
1249 static int intel_850_configure(void)
1250 {
1251         u32 temp;
1252         u16 temp2;
1253         struct aper_size_info_8 *current_size;
1254
1255         current_size = A_SIZE_8(agp_bridge->current_size);
1256
1257         /* aperture size */
1258         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1259
1260         /* address to map to */
1261         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1262         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1263
1264         /* attbase - aperture base */
1265         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1266
1267         /* agpctrl */
1268         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1269
1270         /* mcgcfg */
1271         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1272         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1273         /* clear any possible AGP-related error conditions */
1274         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1275         return 0;
1276 }
1277
1278 static int intel_860_configure(void)
1279 {
1280         u32 temp;
1281         u16 temp2;
1282         struct aper_size_info_8 *current_size;
1283
1284         current_size = A_SIZE_8(agp_bridge->current_size);
1285
1286         /* aperture size */
1287         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1288
1289         /* address to map to */
1290         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1291         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1292
1293         /* attbase - aperture base */
1294         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1295
1296         /* agpctrl */
1297         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1298
1299         /* mcgcfg */
1300         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1301         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1302         /* clear any possible AGP-related error conditions */
1303         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1304         return 0;
1305 }
1306
1307 static int intel_830mp_configure(void)
1308 {
1309         u32 temp;
1310         u16 temp2;
1311         struct aper_size_info_8 *current_size;
1312
1313         current_size = A_SIZE_8(agp_bridge->current_size);
1314
1315         /* aperture size */
1316         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1317
1318         /* address to map to */
1319         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1320         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1321
1322         /* attbase - aperture base */
1323         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1324
1325         /* agpctrl */
1326         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1327
1328         /* gmch */
1329         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1330         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1331         /* clear any possible AGP-related error conditions */
1332         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1333         return 0;
1334 }
1335
1336 static int intel_7505_configure(void)
1337 {
1338         u32 temp;
1339         u16 temp2;
1340         struct aper_size_info_8 *current_size;
1341
1342         current_size = A_SIZE_8(agp_bridge->current_size);
1343
1344         /* aperture size */
1345         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1346
1347         /* address to map to */
1348         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1349         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1350
1351         /* attbase - aperture base */
1352         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1353
1354         /* agpctrl */
1355         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1356
1357         /* mchcfg */
1358         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1359         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1360
1361         return 0;
1362 }
1363
1364 /* Setup function */
1365 static const struct gatt_mask intel_generic_masks[] =
1366 {
1367         {.mask = 0x00000017, .type = 0}
1368 };
1369
1370 static const struct aper_size_info_8 intel_815_sizes[2] =
1371 {
1372         {64, 16384, 4, 0},
1373         {32, 8192, 3, 8},
1374 };
1375
1376 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1377 {
1378         {256, 65536, 6, 0},
1379         {128, 32768, 5, 32},
1380         {64, 16384, 4, 48},
1381         {32, 8192, 3, 56},
1382         {16, 4096, 2, 60},
1383         {8, 2048, 1, 62},
1384         {4, 1024, 0, 63}
1385 };
1386
1387 static const struct aper_size_info_16 intel_generic_sizes[7] =
1388 {
1389         {256, 65536, 6, 0},
1390         {128, 32768, 5, 32},
1391         {64, 16384, 4, 48},
1392         {32, 8192, 3, 56},
1393         {16, 4096, 2, 60},
1394         {8, 2048, 1, 62},
1395         {4, 1024, 0, 63}
1396 };
1397
1398 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1399 {
1400         {256, 65536, 6, 0},
1401         {128, 32768, 5, 32},
1402         {64, 16384, 4, 48},
1403         {32, 8192, 3, 56}
1404 };
1405
1406 static const struct agp_bridge_driver intel_generic_driver = {
1407         .owner                  = THIS_MODULE,
1408         .aperture_sizes         = intel_generic_sizes,
1409         .size_type              = U16_APER_SIZE,
1410         .num_aperture_sizes     = 7,
1411         .configure              = intel_configure,
1412         .fetch_size             = intel_fetch_size,
1413         .cleanup                = intel_cleanup,
1414         .tlb_flush              = intel_tlbflush,
1415         .mask_memory            = agp_generic_mask_memory,
1416         .masks                  = intel_generic_masks,
1417         .agp_enable             = agp_generic_enable,
1418         .cache_flush            = global_cache_flush,
1419         .create_gatt_table      = agp_generic_create_gatt_table,
1420         .free_gatt_table        = agp_generic_free_gatt_table,
1421         .insert_memory          = agp_generic_insert_memory,
1422         .remove_memory          = agp_generic_remove_memory,
1423         .alloc_by_type          = agp_generic_alloc_by_type,
1424         .free_by_type           = agp_generic_free_by_type,
1425         .agp_alloc_page         = agp_generic_alloc_page,
1426         .agp_destroy_page       = agp_generic_destroy_page,
1427         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1428 };
1429
1430 static const struct agp_bridge_driver intel_810_driver = {
1431         .owner                  = THIS_MODULE,
1432         .aperture_sizes         = intel_i810_sizes,
1433         .size_type              = FIXED_APER_SIZE,
1434         .num_aperture_sizes     = 2,
1435         .needs_scratch_page     = TRUE,
1436         .configure              = intel_i810_configure,
1437         .fetch_size             = intel_i810_fetch_size,
1438         .cleanup                = intel_i810_cleanup,
1439         .tlb_flush              = intel_i810_tlbflush,
1440         .mask_memory            = intel_i810_mask_memory,
1441         .masks                  = intel_i810_masks,
1442         .agp_enable             = intel_i810_agp_enable,
1443         .cache_flush            = global_cache_flush,
1444         .create_gatt_table      = agp_generic_create_gatt_table,
1445         .free_gatt_table        = agp_generic_free_gatt_table,
1446         .insert_memory          = intel_i810_insert_entries,
1447         .remove_memory          = intel_i810_remove_entries,
1448         .alloc_by_type          = intel_i810_alloc_by_type,
1449         .free_by_type           = intel_i810_free_by_type,
1450         .agp_alloc_page         = agp_generic_alloc_page,
1451         .agp_destroy_page       = agp_generic_destroy_page,
1452         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1453 };
1454
1455 static const struct agp_bridge_driver intel_815_driver = {
1456         .owner                  = THIS_MODULE,
1457         .aperture_sizes         = intel_815_sizes,
1458         .size_type              = U8_APER_SIZE,
1459         .num_aperture_sizes     = 2,
1460         .configure              = intel_815_configure,
1461         .fetch_size             = intel_815_fetch_size,
1462         .cleanup                = intel_8xx_cleanup,
1463         .tlb_flush              = intel_8xx_tlbflush,
1464         .mask_memory            = agp_generic_mask_memory,
1465         .masks                  = intel_generic_masks,
1466         .agp_enable             = agp_generic_enable,
1467         .cache_flush            = global_cache_flush,
1468         .create_gatt_table      = agp_generic_create_gatt_table,
1469         .free_gatt_table        = agp_generic_free_gatt_table,
1470         .insert_memory          = agp_generic_insert_memory,
1471         .remove_memory          = agp_generic_remove_memory,
1472         .alloc_by_type          = agp_generic_alloc_by_type,
1473         .free_by_type           = agp_generic_free_by_type,
1474         .agp_alloc_page         = agp_generic_alloc_page,
1475         .agp_destroy_page       = agp_generic_destroy_page,
1476         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1477 };
1478
1479 static const struct agp_bridge_driver intel_830_driver = {
1480         .owner                  = THIS_MODULE,
1481         .aperture_sizes         = intel_i830_sizes,
1482         .size_type              = FIXED_APER_SIZE,
1483         .num_aperture_sizes     = 4,
1484         .needs_scratch_page     = TRUE,
1485         .configure              = intel_i830_configure,
1486         .fetch_size             = intel_i830_fetch_size,
1487         .cleanup                = intel_i830_cleanup,
1488         .tlb_flush              = intel_i810_tlbflush,
1489         .mask_memory            = intel_i810_mask_memory,
1490         .masks                  = intel_i810_masks,
1491         .agp_enable             = intel_i810_agp_enable,
1492         .cache_flush            = global_cache_flush,
1493         .create_gatt_table      = intel_i830_create_gatt_table,
1494         .free_gatt_table        = intel_i830_free_gatt_table,
1495         .insert_memory          = intel_i830_insert_entries,
1496         .remove_memory          = intel_i830_remove_entries,
1497         .alloc_by_type          = intel_i830_alloc_by_type,
1498         .free_by_type           = intel_i810_free_by_type,
1499         .agp_alloc_page         = agp_generic_alloc_page,
1500         .agp_destroy_page       = agp_generic_destroy_page,
1501         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1502 };
1503
1504 static const struct agp_bridge_driver intel_820_driver = {
1505         .owner                  = THIS_MODULE,
1506         .aperture_sizes         = intel_8xx_sizes,
1507         .size_type              = U8_APER_SIZE,
1508         .num_aperture_sizes     = 7,
1509         .configure              = intel_820_configure,
1510         .fetch_size             = intel_8xx_fetch_size,
1511         .cleanup                = intel_820_cleanup,
1512         .tlb_flush              = intel_820_tlbflush,
1513         .mask_memory            = agp_generic_mask_memory,
1514         .masks                  = intel_generic_masks,
1515         .agp_enable             = agp_generic_enable,
1516         .cache_flush            = global_cache_flush,
1517         .create_gatt_table      = agp_generic_create_gatt_table,
1518         .free_gatt_table        = agp_generic_free_gatt_table,
1519         .insert_memory          = agp_generic_insert_memory,
1520         .remove_memory          = agp_generic_remove_memory,
1521         .alloc_by_type          = agp_generic_alloc_by_type,
1522         .free_by_type           = agp_generic_free_by_type,
1523         .agp_alloc_page         = agp_generic_alloc_page,
1524         .agp_destroy_page       = agp_generic_destroy_page,
1525         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1526 };
1527
1528 static const struct agp_bridge_driver intel_830mp_driver = {
1529         .owner                  = THIS_MODULE,
1530         .aperture_sizes         = intel_830mp_sizes,
1531         .size_type              = U8_APER_SIZE,
1532         .num_aperture_sizes     = 4,
1533         .configure              = intel_830mp_configure,
1534         .fetch_size             = intel_8xx_fetch_size,
1535         .cleanup                = intel_8xx_cleanup,
1536         .tlb_flush              = intel_8xx_tlbflush,
1537         .mask_memory            = agp_generic_mask_memory,
1538         .masks                  = intel_generic_masks,
1539         .agp_enable             = agp_generic_enable,
1540         .cache_flush            = global_cache_flush,
1541         .create_gatt_table      = agp_generic_create_gatt_table,
1542         .free_gatt_table        = agp_generic_free_gatt_table,
1543         .insert_memory          = agp_generic_insert_memory,
1544         .remove_memory          = agp_generic_remove_memory,
1545         .alloc_by_type          = agp_generic_alloc_by_type,
1546         .free_by_type           = agp_generic_free_by_type,
1547         .agp_alloc_page         = agp_generic_alloc_page,
1548         .agp_destroy_page       = agp_generic_destroy_page,
1549         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1550 };
1551
1552 static const struct agp_bridge_driver intel_840_driver = {
1553         .owner                  = THIS_MODULE,
1554         .aperture_sizes         = intel_8xx_sizes,
1555         .size_type              = U8_APER_SIZE,
1556         .num_aperture_sizes     = 7,
1557         .configure              = intel_840_configure,
1558         .fetch_size             = intel_8xx_fetch_size,
1559         .cleanup                = intel_8xx_cleanup,
1560         .tlb_flush              = intel_8xx_tlbflush,
1561         .mask_memory            = agp_generic_mask_memory,
1562         .masks                  = intel_generic_masks,
1563         .agp_enable             = agp_generic_enable,
1564         .cache_flush            = global_cache_flush,
1565         .create_gatt_table      = agp_generic_create_gatt_table,
1566         .free_gatt_table        = agp_generic_free_gatt_table,
1567         .insert_memory          = agp_generic_insert_memory,
1568         .remove_memory          = agp_generic_remove_memory,
1569         .alloc_by_type          = agp_generic_alloc_by_type,
1570         .free_by_type           = agp_generic_free_by_type,
1571         .agp_alloc_page         = agp_generic_alloc_page,
1572         .agp_destroy_page       = agp_generic_destroy_page,
1573         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1574 };
1575
1576 static const struct agp_bridge_driver intel_845_driver = {
1577         .owner                  = THIS_MODULE,
1578         .aperture_sizes         = intel_8xx_sizes,
1579         .size_type              = U8_APER_SIZE,
1580         .num_aperture_sizes     = 7,
1581         .configure              = intel_845_configure,
1582         .fetch_size             = intel_8xx_fetch_size,
1583         .cleanup                = intel_8xx_cleanup,
1584         .tlb_flush              = intel_8xx_tlbflush,
1585         .mask_memory            = agp_generic_mask_memory,
1586         .masks                  = intel_generic_masks,
1587         .agp_enable             = agp_generic_enable,
1588         .cache_flush            = global_cache_flush,
1589         .create_gatt_table      = agp_generic_create_gatt_table,
1590         .free_gatt_table        = agp_generic_free_gatt_table,
1591         .insert_memory          = agp_generic_insert_memory,
1592         .remove_memory          = agp_generic_remove_memory,
1593         .alloc_by_type          = agp_generic_alloc_by_type,
1594         .free_by_type           = agp_generic_free_by_type,
1595         .agp_alloc_page         = agp_generic_alloc_page,
1596         .agp_destroy_page       = agp_generic_destroy_page,
1597         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1598 };
1599
1600 static const struct agp_bridge_driver intel_850_driver = {
1601         .owner                  = THIS_MODULE,
1602         .aperture_sizes         = intel_8xx_sizes,
1603         .size_type              = U8_APER_SIZE,
1604         .num_aperture_sizes     = 7,
1605         .configure              = intel_850_configure,
1606         .fetch_size             = intel_8xx_fetch_size,
1607         .cleanup                = intel_8xx_cleanup,
1608         .tlb_flush              = intel_8xx_tlbflush,
1609         .mask_memory            = agp_generic_mask_memory,
1610         .masks                  = intel_generic_masks,
1611         .agp_enable             = agp_generic_enable,
1612         .cache_flush            = global_cache_flush,
1613         .create_gatt_table      = agp_generic_create_gatt_table,
1614         .free_gatt_table        = agp_generic_free_gatt_table,
1615         .insert_memory          = agp_generic_insert_memory,
1616         .remove_memory          = agp_generic_remove_memory,
1617         .alloc_by_type          = agp_generic_alloc_by_type,
1618         .free_by_type           = agp_generic_free_by_type,
1619         .agp_alloc_page         = agp_generic_alloc_page,
1620         .agp_destroy_page       = agp_generic_destroy_page,
1621         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1622 };
1623
1624 static const struct agp_bridge_driver intel_860_driver = {
1625         .owner                  = THIS_MODULE,
1626         .aperture_sizes         = intel_8xx_sizes,
1627         .size_type              = U8_APER_SIZE,
1628         .num_aperture_sizes     = 7,
1629         .configure              = intel_860_configure,
1630         .fetch_size             = intel_8xx_fetch_size,
1631         .cleanup                = intel_8xx_cleanup,
1632         .tlb_flush              = intel_8xx_tlbflush,
1633         .mask_memory            = agp_generic_mask_memory,
1634         .masks                  = intel_generic_masks,
1635         .agp_enable             = agp_generic_enable,
1636         .cache_flush            = global_cache_flush,
1637         .create_gatt_table      = agp_generic_create_gatt_table,
1638         .free_gatt_table        = agp_generic_free_gatt_table,
1639         .insert_memory          = agp_generic_insert_memory,
1640         .remove_memory          = agp_generic_remove_memory,
1641         .alloc_by_type          = agp_generic_alloc_by_type,
1642         .free_by_type           = agp_generic_free_by_type,
1643         .agp_alloc_page         = agp_generic_alloc_page,
1644         .agp_destroy_page       = agp_generic_destroy_page,
1645         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1646 };
1647
1648 static const struct agp_bridge_driver intel_915_driver = {
1649         .owner                  = THIS_MODULE,
1650         .aperture_sizes         = intel_i830_sizes,
1651         .size_type              = FIXED_APER_SIZE,
1652         .num_aperture_sizes     = 4,
1653         .needs_scratch_page     = TRUE,
1654         .configure              = intel_i915_configure,
1655         .fetch_size             = intel_i9xx_fetch_size,
1656         .cleanup                = intel_i915_cleanup,
1657         .tlb_flush              = intel_i810_tlbflush,
1658         .mask_memory            = intel_i810_mask_memory,
1659         .masks                  = intel_i810_masks,
1660         .agp_enable             = intel_i810_agp_enable,
1661         .cache_flush            = global_cache_flush,
1662         .create_gatt_table      = intel_i915_create_gatt_table,
1663         .free_gatt_table        = intel_i830_free_gatt_table,
1664         .insert_memory          = intel_i915_insert_entries,
1665         .remove_memory          = intel_i915_remove_entries,
1666         .alloc_by_type          = intel_i830_alloc_by_type,
1667         .free_by_type           = intel_i810_free_by_type,
1668         .agp_alloc_page         = agp_generic_alloc_page,
1669         .agp_destroy_page       = agp_generic_destroy_page,
1670         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1671 };
1672
1673 static const struct agp_bridge_driver intel_i965_driver = {
1674        .owner                  = THIS_MODULE,
1675        .aperture_sizes         = intel_i830_sizes,
1676        .size_type              = FIXED_APER_SIZE,
1677        .num_aperture_sizes     = 4,
1678        .needs_scratch_page     = TRUE,
1679        .configure              = intel_i915_configure,
1680        .fetch_size             = intel_i9xx_fetch_size,
1681        .cleanup                = intel_i915_cleanup,
1682        .tlb_flush              = intel_i810_tlbflush,
1683        .mask_memory            = intel_i965_mask_memory,
1684        .masks                  = intel_i810_masks,
1685        .agp_enable             = intel_i810_agp_enable,
1686        .cache_flush            = global_cache_flush,
1687        .create_gatt_table      = intel_i965_create_gatt_table,
1688        .free_gatt_table        = intel_i830_free_gatt_table,
1689        .insert_memory          = intel_i915_insert_entries,
1690        .remove_memory          = intel_i915_remove_entries,
1691        .alloc_by_type          = intel_i830_alloc_by_type,
1692        .free_by_type           = intel_i810_free_by_type,
1693        .agp_alloc_page         = agp_generic_alloc_page,
1694        .agp_destroy_page       = agp_generic_destroy_page,
1695        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1696 };
1697
1698 static const struct agp_bridge_driver intel_7505_driver = {
1699         .owner                  = THIS_MODULE,
1700         .aperture_sizes         = intel_8xx_sizes,
1701         .size_type              = U8_APER_SIZE,
1702         .num_aperture_sizes     = 7,
1703         .configure              = intel_7505_configure,
1704         .fetch_size             = intel_8xx_fetch_size,
1705         .cleanup                = intel_8xx_cleanup,
1706         .tlb_flush              = intel_8xx_tlbflush,
1707         .mask_memory            = agp_generic_mask_memory,
1708         .masks                  = intel_generic_masks,
1709         .agp_enable             = agp_generic_enable,
1710         .cache_flush            = global_cache_flush,
1711         .create_gatt_table      = agp_generic_create_gatt_table,
1712         .free_gatt_table        = agp_generic_free_gatt_table,
1713         .insert_memory          = agp_generic_insert_memory,
1714         .remove_memory          = agp_generic_remove_memory,
1715         .alloc_by_type          = agp_generic_alloc_by_type,
1716         .free_by_type           = agp_generic_free_by_type,
1717         .agp_alloc_page         = agp_generic_alloc_page,
1718         .agp_destroy_page       = agp_generic_destroy_page,
1719         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1720 };
1721
1722
1723 static int find_gmch(u16 device)
1724 {
1725         struct pci_dev *gmch_device;
1726
1727         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1728         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1729                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1730                                 device, gmch_device);
1731         }
1732
1733         if (!gmch_device)
1734                 return 0;
1735
1736         intel_private.pcidev = gmch_device;
1737         return 1;
1738 }
1739
1740 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1741  * driver and gmch_driver must be non-null, and find_gmch will determine
1742  * which one should be used if a gmch_chip_id is present.
1743  */
1744 static const struct intel_driver_description {
1745         unsigned int chip_id;
1746         unsigned int gmch_chip_id;
1747         char *name;
1748         const struct agp_bridge_driver *driver;
1749         const struct agp_bridge_driver *gmch_driver;
1750 } intel_agp_chipsets[] = {
1751         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL },
1752         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL },
1753         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL },
1754         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1755                 NULL, &intel_810_driver },
1756         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1757                 NULL, &intel_810_driver },
1758         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1759                 NULL, &intel_810_driver },
1760         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1761                 &intel_810_driver, &intel_815_driver },
1762         { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL },
1763         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL },
1764         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1765                 &intel_830mp_driver, &intel_830_driver },
1766         { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL },
1767         { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL },
1768         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1769                 &intel_845_driver, &intel_830_driver },
1770         { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL },
1771         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
1772         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1773                 &intel_845_driver, &intel_830_driver },
1774         { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
1775         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
1776                 &intel_845_driver, &intel_830_driver },
1777         { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
1778         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1779                 &intel_845_driver, &intel_915_driver },
1780         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1781                 &intel_845_driver, &intel_915_driver },
1782         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1783                 &intel_845_driver, &intel_915_driver },
1784         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1785                 &intel_845_driver, &intel_915_driver },
1786         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1787                 &intel_845_driver, &intel_915_driver },
1788         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1789                 &intel_845_driver, &intel_i965_driver },
1790         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, "965G",
1791                 &intel_845_driver, &intel_i965_driver },
1792         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1793                 &intel_845_driver, &intel_i965_driver },
1794         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1795                 &intel_845_driver, &intel_i965_driver },
1796         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1797                 &intel_845_driver, &intel_i965_driver },
1798         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1799                 &intel_845_driver, &intel_i965_driver },
1800         { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
1801         { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
1802         { 0, 0, NULL, NULL, NULL }
1803 };
1804
1805 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1806                                      const struct pci_device_id *ent)
1807 {
1808         struct agp_bridge_data *bridge;
1809         u8 cap_ptr = 0;
1810         struct resource *r;
1811         int i;
1812
1813         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1814
1815         bridge = agp_alloc_bridge();
1816         if (!bridge)
1817                 return -ENOMEM;
1818
1819         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1820                 /* In case that multiple models of gfx chip may
1821                    stand on same host bridge type, this can be
1822                    sure we detect the right IGD. */
1823                 if ((pdev->device == intel_agp_chipsets[i].chip_id) &&
1824                         ((intel_agp_chipsets[i].gmch_chip_id == 0) ||
1825                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)))
1826                         break;
1827         }
1828
1829         if (intel_agp_chipsets[i].name == NULL) {
1830                 if (cap_ptr)
1831                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1832                                "(device id: %04x)\n", pdev->device);
1833                 agp_put_bridge(bridge);
1834                 return -ENODEV;
1835         }
1836
1837         if (intel_agp_chipsets[i].gmch_chip_id != 0)
1838             bridge->driver = intel_agp_chipsets[i].gmch_driver;
1839         else
1840             bridge->driver = intel_agp_chipsets[i].driver;
1841
1842         if (bridge->driver == NULL) {
1843                 printk(KERN_WARNING PFX "Failed to find bridge device "
1844                         "(chip_id: %04x)\n", intel_agp_chipsets[i].gmch_chip_id);
1845                 agp_put_bridge(bridge);
1846                 return -ENODEV;
1847         }
1848
1849         bridge->dev = pdev;
1850         bridge->capndx = cap_ptr;
1851         bridge->dev_private_data = &intel_private;
1852
1853         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1854                 intel_agp_chipsets[i].name);
1855
1856         /*
1857         * The following fixes the case where the BIOS has "forgotten" to
1858         * provide an address range for the GART.
1859         * 20030610 - hamish@zot.org
1860         */
1861         r = &pdev->resource[0];
1862         if (!r->start && r->end) {
1863                 if (pci_assign_resource(pdev, 0)) {
1864                         printk(KERN_ERR PFX "could not assign resource 0\n");
1865                         agp_put_bridge(bridge);
1866                         return -ENODEV;
1867                 }
1868         }
1869
1870         /*
1871         * If the device has not been properly setup, the following will catch
1872         * the problem and should stop the system from crashing.
1873         * 20030610 - hamish@zot.org
1874         */
1875         if (pci_enable_device(pdev)) {
1876                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1877                 agp_put_bridge(bridge);
1878                 return -ENODEV;
1879         }
1880
1881         /* Fill in the mode register */
1882         if (cap_ptr) {
1883                 pci_read_config_dword(pdev,
1884                                 bridge->capndx+PCI_AGP_STATUS,
1885                                 &bridge->mode);
1886         }
1887
1888         pci_set_drvdata(pdev, bridge);
1889         return agp_add_bridge(bridge);
1890 }
1891
1892 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1893 {
1894         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1895
1896         agp_remove_bridge(bridge);
1897
1898         if (intel_private.pcidev)
1899                 pci_dev_put(intel_private.pcidev);
1900
1901         agp_put_bridge(bridge);
1902 }
1903
1904 #ifdef CONFIG_PM
1905 static int agp_intel_resume(struct pci_dev *pdev)
1906 {
1907         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1908
1909         pci_restore_state(pdev);
1910
1911         /* We should restore our graphics device's config space,
1912          * as host bridge (00:00) resumes before graphics device (02:00),
1913          * then our access to its pci space can work right.
1914          */
1915         if (intel_private.pcidev)
1916                 pci_restore_state(intel_private.pcidev);
1917
1918         if (bridge->driver == &intel_generic_driver)
1919                 intel_configure();
1920         else if (bridge->driver == &intel_850_driver)
1921                 intel_850_configure();
1922         else if (bridge->driver == &intel_845_driver)
1923                 intel_845_configure();
1924         else if (bridge->driver == &intel_830mp_driver)
1925                 intel_830mp_configure();
1926         else if (bridge->driver == &intel_915_driver)
1927                 intel_i915_configure();
1928         else if (bridge->driver == &intel_830_driver)
1929                 intel_i830_configure();
1930         else if (bridge->driver == &intel_810_driver)
1931                 intel_i810_configure();
1932         else if (bridge->driver == &intel_i965_driver)
1933                 intel_i915_configure();
1934
1935         return 0;
1936 }
1937 #endif
1938
1939 static struct pci_device_id agp_intel_pci_table[] = {
1940 #define ID(x)                                           \
1941         {                                               \
1942         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
1943         .class_mask     = ~0,                           \
1944         .vendor         = PCI_VENDOR_ID_INTEL,          \
1945         .device         = x,                            \
1946         .subvendor      = PCI_ANY_ID,                   \
1947         .subdevice      = PCI_ANY_ID,                   \
1948         }
1949         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1950         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1951         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1952         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1953         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1954         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1955         ID(PCI_DEVICE_ID_INTEL_82815_MC),
1956         ID(PCI_DEVICE_ID_INTEL_82820_HB),
1957         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1958         ID(PCI_DEVICE_ID_INTEL_82830_HB),
1959         ID(PCI_DEVICE_ID_INTEL_82840_HB),
1960         ID(PCI_DEVICE_ID_INTEL_82845_HB),
1961         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1962         ID(PCI_DEVICE_ID_INTEL_82850_HB),
1963         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1964         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1965         ID(PCI_DEVICE_ID_INTEL_82860_HB),
1966         ID(PCI_DEVICE_ID_INTEL_82865_HB),
1967         ID(PCI_DEVICE_ID_INTEL_82875_HB),
1968         ID(PCI_DEVICE_ID_INTEL_7505_0),
1969         ID(PCI_DEVICE_ID_INTEL_7205_0),
1970         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1971         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1972         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1973         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1974         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1975         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
1976         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1977         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1978         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
1979         { }
1980 };
1981
1982 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1983
1984 static struct pci_driver agp_intel_pci_driver = {
1985         .name           = "agpgart-intel",
1986         .id_table       = agp_intel_pci_table,
1987         .probe          = agp_intel_probe,
1988         .remove         = __devexit_p(agp_intel_remove),
1989 #ifdef CONFIG_PM
1990         .resume         = agp_intel_resume,
1991 #endif
1992 };
1993
1994 static int __init agp_intel_init(void)
1995 {
1996         if (agp_off)
1997                 return -EINVAL;
1998         return pci_register_driver(&agp_intel_pci_driver);
1999 }
2000
2001 static void __exit agp_intel_cleanup(void)
2002 {
2003         pci_unregister_driver(&agp_intel_pci_driver);
2004 }
2005
2006 module_init(agp_intel_init);
2007 module_exit(agp_intel_cleanup);
2008
2009 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2010 MODULE_LICENSE("GPL and additional rights");